drivers/ide/pci/pdc202xx_old.h

   1 #ifndef PDC202XX_H
   2 #define PDC202XX_H
   3
   4 #include <linux/config.h>
   5 #include <linux/pci.h>
   6 #include <linux/ide.h>
   7
   8 #ifndef SPLIT_BYTE
   9 #define SPLIT_BYTE(B,H,L)       ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
  10 #endif
  11
  12 #define PDC202XX_DEBUG_DRIVE_INFO               0
  13 #define PDC202XX_DECODE_REGISTER_INFO           0
  14
  15 static const char *pdc_quirk_drives[] = {
  16         "QUANTUM FIREBALLlct08 08",
  17         "QUANTUM FIREBALLP KA6.4",
  18         "QUANTUM FIREBALLP KA9.1",
  19         "QUANTUM FIREBALLP LM20.4",
  20         "QUANTUM FIREBALLP KX13.6",
  21         "QUANTUM FIREBALLP KX20.5",
  22         "QUANTUM FIREBALLP KX27.3",
  23         "QUANTUM FIREBALLP LM20.5",
  24         NULL
  25 };
  26
  27 static inline u8 *pdc202xx_pio_verbose (u32 drive_pci)
  28 {
  29         if ((drive_pci & 0x000ff000) == 0x000ff000) return("NOTSET");
  30         if ((drive_pci & 0x00000401) == 0x00000401) return("PIO 4");
  31         if ((drive_pci & 0x00000602) == 0x00000602) return("PIO 3");
  32         if ((drive_pci & 0x00000803) == 0x00000803) return("PIO 2");
  33         if ((drive_pci & 0x00000C05) == 0x00000C05) return("PIO 1");
  34         if ((drive_pci & 0x00001309) == 0x00001309) return("PIO 0");
  35         return("PIO ?");
  36 }
  37
  38 static inline u8 *pdc202xx_dma_verbose (u32 drive_pci)
  39 {
  40         if ((drive_pci & 0x00036000) == 0x00036000) return("MWDMA 2");
  41         if ((drive_pci & 0x00046000) == 0x00046000) return("MWDMA 1");
  42         if ((drive_pci & 0x00056000) == 0x00056000) return("MWDMA 0");
  43         if ((drive_pci & 0x00056000) == 0x00056000) return("SWDMA 2");
  44         if ((drive_pci & 0x00068000) == 0x00068000) return("SWDMA 1");
  45         if ((drive_pci & 0x000BC000) == 0x000BC000) return("SWDMA 0");
  46         return("PIO---");
  47 }
  48
  49 static inline u8 *pdc202xx_ultra_verbose (u32 drive_pci, u16 slow_cable)
  50 {
  51         if ((drive_pci & 0x000ff000) == 0x000ff000)
  52                 return("NOTSET");
  53         if ((drive_pci & 0x00012000) == 0x00012000)
  54                 return((slow_cable) ? "UDMA 2" : "UDMA 4");
  55         if ((drive_pci & 0x00024000) == 0x00024000)
  56                 return((slow_cable) ? "UDMA 1" : "UDMA 3");
  57         if ((drive_pci & 0x00036000) == 0x00036000)
  58                 return("UDMA 0");
  59         return(pdc202xx_dma_verbose(drive_pci));
  60 }
  61
  62 /* A Register */
  63 #define SYNC_ERRDY_EN   0xC0
  64
  65 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  66 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  67 #define IORDY_EN        0x20    /* PIO: IOREADY */
  68 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  69
  70 #define PA3             0x08    /* PIO"A" timing */
  71 #define PA2             0x04    /* PIO"A" timing */
  72 #define PA1             0x02    /* PIO"A" timing */
  73 #define PA0             0x01    /* PIO"A" timing */
  74
  75 /* B Register */
  76
  77 #define MB2             0x80    /* DMA"B" timing */
  78 #define MB1             0x40    /* DMA"B" timing */
  79 #define MB0             0x20    /* DMA"B" timing */
  80
  81 #define PB4             0x10    /* PIO_FORCE 1:0 */
  82
  83 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  84 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  85 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  86 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  87
  88 /* C Register */
  89 #define IORDYp_NO_SPEED 0x4F
  90 #define SPEED_DIS       0x0F
  91
  92 #define DMARQp          0x80
  93 #define IORDYp          0x40
  94 #define DMAR_EN         0x20
  95 #define DMAW_EN         0x10
  96
  97 #define MC3             0x08    /* DMA"C" timing */
  98 #define MC2             0x04    /* DMA"C" timing */
  99 #define MC1             0x02    /* DMA"C" timing */
 100 #define MC0             0x01    /* DMA"C" timing */
 101
 102 #if PDC202XX_DECODE_REGISTER_INFO
 103
 104 #define REG_A           0x01
 105 #define REG_B           0x02
 106 #define REG_C           0x04
 107 #define REG_D           0x08
 108
 109 static void decode_registers (u8 registers, u8 value)
 110 {
 111         u8      bit = 0, bit1 = 0, bit2 = 0;
 112
 113         switch(registers) {
 114                 case REG_A:
 115                         bit2 = 0;
 116                         printk("A Register ");
 117                         if (value & 0x80) printk("SYNC_IN ");
 118                         if (value & 0x40) printk("ERRDY_EN ");
 119                         if (value & 0x20) printk("IORDY_EN ");
 120                         if (value & 0x10) printk("PREFETCH_EN ");
 121                         if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
 122                         if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
 123                         if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
 124                         if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
 125                         printk("PIO(A) = %d ", bit2);
 126                         break;
 127                 case REG_B:
 128                         bit1 = 0;bit2 = 0;
 129                         printk("B Register ");
 130                         if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
 131                         if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
 132                         if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
 133                         printk("DMA(B) = %d ", bit1 >> 5);
 134                         if (value & 0x10) printk("PIO_FORCED/PB4 ");
 135                         if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
 136                         if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
 137                         if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
 138                         if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
 139                         printk("PIO(B) = %d ", bit2);
 140                         break;
 141                 case REG_C:
 142                         bit2 = 0;
 143                         printk("C Register ");
 144                         if (value & 0x80) printk("DMARQp ");
 145                         if (value & 0x40) printk("IORDYp ");
 146                         if (value & 0x20) printk("DMAR_EN ");
 147                         if (value & 0x10) printk("DMAW_EN ");
 148
 149                         if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
 150                         if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
 151                         if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
 152                         if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
 153                         printk("DMA(C) = %d ", bit2);
 154                         break;
 155                 case REG_D:
 156                         printk("D Register ");
 157                         break;
 158                 default:
 159                         return;
 160         }
 161         printk("\n        %s ", (registers & REG_D) ? "DP" :
 162                                 (registers & REG_C) ? "CP" :
 163                                 (registers & REG_B) ? "BP" :
 164                                 (registers & REG_A) ? "AP" : "ERROR");
 165         for (bit=128;bit>0;bit/=2)
 166                 printk("%s", (value & bit) ? "1" : "0");
 167         printk("\n");
 168 }
 169
 170 #endif /* PDC202XX_DECODE_REGISTER_INFO */
 171
 172 #define DISPLAY_PDC202XX_TIMINGS
 173
 174 static void init_setup_pdc202ata4(struct pci_dev *dev, ide_pci_device_t *d);
 175 static void init_setup_pdc20265(struct pci_dev *, ide_pci_device_t *);
 176 static void init_setup_pdc202xx(struct pci_dev *, ide_pci_device_t *);
 177 static unsigned int init_chipset_pdc202xx(struct pci_dev *, const char *);
 178 static void init_hwif_pdc202xx(ide_hwif_t *);
 179 static void init_dma_pdc202xx(ide_hwif_t *, unsigned long);
 180
 181 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 182         {       /* 0 */
 183                 .name           = "PDC20246",
 184                 .init_setup     = init_setup_pdc202ata4,
 185                 .init_chipset   = init_chipset_pdc202xx,
 186                 .init_hwif      = init_hwif_pdc202xx,
 187                 .init_dma       = init_dma_pdc202xx,
 188                 .channels       = 2,
 189                 .autodma        = AUTODMA,
 190 #ifndef CONFIG_PDC202XX_FORCE
 191                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 192 #endif
 193                 .bootable       = OFF_BOARD,
 194                 .extra          = 16,
 195         },{     /* 1 */
 196                 .name           = "PDC20262",
 197                 .init_setup     = init_setup_pdc202ata4,
 198                 .init_chipset   = init_chipset_pdc202xx,
 199                 .init_hwif      = init_hwif_pdc202xx,
 200                 .init_dma       = init_dma_pdc202xx,
 201                 .channels       = 2,
 202                 .autodma        = AUTODMA,
 203 #ifndef CONFIG_PDC202XX_FORCE
 204                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 205 #endif
 206                 .bootable       = OFF_BOARD,
 207                 .extra          = 48,
 208                 .flags          = IDEPCI_FLAG_FORCE_PDC,
 209         },{     /* 2 */
 210                 .name           = "PDC20263",
 211                 .init_setup     = init_setup_pdc202ata4,
 212                 .init_chipset   = init_chipset_pdc202xx,
 213                 .init_hwif      = init_hwif_pdc202xx,
 214                 .init_dma       = init_dma_pdc202xx,
 215                 .channels       = 2,
 216                 .autodma        = AUTODMA,
 217 #ifndef CONFIG_PDC202XX_FORCE
 218                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 219 #endif
 220                 .bootable       = OFF_BOARD,
 221                 .extra          = 48,
 222         },{     /* 3 */
 223                 .name           = "PDC20265",
 224                 .init_setup     = init_setup_pdc20265,
 225                 .init_chipset   = init_chipset_pdc202xx,
 226                 .init_hwif      = init_hwif_pdc202xx,
 227                 .init_dma       = init_dma_pdc202xx,
 228                 .channels       = 2,
 229                 .autodma        = AUTODMA,
 230 #ifndef CONFIG_PDC202XX_FORCE
 231                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 232 #endif
 233                 .bootable       = OFF_BOARD,
 234                 .extra          = 48,
 235                 .flags          = IDEPCI_FLAG_FORCE_PDC,
 236         },{     /* 4 */
 237                 .name           = "PDC20267",
 238                 .init_setup     = init_setup_pdc202xx,
 239                 .init_chipset   = init_chipset_pdc202xx,
 240                 .init_hwif      = init_hwif_pdc202xx,
 241                 .init_dma       = init_dma_pdc202xx,
 242                 .channels       = 2,
 243                 .autodma        = AUTODMA,
 244 #ifndef CONFIG_PDC202XX_FORCE
 245                 .enablebits     = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
 246 #endif
 247                 .bootable       = OFF_BOARD,
 248                 .extra          = 48,
 249         }
 250 };
 251
 252 #endif /* PDC202XX_H */