2 * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
4 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2003 Red Hat <alan@redhat.com>
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation available under NDA only
13 * If you are using Marvell SATA-IDE adapters with Maxtor drives
14 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
16 * If you are using WD drives with SATA bridges you must set the
17 * drive to "Single". "Master" will hang
19 * If you have strange problems with nVidia chipset systems please
20 * see the SI support documentation and update your system BIOS
24 #include <linux/types.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/delay.h>
28 #include <linux/hdreg.h>
29 #include <linux/ide.h>
30 #include <linux/init.h>
37 * pdev_is_sata - check if device is SATA
38 * @pdev: PCI device to check
40 * Returns true if this is a SATA controller
43 static int pdev_is_sata(struct pci_dev *pdev)
47 case PCI_DEVICE_ID_SII_3112:
48 case PCI_DEVICE_ID_SII_1210SA:
50 case PCI_DEVICE_ID_SII_680:
58 * is_sata - check if hwif is SATA
59 * @hwif: interface to check
61 * Returns true if this is a SATA controller
64 static inline int is_sata(ide_hwif_t *hwif)
66 return pdev_is_sata(hwif->pci_dev);
70 * siimage_selreg - return register base
74 * Turn a config register offset into the right address in either
75 * PCI space or MMIO space to access the control register in question
76 * Thankfully this is a configuration operation so isnt performance
80 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
82 unsigned long base = (unsigned long)hwif->hwif_data;
85 base += (hwif->channel << 6);
87 base += (hwif->channel << 4);
92 * siimage_seldev - return register base
96 * Turn a config register offset into the right address in either
97 * PCI space or MMIO space to access the control register in question
98 * including accounting for the unit shift.
101 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
103 ide_hwif_t *hwif = HWIF(drive);
104 unsigned long base = (unsigned long)hwif->hwif_data;
107 base += (hwif->channel << 6);
109 base += (hwif->channel << 4);
110 base |= drive->select.b.unit << drive->select.b.unit;
115 * siimage_ratemask - Compute available modes
118 * Compute the available speeds for the devices on the interface.
119 * For the CMD680 this depends on the clocking mode (scsc), for the
120 * SI3312 SATA controller life is a bit simpler. Enforce UDMA33
121 * as a limit if there is no 80pin cable present.
124 static byte siimage_ratemask (ide_drive_t *drive)
126 ide_hwif_t *hwif = HWIF(drive);
127 u8 mode = 0, scsc = 0;
128 unsigned long base = (unsigned long) hwif->hwif_data;
131 scsc = hwif->INB(base + 0x4A);
133 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
137 if(strstr(drive->id->model, "Maxtor"))
142 if ((scsc & 0x30) == 0x10) /* 133 */
144 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
146 else if ((scsc & 0x30) == 0x00) /* 100 */
148 else /* Disabled ? */
151 if (!eighty_ninty_three(drive))
152 mode = min(mode, (u8)1);
157 * siimage_taskfile_timing - turn timing data to a mode
158 * @hwif: interface to query
160 * Read the timing data for the interface and return the
161 * mode that is being used.
164 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
167 unsigned long addr = siimage_selreg(hwif, 2);
170 timing = hwif->INW(addr);
172 pci_read_config_word(hwif->pci_dev, addr, &timing);
175 case 0x10c1: return 4;
176 case 0x10c3: return 3;
178 case 0x1281: return 2;
179 case 0x2283: return 1;
186 * simmage_tuneproc - tune a drive
187 * @drive: drive to tune
188 * @mode_wanted: the target operating mode
190 * Load the timing settings for this device mode into the
191 * controller. If we are in PIO mode 3 or 4 turn on IORDY
192 * monitoring (bit 9). The TF timing is bits 31:16
195 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
197 ide_hwif_t *hwif = HWIF(drive);
200 unsigned long addr = siimage_seldev(drive, 0x04);
201 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
203 /* cheat for now and use the docs */
204 switch(mode_wanted) {
229 hwif->OUTW(speedt, addr);
230 hwif->OUTW(speedp, tfaddr);
231 /* Now set up IORDY */
232 if(mode_wanted == 3 || mode_wanted == 4)
233 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
235 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
239 pci_write_config_word(hwif->pci_dev, addr, speedp);
240 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
241 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
243 /* Set IORDY for mode 3 or 4 */
244 if(mode_wanted == 3 || mode_wanted == 4)
246 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
251 * config_siimage_chipset_for_pio - set drive timings
252 * @drive: drive to tune
255 * Compute the best pio mode we can for a given device. Also honour
256 * the timings for the driver when dealing with mixed devices. Some
257 * of this is ugly but its all wrapped up here
259 * The SI680 can also do VDMA - we need to start using that
261 * FIXME: we use the BIOS channel timings to avoid driving the task
262 * files too fast at the disk. We need to compute the master/slave
263 * drive PIO mode properly so that we can up the speed on a hotplug
267 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
269 u8 channel_timings = siimage_taskfile_timing(HWIF(drive));
270 u8 speed = 0, set_pio = ide_get_best_pio_mode(drive, 4, 5, NULL);
272 /* WARNING PIO timing mess is going to happen b/w devices, argh */
273 if ((channel_timings != set_pio) && (set_pio > channel_timings))
274 set_pio = channel_timings;
276 siimage_tuneproc(drive, set_pio);
277 speed = XFER_PIO_0 + set_pio;
279 (void) ide_config_drive_speed(drive, speed);
282 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
284 config_siimage_chipset_for_pio(drive, set_speed);
288 * siimage_tune_chipset - set controller timings
289 * @drive: Drive to set up
290 * @xferspeed: speed we want to achieve
292 * Tune the SII chipset for the desired mode. If we can't achieve
293 * the desired mode then tune for a lower one, but ultimately
294 * make the thing work.
297 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
299 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
300 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
301 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
303 ide_hwif_t *hwif = HWIF(drive);
304 u16 ultra = 0, multi = 0;
305 u8 mode = 0, unit = drive->select.b.unit;
306 u8 speed = ide_rate_filter(siimage_ratemask(drive), xferspeed);
307 unsigned long base = (unsigned long)hwif->hwif_data;
308 u8 scsc = 0, addr_mask = ((hwif->channel) ?
309 ((hwif->mmio) ? 0xF4 : 0x84) :
310 ((hwif->mmio) ? 0xB4 : 0x80));
312 unsigned long ma = siimage_seldev(drive, 0x08);
313 unsigned long ua = siimage_seldev(drive, 0x0C);
316 scsc = hwif->INB(base + 0x4A);
317 mode = hwif->INB(base + addr_mask);
318 multi = hwif->INW(ma);
319 ultra = hwif->INW(ua);
321 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
322 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
323 pci_read_config_word(hwif->pci_dev, ma, &multi);
324 pci_read_config_word(hwif->pci_dev, ua, &ultra);
327 mode &= ~((unit) ? 0x30 : 0x03);
329 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
331 scsc = is_sata(hwif) ? 1 : scsc;
339 siimage_tuneproc(drive, (speed - XFER_PIO_0));
340 mode |= ((unit) ? 0x10 : 0x01);
345 multi = dma[speed - XFER_MW_DMA_0];
346 mode |= ((unit) ? 0x20 : 0x02);
347 config_siimage_chipset_for_pio(drive, 0);
357 ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
358 (ultra5[speed - XFER_UDMA_0]));
359 mode |= ((unit) ? 0x30 : 0x03);
360 config_siimage_chipset_for_pio(drive, 0);
367 hwif->OUTB(mode, base + addr_mask);
368 hwif->OUTW(multi, ma);
369 hwif->OUTW(ultra, ua);
371 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
372 pci_write_config_word(hwif->pci_dev, ma, multi);
373 pci_write_config_word(hwif->pci_dev, ua, ultra);
375 return (ide_config_drive_speed(drive, speed));
379 * config_chipset_for_dma - configure for DMA
380 * @drive: drive to configure
382 * Called by the IDE layer when it wants the timings set up.
383 * For the CMD680 we also need to set up the PIO timings and
387 static int config_chipset_for_dma (ide_drive_t *drive)
389 u8 speed = ide_dma_speed(drive, siimage_ratemask(drive));
391 config_chipset_for_pio(drive, !speed);
396 if (ide_set_xfer_rate(drive, speed))
399 if (!drive->init_speed)
400 drive->init_speed = speed;
402 return ide_dma_enable(drive);
406 * siimage_configure_drive_for_dma - set up for DMA transfers
407 * @drive: drive we are going to set up
409 * Set up the drive for DMA, tune the controller and drive as
410 * required. If the drive isn't suitable for DMA or we hit
411 * other problems then we will drop down to PIO and set up
415 static int siimage_config_drive_for_dma (ide_drive_t *drive)
417 ide_hwif_t *hwif = HWIF(drive);
418 struct hd_driveid *id = drive->id;
420 if ((id->capability & 1) != 0 && drive->autodma) {
421 /* Consult the list of known "bad" drives */
422 if (__ide_dma_bad_drive(drive))
425 if ((id->field_valid & 4) && siimage_ratemask(drive)) {
426 if (id->dma_ultra & hwif->ultra_mask) {
427 /* Force if Capable UltraDMA */
428 int dma = config_chipset_for_dma(drive);
429 if ((id->field_valid & 2) && !dma)
432 } else if (id->field_valid & 2) {
434 if ((id->dma_mword & hwif->mwdma_mask) ||
435 (id->dma_1word & hwif->swdma_mask)) {
436 /* Force if Capable regular DMA modes */
437 if (!config_chipset_for_dma(drive))
440 } else if (__ide_dma_good_drive(drive) &&
441 (id->eide_dma_time < 150)) {
442 /* Consult the list of known "good" drives */
443 if (!config_chipset_for_dma(drive))
448 return hwif->ide_dma_on(drive);
449 } else if ((id->capability & 8) || (id->field_valid & 2)) {
452 config_chipset_for_pio(drive, 1);
453 return hwif->ide_dma_off_quietly(drive);
455 /* IORDY not supported */
459 /* returns 1 if dma irq issued, 0 otherwise */
460 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
462 ide_hwif_t *hwif = HWIF(drive);
464 unsigned long addr = siimage_selreg(hwif, 1);
466 /* return 1 if INTR asserted */
467 if ((hwif->INB(hwif->dma_status) & 4) == 4)
470 /* return 1 if Device INTR asserted */
471 pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
473 return 0; //return 1;
479 * siimage_mmio_ide_dma_count - DMA bytes done
482 * If we are doing VDMA the CMD680 requires a little bit
483 * of more careful handling and we have to read the counts
484 * off ourselves. For non VDMA life is normal.
487 static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
489 #ifdef SIIMAGE_VIRTUAL_DMAPIO
490 struct request *rq = HWGROUP(drive)->rq;
491 ide_hwif_t *hwif = HWIF(drive);
492 u32 count = (rq->nr_sectors * SECTOR_SIZE);
494 unsigned long addr = siimage_selreg(hwif, 0x1C);
496 hwif->OUTL(count, addr);
497 rcount = hwif->INL(addr);
499 printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
500 drive->name, count, rcount, rq->nr_sectors);
502 #endif /* SIIMAGE_VIRTUAL_DMAPIO */
503 return __ide_dma_count(drive);
508 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
509 * @drive: drive we are testing
511 * Check if we caused an IDE DMA interrupt. We may also have caused
512 * SATA status interrupts, if so we clean them up and continue.
515 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
517 ide_hwif_t *hwif = HWIF(drive);
518 unsigned long base = (unsigned long)hwif->hwif_data;
519 unsigned long addr = siimage_selreg(hwif, 0x1);
521 if (SATA_ERROR_REG) {
522 u32 ext_stat = hwif->INL(base + 0x10);
524 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
525 u32 sata_error = hwif->INL(SATA_ERROR_REG);
526 hwif->OUTL(sata_error, SATA_ERROR_REG);
527 watchdog = (sata_error & 0x00680000) ? 1 : 0;
529 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
530 "watchdog = %d, %s\n",
531 drive->name, sata_error, watchdog,
536 watchdog = (ext_stat & 0x8000) ? 1 : 0;
540 if (!(ext_stat & 0x0404) && !watchdog)
544 /* return 1 if INTR asserted */
545 if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
548 /* return 1 if Device INTR asserted */
549 if ((hwif->INB(addr) & 8) == 8)
550 return 0; //return 1;
555 static int siimage_mmio_ide_dma_verbose (ide_drive_t *drive)
557 int temp = __ide_dma_verbose(drive);
562 * siimage_busproc - bus isolation ioctl
563 * @drive: drive to isolate/restore
564 * @state: bus state to set
566 * Used by the SII3112 to handle bus isolation. As this is a
567 * SATA controller the work required is quite limited, we
568 * just have to clean up the statistics
571 static int siimage_busproc (ide_drive_t * drive, int state)
573 ide_hwif_t *hwif = HWIF(drive);
575 unsigned long addr = siimage_selreg(hwif, 0);
578 stat_config = hwif->INL(addr);
580 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
584 hwif->drives[0].failures = 0;
585 hwif->drives[1].failures = 0;
588 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
589 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
591 case BUSSTATE_TRISTATE:
592 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
593 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
598 hwif->bus_state = state;
603 * siimage_reset_poll - wait for sata reset
604 * @drive: drive we are resetting
606 * Poll the SATA phy and see whether it has come back from the dead
610 static int siimage_reset_poll (ide_drive_t *drive)
612 if (SATA_STATUS_REG) {
613 ide_hwif_t *hwif = HWIF(drive);
615 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
616 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
617 hwif->name, hwif->INL(SATA_STATUS_REG));
618 HWGROUP(drive)->poll_timeout = 0;
628 * siimage_pre_reset - reset hook
629 * @drive: IDE device being reset
631 * For the SATA devices we need to handle recalibration/geometry
635 static void siimage_pre_reset (ide_drive_t *drive)
637 if (drive->media != ide_disk)
640 if (is_sata(HWIF(drive)))
642 drive->special.b.set_geometry = 0;
643 drive->special.b.recalibrate = 0;
648 * siimage_reset - reset a device on an siimage controller
649 * @drive: drive to reset
651 * Perform a controller level reset fo the device. For
652 * SATA we must also check the PHY.
655 static void siimage_reset (ide_drive_t *drive)
657 ide_hwif_t *hwif = HWIF(drive);
659 unsigned long addr = siimage_selreg(hwif, 0);
662 reset = hwif->INB(addr);
663 hwif->OUTB((reset|0x03), addr);
666 hwif->OUTB(reset, addr);
667 (void) hwif->INB(addr);
669 pci_read_config_byte(hwif->pci_dev, addr, &reset);
670 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
672 pci_write_config_byte(hwif->pci_dev, addr, reset);
673 pci_read_config_byte(hwif->pci_dev, addr, &reset);
676 if (SATA_STATUS_REG) {
677 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
678 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
679 hwif->name, sata_stat, __FUNCTION__);
681 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
682 hwif->name, sata_stat);
690 * proc_reports_siimage - add siimage controller to proc
692 * @clocking: SCSC value
693 * @name: controller name
695 * Report the clocking mode of the controller and add it to
696 * the /proc interface layer
699 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
701 if (!pdev_is_sata(dev)) {
702 printk(KERN_INFO "%s: BASE CLOCK ", name);
705 case 0x03: printk("DISABLED!\n"); break;
706 case 0x02: printk("== 2X PCI\n"); break;
707 case 0x01: printk("== 133\n"); break;
708 case 0x00: printk("== 100\n"); break;
714 * setup_mmio_siimage - switch an SI controller into MMIO
715 * @dev: PCI device we are configuring
718 * Attempt to put the device into mmio mode. There are some slight
719 * complications here with certain systems where the mmio bar isnt
720 * mapped so we have to be sure we can fall back to I/O.
723 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
725 unsigned long bar5 = pci_resource_start(dev, 5);
726 unsigned long barsize = pci_resource_len(dev, 5);
732 * Drop back to PIO if we can't map the mmio. Some
733 * systems seem to get terminally confused in the PCI
737 if(!request_mem_region(bar5, barsize, name))
739 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
743 ioaddr = ioremap(bar5, barsize);
747 release_mem_region(bar5, barsize);
752 pci_set_drvdata(dev, ioaddr);
753 addr = (unsigned long) ioaddr;
755 if (pdev_is_sata(dev)) {
756 writel(0, addr + 0x148);
757 writel(0, addr + 0x1C8);
760 writeb(0, addr + 0xB4);
761 writeb(0, addr + 0xF4);
762 tmpbyte = readb(addr + 0x4A);
764 switch(tmpbyte & 0x30) {
766 /* In 100 MHz clocking, try and switch to 133 */
767 writeb(tmpbyte|0x10, addr + 0x4A);
770 /* On 133Mhz clocking */
773 /* On PCIx2 clocking */
776 /* Clocking is disabled */
777 /* 133 clock attempt to force it on */
778 writeb(tmpbyte & ~0x20, addr + 0x4A);
782 writeb( 0x72, addr + 0xA1);
783 writew( 0x328A, addr + 0xA2);
784 writel(0x62DD62DD, addr + 0xA4);
785 writel(0x43924392, addr + 0xA8);
786 writel(0x40094009, addr + 0xAC);
787 writeb( 0x72, addr + 0xE1);
788 writew( 0x328A, addr + 0xE2);
789 writel(0x62DD62DD, addr + 0xE4);
790 writel(0x43924392, addr + 0xE8);
791 writel(0x40094009, addr + 0xEC);
793 if (pdev_is_sata(dev)) {
794 writel(0xFFFF0000, addr + 0x108);
795 writel(0xFFFF0000, addr + 0x188);
796 writel(0x00680000, addr + 0x148);
797 writel(0x00680000, addr + 0x1C8);
800 tmpbyte = readb(addr + 0x4A);
802 proc_reports_siimage(dev, (tmpbyte>>4), name);
807 * init_chipset_siimage - set up an SI device
811 * Perform the initial PCI set up for this device. Attempt to switch
812 * to 133MHz clocking if the system isn't already set up to do it.
815 static unsigned int __init init_chipset_siimage (struct pci_dev *dev, const char *name)
821 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
823 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
825 pci_read_config_byte(dev, 0x8A, &BA5_EN);
826 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
827 if (setup_mmio_siimage(dev, name)) {
832 pci_write_config_byte(dev, 0x80, 0x00);
833 pci_write_config_byte(dev, 0x84, 0x00);
834 pci_read_config_byte(dev, 0x8A, &tmpbyte);
835 switch(tmpbyte & 0x30) {
837 /* 133 clock attempt to force it on */
838 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
840 /* if clocking is disabled */
841 /* 133 clock attempt to force it on */
842 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
847 /* BIOS set PCI x2 clocking */
851 pci_read_config_byte(dev, 0x8A, &tmpbyte);
853 pci_write_config_byte(dev, 0xA1, 0x72);
854 pci_write_config_word(dev, 0xA2, 0x328A);
855 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
856 pci_write_config_dword(dev, 0xA8, 0x43924392);
857 pci_write_config_dword(dev, 0xAC, 0x40094009);
858 pci_write_config_byte(dev, 0xB1, 0x72);
859 pci_write_config_word(dev, 0xB2, 0x328A);
860 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
861 pci_write_config_dword(dev, 0xB8, 0x43924392);
862 pci_write_config_dword(dev, 0xBC, 0x40094009);
864 proc_reports_siimage(dev, (tmpbyte>>4), name);
869 * init_mmio_iops_siimage - set up the iops for MMIO
870 * @hwif: interface to set up
872 * The basic setup here is fairly simple, we can use standard MMIO
873 * operations. However we do have to set the taskfile register offsets
874 * by hand as there isnt a standard defined layout for them this
877 * The hardware supports buffered taskfiles and also some rather nice
878 * extended PRD tables. Unfortunately right now we don't.
881 static void __init init_mmio_iops_siimage (ide_hwif_t *hwif)
883 struct pci_dev *dev = hwif->pci_dev;
884 void *addr = pci_get_drvdata(dev);
885 u8 ch = hwif->channel;
890 * Fill in the basic HWIF bits
893 default_hwif_mmiops(hwif);
894 hwif->hwif_data = addr;
897 * Now set up the hw. We have to do this ourselves as
898 * the MMIO layout isnt the same as the the standard port
902 memset(&hw, 0, sizeof(hw_regs_t));
905 base = (unsigned long)addr;
912 * The buffered task file doesn't have status/control
913 * so we can't currently use it sanely since we want to
917 // hwif->no_lba48 = 1;
919 hw.io_ports[IDE_DATA_OFFSET] = base;
920 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
921 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
922 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
923 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
924 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
925 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
926 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
927 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
929 hw.io_ports[IDE_IRQ_OFFSET] = 0;
931 if (pdev_is_sata(dev)) {
932 base = (unsigned long) addr;
935 hw.sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
936 hw.sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
937 hw.sata_scr[SATA_CONTROL_OFFSET]= base + 0x100;
938 hw.sata_misc[SATA_MISC_OFFSET] = base + 0x140;
939 hw.sata_misc[SATA_PHY_OFFSET] = base + 0x144;
940 hw.sata_misc[SATA_IEN_OFFSET] = base + 0x148;
943 hw.irq = hwif->pci_dev->irq;
945 memcpy(&hwif->hw, &hw, sizeof(hw));
946 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
949 memcpy(hwif->sata_scr, hwif->hw.sata_scr, sizeof(hwif->hw.sata_scr));
950 memcpy(hwif->sata_misc, hwif->hw.sata_misc, sizeof(hwif->hw.sata_misc));
955 base = (unsigned long) addr;
957 #ifdef SIIMAGE_LARGE_DMA
958 /* Watch the brackets - even Ken and Dennis get some language design wrong */
959 hwif->dma_base = base + (ch ? 0x18 : 0x10);
960 hwif->dma_base2 = base + (ch ? 0x08 : 0x00);
961 hwif->dma_prdtable = hwif->dma_base2 + 4;
962 #else /* ! SIIMAGE_LARGE_DMA */
963 hwif->dma_base = base + (ch ? 0x08 : 0x00);
964 hwif->dma_base2 = base + (ch ? 0x18 : 0x10);
965 #endif /* SIIMAGE_LARGE_DMA */
969 static int is_dev_seagate_sata(ide_drive_t *drive)
971 const char *s = &drive->id->model[0];
977 len = strnlen(s, sizeof(drive->id->model));
979 if ((len > 4) && (!memcmp(s, "ST", 2))) {
980 if ((!memcmp(s + len - 2, "AS", 2)) ||
981 (!memcmp(s + len - 3, "ASL", 3))) {
982 printk(KERN_INFO "%s: applying pessimistic Seagate "
983 "errata fix\n", drive->name);
991 * init_iops_siimage - set up iops
992 * @hwif: interface to set up
994 * Do the basic setup for the SIIMAGE hardware interface
995 * and then do the MMIO setup if we can. This is the first
996 * look in we get for setting up the hwif so that we
997 * can get the iops right before using them.
1000 static void __init init_iops_siimage (ide_hwif_t *hwif)
1002 struct pci_dev *dev = hwif->pci_dev;
1005 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1008 hwif->hwif_data = 0;
1011 if (is_sata(hwif) && is_dev_seagate_sata(&hwif->drives[0]))
1014 if (pci_get_drvdata(dev) == NULL)
1016 init_mmio_iops_siimage(hwif);
1020 * ata66_siimage - check for 80 pin cable
1021 * @hwif: interface to check
1023 * Check for the presence of an ATA66 capable cable on the
1027 static unsigned int __init ata66_siimage (ide_hwif_t *hwif)
1029 unsigned long addr = siimage_selreg(hwif, 0);
1030 if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1032 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1033 return (ata66 & 0x01) ? 1 : 0;
1036 return (hwif->INB(addr) & 0x01) ? 1 : 0;
1040 * init_hwif_siimage - set up hwif structs
1041 * @hwif: interface to set up
1043 * We do the basic set up of the interface structure. The SIIMAGE
1044 * requires several custom handlers so we override the default
1045 * ide DMA handlers appropriately
1048 static void __init init_hwif_siimage (ide_hwif_t *hwif)
1052 hwif->resetproc = &siimage_reset;
1053 hwif->speedproc = &siimage_tune_chipset;
1054 hwif->tuneproc = &siimage_tuneproc;
1055 hwif->reset_poll = &siimage_reset_poll;
1056 hwif->pre_reset = &siimage_pre_reset;
1059 hwif->busproc = &siimage_busproc;
1061 if (!hwif->dma_base) {
1062 hwif->drives[0].autotune = 1;
1063 hwif->drives[1].autotune = 1;
1067 hwif->ultra_mask = 0x7f;
1068 hwif->mwdma_mask = 0x07;
1069 hwif->swdma_mask = 0x07;
1072 hwif->atapi_dma = 1;
1074 hwif->ide_dma_check = &siimage_config_drive_for_dma;
1075 if (!(hwif->udma_four))
1076 hwif->udma_four = ata66_siimage(hwif);
1079 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1080 hwif->ide_dma_verbose = &siimage_mmio_ide_dma_verbose;
1082 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1086 * The BIOS often doesn't set up DMA on this controller
1087 * so we always do it.
1091 hwif->drives[0].autodma = hwif->autodma;
1092 hwif->drives[1].autodma = hwif->autodma;
1096 * siimage_init_one - pci layer discovery entry
1098 * @id: ident table entry
1100 * Called by the PCI code when it finds an SI680 or SI3112 controller.
1101 * We then use the IDE PCI generic helper to do most of the work.
1104 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1106 ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1110 static struct pci_device_id siimage_pci_tbl[] = {
1111 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1112 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1113 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1116 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1118 static struct pci_driver driver = {
1120 .id_table = siimage_pci_tbl,
1121 .probe = siimage_init_one,
1124 static int siimage_ide_init(void)
1126 return ide_pci_register_driver(&driver);
1129 module_init(siimage_ide_init);
1131 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1132 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1133 MODULE_LICENSE("GPL");