drivers/ide/pci/sis5513.c

   1 /*
   2  * linux/drivers/ide/pci/sis5513.c      Version 0.16ac+vp       Jun 18, 2003
   3  *
   4  * Copyright (C) 1999-2000      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2002           Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer
   6  * Copyright (C) 2003           Vojtech Pavlik <vojtech@suse.cz>
   7  * May be copied or modified under the terms of the GNU General Public License
   8  *
   9  *
  10  * Thanks :
  11  *
  12  * SiS Taiwan           : for direct support and hardware.
  13  * Daniela Engert       : for initial ATA100 advices and numerous others.
  14  * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt        :
  15  *                        for checking code correctness, providing patches.
  16  *
  17  *
  18  * Original tests and design on the SiS620 chipset.
  19  * ATA100 tests and design on the SiS735 chipset.
  20  * ATA16/33 support from specs
  21  * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw>
  22  * ATA133 961/962/963 fixes by Vojtech Pavlik <vojtech@suse.cz>
  23  *
  24  * Documentation:
  25  *      SiS chipset documentation available under NDA to companies only
  26  *      (not to individuals).
  27  */
  28
  29 /*
  30  * The original SiS5513 comes from a SiS5511/55112/5513 chipset. The original
  31  * SiS5513 was also used in the SiS5596/5513 chipset. Thus if we see a SiS5511
  32  * or SiS5596, we can assume we see the first MWDMA-16 capable SiS5513 chip.
  33  *
  34  * Later SiS chipsets integrated the 5513 functionality into the NorthBridge,
  35  * starting with SiS5571 and up to SiS745. The PCI ID didn't change, though. We
  36  * can figure out that we have a more modern and more capable 5513 by looking
  37  * for the respective NorthBridge IDs.
  38  *
  39  * Even later (96x family) SiS chipsets use the MuTIOL link and place the 5513
  40  * into the SouthBrige. Here we cannot rely on looking up the NorthBridge PCI
  41  * ID, while the now ATA-133 capable 5513 still has the same PCI ID.
  42  * Fortunately the 5513 can be 'unmasked' by fiddling with some config space
  43  * bits, changing its device id to the true one - 5517 for 961 and 5518 for
  44  * 962/963.
  45  */
  46
  47 #include <linux/config.h>
  48 #include <linux/types.h>
  49 #include <linux/module.h>
  50 #include <linux/kernel.h>
  51 #include <linux/delay.h>
  52 #include <linux/timer.h>
  53 #include <linux/mm.h>
  54 #include <linux/ioport.h>
  55 #include <linux/blkdev.h>
  56 #include <linux/hdreg.h>
  57
  58 #include <linux/interrupt.h>
  59 #include <linux/pci.h>
  60 #include <linux/init.h>
  61 #include <linux/ide.h>
  62
  63 #include <asm/irq.h>
  64
  65 #include "ide-timing.h"
  66 #include "sis5513.h"
  67
  68 /* registers layout and init values are chipset family dependant */
  69
  70 #define ATA_16          0x01
  71 #define ATA_33          0x02
  72 #define ATA_66          0x03
  73 #define ATA_100a        0x04 // SiS730/SiS550 is ATA100 with ATA66 layout
  74 #define ATA_100         0x05
  75 #define ATA_133a        0x06 // SiS961b with 133 support
  76 #define ATA_133         0x07 // SiS962/963
  77
  78 static u8 chipset_family;
  79
  80 /*
  81  * Devices supported
  82  */
  83 static const struct {
  84         const char *name;
  85         u16 host_id;
  86         u8 chipset_family;
  87         u8 flags;
  88 } SiSHostChipInfo[] = {
  89         { "SiS745",     PCI_DEVICE_ID_SI_745,   ATA_100  },
  90         { "SiS735",     PCI_DEVICE_ID_SI_735,   ATA_100  },
  91         { "SiS733",     PCI_DEVICE_ID_SI_733,   ATA_100  },
  92         { "SiS635",     PCI_DEVICE_ID_SI_635,   ATA_100  },
  93         { "SiS633",     PCI_DEVICE_ID_SI_633,   ATA_100  },
  94
  95         { "SiS730",     PCI_DEVICE_ID_SI_730,   ATA_100a },
  96         { "SiS550",     PCI_DEVICE_ID_SI_550,   ATA_100a },
  97
  98         { "SiS640",     PCI_DEVICE_ID_SI_640,   ATA_66   },
  99         { "SiS630",     PCI_DEVICE_ID_SI_630,   ATA_66   },
 100         { "SiS620",     PCI_DEVICE_ID_SI_620,   ATA_66   },
 101         { "SiS540",     PCI_DEVICE_ID_SI_540,   ATA_66   },
 102         { "SiS530",     PCI_DEVICE_ID_SI_530,   ATA_66   },
 103
 104         { "SiS5600",    PCI_DEVICE_ID_SI_5600,  ATA_33   },
 105         { "SiS5598",    PCI_DEVICE_ID_SI_5598,  ATA_33   },
 106         { "SiS5597",    PCI_DEVICE_ID_SI_5597,  ATA_33   },
 107         { "SiS5591/2",  PCI_DEVICE_ID_SI_5591,  ATA_33   },
 108         { "SiS5582",    PCI_DEVICE_ID_SI_5582,  ATA_33   },
 109         { "SiS5581",    PCI_DEVICE_ID_SI_5581,  ATA_33   },
 110
 111         { "SiS5596",    PCI_DEVICE_ID_SI_5596,  ATA_16   },
 112         { "SiS5571",    PCI_DEVICE_ID_SI_5571,  ATA_16   },
 113         { "SiS551x",    PCI_DEVICE_ID_SI_5511,  ATA_16   },
 114 };
 115
 116 /* Cycle time bits and values vary across chip dma capabilities
 117    These three arrays hold the register layout and the values to set.
 118    Indexed by chipset_family and (dma_mode - XFER_UDMA_0) */
 119
 120 /* {0, ATA_16, ATA_33, ATA_66, ATA_100a, ATA_100, ATA_133} */
 121 static u8 cycle_time_offset[] = {0,0,5,4,4,0,0};
 122 static u8 cycle_time_range[] = {0,0,2,3,3,4,4};
 123 static u8 cycle_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 124         {0,0,0,0,0,0,0}, /* no udma */
 125         {0,0,0,0,0,0,0}, /* no udma */
 126         {3,2,1,0,0,0,0}, /* ATA_33 */
 127         {7,5,3,2,1,0,0}, /* ATA_66 */
 128         {7,5,3,2,1,0,0}, /* ATA_100a (730 specific), differences are on cycle_time range and offset */
 129         {11,7,5,4,2,1,0}, /* ATA_100 */
 130         {15,10,7,5,3,2,1}, /* ATA_133a (earliest 691 southbridges) */
 131         {15,10,7,5,3,2,1}, /* ATA_133 */
 132 };
 133 /* CRC Valid Setup Time vary across IDE clock setting 33/66/100/133
 134    See SiS962 data sheet for more detail */
 135 static u8 cvs_time_value[][XFER_UDMA_6 - XFER_UDMA_0 + 1] = {
 136         {0,0,0,0,0,0,0}, /* no udma */
 137         {0,0,0,0,0,0,0}, /* no udma */
 138         {2,1,1,0,0,0,0},
 139         {4,3,2,1,0,0,0},
 140         {4,3,2,1,0,0,0},
 141         {6,4,3,1,1,1,0},
 142         {9,6,4,2,2,2,2},
 143         {9,6,4,2,2,2,2},
 144 };
 145 /* Initialize time, Active time, Recovery time vary across
 146    IDE clock settings. These 3 arrays hold the register value
 147    for PIO0/1/2/3/4 and DMA0/1/2 mode in order */
 148 static u8 ini_time_value[][8] = {
 149         {0,0,0,0,0,0,0,0},
 150         {0,0,0,0,0,0,0,0},
 151         {2,1,0,0,0,1,0,0},
 152         {4,3,1,1,1,3,1,1},
 153         {4,3,1,1,1,3,1,1},
 154         {6,4,2,2,2,4,2,2},
 155         {9,6,3,3,3,6,3,3},
 156         {9,6,3,3,3,6,3,3},
 157 };
 158 static u8 act_time_value[][8] = {
 159         {0,0,0,0,0,0,0,0},
 160         {0,0,0,0,0,0,0,0},
 161         {9,9,9,2,2,7,2,2},
 162         {19,19,19,5,4,14,5,4},
 163         {19,19,19,5,4,14,5,4},
 164         {28,28,28,7,6,21,7,6},
 165         {38,38,38,10,9,28,10,9},
 166         {38,38,38,10,9,28,10,9},
 167 };
 168 static u8 rco_time_value[][8] = {
 169         {0,0,0,0,0,0,0,0},
 170         {0,0,0,0,0,0,0,0},
 171         {9,2,0,2,0,7,1,1},
 172         {19,5,1,5,2,16,3,2},
 173         {19,5,1,5,2,16,3,2},
 174         {30,9,3,9,4,25,6,4},
 175         {40,12,4,12,5,34,12,5},
 176         {40,12,4,12,5,34,12,5},
 177 };
 178
 179 /*
 180  * Printing configuration
 181  */
 182 /* Used for chipset type printing at boot time */
 183 static char* chipset_capability[] = {
 184         "ATA", "ATA 16",
 185         "ATA 33", "ATA 66",
 186         "ATA 100 (1st gen)", "ATA 100 (2nd gen)",
 187         "ATA 133 (1st gen)", "ATA 133 (2nd gen)"
 188 };
 189
 190 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
 191 #include <linux/stat.h>
 192 #include <linux/proc_fs.h>
 193
 194 static u8 sis_proc = 0;
 195
 196 static struct pci_dev *bmide_dev;
 197
 198 static char* cable_type[] = {
 199         "80 pins",
 200         "40 pins"
 201 };
 202
 203 static char* recovery_time[] ={
 204         "12 PCICLK", "1 PCICLK",
 205         "2 PCICLK", "3 PCICLK",
 206         "4 PCICLK", "5 PCICLCK",
 207         "6 PCICLK", "7 PCICLCK",
 208         "8 PCICLK", "9 PCICLCK",
 209         "10 PCICLK", "11 PCICLK",
 210         "13 PCICLK", "14 PCICLK",
 211         "15 PCICLK", "15 PCICLK"
 212 };
 213
 214 static char* active_time[] = {
 215         "8 PCICLK", "1 PCICLCK",
 216         "2 PCICLK", "3 PCICLK",
 217         "4 PCICLK", "5 PCICLK",
 218         "6 PCICLK", "12 PCICLK"
 219 };
 220
 221 static char* cycle_time[] = {
 222         "Reserved", "2 CLK",
 223         "3 CLK", "4 CLK",
 224         "5 CLK", "6 CLK",
 225         "7 CLK", "8 CLK",
 226         "9 CLK", "10 CLK",
 227         "11 CLK", "12 CLK",
 228         "13 CLK", "14 CLK",
 229         "15 CLK", "16 CLK"
 230 };
 231
 232 /* Generic add master or slave info function */
 233 static char* get_drives_info (char *buffer, u8 pos)
 234 {
 235         u8 reg00, reg01, reg10, reg11; /* timing registers */
 236         u32 regdw0, regdw1;
 237         char* p = buffer;
 238
 239 /* Postwrite/Prefetch */
 240         if (chipset_family < ATA_133) {
 241                 pci_read_config_byte(bmide_dev, 0x4b, &reg00);
 242                 p += sprintf(p, "Drive %d:        Postwrite %s \t \t Postwrite %s\n",
 243                              pos, (reg00 & (0x10 << pos)) ? "Enabled" : "Disabled",
 244                              (reg00 & (0x40 << pos)) ? "Enabled" : "Disabled");
 245                 p += sprintf(p, "                Prefetch  %s \t \t Prefetch  %s\n",
 246                              (reg00 & (0x01 << pos)) ? "Enabled" : "Disabled",
 247                              (reg00 & (0x04 << pos)) ? "Enabled" : "Disabled");
 248                 pci_read_config_byte(bmide_dev, 0x40+2*pos, &reg00);
 249                 pci_read_config_byte(bmide_dev, 0x41+2*pos, &reg01);
 250                 pci_read_config_byte(bmide_dev, 0x44+2*pos, &reg10);
 251                 pci_read_config_byte(bmide_dev, 0x45+2*pos, &reg11);
 252         } else {
 253                 u32 reg54h;
 254                 u8 drive_pci = 0x40;
 255                 pci_read_config_dword(bmide_dev, 0x54, &reg54h);
 256                 if (reg54h & 0x40000000) {
 257                         // Configuration space remapped to 0x70
 258                         drive_pci = 0x70;
 259                 }
 260                 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos, &regdw0);
 261                 pci_read_config_dword(bmide_dev, (unsigned long)drive_pci+4*pos+8, &regdw1);
 262
 263                 p += sprintf(p, "Drive %d:\n", pos);
 264         }
 265
 266
 267 /* UDMA */
 268         if (chipset_family >= ATA_133) {
 269                 p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
 270                              (regdw0 & 0x04) ? "Enabled" : "Disabled",
 271                              (regdw1 & 0x04) ? "Enabled" : "Disabled");
 272                 p += sprintf(p, "                UDMA Cycle Time    %s \t UDMA Cycle Time    %s\n",
 273                              cycle_time[(regdw0 & 0xF0) >> 4],
 274                              cycle_time[(regdw1 & 0xF0) >> 4]);
 275         } else if (chipset_family >= ATA_33) {
 276                 p += sprintf(p, "                UDMA %s \t \t \t UDMA %s\n",
 277                              (reg01 & 0x80) ? "Enabled" : "Disabled",
 278                              (reg11 & 0x80) ? "Enabled" : "Disabled");
 279
 280                 p += sprintf(p, "                UDMA Cycle Time    ");
 281                 switch(chipset_family) {
 282                         case ATA_33:    p += sprintf(p, cycle_time[(reg01 & 0x60) >> 5]); break;
 283                         case ATA_66:
 284                         case ATA_100a:  p += sprintf(p, cycle_time[(reg01 & 0x70) >> 4]); break;
 285                         case ATA_100:
 286                         case ATA_133a:  p += sprintf(p, cycle_time[reg01 & 0x0F]); break;
 287                         default:        p += sprintf(p, "?"); break;
 288                 }
 289                 p += sprintf(p, " \t UDMA Cycle Time    ");
 290                 switch(chipset_family) {
 291                         case ATA_33:    p += sprintf(p, cycle_time[(reg11 & 0x60) >> 5]); break;
 292                         case ATA_66:
 293                         case ATA_100a:  p += sprintf(p, cycle_time[(reg11 & 0x70) >> 4]); break;
 294                         case ATA_100:
 295                         case ATA_133a:  p += sprintf(p, cycle_time[reg11 & 0x0F]); break;
 296                         default:        p += sprintf(p, "?"); break;
 297                 }
 298                 p += sprintf(p, "\n");
 299         }
 300
 301
 302         if (chipset_family < ATA_133) { /* else case TODO */
 303
 304 /* Data Active */
 305                 p += sprintf(p, "                Data Active Time   ");
 306                 switch(chipset_family) {
 307                         case ATA_16: /* confirmed */
 308                         case ATA_33:
 309                         case ATA_66:
 310                         case ATA_100a: p += sprintf(p, active_time[reg01 & 0x07]); break;
 311                         case ATA_100:
 312                         case ATA_133a: p += sprintf(p, active_time[(reg00 & 0x70) >> 4]); break;
 313                         default: p += sprintf(p, "?"); break;
 314                 }
 315                 p += sprintf(p, " \t Data Active Time   ");
 316                 switch(chipset_family) {
 317                         case ATA_16:
 318                         case ATA_33:
 319                         case ATA_66:
 320                         case ATA_100a: p += sprintf(p, active_time[reg11 & 0x07]); break;
 321                         case ATA_100:
 322                         case ATA_133a: p += sprintf(p, active_time[(reg10 & 0x70) >> 4]); break;
 323                         default: p += sprintf(p, "?"); break;
 324                 }
 325                 p += sprintf(p, "\n");
 326
 327 /* Data Recovery */
 328         /* warning: may need (reg&0x07) for pre ATA66 chips */
 329                 p += sprintf(p, "                Data Recovery Time %s \t Data Recovery Time %s\n",
 330                              recovery_time[reg00 & 0x0f], recovery_time[reg10 & 0x0f]);
 331         }
 332
 333         return p;
 334 }
 335
 336 static char* get_masters_info(char* buffer)
 337 {
 338         return get_drives_info(buffer, 0);
 339 }
 340
 341 static char* get_slaves_info(char* buffer)
 342 {
 343         return get_drives_info(buffer, 1);
 344 }
 345
 346 /* Main get_info, called on /proc/ide/sis reads */
 347 static int sis_get_info (char *buffer, char **addr, off_t offset, int count)
 348 {
 349         char *p = buffer;
 350         int len;
 351         u8 reg;
 352         u16 reg2, reg3;
 353
 354         p += sprintf(p, "\nSiS 5513 ");
 355         switch(chipset_family) {
 356                 case ATA_16: p += sprintf(p, "DMA 16"); break;
 357                 case ATA_33: p += sprintf(p, "Ultra 33"); break;
 358                 case ATA_66: p += sprintf(p, "Ultra 66"); break;
 359                 case ATA_100a:
 360                 case ATA_100: p += sprintf(p, "Ultra 100"); break;
 361                 case ATA_133a:
 362                 case ATA_133: p += sprintf(p, "Ultra 133"); break;
 363                 default: p+= sprintf(p, "Unknown???"); break;
 364         }
 365         p += sprintf(p, " chipset\n");
 366         p += sprintf(p, "--------------- Primary Channel "
 367                      "---------------- Secondary Channel "
 368                      "-------------\n");
 369
 370 /* Status */
 371         pci_read_config_byte(bmide_dev, 0x4a, &reg);
 372         if (chipset_family == ATA_133) {
 373                 pci_read_config_word(bmide_dev, 0x50, &reg2);
 374                 pci_read_config_word(bmide_dev, 0x52, &reg3);
 375         }
 376         p += sprintf(p, "Channel Status: ");
 377         if (chipset_family < ATA_66) {
 378                 p += sprintf(p, "%s \t \t \t \t %s\n",
 379                              (reg & 0x04) ? "On" : "Off",
 380                              (reg & 0x02) ? "On" : "Off");
 381         } else if (chipset_family < ATA_133) {
 382                 p += sprintf(p, "%s \t \t \t \t %s \n",
 383                              (reg & 0x02) ? "On" : "Off",
 384                              (reg & 0x04) ? "On" : "Off");
 385         } else { /* ATA_133 */
 386                 p += sprintf(p, "%s \t \t \t \t %s \n",
 387                              (reg2 & 0x02) ? "On" : "Off",
 388                              (reg3 & 0x02) ? "On" : "Off");
 389         }
 390
 391 /* Operation Mode */
 392         pci_read_config_byte(bmide_dev, 0x09, &reg);
 393         p += sprintf(p, "Operation Mode: %s \t \t \t %s \n",
 394                      (reg & 0x01) ? "Native" : "Compatible",
 395                      (reg & 0x04) ? "Native" : "Compatible");
 396
 397 /* 80-pin cable ? */
 398         if (chipset_family >= ATA_133) {
 399                 p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
 400                              (reg2 & 0x01) ? cable_type[1] : cable_type[0],
 401                              (reg3 & 0x01) ? cable_type[1] : cable_type[0]);
 402         } else if (chipset_family > ATA_33) {
 403                 pci_read_config_byte(bmide_dev, 0x48, &reg);
 404                 p += sprintf(p, "Cable Type:     %s \t \t \t %s\n",
 405                              (reg & 0x10) ? cable_type[1] : cable_type[0],
 406                              (reg & 0x20) ? cable_type[1] : cable_type[0]);
 407         }
 408
 409 /* Prefetch Count */
 410         if (chipset_family < ATA_133) {
 411                 pci_read_config_word(bmide_dev, 0x4c, &reg2);
 412                 pci_read_config_word(bmide_dev, 0x4e, &reg3);
 413                 p += sprintf(p, "Prefetch Count: %d \t \t \t \t %d\n",
 414                              reg2, reg3);
 415         }
 416
 417         p = get_masters_info(p);
 418         p = get_slaves_info(p);
 419
 420         len = (p - buffer) - offset;
 421         *addr = buffer + offset;
 422
 423         return len > count ? count : len;
 424 }
 425 #endif /* defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS) */
 426
 427 static u8 sis5513_ratemask (ide_drive_t *drive)
 428 {
 429         u8 rates[] = { 0, 0, 1, 2, 3, 3, 4, 4 };
 430         u8 mode = rates[chipset_family];
 431
 432         if (!eighty_ninty_three(drive))
 433                 mode = min(mode, (u8)1);
 434         return mode;
 435 }
 436
 437 /*
 438  * Configuration functions
 439  */
 440 /* Enables per-drive prefetch and postwrite */
 441 static void config_drive_art_rwp (ide_drive_t *drive)
 442 {
 443         ide_hwif_t *hwif        = HWIF(drive);
 444         struct pci_dev *dev     = hwif->pci_dev;
 445
 446         u8 reg4bh               = 0;
 447         u8 rw_prefetch          = (0x11 << drive->dn);
 448
 449         if (drive->media != ide_disk)
 450                 return;
 451         pci_read_config_byte(dev, 0x4b, &reg4bh);
 452
 453         if ((reg4bh & rw_prefetch) != rw_prefetch)
 454                 pci_write_config_byte(dev, 0x4b, reg4bh|rw_prefetch);
 455 }
 456
 457
 458 /* Set per-drive active and recovery time */
 459 static void config_art_rwp_pio (ide_drive_t *drive, u8 pio)
 460 {
 461         ide_hwif_t *hwif        = HWIF(drive);
 462         struct pci_dev *dev     = hwif->pci_dev;
 463
 464         u8                      timing, drive_pci, test1, test2;
 465
 466         u16 eide_pio_timing[6] = {600, 390, 240, 180, 120, 90};
 467         u16 xfer_pio = drive->id->eide_pio_modes;
 468
 469         config_drive_art_rwp(drive);
 470         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 471
 472         if (xfer_pio> 4)
 473                 xfer_pio = 0;
 474
 475         if (drive->id->eide_pio_iordy > 0) {
 476                 for (xfer_pio = 5;
 477                         (xfer_pio > 0) &&
 478                         (drive->id->eide_pio_iordy > eide_pio_timing[xfer_pio]);
 479                         xfer_pio--);
 480         } else {
 481                 xfer_pio = (drive->id->eide_pio_modes & 4) ? 0x05 :
 482                            (drive->id->eide_pio_modes & 2) ? 0x04 :
 483                            (drive->id->eide_pio_modes & 1) ? 0x03 : xfer_pio;
 484         }
 485
 486         timing = (xfer_pio >= pio) ? xfer_pio : pio;
 487
 488         /* In pre ATA_133 case, drives sit at 0x40 + 4*drive->dn */
 489         drive_pci = 0x40;
 490         /* In SiS962 case drives sit at (0x40 or 0x70) + 8*drive->dn) */
 491         if (chipset_family >= ATA_133) {
 492                 u32 reg54h;
 493                 pci_read_config_dword(dev, 0x54, &reg54h);
 494                 if (reg54h & 0x40000000) drive_pci = 0x70;
 495                 drive_pci += ((drive->dn)*0x4);
 496         } else {
 497                 drive_pci += ((drive->dn)*0x2);
 498         }
 499
 500         /* register layout changed with newer ATA100 chips */
 501         if (chipset_family < ATA_100) {
 502                 pci_read_config_byte(dev, drive_pci, &test1);
 503                 pci_read_config_byte(dev, drive_pci+1, &test2);
 504
 505                 /* Clear active and recovery timings */
 506                 test1 &= ~0x0F;
 507                 test2 &= ~0x07;
 508
 509                 switch(timing) {
 510                         case 4:         test1 |= 0x01; test2 |= 0x03; break;
 511                         case 3:         test1 |= 0x03; test2 |= 0x03; break;
 512                         case 2:         test1 |= 0x04; test2 |= 0x04; break;
 513                         case 1:         test1 |= 0x07; test2 |= 0x06; break;
 514                         default:        break;
 515                 }
 516                 pci_write_config_byte(dev, drive_pci, test1);
 517                 pci_write_config_byte(dev, drive_pci+1, test2);
 518         } else if (chipset_family < ATA_133) {
 519                 switch(timing) { /*             active  recovery
 520                                                   v     v */
 521                         case 4:         test1 = 0x30|0x01; break;
 522                         case 3:         test1 = 0x30|0x03; break;
 523                         case 2:         test1 = 0x40|0x04; break;
 524                         case 1:         test1 = 0x60|0x07; break;
 525                         default:        break;
 526                 }
 527                 pci_write_config_byte(dev, drive_pci, test1);
 528         } else { /* ATA_133 */
 529                 u32 test3;
 530                 pci_read_config_dword(dev, drive_pci, &test3);
 531                 test3 &= 0xc0c00fff;
 532                 if (test3 & 0x08) {
 533                         test3 |= (unsigned long)ini_time_value[ATA_133][timing] << 12;
 534                         test3 |= (unsigned long)act_time_value[ATA_133][timing] << 16;
 535                         test3 |= (unsigned long)rco_time_value[ATA_133][timing] << 24;
 536                 } else {
 537                         test3 |= (unsigned long)ini_time_value[ATA_100][timing] << 12;
 538                         test3 |= (unsigned long)act_time_value[ATA_100][timing] << 16;
 539                         test3 |= (unsigned long)rco_time_value[ATA_100][timing] << 24;
 540                 }
 541                 pci_write_config_dword(dev, drive_pci, test3);
 542         }
 543 }
 544
 545 static int config_chipset_for_pio (ide_drive_t *drive, u8 pio)
 546 {
 547         if (pio == 255)
 548                 pio = ide_find_best_mode(drive, XFER_PIO | XFER_EPIO) - XFER_PIO_0;
 549         config_art_rwp_pio(drive, pio);
 550         return ide_config_drive_speed(drive, XFER_PIO_0 + min_t(u8, pio, 4));
 551 }
 552
 553 static int sis5513_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 554 {
 555         ide_hwif_t *hwif        = HWIF(drive);
 556         struct pci_dev *dev     = hwif->pci_dev;
 557
 558         u8 drive_pci, reg, speed;
 559         u32 regdw;
 560
 561         speed = ide_rate_filter(sis5513_ratemask(drive), xferspeed);
 562
 563         /* See config_art_rwp_pio for drive pci config registers */
 564         drive_pci = 0x40;
 565         if (chipset_family >= ATA_133) {
 566                 u32 reg54h;
 567                 pci_read_config_dword(dev, 0x54, &reg54h);
 568                 if (reg54h & 0x40000000) drive_pci = 0x70;
 569                 drive_pci += ((drive->dn)*0x4);
 570                 pci_read_config_dword(dev, (unsigned long)drive_pci, &regdw);
 571                 /* Disable UDMA bit for non UDMA modes on UDMA chips */
 572                 if (speed < XFER_UDMA_0) {
 573                         regdw &= 0xfffffffb;
 574                         pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 575                 }
 576
 577         } else {
 578                 drive_pci += ((drive->dn)*0x2);
 579                 pci_read_config_byte(dev, drive_pci+1, &reg);
 580                 /* Disable UDMA bit for non UDMA modes on UDMA chips */
 581                 if ((speed < XFER_UDMA_0) && (chipset_family > ATA_16)) {
 582                         reg &= 0x7F;
 583                         pci_write_config_byte(dev, drive_pci+1, reg);
 584                 }
 585         }
 586
 587         /* Config chip for mode */
 588         switch(speed) {
 589                 case XFER_UDMA_6:
 590                 case XFER_UDMA_5:
 591                 case XFER_UDMA_4:
 592                 case XFER_UDMA_3:
 593                 case XFER_UDMA_2:
 594                 case XFER_UDMA_1:
 595                 case XFER_UDMA_0:
 596                         if (chipset_family >= ATA_133) {
 597                                 regdw |= 0x04;
 598                                 regdw &= 0xfffff00f;
 599                                 /* check if ATA133 enable */
 600                                 if (regdw & 0x08) {
 601                                         regdw |= (unsigned long)cycle_time_value[ATA_133][speed-XFER_UDMA_0] << 4;
 602                                         regdw |= (unsigned long)cvs_time_value[ATA_133][speed-XFER_UDMA_0] << 8;
 603                                 } else {
 604                                 /* if ATA133 disable, we should not set speed above UDMA5 */
 605                                         if (speed > XFER_UDMA_5)
 606                                                 speed = XFER_UDMA_5;
 607                                         regdw |= (unsigned long)cycle_time_value[ATA_100][speed-XFER_UDMA_0] << 4;
 608                                         regdw |= (unsigned long)cvs_time_value[ATA_100][speed-XFER_UDMA_0] << 8;
 609                                 }
 610                                 pci_write_config_dword(dev, (unsigned long)drive_pci, regdw);
 611                         } else {
 612                                 /* Force the UDMA bit on if we want to use UDMA */
 613                                 reg |= 0x80;
 614                                 /* clean reg cycle time bits */
 615                                 reg &= ~((0xFF >> (8 - cycle_time_range[chipset_family]))
 616                                          << cycle_time_offset[chipset_family]);
 617                                 /* set reg cycle time bits */
 618                                 reg |= cycle_time_value[chipset_family][speed-XFER_UDMA_0]
 619                                         << cycle_time_offset[chipset_family];
 620                                 pci_write_config_byte(dev, drive_pci+1, reg);
 621                         }
 622                         break;
 623                 case XFER_MW_DMA_2:
 624                 case XFER_MW_DMA_1:
 625                 case XFER_MW_DMA_0:
 626                 case XFER_SW_DMA_2:
 627                 case XFER_SW_DMA_1:
 628                 case XFER_SW_DMA_0:
 629                         break;
 630                 case XFER_PIO_4: return((int) config_chipset_for_pio(drive, 4));
 631                 case XFER_PIO_3: return((int) config_chipset_for_pio(drive, 3));
 632                 case XFER_PIO_2: return((int) config_chipset_for_pio(drive, 2));
 633                 case XFER_PIO_1: return((int) config_chipset_for_pio(drive, 1));
 634                 case XFER_PIO_0:
 635                 default:         return((int) config_chipset_for_pio(drive, 0));
 636         }
 637
 638         return ((int) ide_config_drive_speed(drive, speed));
 639 }
 640
 641 static void sis5513_tune_drive (ide_drive_t *drive, u8 pio)
 642 {
 643         (void) config_chipset_for_pio(drive, pio);
 644 }
 645
 646 /*
 647  * ((id->hw_config & 0x4000|0x2000) && (HWIF(drive)->udma_four))
 648  */
 649 static int config_chipset_for_dma (ide_drive_t *drive)
 650 {
 651         u8 speed        = ide_dma_speed(drive, sis5513_ratemask(drive));
 652
 653 #ifdef DEBUG
 654         printk("SIS5513: config_chipset_for_dma, drive %d, ultra %x\n",
 655                drive->dn, drive->id->dma_ultra);
 656 #endif
 657
 658         if (!(speed))
 659                 return 0;
 660
 661         sis5513_tune_chipset(drive, speed);
 662         return ide_dma_enable(drive);
 663 }
 664
 665 static int sis5513_config_drive_xfer_rate (ide_drive_t *drive)
 666 {
 667         ide_hwif_t *hwif        = HWIF(drive);
 668         struct hd_driveid *id   = drive->id;
 669
 670         drive->init_speed = 0;
 671
 672         if (id && (id->capability & 1) && drive->autodma) {
 673                 /* Consult the list of known "bad" drives */
 674                 if (__ide_dma_bad_drive(drive))
 675                         goto fast_ata_pio;
 676                 if (id->field_valid & 4) {
 677                         if (id->dma_ultra & hwif->ultra_mask) {
 678                                 /* Force if Capable UltraDMA */
 679                                 int dma = config_chipset_for_dma(drive);
 680                                 if ((id->field_valid & 2) && !dma)
 681                                         goto try_dma_modes;
 682                         }
 683                 } else if (id->field_valid & 2) {
 684 try_dma_modes:
 685                         if ((id->dma_mword & hwif->mwdma_mask) ||
 686                             (id->dma_1word & hwif->swdma_mask)) {
 687                                 /* Force if Capable regular DMA modes */
 688                                 if (!config_chipset_for_dma(drive))
 689                                         goto no_dma_set;
 690                         }
 691                 } else if (__ide_dma_good_drive(drive) &&
 692                            (id->eide_dma_time < 150)) {
 693                         /* Consult the list of known "good" drives */
 694                         if (!config_chipset_for_dma(drive))
 695                                 goto no_dma_set;
 696                 } else {
 697                         goto fast_ata_pio;
 698                 }
 699                 return hwif->ide_dma_on(drive);
 700         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 701 fast_ata_pio:
 702 no_dma_set:
 703                 sis5513_tune_drive(drive, 5);
 704                 return hwif->ide_dma_off_quietly(drive);
 705         }
 706         /* IORDY not supported */
 707         return 0;
 708 }
 709
 710 /* initiates/aborts (U)DMA read/write operations on a drive. */
 711 static int sis5513_config_xfer_rate (ide_drive_t *drive)
 712 {
 713         config_drive_art_rwp(drive);
 714         config_art_rwp_pio(drive, 5);
 715         return sis5513_config_drive_xfer_rate(drive);
 716 }
 717
 718 /*
 719   Future simpler config_xfer_rate :
 720    When ide_find_best_mode is made bad-drive aware
 721    - remove config_drive_xfer_rate and config_chipset_for_dma,
 722    - replace config_xfer_rate with the following
 723
 724 static int sis5513_config_xfer_rate (ide_drive_t *drive)
 725 {
 726         u16 w80 = HWIF(drive)->udma_four;
 727         u16 speed;
 728
 729         config_drive_art_rwp(drive);
 730         config_art_rwp_pio(drive, 5);
 731
 732         speed = ide_find_best_mode(drive,
 733                 XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
 734                 (chipset_family >= ATA_33 ? XFER_UDMA : 0) |
 735                 (w80 && chipset_family >= ATA_66 ? XFER_UDMA_66 : 0) |
 736                 (w80 && chipset_family >= ATA_100a ? XFER_UDMA_100 : 0) |
 737                 (w80 && chipset_family >= ATA_133a ? XFER_UDMA_133 : 0));
 738
 739         sis5513_tune_chipset(drive, speed);
 740
 741         if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
 742                 return HWIF(drive)->ide_dma_on(drive);
 743         return HWIF(drive)->ide_dma_off_quietly(drive);
 744 }
 745 */
 746
 747 /* Chip detection and general config */
 748 static unsigned int __init init_chipset_sis5513 (struct pci_dev *dev, const char *name)
 749 {
 750         struct pci_dev *host;
 751         int i = 0;
 752
 753         chipset_family = 0;
 754
 755         for (i = 0; i < ARRAY_SIZE(SiSHostChipInfo) && !chipset_family; i++) {
 756
 757                 host = pci_find_device(PCI_VENDOR_ID_SI, SiSHostChipInfo[i].host_id, NULL);
 758
 759                 if (!host)
 760                         continue;
 761
 762                 chipset_family = SiSHostChipInfo[i].chipset_family;
 763
 764                 /* Special case for SiS630 : 630S/ET is ATA_100a */
 765                 if (SiSHostChipInfo[i].host_id == PCI_DEVICE_ID_SI_630) {
 766                         u8 hostrev;
 767                         pci_read_config_byte(host, PCI_REVISION_ID, &hostrev);
 768                         if (hostrev >= 0x30)
 769                                 chipset_family = ATA_100a;
 770                 }
 771
 772                 printk(KERN_INFO "SIS5513: %s %s controller\n",
 773                          SiSHostChipInfo[i].name, chipset_capability[chipset_family]);
 774         }
 775
 776         if (!chipset_family) { /* Belongs to pci-quirks */
 777
 778                         u32 idemisc;
 779                         u16 trueid;
 780
 781                         /* Disable ID masking and register remapping */
 782                         pci_read_config_dword(dev, 0x54, &idemisc);
 783                         pci_write_config_dword(dev, 0x54, (idemisc & 0x7fffffff));
 784                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 785                         pci_write_config_dword(dev, 0x54, idemisc);
 786
 787                         if (trueid == 0x5518) {
 788                                 printk(KERN_INFO "SIS5513: SiS 962/963 MuTIOL IDE UDMA133 controller\n");
 789                                 chipset_family = ATA_133;
 790                         }
 791         }
 792
 793         if (!chipset_family) { /* Belongs to pci-quirks */
 794
 795                         struct pci_dev *lpc_bridge;
 796                         u16 trueid;
 797                         u8 prefctl;
 798                         u8 idecfg;
 799                         u8 sbrev;
 800
 801                         pci_read_config_byte(dev, 0x4a, &idecfg);
 802                         pci_write_config_byte(dev, 0x4a, idecfg | 0x10);
 803                         pci_read_config_word(dev, PCI_DEVICE_ID, &trueid);
 804                         pci_write_config_byte(dev, 0x4a, idecfg);
 805
 806                         if (trueid == 0x5517) { /* SiS 961/961B */
 807
 808                                 lpc_bridge = pci_find_slot(0x00, 0x10); /* Bus 0, Dev 2, Fn 0 */
 809                                 pci_read_config_byte(lpc_bridge, PCI_REVISION_ID, &sbrev);
 810                                 pci_read_config_byte(dev, 0x49, &prefctl);
 811
 812                                 if (sbrev == 0x10 && (prefctl & 0x80)) {
 813                                         printk(KERN_INFO "SIS5513: SiS 961B MuTIOL IDE UDMA133 controller\n");
 814                                         chipset_family = ATA_133a;
 815                                 } else {
 816                                         printk(KERN_INFO "SIS5513: SiS 961 MuTIOL IDE UDMA100 controller\n");
 817                                         chipset_family = ATA_100;
 818                                 }
 819                         }
 820         }
 821
 822         if (!chipset_family)
 823                 return -1;
 824
 825         /* Make general config ops here
 826            1/ tell IDE channels to operate in Compatibility mode only
 827            2/ tell old chips to allow per drive IDE timings */
 828
 829         {
 830                 u8 reg;
 831                 u16 regw;
 832
 833                 switch(chipset_family) {
 834                         case ATA_133:
 835                                 /* SiS962 operation mode */
 836                                 pci_read_config_word(dev, 0x50, &regw);
 837                                 if (regw & 0x08)
 838                                         pci_write_config_word(dev, 0x50, regw&0xfff7);
 839                                 pci_read_config_word(dev, 0x52, &regw);
 840                                 if (regw & 0x08)
 841                                         pci_write_config_word(dev, 0x52, regw&0xfff7);
 842                                 break;
 843                         case ATA_133a:
 844                         case ATA_100:
 845                                 /* Fixup latency */
 846                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x80);
 847                                 /* Set compatibility bit */
 848                                 pci_read_config_byte(dev, 0x49, &reg);
 849                                 if (!(reg & 0x01)) {
 850                                         pci_write_config_byte(dev, 0x49, reg|0x01);
 851                                 }
 852                                 break;
 853                         case ATA_100a:
 854                         case ATA_66:
 855                                 /* Fixup latency */
 856                                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x10);
 857
 858                                 /* On ATA_66 chips the bit was elsewhere */
 859                                 pci_read_config_byte(dev, 0x52, &reg);
 860                                 if (!(reg & 0x04)) {
 861                                         pci_write_config_byte(dev, 0x52, reg|0x04);
 862                                 }
 863                                 break;
 864                         case ATA_33:
 865                                 /* On ATA_33 we didn't have a single bit to set */
 866                                 pci_read_config_byte(dev, 0x09, &reg);
 867                                 if ((reg & 0x0f) != 0x00) {
 868                                         pci_write_config_byte(dev, 0x09, reg&0xf0);
 869                                 }
 870                         case ATA_16:
 871                                 /* force per drive recovery and active timings
 872                                    needed on ATA_33 and below chips */
 873                                 pci_read_config_byte(dev, 0x52, &reg);
 874                                 if (!(reg & 0x08)) {
 875                                         pci_write_config_byte(dev, 0x52, reg|0x08);
 876                                 }
 877                                 break;
 878                 }
 879
 880 #if defined(DISPLAY_SIS_TIMINGS) && defined(CONFIG_PROC_FS)
 881                 if (!sis_proc) {
 882                         sis_proc = 1;
 883                         bmide_dev = dev;
 884                         ide_pci_create_host_proc("sis", sis_get_info);
 885                 }
 886 #endif
 887         }
 888
 889         return 0;
 890 }
 891
 892 static unsigned int __init ata66_sis5513 (ide_hwif_t *hwif)
 893 {
 894         u8 ata66 = 0;
 895
 896         if (chipset_family >= ATA_133) {
 897                 u16 regw = 0;
 898                 u16 reg_addr = hwif->channel ? 0x52: 0x50;
 899                 pci_read_config_word(hwif->pci_dev, reg_addr, &regw);
 900                 ata66 = (regw & 0x8000) ? 0 : 1;
 901         } else if (chipset_family >= ATA_66) {
 902                 u8 reg48h = 0;
 903                 u8 mask = hwif->channel ? 0x20 : 0x10;
 904                 pci_read_config_byte(hwif->pci_dev, 0x48, &reg48h);
 905                 ata66 = (reg48h & mask) ? 0 : 1;
 906         }
 907         return ata66;
 908 }
 909
 910 static void __init init_hwif_sis5513 (ide_hwif_t *hwif)
 911 {
 912         hwif->autodma = 0;
 913
 914         if (!hwif->irq)
 915                 hwif->irq = hwif->channel ? 15 : 14;
 916
 917         hwif->tuneproc = &sis5513_tune_drive;
 918         hwif->speedproc = &sis5513_tune_chipset;
 919
 920         if (!(hwif->dma_base)) {
 921                 hwif->drives[0].autotune = 1;
 922                 hwif->drives[1].autotune = 1;
 923                 return;
 924         }
 925
 926         hwif->atapi_dma = 1;
 927         hwif->ultra_mask = 0x7f;
 928         hwif->mwdma_mask = 0x07;
 929         hwif->swdma_mask = 0x07;
 930
 931         if (!chipset_family)
 932                 return;
 933
 934         if (!(hwif->udma_four))
 935                 hwif->udma_four = ata66_sis5513(hwif);
 936
 937         if (chipset_family > ATA_16) {
 938                 hwif->ide_dma_check = &sis5513_config_xfer_rate;
 939                 if (!noautodma)
 940                         hwif->autodma = 1;
 941         }
 942         hwif->drives[0].autodma = hwif->autodma;
 943         hwif->drives[1].autodma = hwif->autodma;
 944         return;
 945 }
 946
 947 static int __devinit sis5513_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 948 {
 949         ide_pci_device_t *d = &sis5513_chipsets[id->driver_data];
 950         if (dev->device != d->device)
 951                 BUG();
 952         ide_setup_pci_device(dev, d);
 953         return 0;
 954 }
 955
 956 static struct pci_device_id sis5513_pci_tbl[] = {
 957         { PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 958         { 0, },
 959 };
 960 MODULE_DEVICE_TABLE(pci, sis5513_pci_tbl);
 961
 962 static struct pci_driver driver = {
 963         .name           = "SIS IDE",
 964         .id_table       = sis5513_pci_tbl,
 965         .probe          = sis5513_init_one,
 966 };
 967
 968 static int sis5513_ide_init(void)
 969 {
 970         return ide_pci_register_driver(&driver);
 971 }
 972
 973 module_init(sis5513_ide_init);
 974
 975 MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
 976 MODULE_DESCRIPTION("PCI driver module for SIS IDE");
 977 MODULE_LICENSE("GPL");
 978
 979 /*
 980  * TODO:
 981  *      - CLEANUP
 982  *      - Use drivers/ide/ide-timing.h !
 983  *      - More checks in the config registers (force values instead of
 984  *        relying on the BIOS setting them correctly).
 985  *      - Further optimisations ?
 986  *        . for example ATA66+ regs 0x48 & 0x4A
 987  */