drivers/ide/pci/slc90e66.c

   1 /*
   2  *  linux/drivers/ide/pci/slc90e66.c    Version 0.11    September 11, 2002
   3  *
   4  *  Copyright (C) 2000-2002 Andre Hedrick <andre@linux-ide.org>
   5  *
   6  * This a look-a-like variation of the ICH0 PIIX4 Ultra-66,
   7  * but this keeps the ISA-Bridge and slots alive.
   8  *
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/types.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/ioport.h>
  16 #include <linux/pci.h>
  17 #include <linux/hdreg.h>
  18 #include <linux/ide.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21
  22 #include <asm/io.h>
  23
  24 static u8 slc90e66_ratemask (ide_drive_t *drive)
  25 {
  26         u8 mode = 2;
  27
  28         if (!eighty_ninty_three(drive))
  29                 mode = min(mode, (u8)1);
  30         return mode;
  31 }
  32
  33 static u8 slc90e66_dma_2_pio (u8 xfer_rate) {
  34         switch(xfer_rate) {
  35                 case XFER_UDMA_4:
  36                 case XFER_UDMA_3:
  37                 case XFER_UDMA_2:
  38                 case XFER_UDMA_1:
  39                 case XFER_UDMA_0:
  40                 case XFER_MW_DMA_2:
  41                 case XFER_PIO_4:
  42                         return 4;
  43                 case XFER_MW_DMA_1:
  44                 case XFER_PIO_3:
  45                         return 3;
  46                 case XFER_SW_DMA_2:
  47                 case XFER_PIO_2:
  48                         return 2;
  49                 case XFER_MW_DMA_0:
  50                 case XFER_SW_DMA_1:
  51                 case XFER_SW_DMA_0:
  52                 case XFER_PIO_1:
  53                 case XFER_PIO_0:
  54                 case XFER_PIO_SLOW:
  55                 default:
  56                         return 0;
  57         }
  58 }
  59
  60 /*
  61  *  Based on settings done by AMI BIOS
  62  *  (might be useful if drive is not registered in CMOS for any reason).
  63  */
  64 static void slc90e66_tune_drive (ide_drive_t *drive, u8 pio)
  65 {
  66         ide_hwif_t *hwif        = HWIF(drive);
  67         struct pci_dev *dev     = hwif->pci_dev;
  68         int is_slave            = (&hwif->drives[1] == drive);
  69         int master_port         = hwif->channel ? 0x42 : 0x40;
  70         int slave_port          = 0x44;
  71         unsigned long flags;
  72         u16 master_data;
  73         u8 slave_data;
  74                                  /* ISP  RTC */
  75         u8 timings[][2] = { { 0, 0 },
  76                                     { 0, 0 },
  77                                     { 1, 0 },
  78                                     { 2, 1 },
  79                                     { 2, 3 }, };
  80
  81         pio = ide_get_best_pio_mode(drive, pio, 5, NULL);
  82         spin_lock_irqsave(&ide_lock, flags);
  83         pci_read_config_word(dev, master_port, &master_data);
  84         if (is_slave) {
  85                 master_data = master_data | 0x4000;
  86                 if (pio > 1)
  87                         /* enable PPE, IE and TIME */
  88                         master_data = master_data | 0x0070;
  89                 pci_read_config_byte(dev, slave_port, &slave_data);
  90                 slave_data = slave_data & (hwif->channel ? 0x0f : 0xf0);
  91                 slave_data = slave_data | (((timings[pio][0] << 2) | timings[pio][1]) << (hwif->channel ? 4 : 0));
  92         } else {
  93                 master_data = master_data & 0xccf8;
  94                 if (pio > 1)
  95                         /* enable PPE, IE and TIME */
  96                         master_data = master_data | 0x0007;
  97                 master_data = master_data | (timings[pio][0] << 12) | (timings[pio][1] << 8);
  98         }
  99         pci_write_config_word(dev, master_port, master_data);
 100         if (is_slave)
 101                 pci_write_config_byte(dev, slave_port, slave_data);
 102         spin_unlock_irqrestore(&ide_lock, flags);
 103 }
 104
 105 static int slc90e66_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 106 {
 107         ide_hwif_t *hwif        = HWIF(drive);
 108         struct pci_dev *dev     = hwif->pci_dev;
 109         u8 maslave              = hwif->channel ? 0x42 : 0x40;
 110         u8 speed        = ide_rate_filter(slc90e66_ratemask(drive), xferspeed);
 111         int sitre = 0, a_speed  = 7 << (drive->dn * 4);
 112         int u_speed = 0, u_flag = 1 << drive->dn;
 113         u16                     reg4042, reg44, reg48, reg4a;
 114
 115         pci_read_config_word(dev, maslave, &reg4042);
 116         sitre = (reg4042 & 0x4000) ? 1 : 0;
 117         pci_read_config_word(dev, 0x44, &reg44);
 118         pci_read_config_word(dev, 0x48, &reg48);
 119         pci_read_config_word(dev, 0x4a, &reg4a);
 120
 121         switch(speed) {
 122 #ifdef CONFIG_BLK_DEV_IDEDMA
 123                 case XFER_UDMA_4:       u_speed = 4 << (drive->dn * 4); break;
 124                 case XFER_UDMA_3:       u_speed = 3 << (drive->dn * 4); break;
 125                 case XFER_UDMA_2:       u_speed = 2 << (drive->dn * 4); break;
 126                 case XFER_UDMA_1:       u_speed = 1 << (drive->dn * 4); break;
 127                 case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
 128                 case XFER_MW_DMA_2:
 129                 case XFER_MW_DMA_1:
 130                 case XFER_SW_DMA_2:     break;
 131 #endif /* CONFIG_BLK_DEV_IDEDMA */
 132                 case XFER_PIO_4:
 133                 case XFER_PIO_3:
 134                 case XFER_PIO_2:
 135                 case XFER_PIO_0:        break;
 136                 default:                return -1;
 137         }
 138
 139         if (speed >= XFER_UDMA_0) {
 140                 if (!(reg48 & u_flag))
 141                         pci_write_config_word(dev, 0x48, reg48|u_flag);
 142                 /* FIXME: (reg4a & a_speed) ? */
 143                 if ((reg4a & u_speed) != u_speed) {
 144                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 145                         pci_read_config_word(dev, 0x4a, &reg4a);
 146                         pci_write_config_word(dev, 0x4a, reg4a|u_speed);
 147                 }
 148         } else {
 149                 if (reg48 & u_flag)
 150                         pci_write_config_word(dev, 0x48, reg48 & ~u_flag);
 151                 if (reg4a & a_speed)
 152                         pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
 153         }
 154
 155         slc90e66_tune_drive(drive, slc90e66_dma_2_pio(speed));
 156         return (ide_config_drive_speed(drive, speed));
 157 }
 158
 159 #ifdef CONFIG_BLK_DEV_IDEDMA
 160 static int slc90e66_config_drive_for_dma (ide_drive_t *drive)
 161 {
 162         u8 speed = ide_dma_speed(drive, slc90e66_ratemask(drive));
 163
 164         if (!(speed)) {
 165                 u8 tspeed = ide_get_best_pio_mode(drive, 255, 5, NULL);
 166                 speed = slc90e66_dma_2_pio(XFER_PIO_0 + tspeed);
 167         }
 168
 169         (void) slc90e66_tune_chipset(drive, speed);
 170         return ide_dma_enable(drive);
 171 }
 172
 173 static int slc90e66_config_drive_xfer_rate (ide_drive_t *drive)
 174 {
 175         ide_hwif_t *hwif        = HWIF(drive);
 176         struct hd_driveid *id   = drive->id;
 177
 178         drive->init_speed = 0;
 179
 180         if (id && (id->capability & 1) && drive->autodma) {
 181
 182                 if (ide_use_dma(drive)) {
 183                         if (slc90e66_config_drive_for_dma(drive))
 184                                 return hwif->ide_dma_on(drive);
 185                 }
 186
 187                 goto fast_ata_pio;
 188
 189         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 190 fast_ata_pio:
 191                 hwif->tuneproc(drive, 5);
 192                 return hwif->ide_dma_off_quietly(drive);
 193         }
 194         /* IORDY not supported */
 195         return 0;
 196 }
 197 #endif /* CONFIG_BLK_DEV_IDEDMA */
 198
 199 static void __init init_hwif_slc90e66 (ide_hwif_t *hwif)
 200 {
 201         u8 reg47 = 0;
 202         u8 mask = hwif->channel ? 0x01 : 0x02;  /* bit0:Primary */
 203
 204         hwif->autodma = 0;
 205
 206         if (!hwif->irq)
 207                 hwif->irq = hwif->channel ? 15 : 14;
 208
 209         hwif->speedproc = &slc90e66_tune_chipset;
 210         hwif->tuneproc = &slc90e66_tune_drive;
 211
 212         pci_read_config_byte(hwif->pci_dev, 0x47, &reg47);
 213
 214         if (!hwif->dma_base) {
 215                 hwif->drives[0].autotune = 1;
 216                 hwif->drives[1].autotune = 1;
 217                 return;
 218         }
 219
 220         hwif->atapi_dma = 1;
 221         hwif->ultra_mask = 0x1f;
 222         hwif->mwdma_mask = 0x07;
 223         hwif->swdma_mask = 0x07;
 224
 225 #ifdef CONFIG_BLK_DEV_IDEDMA
 226         if (!(hwif->udma_four))
 227                 /* bit[0(1)]: 0:80, 1:40 */
 228                 hwif->udma_four = (reg47 & mask) ? 0 : 1;
 229
 230         hwif->ide_dma_check = &slc90e66_config_drive_xfer_rate;
 231         if (!noautodma)
 232                 hwif->autodma = 1;
 233         hwif->drives[0].autodma = hwif->autodma;
 234         hwif->drives[1].autodma = hwif->autodma;
 235 #endif /* !CONFIG_BLK_DEV_IDEDMA */
 236 }
 237
 238 static ide_pci_device_t slc90e66_chipset __devinitdata = {
 239         .name           = "SLC90E66",
 240         .init_hwif      = init_hwif_slc90e66,
 241         .channels       = 2,
 242         .autodma        = AUTODMA,
 243         .enablebits     = {{0x41,0x80,0x80}, {0x43,0x80,0x80}},
 244         .bootable       = ON_BOARD,
 245 };
 246
 247 static int __devinit slc90e66_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 248 {
 249         return ide_setup_pci_device(dev, &slc90e66_chipset);
 250 }
 251
 252 static struct pci_device_id slc90e66_pci_tbl[] = {
 253         { PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 254         { 0, },
 255 };
 256 MODULE_DEVICE_TABLE(pci, slc90e66_pci_tbl);
 257
 258 static struct pci_driver driver = {
 259         .name           = "SLC90e66_IDE",
 260         .id_table       = slc90e66_pci_tbl,
 261         .probe          = slc90e66_init_one,
 262 };
 263
 264 static int slc90e66_ide_init(void)
 265 {
 266         return ide_pci_register_driver(&driver);
 267 }
 268
 269 module_init(slc90e66_ide_init);
 270
 271 MODULE_AUTHOR("Andre Hedrick");
 272 MODULE_DESCRIPTION("PCI driver module for SLC90E66 IDE");
 273 MODULE_LICENSE("GPL");