drivers/ieee1394/csr.c

   1 /*
   2  * IEEE 1394 for Linux
   3  *
   4  * CSR implementation, iso/bus manager implementation.
   5  *
   6  * Copyright (C) 1999 Andreas E. Bombe
   7  *               2002 Manfred Weihs <weihs@ict.tuwien.ac.at>
   8  *
   9  * This code is licensed under the GPL.  See the file COPYING in the root
  10  * directory of the kernel sources for details.
  11  *
  12  *
  13  * Contributions:
  14  *
  15  * Manfred Weihs <weihs@ict.tuwien.ac.at>
  16  *        configuration ROM manipulation
  17  *
  18  */
  19
  20 #include <linux/string.h>
  21 #include <linux/module.h>
  22 #include <linux/moduleparam.h>
  23 #include <linux/param.h>
  24 #include <linux/spinlock.h>
  25
  26 #include "csr1212.h"
  27 #include "ieee1394_types.h"
  28 #include "hosts.h"
  29 #include "ieee1394.h"
  30 #include "highlevel.h"
  31
  32 /* Module Parameters */
  33 /* this module parameter can be used to disable mapping of the FCP registers */
  34
  35 static int fcp = 1;
  36 module_param(fcp, int, 0444);
  37 MODULE_PARM_DESC(fcp, "Map FCP registers (default = 1, disable = 0).");
  38
  39 static struct csr1212_keyval *node_cap = NULL;
  40
  41 static void add_host(struct hpsb_host *host);
  42 static void remove_host(struct hpsb_host *host);
  43 static void host_reset(struct hpsb_host *host);
  44 static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
  45                      u64 addr, size_t length, u16 fl);
  46 static int write_fcp(struct hpsb_host *host, int nodeid, int dest,
  47                      quadlet_t *data, u64 addr, size_t length, u16 flags);
  48 static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf,
  49                      u64 addr, size_t length, u16 flags);
  50 static int write_regs(struct hpsb_host *host, int nodeid, int destid,
  51                       quadlet_t *data, u64 addr, size_t length, u16 flags);
  52 static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,
  53                      u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl);
  54 static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,
  55                        u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl);
  56 static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
  57                            u64 addr, size_t length, u16 fl);
  58 static u64 allocate_addr_range(u64 size, u32 alignment, void *__host);
  59 static void release_addr_range(u64 addr, void *__host);
  60
  61 static struct hpsb_highlevel csr_highlevel = {
  62         .name =         "standard registers",
  63         .add_host =     add_host,
  64         .remove_host =  remove_host,
  65         .host_reset =   host_reset,
  66 };
  67
  68 static struct hpsb_address_ops map_ops = {
  69         .read = read_maps,
  70 };
  71
  72 static struct hpsb_address_ops fcp_ops = {
  73         .write = write_fcp,
  74 };
  75
  76 static struct hpsb_address_ops reg_ops = {
  77         .read = read_regs,
  78         .write = write_regs,
  79         .lock = lock_regs,
  80         .lock64 = lock64_regs,
  81 };
  82
  83 static struct hpsb_address_ops config_rom_ops = {
  84         .read = read_config_rom,
  85 };
  86
  87 struct csr1212_bus_ops csr_bus_ops = {
  88         .allocate_addr_range =  allocate_addr_range,
  89         .release_addr =         release_addr_range,
  90 };
  91
  92
  93 static u16 csr_crc16(unsigned *data, int length)
  94 {
  95         int check=0, i;
  96         int shift, sum, next=0;
  97
  98         for (i = length; i; i--) {
  99                 for (next = check, shift = 28; shift >= 0; shift -= 4 ) {
 100                         sum = ((next >> 12) ^ (be32_to_cpu(*data) >> shift)) & 0xf;
 101                         next = (next << 4) ^ (sum << 12) ^ (sum << 5) ^ (sum);
 102                 }
 103                 check = next & 0xffff;
 104                 data++;
 105         }
 106
 107         return check;
 108 }
 109
 110 static void host_reset(struct hpsb_host *host)
 111 {
 112         host->csr.state &= 0x300;
 113
 114         host->csr.bus_manager_id = 0x3f;
 115         host->csr.bandwidth_available = 4915;
 116         host->csr.channels_available_hi = 0xfffffffe;   /* pre-alloc ch 31 per 1394a-2000 */
 117         host->csr.channels_available_lo = ~0;
 118         host->csr.broadcast_channel = 0x80000000 | 31;
 119
 120         if (host->is_irm) {
 121                 if (host->driver->hw_csr_reg) {
 122                         host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0);
 123                 }
 124         }
 125
 126         host->csr.node_ids = host->node_id << 16;
 127
 128         if (!host->is_root) {
 129                 /* clear cmstr bit */
 130                 host->csr.state &= ~0x100;
 131         }
 132
 133         host->csr.topology_map[1] =
 134                 cpu_to_be32(be32_to_cpu(host->csr.topology_map[1]) + 1);
 135         host->csr.topology_map[2] = cpu_to_be32(host->node_count << 16
 136                                                 | host->selfid_count);
 137         host->csr.topology_map[0] =
 138                 cpu_to_be32((host->selfid_count + 2) << 16
 139                             | csr_crc16(host->csr.topology_map + 1,
 140                                         host->selfid_count + 2));
 141
 142         host->csr.speed_map[1] =
 143                 cpu_to_be32(be32_to_cpu(host->csr.speed_map[1]) + 1);
 144         host->csr.speed_map[0] = cpu_to_be32(0x3f1 << 16
 145                                              | csr_crc16(host->csr.speed_map+1,
 146                                                          0x3f1));
 147 }
 148
 149 /*
 150  * HI == seconds (bits 0:2)
 151  * LO == fraction units of 1/8000 of a second, as per 1394 (bits 19:31)
 152  *
 153  * Convert to units and then to HZ, for comparison to jiffies.
 154  *
 155  * By default this will end up being 800 units, or 100ms (125usec per
 156  * unit).
 157  *
 158  * NOTE: The spec says 1/8000, but also says we can compute based on 1/8192
 159  * like CSR specifies. Should make our math less complex.
 160  */
 161 static inline void calculate_expire(struct csr_control *csr)
 162 {
 163         unsigned long units;
 164
 165         /* Take the seconds, and convert to units */
 166         units = (unsigned long)(csr->split_timeout_hi & 0x07) << 13;
 167
 168         /* Add in the fractional units */
 169         units += (unsigned long)(csr->split_timeout_lo >> 19);
 170
 171         /* Convert to jiffies */
 172         csr->expire = (unsigned long)(units * HZ) >> 13UL;
 173
 174         /* Just to keep from rounding low */
 175         csr->expire++;
 176
 177         HPSB_VERBOSE("CSR: setting expire to %lu, HZ=%u", csr->expire, HZ);
 178 }
 179
 180
 181 static void add_host(struct hpsb_host *host)
 182 {
 183         struct csr1212_keyval *root;
 184         quadlet_t bus_info[CSR_BUS_INFO_SIZE];
 185
 186         hpsb_register_addrspace(&csr_highlevel, host, &reg_ops,
 187                                 CSR_REGISTER_BASE,
 188                                 CSR_REGISTER_BASE + CSR_CONFIG_ROM);
 189         hpsb_register_addrspace(&csr_highlevel, host, &config_rom_ops,
 190                                 CSR_REGISTER_BASE + CSR_CONFIG_ROM,
 191                                 CSR_REGISTER_BASE + CSR_CONFIG_ROM_END);
 192         if (fcp) {
 193                 hpsb_register_addrspace(&csr_highlevel, host, &fcp_ops,
 194                                         CSR_REGISTER_BASE + CSR_FCP_COMMAND,
 195                                         CSR_REGISTER_BASE + CSR_FCP_END);
 196         }
 197         hpsb_register_addrspace(&csr_highlevel, host, &map_ops,
 198                                 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP,
 199                                 CSR_REGISTER_BASE + CSR_TOPOLOGY_MAP_END);
 200         hpsb_register_addrspace(&csr_highlevel, host, &map_ops,
 201                                 CSR_REGISTER_BASE + CSR_SPEED_MAP,
 202                                 CSR_REGISTER_BASE + CSR_SPEED_MAP_END);
 203
 204         host->csr.lock = SPIN_LOCK_UNLOCKED;
 205
 206         host->csr.state                 = 0;
 207         host->csr.node_ids              = 0;
 208         host->csr.split_timeout_hi      = 0;
 209         host->csr.split_timeout_lo      = 800 << 19;
 210         calculate_expire(&host->csr);
 211         host->csr.cycle_time            = 0;
 212         host->csr.bus_time              = 0;
 213         host->csr.bus_manager_id        = 0x3f;
 214         host->csr.bandwidth_available   = 4915;
 215         host->csr.channels_available_hi = 0xfffffffe;   /* pre-alloc ch 31 per 1394a-2000 */
 216         host->csr.channels_available_lo = ~0;
 217         host->csr.broadcast_channel = 0x80000000 | 31;
 218
 219         if (host->is_irm) {
 220                 if (host->driver->hw_csr_reg) {
 221                         host->driver->hw_csr_reg(host, 2, 0xfffffffe, ~0);
 222                 }
 223         }
 224
 225         if (host->csr.max_rec >= 9)
 226                 host->csr.max_rom = 2;
 227         else if (host->csr.max_rec >= 5)
 228                 host->csr.max_rom = 1;
 229         else
 230                 host->csr.max_rom = 0;
 231
 232         host->csr.generation = 2;
 233
 234         bus_info[1] = __constant_cpu_to_be32(0x31333934);
 235         bus_info[2] = cpu_to_be32((1 << CSR_IRMC_SHIFT) |
 236                                   (1 << CSR_CMC_SHIFT) |
 237                                   (1 << CSR_ISC_SHIFT) |
 238                                   (0 << CSR_BMC_SHIFT) |
 239                                   (0 << CSR_PMC_SHIFT) |
 240                                   (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
 241                                   (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
 242                                   (host->csr.max_rom << CSR_MAX_ROM_SHIFT) |
 243                                   (host->csr.generation << CSR_GENERATION_SHIFT) |
 244                                   host->csr.lnk_spd);
 245
 246         bus_info[3] = cpu_to_be32(host->csr.guid_hi);
 247         bus_info[4] = cpu_to_be32(host->csr.guid_lo);
 248
 249         /* The hardware copy of the bus info block will be set later when a
 250          * bus reset is issued. */
 251
 252         csr1212_init_local_csr(host->csr.rom, bus_info, host->csr.max_rom);
 253
 254         host->csr.rom->max_rom = host->csr.max_rom;
 255
 256         root = host->csr.rom->root_kv;
 257
 258         if(csr1212_attach_keyval_to_directory(root, node_cap) != CSR1212_SUCCESS) {
 259                 HPSB_ERR("Failed to attach Node Capabilities to root directory");
 260         }
 261
 262         host->update_config_rom = 1;
 263 }
 264
 265 static void remove_host(struct hpsb_host *host)
 266 {
 267         quadlet_t bus_info[CSR_BUS_INFO_SIZE];
 268
 269         bus_info[1] = __constant_cpu_to_be32(0x31333934);
 270         bus_info[2] = cpu_to_be32((0 << CSR_IRMC_SHIFT) |
 271                                   (0 << CSR_CMC_SHIFT) |
 272                                   (0 << CSR_ISC_SHIFT) |
 273                                   (0 << CSR_BMC_SHIFT) |
 274                                   (0 << CSR_PMC_SHIFT) |
 275                                   (host->csr.cyc_clk_acc << CSR_CYC_CLK_ACC_SHIFT) |
 276                                   (host->csr.max_rec << CSR_MAX_REC_SHIFT) |
 277                                   (0 << CSR_MAX_ROM_SHIFT) |
 278                                   (0 << CSR_GENERATION_SHIFT) |
 279                                   host->csr.lnk_spd);
 280
 281         bus_info[3] = cpu_to_be32(host->csr.guid_hi);
 282         bus_info[4] = cpu_to_be32(host->csr.guid_lo);
 283
 284         csr1212_detach_keyval_from_directory(host->csr.rom->root_kv, node_cap);
 285
 286         csr1212_init_local_csr(host->csr.rom, bus_info, 0);
 287         host->update_config_rom = 1;
 288 }
 289
 290
 291 int hpsb_update_config_rom(struct hpsb_host *host, const quadlet_t *new_rom,
 292         size_t buffersize, unsigned char rom_version)
 293 {
 294         unsigned long flags;
 295         int ret;
 296
 297         HPSB_NOTICE("hpsb_update_config_rom() is deprecated");
 298
 299         spin_lock_irqsave(&host->csr.lock, flags);
 300         if (rom_version != host->csr.generation)
 301                 ret = -1;
 302         else if (buffersize > host->csr.rom->cache_head->size)
 303                 ret = -2;
 304         else {
 305                 /* Just overwrite the generated ConfigROM image with new data,
 306                  * it can be regenerated later. */
 307                 memcpy(host->csr.rom->cache_head->data, new_rom, buffersize);
 308                 host->csr.rom->cache_head->len = buffersize;
 309
 310                 if (host->driver->set_hw_config_rom)
 311                         host->driver->set_hw_config_rom(host, host->csr.rom->bus_info_data);
 312                 /* Increment the generation number to keep some sort of sync
 313                  * with the newer ConfigROM manipulation method. */
 314                 host->csr.generation++;
 315                 if (host->csr.generation > 0xf || host->csr.generation < 2)
 316                         host->csr.generation = 2;
 317                 ret=0;
 318         }
 319         spin_unlock_irqrestore(&host->csr.lock, flags);
 320         return ret;
 321 }
 322
 323
 324 /* Read topology / speed maps and configuration ROM */
 325 static int read_maps(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
 326                      u64 addr, size_t length, u16 fl)
 327 {
 328         unsigned long flags;
 329         int csraddr = addr - CSR_REGISTER_BASE;
 330         const char *src;
 331
 332         spin_lock_irqsave(&host->csr.lock, flags);
 333
 334         if (csraddr < CSR_SPEED_MAP) {
 335                 src = ((char *)host->csr.topology_map) + csraddr
 336                         - CSR_TOPOLOGY_MAP;
 337         } else {
 338                 src = ((char *)host->csr.speed_map) + csraddr - CSR_SPEED_MAP;
 339         }
 340
 341         memcpy(buffer, src, length);
 342         spin_unlock_irqrestore(&host->csr.lock, flags);
 343         return RCODE_COMPLETE;
 344 }
 345
 346
 347 #define out if (--length == 0) break
 348
 349 static int read_regs(struct hpsb_host *host, int nodeid, quadlet_t *buf,
 350                      u64 addr, size_t length, u16 flags)
 351 {
 352         int csraddr = addr - CSR_REGISTER_BASE;
 353         int oldcycle;
 354         quadlet_t ret;
 355
 356         if ((csraddr | length) & 0x3)
 357                 return RCODE_TYPE_ERROR;
 358
 359         length /= 4;
 360
 361         switch (csraddr) {
 362         case CSR_STATE_CLEAR:
 363                 *(buf++) = cpu_to_be32(host->csr.state);
 364                 out;
 365         case CSR_STATE_SET:
 366                 *(buf++) = cpu_to_be32(host->csr.state);
 367                 out;
 368         case CSR_NODE_IDS:
 369                 *(buf++) = cpu_to_be32(host->csr.node_ids);
 370                 out;
 371
 372         case CSR_RESET_START:
 373                 return RCODE_TYPE_ERROR;
 374
 375                 /* address gap - handled by default below */
 376
 377         case CSR_SPLIT_TIMEOUT_HI:
 378                 *(buf++) = cpu_to_be32(host->csr.split_timeout_hi);
 379                 out;
 380         case CSR_SPLIT_TIMEOUT_LO:
 381                 *(buf++) = cpu_to_be32(host->csr.split_timeout_lo);
 382                 out;
 383
 384                 /* address gap */
 385                 return RCODE_ADDRESS_ERROR;
 386
 387         case CSR_CYCLE_TIME:
 388                 oldcycle = host->csr.cycle_time;
 389                 host->csr.cycle_time =
 390                         host->driver->devctl(host, GET_CYCLE_COUNTER, 0);
 391
 392                 if (oldcycle > host->csr.cycle_time) {
 393                         /* cycle time wrapped around */
 394                         host->csr.bus_time += 1 << 7;
 395                 }
 396                 *(buf++) = cpu_to_be32(host->csr.cycle_time);
 397                 out;
 398         case CSR_BUS_TIME:
 399                 oldcycle = host->csr.cycle_time;
 400                 host->csr.cycle_time =
 401                         host->driver->devctl(host, GET_CYCLE_COUNTER, 0);
 402
 403                 if (oldcycle > host->csr.cycle_time) {
 404                         /* cycle time wrapped around */
 405                         host->csr.bus_time += (1 << 7);
 406                 }
 407                 *(buf++) = cpu_to_be32(host->csr.bus_time
 408                                        | (host->csr.cycle_time >> 25));
 409                 out;
 410
 411                 /* address gap */
 412                 return RCODE_ADDRESS_ERROR;
 413
 414         case CSR_BUSY_TIMEOUT:
 415                 /* not yet implemented */
 416                 return RCODE_ADDRESS_ERROR;
 417
 418         case CSR_BUS_MANAGER_ID:
 419                 if (host->driver->hw_csr_reg)
 420                         ret = host->driver->hw_csr_reg(host, 0, 0, 0);
 421                 else
 422                         ret = host->csr.bus_manager_id;
 423
 424                 *(buf++) = cpu_to_be32(ret);
 425                 out;
 426         case CSR_BANDWIDTH_AVAILABLE:
 427                 if (host->driver->hw_csr_reg)
 428                         ret = host->driver->hw_csr_reg(host, 1, 0, 0);
 429                 else
 430                         ret = host->csr.bandwidth_available;
 431
 432                 *(buf++) = cpu_to_be32(ret);
 433                 out;
 434         case CSR_CHANNELS_AVAILABLE_HI:
 435                 if (host->driver->hw_csr_reg)
 436                         ret = host->driver->hw_csr_reg(host, 2, 0, 0);
 437                 else
 438                         ret = host->csr.channels_available_hi;
 439
 440                 *(buf++) = cpu_to_be32(ret);
 441                 out;
 442         case CSR_CHANNELS_AVAILABLE_LO:
 443                 if (host->driver->hw_csr_reg)
 444                         ret = host->driver->hw_csr_reg(host, 3, 0, 0);
 445                 else
 446                         ret = host->csr.channels_available_lo;
 447
 448                 *(buf++) = cpu_to_be32(ret);
 449                 out;
 450
 451         case CSR_BROADCAST_CHANNEL:
 452                 *(buf++) = cpu_to_be32(host->csr.broadcast_channel);
 453                 out;
 454
 455                 /* address gap to end - fall through to default */
 456         default:
 457                 return RCODE_ADDRESS_ERROR;
 458         }
 459
 460         return RCODE_COMPLETE;
 461 }
 462
 463 static int write_regs(struct hpsb_host *host, int nodeid, int destid,
 464                       quadlet_t *data, u64 addr, size_t length, u16 flags)
 465 {
 466         int csraddr = addr - CSR_REGISTER_BASE;
 467
 468         if ((csraddr | length) & 0x3)
 469                 return RCODE_TYPE_ERROR;
 470
 471         length /= 4;
 472
 473         switch (csraddr) {
 474         case CSR_STATE_CLEAR:
 475                 /* FIXME FIXME FIXME */
 476                 printk("doh, someone wants to mess with state clear\n");
 477                 out;
 478         case CSR_STATE_SET:
 479                 printk("doh, someone wants to mess with state set\n");
 480                 out;
 481
 482         case CSR_NODE_IDS:
 483                 host->csr.node_ids &= NODE_MASK << 16;
 484                 host->csr.node_ids |= be32_to_cpu(*(data++)) & (BUS_MASK << 16);
 485                 host->node_id = host->csr.node_ids >> 16;
 486                 host->driver->devctl(host, SET_BUS_ID, host->node_id >> 6);
 487                 out;
 488
 489         case CSR_RESET_START:
 490                 /* FIXME - perform command reset */
 491                 out;
 492
 493                 /* address gap */
 494                 return RCODE_ADDRESS_ERROR;
 495
 496         case CSR_SPLIT_TIMEOUT_HI:
 497                 host->csr.split_timeout_hi =
 498                         be32_to_cpu(*(data++)) & 0x00000007;
 499                 calculate_expire(&host->csr);
 500                 out;
 501         case CSR_SPLIT_TIMEOUT_LO:
 502                 host->csr.split_timeout_lo =
 503                         be32_to_cpu(*(data++)) & 0xfff80000;
 504                 calculate_expire(&host->csr);
 505                 out;
 506
 507                 /* address gap */
 508                 return RCODE_ADDRESS_ERROR;
 509
 510         case CSR_CYCLE_TIME:
 511                 /* should only be set by cycle start packet, automatically */
 512                 host->csr.cycle_time = be32_to_cpu(*data);
 513                 host->driver->devctl(host, SET_CYCLE_COUNTER,
 514                                        be32_to_cpu(*(data++)));
 515                 out;
 516         case CSR_BUS_TIME:
 517                 host->csr.bus_time = be32_to_cpu(*(data++)) & 0xffffff80;
 518                 out;
 519
 520                 /* address gap */
 521                 return RCODE_ADDRESS_ERROR;
 522
 523         case CSR_BUSY_TIMEOUT:
 524                 /* not yet implemented */
 525                 return RCODE_ADDRESS_ERROR;
 526
 527         case CSR_BUS_MANAGER_ID:
 528         case CSR_BANDWIDTH_AVAILABLE:
 529         case CSR_CHANNELS_AVAILABLE_HI:
 530         case CSR_CHANNELS_AVAILABLE_LO:
 531                 /* these are not writable, only lockable */
 532                 return RCODE_TYPE_ERROR;
 533
 534         case CSR_BROADCAST_CHANNEL:
 535                 /* only the valid bit can be written */
 536                 host->csr.broadcast_channel = (host->csr.broadcast_channel & ~0x40000000)
 537                         | (be32_to_cpu(*data) & 0x40000000);
 538                 out;
 539
 540                 /* address gap to end - fall through */
 541         default:
 542                 return RCODE_ADDRESS_ERROR;
 543         }
 544
 545         return RCODE_COMPLETE;
 546 }
 547
 548 #undef out
 549
 550
 551 static int lock_regs(struct hpsb_host *host, int nodeid, quadlet_t *store,
 552                      u64 addr, quadlet_t data, quadlet_t arg, int extcode, u16 fl)
 553 {
 554         int csraddr = addr - CSR_REGISTER_BASE;
 555         unsigned long flags;
 556         quadlet_t *regptr = NULL;
 557
 558         if (csraddr & 0x3)
 559                 return RCODE_TYPE_ERROR;
 560
 561         if (csraddr < CSR_BUS_MANAGER_ID || csraddr > CSR_CHANNELS_AVAILABLE_LO
 562             || extcode != EXTCODE_COMPARE_SWAP)
 563                 goto unsupported_lockreq;
 564
 565         data = be32_to_cpu(data);
 566         arg = be32_to_cpu(arg);
 567
 568         /* Is somebody releasing the broadcast_channel on us? */
 569         if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x1)) {
 570                 /* Note: this is may not be the right way to handle
 571                  * the problem, so we should look into the proper way
 572                  * eventually. */
 573                 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "
 574                           "broadcast channel 31.  Ignoring.",
 575                           NODE_BUS_ARGS(host, nodeid));
 576
 577                 data &= ~0x1;   /* keep broadcast channel allocated */
 578         }
 579
 580         if (host->driver->hw_csr_reg) {
 581                 quadlet_t old;
 582
 583                 old = host->driver->
 584                         hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,
 585                                    data, arg);
 586
 587                 *store = cpu_to_be32(old);
 588                 return RCODE_COMPLETE;
 589         }
 590
 591         spin_lock_irqsave(&host->csr.lock, flags);
 592
 593         switch (csraddr) {
 594         case CSR_BUS_MANAGER_ID:
 595                 regptr = &host->csr.bus_manager_id;
 596                 *store = cpu_to_be32(*regptr);
 597                 if (*regptr == arg)
 598                         *regptr = data;
 599                 break;
 600
 601         case CSR_BANDWIDTH_AVAILABLE:
 602         {
 603                 quadlet_t bandwidth;
 604                 quadlet_t old;
 605                 quadlet_t new;
 606
 607                 regptr = &host->csr.bandwidth_available;
 608                 old = *regptr;
 609
 610                 /* bandwidth available algorithm adapted from IEEE 1394a-2000 spec */
 611                 if (arg > 0x1fff) {
 612                         *store = cpu_to_be32(old);      /* change nothing */
 613                         break;
 614                 }
 615                 data &= 0x1fff;
 616                 if (arg >= data) {
 617                         /* allocate bandwidth */
 618                         bandwidth = arg - data;
 619                         if (old >= bandwidth) {
 620                                 new = old - bandwidth;
 621                                 *store = cpu_to_be32(arg);
 622                                 *regptr = new;
 623                         } else {
 624                                 *store = cpu_to_be32(old);
 625                         }
 626                 } else {
 627                         /* deallocate bandwidth */
 628                         bandwidth = data - arg;
 629                         if (old + bandwidth < 0x2000) {
 630                                 new = old + bandwidth;
 631                                 *store = cpu_to_be32(arg);
 632                                 *regptr = new;
 633                         } else {
 634                                 *store = cpu_to_be32(old);
 635                         }
 636                 }
 637                 break;
 638         }
 639
 640         case CSR_CHANNELS_AVAILABLE_HI:
 641         {
 642                 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */
 643                 quadlet_t affected_channels = arg ^ data;
 644
 645                 regptr = &host->csr.channels_available_hi;
 646
 647                 if ((arg & affected_channels) == (*regptr & affected_channels)) {
 648                         *regptr ^= affected_channels;
 649                         *store = cpu_to_be32(arg);
 650                 } else {
 651                         *store = cpu_to_be32(*regptr);
 652                 }
 653
 654                 break;
 655         }
 656
 657         case CSR_CHANNELS_AVAILABLE_LO:
 658         {
 659                 /* Lock algorithm for CHANNELS_AVAILABLE as recommended by 1394a-2000 */
 660                 quadlet_t affected_channels = arg ^ data;
 661
 662                 regptr = &host->csr.channels_available_lo;
 663
 664                 if ((arg & affected_channels) == (*regptr & affected_channels)) {
 665                         *regptr ^= affected_channels;
 666                         *store = cpu_to_be32(arg);
 667                 } else {
 668                         *store = cpu_to_be32(*regptr);
 669                 }
 670                 break;
 671         }
 672         }
 673
 674         spin_unlock_irqrestore(&host->csr.lock, flags);
 675
 676         return RCODE_COMPLETE;
 677
 678  unsupported_lockreq:
 679         switch (csraddr) {
 680         case CSR_STATE_CLEAR:
 681         case CSR_STATE_SET:
 682         case CSR_RESET_START:
 683         case CSR_NODE_IDS:
 684         case CSR_SPLIT_TIMEOUT_HI:
 685         case CSR_SPLIT_TIMEOUT_LO:
 686         case CSR_CYCLE_TIME:
 687         case CSR_BUS_TIME:
 688         case CSR_BROADCAST_CHANNEL:
 689                 return RCODE_TYPE_ERROR;
 690
 691         case CSR_BUSY_TIMEOUT:
 692                 /* not yet implemented - fall through */
 693         default:
 694                 return RCODE_ADDRESS_ERROR;
 695         }
 696 }
 697
 698 static int lock64_regs(struct hpsb_host *host, int nodeid, octlet_t * store,
 699                        u64 addr, octlet_t data, octlet_t arg, int extcode, u16 fl)
 700 {
 701         int csraddr = addr - CSR_REGISTER_BASE;
 702         unsigned long flags;
 703
 704         data = be64_to_cpu(data);
 705         arg = be64_to_cpu(arg);
 706
 707         if (csraddr & 0x3)
 708                 return RCODE_TYPE_ERROR;
 709
 710         if (csraddr != CSR_CHANNELS_AVAILABLE
 711             || extcode != EXTCODE_COMPARE_SWAP)
 712                 goto unsupported_lock64req;
 713
 714         /* Is somebody releasing the broadcast_channel on us? */
 715         if (csraddr == CSR_CHANNELS_AVAILABLE_HI && (data & 0x100000000ULL)) {
 716                 /* Note: this is may not be the right way to handle
 717                  * the problem, so we should look into the proper way
 718                  * eventually. */
 719                 HPSB_WARN("Node [" NODE_BUS_FMT "] wants to release "
 720                           "broadcast channel 31.  Ignoring.",
 721                           NODE_BUS_ARGS(host, nodeid));
 722
 723                 data &= ~0x100000000ULL;        /* keep broadcast channel allocated */
 724         }
 725
 726         if (host->driver->hw_csr_reg) {
 727                 quadlet_t data_hi, data_lo;
 728                 quadlet_t arg_hi, arg_lo;
 729                 quadlet_t old_hi, old_lo;
 730
 731                 data_hi = data >> 32;
 732                 data_lo = data & 0xFFFFFFFF;
 733                 arg_hi = arg >> 32;
 734                 arg_lo = arg & 0xFFFFFFFF;
 735
 736                 old_hi = host->driver->hw_csr_reg(host, (csraddr - CSR_BUS_MANAGER_ID) >> 2,
 737                                                   data_hi, arg_hi);
 738
 739                 old_lo = host->driver->hw_csr_reg(host, ((csraddr + 4) - CSR_BUS_MANAGER_ID) >> 2,
 740                                                   data_lo, arg_lo);
 741
 742                 *store = cpu_to_be64(((octlet_t)old_hi << 32) | old_lo);
 743         } else {
 744                 octlet_t old;
 745                 octlet_t affected_channels = arg ^ data;
 746
 747                 spin_lock_irqsave(&host->csr.lock, flags);
 748
 749                 old = ((octlet_t)host->csr.channels_available_hi << 32) | host->csr.channels_available_lo;
 750
 751                 if ((arg & affected_channels) == (old & affected_channels)) {
 752                         host->csr.channels_available_hi ^= (affected_channels >> 32);
 753                         host->csr.channels_available_lo ^= (affected_channels & 0xffffffff);
 754                         *store = cpu_to_be64(arg);
 755                 } else {
 756                         *store = cpu_to_be64(old);
 757                 }
 758
 759                 spin_unlock_irqrestore(&host->csr.lock, flags);
 760         }
 761
 762         /* Is somebody erroneously releasing the broadcast_channel on us? */
 763         if (host->csr.channels_available_hi & 0x1)
 764                 host->csr.channels_available_hi &= ~0x1;
 765
 766         return RCODE_COMPLETE;
 767
 768  unsupported_lock64req:
 769         switch (csraddr) {
 770         case CSR_STATE_CLEAR:
 771         case CSR_STATE_SET:
 772         case CSR_RESET_START:
 773         case CSR_NODE_IDS:
 774         case CSR_SPLIT_TIMEOUT_HI:
 775         case CSR_SPLIT_TIMEOUT_LO:
 776         case CSR_CYCLE_TIME:
 777         case CSR_BUS_TIME:
 778         case CSR_BUS_MANAGER_ID:
 779         case CSR_BROADCAST_CHANNEL:
 780         case CSR_BUSY_TIMEOUT:
 781         case CSR_BANDWIDTH_AVAILABLE:
 782                 return RCODE_TYPE_ERROR;
 783
 784         default:
 785                 return RCODE_ADDRESS_ERROR;
 786         }
 787 }
 788
 789 static int write_fcp(struct hpsb_host *host, int nodeid, int dest,
 790                      quadlet_t *data, u64 addr, size_t length, u16 flags)
 791 {
 792         int csraddr = addr - CSR_REGISTER_BASE;
 793
 794         if (length > 512)
 795                 return RCODE_TYPE_ERROR;
 796
 797         switch (csraddr) {
 798         case CSR_FCP_COMMAND:
 799                 highlevel_fcp_request(host, nodeid, 0, (u8 *)data, length);
 800                 break;
 801         case CSR_FCP_RESPONSE:
 802                 highlevel_fcp_request(host, nodeid, 1, (u8 *)data, length);
 803                 break;
 804         default:
 805                 return RCODE_TYPE_ERROR;
 806         }
 807
 808         return RCODE_COMPLETE;
 809 }
 810
 811 static int read_config_rom(struct hpsb_host *host, int nodeid, quadlet_t *buffer,
 812                            u64 addr, size_t length, u16 fl)
 813 {
 814         u32 offset = addr - CSR1212_REGISTER_SPACE_BASE;
 815
 816         if (csr1212_read(host->csr.rom, offset, buffer, length) == CSR1212_SUCCESS)
 817                 return RCODE_COMPLETE;
 818         else
 819                 return RCODE_ADDRESS_ERROR;
 820 }
 821
 822 static u64 allocate_addr_range(u64 size, u32 alignment, void *__host)
 823 {
 824         struct hpsb_host *host = (struct hpsb_host*)__host;
 825
 826         return hpsb_allocate_and_register_addrspace(&csr_highlevel,
 827                                                     host,
 828                                                     &config_rom_ops,
 829                                                     size, alignment,
 830                                                     CSR1212_UNITS_SPACE_BASE,
 831                                                     CSR1212_UNITS_SPACE_END);
 832 }
 833
 834 static void release_addr_range(u64 addr, void *__host)
 835 {
 836         struct hpsb_host *host = (struct hpsb_host*)__host;
 837         hpsb_unregister_addrspace(&csr_highlevel, host, addr);
 838 }
 839
 840
 841 int init_csr(void)
 842 {
 843         node_cap = csr1212_new_immediate(CSR1212_KV_ID_NODE_CAPABILITIES, 0x0083c0);
 844         if (!node_cap) {
 845                 HPSB_ERR("Failed to allocate memory for Node Capabilties ConfigROM entry!");
 846                 return -ENOMEM;
 847         }
 848
 849         hpsb_register_highlevel(&csr_highlevel);
 850
 851         return 0;
 852 }
 853
 854 void cleanup_csr(void)
 855 {
 856         if (node_cap)
 857                 csr1212_release_keyval(node_cap);
 858         hpsb_unregister_highlevel(&csr_highlevel);
 859 }