drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  *
  32  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  33  */
  34
  35 #include <linux/init.h>
  36
  37 #include <ib_verbs.h>
  38 #include <ib_cache.h>
  39 #include <ib_pack.h>
  40
  41 #include "mthca_dev.h"
  42 #include "mthca_cmd.h"
  43
  44 enum {
  45         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  46         MTHCA_ACK_REQ_FREQ       = 10,
  47         MTHCA_FLIGHT_LIMIT       = 9,
  48         MTHCA_UD_HEADER_SIZE     = 72 /* largest UD header possible */
  49 };
  50
  51 enum {
  52         MTHCA_QP_STATE_RST  = 0,
  53         MTHCA_QP_STATE_INIT = 1,
  54         MTHCA_QP_STATE_RTR  = 2,
  55         MTHCA_QP_STATE_RTS  = 3,
  56         MTHCA_QP_STATE_SQE  = 4,
  57         MTHCA_QP_STATE_SQD  = 5,
  58         MTHCA_QP_STATE_ERR  = 6,
  59         MTHCA_QP_STATE_DRAINING = 7
  60 };
  61
  62 enum {
  63         MTHCA_QP_ST_RC  = 0x0,
  64         MTHCA_QP_ST_UC  = 0x1,
  65         MTHCA_QP_ST_RD  = 0x2,
  66         MTHCA_QP_ST_UD  = 0x3,
  67         MTHCA_QP_ST_MLX = 0x7
  68 };
  69
  70 enum {
  71         MTHCA_QP_PM_MIGRATED = 0x3,
  72         MTHCA_QP_PM_ARMED    = 0x0,
  73         MTHCA_QP_PM_REARM    = 0x1
  74 };
  75
  76 enum {
  77         /* qp_context flags */
  78         MTHCA_QP_BIT_DE  = 1 <<  8,
  79         /* params1 */
  80         MTHCA_QP_BIT_SRE = 1 << 15,
  81         MTHCA_QP_BIT_SWE = 1 << 14,
  82         MTHCA_QP_BIT_SAE = 1 << 13,
  83         MTHCA_QP_BIT_SIC = 1 <<  4,
  84         MTHCA_QP_BIT_SSC = 1 <<  3,
  85         /* params2 */
  86         MTHCA_QP_BIT_RRE = 1 << 15,
  87         MTHCA_QP_BIT_RWE = 1 << 14,
  88         MTHCA_QP_BIT_RAE = 1 << 13,
  89         MTHCA_QP_BIT_RIC = 1 <<  4,
  90         MTHCA_QP_BIT_RSC = 1 <<  3
  91 };
  92
  93 struct mthca_qp_path {
  94         u32 port_pkey;
  95         u8  rnr_retry;
  96         u8  g_mylmc;
  97         u16 rlid;
  98         u8  ackto;
  99         u8  mgid_index;
 100         u8  static_rate;
 101         u8  hop_limit;
 102         u32 sl_tclass_flowlabel;
 103         u8  rgid[16];
 104 } __attribute__((packed));
 105
 106 struct mthca_qp_context {
 107         u32 flags;
 108         u32 sched_queue;
 109         u32 mtu_msgmax;
 110         u32 usr_page;
 111         u32 local_qpn;
 112         u32 remote_qpn;
 113         u32 reserved1[2];
 114         struct mthca_qp_path pri_path;
 115         struct mthca_qp_path alt_path;
 116         u32 rdd;
 117         u32 pd;
 118         u32 wqe_base;
 119         u32 wqe_lkey;
 120         u32 params1;
 121         u32 reserved2;
 122         u32 next_send_psn;
 123         u32 cqn_snd;
 124         u32 next_snd_wqe[2];
 125         u32 last_acked_psn;
 126         u32 ssn;
 127         u32 params2;
 128         u32 rnr_nextrecvpsn;
 129         u32 ra_buff_indx;
 130         u32 cqn_rcv;
 131         u32 next_rcv_wqe[2];
 132         u32 qkey;
 133         u32 srqn;
 134         u32 rmsn;
 135         u32 reserved3[19];
 136 } __attribute__((packed));
 137
 138 struct mthca_qp_param {
 139         u32 opt_param_mask;
 140         u32 reserved1;
 141         struct mthca_qp_context context;
 142         u32 reserved2[62];
 143 } __attribute__((packed));
 144
 145 enum {
 146         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 147         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 148         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 149         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 150         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 151         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 152         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 153         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 154         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 155         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 156         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 157         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 158         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 159         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 160         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 161         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 162         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 163 };
 164
 165 enum {
 166         MTHCA_OPCODE_NOP            = 0x00,
 167         MTHCA_OPCODE_RDMA_WRITE     = 0x08,
 168         MTHCA_OPCODE_RDMA_WRITE_IMM = 0x09,
 169         MTHCA_OPCODE_SEND           = 0x0a,
 170         MTHCA_OPCODE_SEND_IMM       = 0x0b,
 171         MTHCA_OPCODE_RDMA_READ      = 0x10,
 172         MTHCA_OPCODE_ATOMIC_CS      = 0x11,
 173         MTHCA_OPCODE_ATOMIC_FA      = 0x12,
 174         MTHCA_OPCODE_BIND_MW        = 0x18,
 175         MTHCA_OPCODE_INVALID        = 0xff
 176 };
 177
 178 enum {
 179         MTHCA_NEXT_DBD       = 1 << 7,
 180         MTHCA_NEXT_FENCE     = 1 << 6,
 181         MTHCA_NEXT_CQ_UPDATE = 1 << 3,
 182         MTHCA_NEXT_EVENT_GEN = 1 << 2,
 183         MTHCA_NEXT_SOLICIT   = 1 << 1,
 184
 185         MTHCA_MLX_VL15       = 1 << 17,
 186         MTHCA_MLX_SLR        = 1 << 16
 187 };
 188
 189 struct mthca_next_seg {
 190         u32 nda_op;             /* [31:6] next WQE [4:0] next opcode */
 191         u32 ee_nds;             /* [31:8] next EE  [7] DBD [6] F [5:0] next WQE size */
 192         u32 flags;              /* [3] CQ [2] Event [1] Solicit */
 193         u32 imm;                /* immediate data */
 194 };
 195
 196 struct mthca_ud_seg {
 197         u32 reserved1;
 198         u32 lkey;
 199         u64 av_addr;
 200         u32 reserved2[4];
 201         u32 dqpn;
 202         u32 qkey;
 203         u32 reserved3[2];
 204 };
 205
 206 struct mthca_bind_seg {
 207         u32 flags;              /* [31] Atomic [30] rem write [29] rem read */
 208         u32 reserved;
 209         u32 new_rkey;
 210         u32 lkey;
 211         u64 addr;
 212         u64 length;
 213 };
 214
 215 struct mthca_raddr_seg {
 216         u64 raddr;
 217         u32 rkey;
 218         u32 reserved;
 219 };
 220
 221 struct mthca_atomic_seg {
 222         u64 swap_add;
 223         u64 compare;
 224 };
 225
 226 struct mthca_data_seg {
 227         u32 byte_count;
 228         u32 lkey;
 229         u64 addr;
 230 };
 231
 232 struct mthca_mlx_seg {
 233         u32 nda_op;
 234         u32 nds;
 235         u32 flags;              /* [17] VL15 [16] SLR [14:12] static rate
 236                                    [11:8] SL [3] C [2] E */
 237         u16 rlid;
 238         u16 vcrc;
 239 };
 240
 241 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 242 {
 243         return qp->qpn >= dev->qp_table.sqp_start &&
 244                 qp->qpn <= dev->qp_table.sqp_start + 3;
 245 }
 246
 247 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 248 {
 249         return qp->qpn >= dev->qp_table.sqp_start &&
 250                 qp->qpn <= dev->qp_table.sqp_start + 1;
 251 }
 252
 253 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 254 {
 255         if (qp->is_direct)
 256                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 257         else
 258                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 259                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 260 }
 261
 262 static void *get_send_wqe(struct mthca_qp *qp, int n)
 263 {
 264         if (qp->is_direct)
 265                 return qp->queue.direct.buf + qp->send_wqe_offset +
 266                         (n << qp->sq.wqe_shift);
 267         else
 268                 return qp->queue.page_list[(qp->send_wqe_offset +
 269                                             (n << qp->sq.wqe_shift)) >>
 270                                            PAGE_SHIFT].buf +
 271                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 272                          (PAGE_SIZE - 1));
 273 }
 274
 275 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 276                     enum ib_event_type event_type)
 277 {
 278         struct mthca_qp *qp;
 279         struct ib_event event;
 280
 281         spin_lock(&dev->qp_table.lock);
 282         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 283         if (qp)
 284                 atomic_inc(&qp->refcount);
 285         spin_unlock(&dev->qp_table.lock);
 286
 287         if (!qp) {
 288                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 289                 return;
 290         }
 291
 292         event.device      = &dev->ib_dev;
 293         event.event       = event_type;
 294         event.element.qp  = &qp->ibqp;
 295         if (qp->ibqp.event_handler)
 296                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 297
 298         if (atomic_dec_and_test(&qp->refcount))
 299                 wake_up(&qp->wait);
 300 }
 301
 302 static int to_mthca_state(enum ib_qp_state ib_state)
 303 {
 304         switch (ib_state) {
 305         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 306         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 307         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 308         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 309         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 310         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 311         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 312         default:                return -1;
 313         }
 314 }
 315
 316 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 317
 318 static int to_mthca_st(int transport)
 319 {
 320         switch (transport) {
 321         case RC:  return MTHCA_QP_ST_RC;
 322         case UC:  return MTHCA_QP_ST_UC;
 323         case UD:  return MTHCA_QP_ST_UD;
 324         case RD:  return MTHCA_QP_ST_RD;
 325         case MLX: return MTHCA_QP_ST_MLX;
 326         default:  return -1;
 327         }
 328 }
 329
 330 static const struct {
 331         int trans;
 332         u32 req_param[NUM_TRANS];
 333         u32 opt_param[NUM_TRANS];
 334 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 335         [IB_QPS_RESET] = {
 336                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 337                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 338                 [IB_QPS_INIT]  = {
 339                         .trans = MTHCA_TRANS_RST2INIT,
 340                         .req_param = {
 341                                 [UD]  = (IB_QP_PKEY_INDEX |
 342                                          IB_QP_PORT       |
 343                                          IB_QP_QKEY),
 344                                 [RC]  = (IB_QP_PKEY_INDEX |
 345                                          IB_QP_PORT       |
 346                                          IB_QP_ACCESS_FLAGS),
 347                                 [MLX] = (IB_QP_PKEY_INDEX |
 348                                          IB_QP_QKEY),
 349                         },
 350                         /* bug-for-bug compatibility with VAPI: */
 351                         .opt_param = {
 352                                 [MLX] = IB_QP_PORT
 353                         }
 354                 },
 355         },
 356         [IB_QPS_INIT]  = {
 357                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 358                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 359                 [IB_QPS_INIT]  = {
 360                         .trans = MTHCA_TRANS_INIT2INIT,
 361                         .opt_param = {
 362                                 [UD]  = (IB_QP_PKEY_INDEX |
 363                                          IB_QP_PORT       |
 364                                          IB_QP_QKEY),
 365                                 [RC]  = (IB_QP_PKEY_INDEX |
 366                                          IB_QP_PORT       |
 367                                          IB_QP_ACCESS_FLAGS),
 368                                 [MLX] = (IB_QP_PKEY_INDEX |
 369                                          IB_QP_QKEY),
 370                         }
 371                 },
 372                 [IB_QPS_RTR]   = {
 373                         .trans = MTHCA_TRANS_INIT2RTR,
 374                         .req_param = {
 375                                 [RC]  = (IB_QP_AV                  |
 376                                          IB_QP_PATH_MTU            |
 377                                          IB_QP_DEST_QPN            |
 378                                          IB_QP_RQ_PSN              |
 379                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 380                                          IB_QP_MIN_RNR_TIMER),
 381                         },
 382                         .opt_param = {
 383                                 [UD]  = (IB_QP_PKEY_INDEX |
 384                                          IB_QP_QKEY),
 385                                 [RC]  = (IB_QP_ALT_PATH     |
 386                                          IB_QP_ACCESS_FLAGS |
 387                                          IB_QP_PKEY_INDEX),
 388                                 [MLX] = (IB_QP_PKEY_INDEX |
 389                                          IB_QP_QKEY),
 390                         }
 391                 }
 392         },
 393         [IB_QPS_RTR]   = {
 394                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 395                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 396                 [IB_QPS_RTS]   = {
 397                         .trans = MTHCA_TRANS_RTR2RTS,
 398                         .req_param = {
 399                                 [UD]  = IB_QP_SQ_PSN,
 400                                 [RC]  = (IB_QP_TIMEOUT           |
 401                                          IB_QP_RETRY_CNT         |
 402                                          IB_QP_RNR_RETRY         |
 403                                          IB_QP_SQ_PSN            |
 404                                          IB_QP_MAX_QP_RD_ATOMIC),
 405                                 [MLX] = IB_QP_SQ_PSN,
 406                         },
 407                         .opt_param = {
 408                                 [UD]  = (IB_QP_CUR_STATE             |
 409                                          IB_QP_QKEY),
 410                                 [RC]  = (IB_QP_CUR_STATE             |
 411                                          IB_QP_ALT_PATH              |
 412                                          IB_QP_ACCESS_FLAGS          |
 413                                          IB_QP_PKEY_INDEX            |
 414                                          IB_QP_MIN_RNR_TIMER         |
 415                                          IB_QP_PATH_MIG_STATE),
 416                                 [MLX] = (IB_QP_CUR_STATE             |
 417                                          IB_QP_QKEY),
 418                         }
 419                 }
 420         },
 421         [IB_QPS_RTS]   = {
 422                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 423                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 424                 [IB_QPS_RTS]   = {
 425                         .trans = MTHCA_TRANS_RTS2RTS,
 426                         .opt_param = {
 427                                 [UD]  = (IB_QP_CUR_STATE             |
 428                                          IB_QP_QKEY),
 429                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 430                                          IB_QP_ALT_PATH              |
 431                                          IB_QP_PATH_MIG_STATE        |
 432                                          IB_QP_MIN_RNR_TIMER),
 433                                 [MLX] = (IB_QP_CUR_STATE             |
 434                                          IB_QP_QKEY),
 435                         }
 436                 },
 437                 [IB_QPS_SQD]   = {
 438                         .trans = MTHCA_TRANS_RTS2SQD,
 439                 },
 440         },
 441         [IB_QPS_SQD]   = {
 442                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 443                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 444                 [IB_QPS_RTS]   = {
 445                         .trans = MTHCA_TRANS_SQD2RTS,
 446                         .opt_param = {
 447                                 [UD]  = (IB_QP_CUR_STATE             |
 448                                          IB_QP_QKEY),
 449                                 [RC]  = (IB_QP_CUR_STATE             |
 450                                          IB_QP_ALT_PATH              |
 451                                          IB_QP_ACCESS_FLAGS          |
 452                                          IB_QP_MIN_RNR_TIMER         |
 453                                          IB_QP_PATH_MIG_STATE),
 454                                 [MLX] = (IB_QP_CUR_STATE             |
 455                                          IB_QP_QKEY),
 456                         }
 457                 },
 458                 [IB_QPS_SQD]   = {
 459                         .trans = MTHCA_TRANS_SQD2SQD,
 460                         .opt_param = {
 461                                 [UD]  = (IB_QP_PKEY_INDEX            |
 462                                          IB_QP_QKEY),
 463                                 [RC]  = (IB_QP_AV                    |
 464                                          IB_QP_TIMEOUT               |
 465                                          IB_QP_RETRY_CNT             |
 466                                          IB_QP_RNR_RETRY             |
 467                                          IB_QP_MAX_QP_RD_ATOMIC      |
 468                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 469                                          IB_QP_CUR_STATE             |
 470                                          IB_QP_ALT_PATH              |
 471                                          IB_QP_ACCESS_FLAGS          |
 472                                          IB_QP_PKEY_INDEX            |
 473                                          IB_QP_MIN_RNR_TIMER         |
 474                                          IB_QP_PATH_MIG_STATE),
 475                                 [MLX] = (IB_QP_PKEY_INDEX            |
 476                                          IB_QP_QKEY),
 477                         }
 478                 }
 479         },
 480         [IB_QPS_SQE]   = {
 481                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 482                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 483                 [IB_QPS_RTS]   = {
 484                         .trans = MTHCA_TRANS_SQERR2RTS,
 485                         .opt_param = {
 486                                 [UD]  = (IB_QP_CUR_STATE             |
 487                                          IB_QP_QKEY),
 488                                 [RC]  = (IB_QP_CUR_STATE             |
 489                                          IB_QP_MIN_RNR_TIMER),
 490                                 [MLX] = (IB_QP_CUR_STATE             |
 491                                          IB_QP_QKEY),
 492                         }
 493                 }
 494         },
 495         [IB_QPS_ERR] = {
 496                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 497                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 498         }
 499 };
 500
 501 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 502                         int attr_mask)
 503 {
 504         if (attr_mask & IB_QP_PKEY_INDEX)
 505                 sqp->pkey_index = attr->pkey_index;
 506         if (attr_mask & IB_QP_QKEY)
 507                 sqp->qkey = attr->qkey;
 508         if (attr_mask & IB_QP_SQ_PSN)
 509                 sqp->send_psn = attr->sq_psn;
 510 }
 511
 512 static void init_port(struct mthca_dev *dev, int port)
 513 {
 514         int err;
 515         u8 status;
 516         struct mthca_init_ib_param param;
 517
 518         memset(&param, 0, sizeof param);
 519
 520         param.enable_1x = 1;
 521         param.enable_4x = 1;
 522         param.vl_cap    = dev->limits.vl_cap;
 523         param.mtu_cap   = dev->limits.mtu_cap;
 524         param.gid_cap   = dev->limits.gid_table_len;
 525         param.pkey_cap  = dev->limits.pkey_table_len;
 526
 527         err = mthca_INIT_IB(dev, &param, port, &status);
 528         if (err)
 529                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 530         if (status)
 531                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 532 }
 533
 534 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 535 {
 536         struct mthca_dev *dev = to_mdev(ibqp->device);
 537         struct mthca_qp *qp = to_mqp(ibqp);
 538         enum ib_qp_state cur_state, new_state;
 539         void *mailbox = NULL;
 540         struct mthca_qp_param *qp_param;
 541         struct mthca_qp_context *qp_context;
 542         u32 req_param, opt_param;
 543         u8 status;
 544         int err;
 545
 546         if (attr_mask & IB_QP_CUR_STATE) {
 547                 if (attr->cur_qp_state != IB_QPS_RTR &&
 548                     attr->cur_qp_state != IB_QPS_RTS &&
 549                     attr->cur_qp_state != IB_QPS_SQD &&
 550                     attr->cur_qp_state != IB_QPS_SQE)
 551                         return -EINVAL;
 552                 else
 553                         cur_state = attr->cur_qp_state;
 554         } else {
 555                 spin_lock_irq(&qp->lock);
 556                 cur_state = qp->state;
 557                 spin_unlock_irq(&qp->lock);
 558         }
 559
 560         if (attr_mask & IB_QP_STATE) {
 561                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 562                         return -EINVAL;
 563                 new_state = attr->qp_state;
 564         } else
 565                 new_state = cur_state;
 566
 567         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 568                 mthca_dbg(dev, "Illegal QP transition "
 569                           "%d->%d\n", cur_state, new_state);
 570                 return -EINVAL;
 571         }
 572
 573         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 574         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 575
 576         if ((req_param & attr_mask) != req_param) {
 577                 mthca_dbg(dev, "QP transition "
 578                           "%d->%d missing req attr 0x%08x\n",
 579                           cur_state, new_state,
 580                           req_param & ~attr_mask);
 581                 return -EINVAL;
 582         }
 583
 584         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 585                 mthca_dbg(dev, "QP transition (transport %d) "
 586                           "%d->%d has extra attr 0x%08x\n",
 587                           qp->transport,
 588                           cur_state, new_state,
 589                           attr_mask & ~(req_param | opt_param |
 590                                                  IB_QP_STATE));
 591                 return -EINVAL;
 592         }
 593
 594         mailbox = kmalloc(sizeof (*qp_param) + MTHCA_CMD_MAILBOX_EXTRA, GFP_KERNEL);
 595         if (!mailbox)
 596                 return -ENOMEM;
 597         qp_param = MAILBOX_ALIGN(mailbox);
 598         qp_context = &qp_param->context;
 599         memset(qp_param, 0, sizeof *qp_param);
 600
 601         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 602                                              (to_mthca_st(qp->transport) << 16));
 603         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 604         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 605                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 606         else {
 607                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 608                 switch (attr->path_mig_state) {
 609                 case IB_MIG_MIGRATED:
 610                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 611                         break;
 612                 case IB_MIG_REARM:
 613                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 614                         break;
 615                 case IB_MIG_ARMED:
 616                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 617                         break;
 618                 }
 619         }
 620         /* leave sched_queue as 0 */
 621         if (qp->transport == MLX || qp->transport == UD)
 622                 qp_context->mtu_msgmax = cpu_to_be32((IB_MTU_2048 << 29) |
 623                                                      (11 << 24));
 624         else if (attr_mask & IB_QP_PATH_MTU) {
 625                 qp_context->mtu_msgmax = cpu_to_be32((attr->path_mtu << 29) |
 626                                                      (31 << 24));
 627         }
 628         qp_context->usr_page   = cpu_to_be32(MTHCA_KAR_PAGE);
 629         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 630         if (attr_mask & IB_QP_DEST_QPN) {
 631                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 632         }
 633
 634         if (qp->transport == MLX)
 635                 qp_context->pri_path.port_pkey |=
 636                         cpu_to_be32(to_msqp(qp)->port << 24);
 637         else {
 638                 if (attr_mask & IB_QP_PORT) {
 639                         qp_context->pri_path.port_pkey |=
 640                                 cpu_to_be32(attr->port_num << 24);
 641                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 642                 }
 643         }
 644
 645         if (attr_mask & IB_QP_PKEY_INDEX) {
 646                 qp_context->pri_path.port_pkey |=
 647                         cpu_to_be32(attr->pkey_index);
 648                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 649         }
 650
 651         if (attr_mask & IB_QP_RNR_RETRY) {
 652                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 653                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 654         }
 655
 656         if (attr_mask & IB_QP_AV) {
 657                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 658                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 659                 qp_context->pri_path.static_rate = (!!attr->ah_attr.static_rate) << 3;
 660                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 661                         qp_context->pri_path.g_mylmc |= 1 << 7;
 662                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 663                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 664                         qp_context->pri_path.sl_tclass_flowlabel =
 665                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 666                                             (attr->ah_attr.grh.traffic_class << 20) |
 667                                             (attr->ah_attr.grh.flow_label));
 668                         memcpy(qp_context->pri_path.rgid,
 669                                attr->ah_attr.grh.dgid.raw, 16);
 670                 } else {
 671                         qp_context->pri_path.sl_tclass_flowlabel =
 672                                 cpu_to_be32(attr->ah_attr.sl << 28);
 673                 }
 674                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 675         }
 676
 677         if (attr_mask & IB_QP_TIMEOUT) {
 678                 qp_context->pri_path.ackto = attr->timeout;
 679                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 680         }
 681
 682         /* XXX alt_path */
 683
 684         /* leave rdd as 0 */
 685         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 686         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 687         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 688         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 689                                              (MTHCA_FLIGHT_LIMIT << 24) |
 690                                              MTHCA_QP_BIT_SRE           |
 691                                              MTHCA_QP_BIT_SWE           |
 692                                              MTHCA_QP_BIT_SAE);
 693         if (qp->sq.policy == IB_SIGNAL_ALL_WR)
 694                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 695         if (attr_mask & IB_QP_RETRY_CNT) {
 696                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 697                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 698         }
 699
 700         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 701                 qp_context->params1 |= cpu_to_be32(min(attr->max_dest_rd_atomic ?
 702                                                        ffs(attr->max_dest_rd_atomic) - 1 : 0,
 703                                                        7) << 21);
 704                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 705         }
 706
 707         if (attr_mask & IB_QP_SQ_PSN)
 708                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 709         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 710
 711         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 712                 /*
 713                  * Only enable RDMA/atomics if we have responder
 714                  * resources set to a non-zero value.
 715                  */
 716                 if (qp->resp_depth) {
 717                         qp_context->params2 |=
 718                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 719                                             MTHCA_QP_BIT_RWE : 0);
 720                         qp_context->params2 |=
 721                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 722                                             MTHCA_QP_BIT_RRE : 0);
 723                         qp_context->params2 |=
 724                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 725                                             MTHCA_QP_BIT_RAE : 0);
 726                 }
 727
 728                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 729                                                         MTHCA_QP_OPTPAR_RRE |
 730                                                         MTHCA_QP_OPTPAR_RAE);
 731
 732                 qp->atomic_rd_en = attr->qp_access_flags;
 733         }
 734
 735         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 736                 u8 rra_max;
 737
 738                 if (qp->resp_depth && !attr->max_rd_atomic) {
 739                         /*
 740                          * Lowering our responder resources to zero.
 741                          * Turn off RDMA/atomics as responder.
 742                          * (RWE/RRE/RAE in params2 already zero)
 743                          */
 744                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 745                                                                 MTHCA_QP_OPTPAR_RRE |
 746                                                                 MTHCA_QP_OPTPAR_RAE);
 747                 }
 748
 749                 if (!qp->resp_depth && attr->max_rd_atomic) {
 750                         /*
 751                          * Increasing our responder resources from
 752                          * zero.  Turn on RDMA/atomics as appropriate.
 753                          */
 754                         qp_context->params2 |=
 755                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
 756                                             MTHCA_QP_BIT_RWE : 0);
 757                         qp_context->params2 |=
 758                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 759                                             MTHCA_QP_BIT_RRE : 0);
 760                         qp_context->params2 |=
 761                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 762                                             MTHCA_QP_BIT_RAE : 0);
 763
 764                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 765                                                                 MTHCA_QP_OPTPAR_RRE |
 766                                                                 MTHCA_QP_OPTPAR_RAE);
 767                 }
 768
 769                 for (rra_max = 0;
 770                      1 << rra_max < attr->max_rd_atomic &&
 771                              rra_max < dev->qp_table.rdb_shift;
 772                      ++rra_max)
 773                         ; /* nothing */
 774
 775                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 776                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 777
 778                 qp->resp_depth = attr->max_rd_atomic;
 779         }
 780
 781         if (qp->rq.policy == IB_SIGNAL_ALL_WR)
 782                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 783         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 784                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 785                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 786         }
 787         if (attr_mask & IB_QP_RQ_PSN)
 788                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 789
 790         qp_context->ra_buff_indx = dev->qp_table.rdb_base +
 791                 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 792                  dev->qp_table.rdb_shift);
 793
 794         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 795
 796         if (attr_mask & IB_QP_QKEY) {
 797                 qp_context->qkey = cpu_to_be32(attr->qkey);
 798                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 799         }
 800
 801         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 802                               qp->qpn, 0, qp_param, 0, &status);
 803         if (status) {
 804                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 805                            state_table[cur_state][new_state].trans, status);
 806                 err = -EINVAL;
 807         }
 808
 809         if (!err)
 810                 qp->state = new_state;
 811
 812         kfree(mailbox);
 813
 814         if (is_sqp(dev, qp))
 815                 store_attrs(to_msqp(qp), attr, attr_mask);
 816
 817         /*
 818          * If we are moving QP0 to RTR, bring the IB link up; if we
 819          * are moving QP0 to RESET or ERROR, bring the link back down.
 820          */
 821         if (is_qp0(dev, qp)) {
 822                 if (cur_state != IB_QPS_RTR &&
 823                     new_state == IB_QPS_RTR)
 824                         init_port(dev, to_msqp(qp)->port);
 825
 826                 if (cur_state != IB_QPS_RESET &&
 827                     cur_state != IB_QPS_ERR &&
 828                     (new_state == IB_QPS_RESET ||
 829                      new_state == IB_QPS_ERR))
 830                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 831         }
 832
 833         return err;
 834 }
 835
 836 /*
 837  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 838  * rq.max_gs and sq.max_gs must all be assigned.
 839  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 840  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 841  * queue)
 842  */
 843 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 844                                struct mthca_pd *pd,
 845                                struct mthca_qp *qp)
 846 {
 847         int size;
 848         int i;
 849         int npages, shift;
 850         dma_addr_t t;
 851         u64 *dma_list = NULL;
 852         int err = -ENOMEM;
 853
 854         size = sizeof (struct mthca_next_seg) +
 855                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 856
 857         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 858              qp->rq.wqe_shift++)
 859                 ; /* nothing */
 860
 861         size = sizeof (struct mthca_next_seg) +
 862                 qp->sq.max_gs * sizeof (struct mthca_data_seg);
 863         if (qp->transport == MLX)
 864                 size += 2 * sizeof (struct mthca_data_seg);
 865         else if (qp->transport == UD)
 866                 size += sizeof (struct mthca_ud_seg);
 867         else /* bind seg is as big as atomic + raddr segs */
 868                 size += sizeof (struct mthca_bind_seg);
 869
 870         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 871              qp->sq.wqe_shift++)
 872                 ; /* nothing */
 873
 874         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 875                                     1 << qp->sq.wqe_shift);
 876         size = PAGE_ALIGN(qp->send_wqe_offset +
 877                           (qp->sq.max << qp->sq.wqe_shift));
 878
 879         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 880                            GFP_KERNEL);
 881         if (!qp->wrid)
 882                 goto err_out;
 883
 884         if (size <= MTHCA_MAX_DIRECT_QP_SIZE) {
 885                 qp->is_direct = 1;
 886                 npages = 1;
 887                 shift = get_order(size) + PAGE_SHIFT;
 888
 889                 if (0)
 890                         mthca_dbg(dev, "Creating direct QP of size %d (shift %d)\n",
 891                                   size, shift);
 892
 893                 qp->queue.direct.buf = pci_alloc_consistent(dev->pdev, size, &t);
 894                 if (!qp->queue.direct.buf)
 895                         goto err_out;
 896
 897                 pci_unmap_addr_set(&qp->queue.direct, mapping, t);
 898
 899                 memset(qp->queue.direct.buf, 0, size);
 900
 901                 while (t & ((1 << shift) - 1)) {
 902                         --shift;
 903                         npages *= 2;
 904                 }
 905
 906                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 907                 if (!dma_list)
 908                         goto err_out_free;
 909
 910                 for (i = 0; i < npages; ++i)
 911                         dma_list[i] = t + i * (1 << shift);
 912         } else {
 913                 qp->is_direct = 0;
 914                 npages = size / PAGE_SIZE;
 915                 shift = PAGE_SHIFT;
 916
 917                 if (0)
 918                         mthca_dbg(dev, "Creating indirect QP with %d pages\n", npages);
 919
 920                 dma_list = kmalloc(npages * sizeof *dma_list, GFP_KERNEL);
 921                 if (!dma_list)
 922                         goto err_out;
 923
 924                 qp->queue.page_list = kmalloc(npages *
 925                                               sizeof *qp->queue.page_list,
 926                                               GFP_KERNEL);
 927                 if (!qp->queue.page_list)
 928                         goto err_out;
 929
 930                 for (i = 0; i < npages; ++i) {
 931                         qp->queue.page_list[i].buf =
 932                                 pci_alloc_consistent(dev->pdev, PAGE_SIZE, &t);
 933                         if (!qp->queue.page_list[i].buf)
 934                                 goto err_out_free;
 935
 936                         memset(qp->queue.page_list[i].buf, 0, PAGE_SIZE);
 937
 938                         pci_unmap_addr_set(&qp->queue.page_list[i], mapping, t);
 939                         dma_list[i] = t;
 940                 }
 941         }
 942
 943         err = mthca_mr_alloc_phys(dev, pd->pd_num, dma_list, shift,
 944                                   npages, 0, size,
 945                                   MTHCA_MPT_FLAG_LOCAL_WRITE |
 946                                   MTHCA_MPT_FLAG_LOCAL_READ,
 947                                   &qp->mr);
 948         if (err)
 949                 goto err_out_free;
 950
 951         kfree(dma_list);
 952         return 0;
 953
 954  err_out_free:
 955         if (qp->is_direct) {
 956                 pci_free_consistent(dev->pdev, size,
 957                                     qp->queue.direct.buf,
 958                                     pci_unmap_addr(&qp->queue.direct, mapping));
 959         } else
 960                 for (i = 0; i < npages; ++i) {
 961                         if (qp->queue.page_list[i].buf)
 962                                 pci_free_consistent(dev->pdev, PAGE_SIZE,
 963                                                     qp->queue.page_list[i].buf,
 964                                                     pci_unmap_addr(&qp->queue.page_list[i],
 965                                                                    mapping));
 966
 967                 }
 968
 969  err_out:
 970         kfree(qp->wrid);
 971         kfree(dma_list);
 972         return err;
 973 }
 974
 975 static int mthca_alloc_qp_common(struct mthca_dev *dev,
 976                                  struct mthca_pd *pd,
 977                                  struct mthca_cq *send_cq,
 978                                  struct mthca_cq *recv_cq,
 979                                  enum ib_sig_type send_policy,
 980                                  enum ib_sig_type recv_policy,
 981                                  struct mthca_qp *qp)
 982 {
 983         int err;
 984
 985         spin_lock_init(&qp->lock);
 986         atomic_set(&qp->refcount, 1);
 987         qp->state        = IB_QPS_RESET;
 988         qp->atomic_rd_en = 0;
 989         qp->resp_depth   = 0;
 990         qp->sq.policy    = send_policy;
 991         qp->rq.policy    = recv_policy;
 992         qp->rq.cur       = 0;
 993         qp->sq.cur       = 0;
 994         qp->rq.next      = 0;
 995         qp->sq.next      = 0;
 996         qp->rq.last_comp = qp->rq.max - 1;
 997         qp->sq.last_comp = qp->sq.max - 1;
 998         qp->rq.last      = NULL;
 999         qp->sq.last      = NULL;
1000
1001         err = mthca_alloc_wqe_buf(dev, pd, qp);
1002         return err;
1003 }
1004
1005 int mthca_alloc_qp(struct mthca_dev *dev,
1006                    struct mthca_pd *pd,
1007                    struct mthca_cq *send_cq,
1008                    struct mthca_cq *recv_cq,
1009                    enum ib_qp_type type,
1010                    enum ib_sig_type send_policy,
1011                    enum ib_sig_type recv_policy,
1012                    struct mthca_qp *qp)
1013 {
1014         int err;
1015
1016         switch (type) {
1017         case IB_QPT_RC: qp->transport = RC; break;
1018         case IB_QPT_UC: qp->transport = UC; break;
1019         case IB_QPT_UD: qp->transport = UD; break;
1020         default: return -EINVAL;
1021         }
1022
1023         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1024         if (qp->qpn == -1)
1025                 return -ENOMEM;
1026
1027         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1028                                     send_policy, recv_policy, qp);
1029         if (err) {
1030                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1031                 return err;
1032         }
1033
1034         spin_lock_irq(&dev->qp_table.lock);
1035         mthca_array_set(&dev->qp_table.qp,
1036                         qp->qpn & (dev->limits.num_qps - 1), qp);
1037         spin_unlock_irq(&dev->qp_table.lock);
1038
1039         return 0;
1040 }
1041
1042 int mthca_alloc_sqp(struct mthca_dev *dev,
1043                     struct mthca_pd *pd,
1044                     struct mthca_cq *send_cq,
1045                     struct mthca_cq *recv_cq,
1046                     enum ib_sig_type send_policy,
1047                     enum ib_sig_type recv_policy,
1048                     int qpn,
1049                     int port,
1050                     struct mthca_sqp *sqp)
1051 {
1052         int err = 0;
1053         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1054
1055         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1056         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1057                                              &sqp->header_dma, GFP_KERNEL);
1058         if (!sqp->header_buf)
1059                 return -ENOMEM;
1060
1061         spin_lock_irq(&dev->qp_table.lock);
1062         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1063                 err = -EBUSY;
1064         else
1065                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1066         spin_unlock_irq(&dev->qp_table.lock);
1067
1068         if (err)
1069                 goto err_out;
1070
1071         sqp->port = port;
1072         sqp->qp.qpn       = mqpn;
1073         sqp->qp.transport = MLX;
1074
1075         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1076                                     send_policy, recv_policy,
1077                                     &sqp->qp);
1078         if (err)
1079                 goto err_out_free;
1080
1081         atomic_inc(&pd->sqp_count);
1082
1083         return 0;
1084
1085  err_out_free:
1086         spin_lock_irq(&dev->qp_table.lock);
1087         mthca_array_clear(&dev->qp_table.qp, mqpn);
1088         spin_unlock_irq(&dev->qp_table.lock);
1089
1090  err_out:
1091         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1092                           sqp->header_buf, sqp->header_dma);
1093
1094         return err;
1095 }
1096
1097 void mthca_free_qp(struct mthca_dev *dev,
1098                    struct mthca_qp *qp)
1099 {
1100         u8 status;
1101         int size;
1102         int i;
1103
1104         spin_lock_irq(&dev->qp_table.lock);
1105         mthca_array_clear(&dev->qp_table.qp,
1106                           qp->qpn & (dev->limits.num_qps - 1));
1107         spin_unlock_irq(&dev->qp_table.lock);
1108
1109         atomic_dec(&qp->refcount);
1110         wait_event(qp->wait, !atomic_read(&qp->refcount));
1111
1112         if (qp->state != IB_QPS_RESET)
1113                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1114
1115         mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn);
1116         if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1117                 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn);
1118
1119         mthca_free_mr(dev, &qp->mr);
1120
1121         size = PAGE_ALIGN(qp->send_wqe_offset +
1122                           (qp->sq.max << qp->sq.wqe_shift));
1123
1124         if (qp->is_direct) {
1125                 pci_free_consistent(dev->pdev, size,
1126                                     qp->queue.direct.buf,
1127                                     pci_unmap_addr(&qp->queue.direct, mapping));
1128         } else {
1129                 for (i = 0; i < size / PAGE_SIZE; ++i) {
1130                         pci_free_consistent(dev->pdev, PAGE_SIZE,
1131                                             qp->queue.page_list[i].buf,
1132                                             pci_unmap_addr(&qp->queue.page_list[i],
1133                                                            mapping));
1134                 }
1135         }
1136
1137         kfree(qp->wrid);
1138
1139         if (is_sqp(dev, qp)) {
1140                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1141                 dma_free_coherent(&dev->pdev->dev,
1142                                   to_msqp(qp)->header_buf_size,
1143                                   to_msqp(qp)->header_buf,
1144                                   to_msqp(qp)->header_dma);
1145         }
1146         else
1147                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1148 }
1149
1150 /* Create UD header for an MLX send and build a data segment for it */
1151 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1152                             int ind, struct ib_send_wr *wr,
1153                             struct mthca_mlx_seg *mlx,
1154                             struct mthca_data_seg *data)
1155 {
1156         int header_size;
1157         int err;
1158
1159         ib_ud_header_init(256, /* assume a MAD */
1160                           sqp->ud_header.grh_present,
1161                           &sqp->ud_header);
1162
1163         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1164         if (err)
1165                 return err;
1166         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1167         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1168                                   (sqp->ud_header.lrh.destination_lid == 0xffff ?
1169                                    MTHCA_MLX_SLR : 0) |
1170                                   (sqp->ud_header.lrh.service_level << 8));
1171         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1172         mlx->vcrc = 0;
1173
1174         switch (wr->opcode) {
1175         case IB_WR_SEND:
1176                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1177                 sqp->ud_header.immediate_present = 0;
1178                 break;
1179         case IB_WR_SEND_WITH_IMM:
1180                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1181                 sqp->ud_header.immediate_present = 1;
1182                 sqp->ud_header.immediate_data = wr->imm_data;
1183                 break;
1184         default:
1185                 return -EINVAL;
1186         }
1187
1188         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1189         if (sqp->ud_header.lrh.destination_lid == 0xffff)
1190                 sqp->ud_header.lrh.source_lid = 0xffff;
1191         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1192         if (!sqp->qp.ibqp.qp_num)
1193                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1194                                    sqp->pkey_index,
1195                                    &sqp->ud_header.bth.pkey);
1196         else
1197                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1198                                    wr->wr.ud.pkey_index,
1199                                    &sqp->ud_header.bth.pkey);
1200         cpu_to_be16s(&sqp->ud_header.bth.pkey);
1201         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1202         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1203         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1204                                                sqp->qkey : wr->wr.ud.remote_qkey);
1205         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1206
1207         header_size = ib_ud_header_pack(&sqp->ud_header,
1208                                         sqp->header_buf +
1209                                         ind * MTHCA_UD_HEADER_SIZE);
1210
1211         data->byte_count = cpu_to_be32(header_size);
1212         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1213         data->addr       = cpu_to_be64(sqp->header_dma +
1214                                        ind * MTHCA_UD_HEADER_SIZE);
1215
1216         return 0;
1217 }
1218
1219 int mthca_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1220                     struct ib_send_wr **bad_wr)
1221 {
1222         struct mthca_dev *dev = to_mdev(ibqp->device);
1223         struct mthca_qp *qp = to_mqp(ibqp);
1224         void *wqe;
1225         void *prev_wqe;
1226         unsigned long flags;
1227         int err = 0;
1228         int nreq;
1229         int i;
1230         int size;
1231         int size0 = 0;
1232         u32 f0 = 0;
1233         int ind;
1234         u8 op0 = 0;
1235
1236         static const u8 opcode[] = {
1237                 [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
1238                 [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
1239                 [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
1240                 [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
1241                 [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
1242                 [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
1243                 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
1244         };
1245
1246         spin_lock_irqsave(&qp->lock, flags);
1247
1248         /* XXX check that state is OK to post send */
1249
1250         ind = qp->sq.next;
1251
1252         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1253                 if (qp->sq.cur + nreq >= qp->sq.max) {
1254                         mthca_err(dev, "SQ full (%d posted, %d max, %d nreq)\n",
1255                                   qp->sq.cur, qp->sq.max, nreq);
1256                         err = -ENOMEM;
1257                         *bad_wr = wr;
1258                         goto out;
1259                 }
1260
1261                 wqe = get_send_wqe(qp, ind);
1262                 prev_wqe = qp->sq.last;
1263                 qp->sq.last = wqe;
1264
1265                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1266                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1267                 ((struct mthca_next_seg *) wqe)->flags =
1268                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1269                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1270                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1271                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1272                         cpu_to_be32(1);
1273                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1274                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1275                         ((struct mthca_next_seg *) wqe)->flags = wr->imm_data;
1276
1277                 wqe += sizeof (struct mthca_next_seg);
1278                 size = sizeof (struct mthca_next_seg) / 16;
1279
1280                 switch (qp->transport) {
1281                 case RC:
1282                         switch (wr->opcode) {
1283                         case IB_WR_ATOMIC_CMP_AND_SWP:
1284                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1285                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1286                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1287                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1288                                         cpu_to_be32(wr->wr.atomic.rkey);
1289                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1290
1291                                 wqe += sizeof (struct mthca_raddr_seg);
1292
1293                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1294                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1295                                                 cpu_to_be64(wr->wr.atomic.swap);
1296                                         ((struct mthca_atomic_seg *) wqe)->compare =
1297                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1298                                 } else {
1299                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1300                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1301                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1302                                 }
1303
1304                                 wqe += sizeof (struct mthca_atomic_seg);
1305                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1306                                         sizeof (struct mthca_atomic_seg);
1307                                 break;
1308
1309                         case IB_WR_RDMA_WRITE:
1310                         case IB_WR_RDMA_WRITE_WITH_IMM:
1311                         case IB_WR_RDMA_READ:
1312                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1313                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1314                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1315                                         cpu_to_be32(wr->wr.rdma.rkey);
1316                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1317                                 wqe += sizeof (struct mthca_raddr_seg);
1318                                 size += sizeof (struct mthca_raddr_seg) / 16;
1319                                 break;
1320
1321                         default:
1322                                 /* No extra segments required for sends */
1323                                 break;
1324                         }
1325
1326                         break;
1327
1328                 case UD:
1329                         ((struct mthca_ud_seg *) wqe)->lkey =
1330                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1331                         ((struct mthca_ud_seg *) wqe)->av_addr =
1332                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1333                         ((struct mthca_ud_seg *) wqe)->dqpn =
1334                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1335                         ((struct mthca_ud_seg *) wqe)->qkey =
1336                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1337
1338                         wqe += sizeof (struct mthca_ud_seg);
1339                         size += sizeof (struct mthca_ud_seg) / 16;
1340                         break;
1341
1342                 case MLX:
1343                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1344                                                wqe - sizeof (struct mthca_next_seg),
1345                                                wqe);
1346                         if (err) {
1347                                 *bad_wr = wr;
1348                                 goto out;
1349                         }
1350                         wqe += sizeof (struct mthca_data_seg);
1351                         size += sizeof (struct mthca_data_seg) / 16;
1352                         break;
1353                 }
1354
1355                 if (wr->num_sge > qp->sq.max_gs) {
1356                         mthca_err(dev, "too many gathers\n");
1357                         err = -EINVAL;
1358                         *bad_wr = wr;
1359                         goto out;
1360                 }
1361
1362                 for (i = 0; i < wr->num_sge; ++i) {
1363                         ((struct mthca_data_seg *) wqe)->byte_count =
1364                                 cpu_to_be32(wr->sg_list[i].length);
1365                         ((struct mthca_data_seg *) wqe)->lkey =
1366                                 cpu_to_be32(wr->sg_list[i].lkey);
1367                         ((struct mthca_data_seg *) wqe)->addr =
1368                                 cpu_to_be64(wr->sg_list[i].addr);
1369                         wqe += sizeof (struct mthca_data_seg);
1370                         size += sizeof (struct mthca_data_seg) / 16;
1371                 }
1372
1373                 /* Add one more inline data segment for ICRC */
1374                 if (qp->transport == MLX) {
1375                         ((struct mthca_data_seg *) wqe)->byte_count =
1376                                 cpu_to_be32((1 << 31) | 4);
1377                         ((u32 *) wqe)[1] = 0;
1378                         wqe += sizeof (struct mthca_data_seg);
1379                         size += sizeof (struct mthca_data_seg) / 16;
1380                 }
1381
1382                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1383
1384                 if (wr->opcode >= ARRAY_SIZE(opcode)) {
1385                         mthca_err(dev, "opcode invalid\n");
1386                         err = -EINVAL;
1387                         *bad_wr = wr;
1388                         goto out;
1389                 }
1390
1391                 if (prev_wqe) {
1392                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1393                                 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1394                                              qp->send_wqe_offset) |
1395                                             opcode[wr->opcode]);
1396                         smp_wmb();
1397                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1398                                 cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1399                 }
1400
1401                 if (!size0) {
1402                         size0 = size;
1403                         op0   = opcode[wr->opcode];
1404                 }
1405
1406                 ++ind;
1407                 if (unlikely(ind >= qp->sq.max))
1408                         ind -= qp->sq.max;
1409         }
1410
1411 out:
1412         if (nreq) {
1413                 u32 doorbell[2];
1414
1415                 doorbell[0] = cpu_to_be32(((qp->sq.next << qp->sq.wqe_shift) +
1416                                            qp->send_wqe_offset) | f0 | op0);
1417                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1418
1419                 wmb();
1420
1421                 mthca_write64(doorbell,
1422                               dev->kar + MTHCA_SEND_DOORBELL,
1423                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1424         }
1425
1426         qp->sq.cur += nreq;
1427         qp->sq.next = ind;
1428
1429         spin_unlock_irqrestore(&qp->lock, flags);
1430         return err;
1431 }
1432
1433 int mthca_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1434                        struct ib_recv_wr **bad_wr)
1435 {
1436         struct mthca_dev *dev = to_mdev(ibqp->device);
1437         struct mthca_qp *qp = to_mqp(ibqp);
1438         unsigned long flags;
1439         int err = 0;
1440         int nreq;
1441         int i;
1442         int size;
1443         int size0 = 0;
1444         int ind;
1445         void *wqe;
1446         void *prev_wqe;
1447
1448         spin_lock_irqsave(&qp->lock, flags);
1449
1450         /* XXX check that state is OK to post receive */
1451
1452         ind = qp->rq.next;
1453
1454         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1455                 if (qp->rq.cur + nreq >= qp->rq.max) {
1456                         mthca_err(dev, "RQ %06x full\n", qp->qpn);
1457                         err = -ENOMEM;
1458                         *bad_wr = wr;
1459                         goto out;
1460                 }
1461
1462                 wqe = get_recv_wqe(qp, ind);
1463                 prev_wqe = qp->rq.last;
1464                 qp->rq.last = wqe;
1465
1466                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1467                 ((struct mthca_next_seg *) wqe)->ee_nds =
1468                         cpu_to_be32(MTHCA_NEXT_DBD);
1469                 ((struct mthca_next_seg *) wqe)->flags =
1470                         (wr->recv_flags & IB_RECV_SIGNALED) ?
1471                         cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0;
1472
1473                 wqe += sizeof (struct mthca_next_seg);
1474                 size = sizeof (struct mthca_next_seg) / 16;
1475
1476                 if (wr->num_sge > qp->rq.max_gs) {
1477                         err = -EINVAL;
1478                         *bad_wr = wr;
1479                         goto out;
1480                 }
1481
1482                 for (i = 0; i < wr->num_sge; ++i) {
1483                         ((struct mthca_data_seg *) wqe)->byte_count =
1484                                 cpu_to_be32(wr->sg_list[i].length);
1485                         ((struct mthca_data_seg *) wqe)->lkey =
1486                                 cpu_to_be32(wr->sg_list[i].lkey);
1487                         ((struct mthca_data_seg *) wqe)->addr =
1488                                 cpu_to_be64(wr->sg_list[i].addr);
1489                         wqe += sizeof (struct mthca_data_seg);
1490                         size += sizeof (struct mthca_data_seg) / 16;
1491                 }
1492
1493                 qp->wrid[ind] = wr->wr_id;
1494
1495                 if (prev_wqe) {
1496                         ((struct mthca_next_seg *) prev_wqe)->nda_op =
1497                                 cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1498                         smp_wmb();
1499                         ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1500                                 cpu_to_be32(MTHCA_NEXT_DBD | size);
1501                 }
1502
1503                 if (!size0)
1504                         size0 = size;
1505
1506                 ++ind;
1507                 if (unlikely(ind >= qp->rq.max))
1508                         ind -= qp->rq.max;
1509         }
1510
1511 out:
1512         if (nreq) {
1513                 u32 doorbell[2];
1514
1515                 doorbell[0] = cpu_to_be32((qp->rq.next << qp->rq.wqe_shift) | size0);
1516                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1517
1518                 wmb();
1519
1520                 mthca_write64(doorbell,
1521                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1522                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1523         }
1524
1525         qp->rq.cur += nreq;
1526         qp->rq.next = ind;
1527
1528         spin_unlock_irqrestore(&qp->lock, flags);
1529         return err;
1530 }
1531
1532 int mthca_free_err_wqe(struct mthca_qp *qp, int is_send,
1533                        int index, int *dbd, u32 *new_wqe)
1534 {
1535         struct mthca_next_seg *next;
1536
1537         if (is_send)
1538                 next = get_send_wqe(qp, index);
1539         else
1540                 next = get_recv_wqe(qp, index);
1541
1542         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
1543         if (next->ee_nds & cpu_to_be32(0x3f))
1544                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
1545                         (next->ee_nds & cpu_to_be32(0x3f));
1546         else
1547                 *new_wqe = 0;
1548
1549         return 0;
1550 }
1551
1552 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
1553 {
1554         int err;
1555         u8 status;
1556         int i;
1557
1558         spin_lock_init(&dev->qp_table.lock);
1559
1560         /*
1561          * We reserve 2 extra QPs per port for the special QPs.  The
1562          * special QP for port 1 has to be even, so round up.
1563          */
1564         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
1565         err = mthca_alloc_init(&dev->qp_table.alloc,
1566                                dev->limits.num_qps,
1567                                (1 << 24) - 1,
1568                                dev->qp_table.sqp_start +
1569                                MTHCA_MAX_PORTS * 2);
1570         if (err)
1571                 return err;
1572
1573         err = mthca_array_init(&dev->qp_table.qp,
1574                                dev->limits.num_qps);
1575         if (err) {
1576                 mthca_alloc_cleanup(&dev->qp_table.alloc);
1577                 return err;
1578         }
1579
1580         for (i = 0; i < 2; ++i) {
1581                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
1582                                             dev->qp_table.sqp_start + i * 2,
1583                                             &status);
1584                 if (err)
1585                         goto err_out;
1586                 if (status) {
1587                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
1588                                    "status %02x, aborting.\n",
1589                                    status);
1590                         err = -EINVAL;
1591                         goto err_out;
1592                 }
1593         }
1594         return 0;
1595
1596  err_out:
1597         for (i = 0; i < 2; ++i)
1598                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
1599
1600         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
1601         mthca_alloc_cleanup(&dev->qp_table.alloc);
1602
1603         return err;
1604 }
1605
1606 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
1607 {
1608         int i;
1609         u8 status;
1610
1611         for (i = 0; i < 2; ++i)
1612                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
1613
1614         mthca_alloc_cleanup(&dev->qp_table.alloc);
1615 }