2 * SGI O2 MACE PS2 controller driver for linux
4 * Copyright (C) 2002 Vivien Chappelier
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation
10 #include <linux/module.h>
11 #include <linux/init.h>
12 #include <linux/serio.h>
13 #include <linux/errno.h>
14 #include <linux/interrupt.h>
15 #include <linux/ioport.h>
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/slab.h>
19 #include <linux/spinlock.h>
23 #include <asm/system.h>
24 #include <asm/ip32/mace.h>
25 #include <asm/ip32/ip32_ints.h>
27 MODULE_AUTHOR("Vivien Chappelier <vivien.chappelier@linux-mips.org");
28 MODULE_DESCRIPTION("SGI O2 MACE PS2 controller driver");
29 MODULE_LICENSE("GPL");
31 #define MACE_PS2_TIMEOUT 10000 /* in 50us unit */
33 #define PS2_STATUS_CLOCK_SIGNAL BIT(0) /* external clock signal */
34 #define PS2_STATUS_CLOCK_INHIBIT BIT(1) /* clken output signal */
35 #define PS2_STATUS_TX_INPROGRESS BIT(2) /* transmission in progress */
36 #define PS2_STATUS_TX_EMPTY BIT(3) /* empty transmit buffer */
37 #define PS2_STATUS_RX_FULL BIT(4) /* full receive buffer */
38 #define PS2_STATUS_RX_INPROGRESS BIT(5) /* reception in progress */
39 #define PS2_STATUS_ERROR_PARITY BIT(6) /* parity error */
40 #define PS2_STATUS_ERROR_FRAMING BIT(7) /* framing error */
42 #define PS2_CONTROL_TX_CLOCK_DISABLE BIT(0) /* inhibit clock signal after TX */
43 #define PS2_CONTROL_TX_ENABLE BIT(1) /* transmit enable */
44 #define PS2_CONTROL_TX_INT_ENABLE BIT(2) /* enable transmit interrupt */
45 #define PS2_CONTROL_RX_INT_ENABLE BIT(3) /* enable receive interrupt */
46 #define PS2_CONTROL_RX_CLOCK_ENABLE BIT(4) /* pause reception if set to 0 */
47 #define PS2_CONTROL_RESET BIT(5) /* reset */
51 struct mace_ps2port *port;
55 static int maceps2_write(struct serio *dev, unsigned char val)
57 struct mace_ps2port *port = ((struct maceps2_data *)dev->driver)->port;
58 unsigned int timeout = MACE_PS2_TIMEOUT;
61 if (mace_read(port->status) & PS2_STATUS_TX_EMPTY) {
62 mace_write(val, port->tx);
71 static irqreturn_t maceps2_interrupt(int irq, void *dev_id,
74 struct serio *dev = dev_id;
75 struct mace_ps2port *port = ((struct maceps2_data *)dev->driver)->port;
78 if (mace_read(port->status) & PS2_STATUS_RX_FULL) {
79 byte = mace_read(port->rx);
80 serio_interrupt(dev, byte & 0xff, 0, regs);
86 static int maceps2_open(struct serio *dev)
88 struct maceps2_data *data = (struct maceps2_data *)dev->driver;
90 if (request_irq(data->irq, maceps2_interrupt, 0, "PS/2 port", dev)) {
91 printk(KERN_ERR "Could not allocate PS/2 IRQ\n");
96 mace_write(PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET,
100 /* Enable interrupts */
101 mace_write(PS2_CONTROL_RX_CLOCK_ENABLE | PS2_CONTROL_TX_ENABLE |
102 PS2_CONTROL_RX_INT_ENABLE, data->port->control);
107 static void maceps2_close(struct serio *dev)
109 struct maceps2_data *data = (struct maceps2_data *)dev->driver;
111 mace_write(PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET,
112 data->port->control);
114 free_irq(data->irq, dev);
117 static struct maceps2_data port0_data, port1_data;
119 static struct serio maceps2_port0 =
122 .open = maceps2_open,
123 .close = maceps2_close,
124 .write = maceps2_write,
125 .name = "MACE PS/2 port0",
126 .phys = "mace/serio0",
127 .driver = &port0_data,
130 static struct serio maceps2_port1 =
133 .open = maceps2_open,
134 .close = maceps2_close,
135 .write = maceps2_write,
136 .name = "MACE PS/2 port1",
137 .phys = "mace/serio1",
138 .driver = &port1_data,
141 static int __init maceps2_init(void)
143 port0_data.port = &mace->perif.ps2.keyb;
144 port0_data.irq = MACEISA_KEYB_IRQ;
145 port1_data.port = &mace->perif.ps2.mouse;
146 port1_data.irq = MACEISA_MOUSE_IRQ;
147 serio_register_port(&maceps2_port0);
148 serio_register_port(&maceps2_port1);
153 static void __exit maceps2_exit(void)
155 serio_unregister_port(&maceps2_port0);
156 serio_unregister_port(&maceps2_port1);
159 module_init(maceps2_init);
160 module_exit(maceps2_exit);