drivers/isdn/hisax/hfc_sx.c

   1 /* $Id: hfc_sx.c,v 1.12.2.5 2004/02/11 13:21:33 keil Exp $
   2  *
   3  * level driver for Cologne Chip Designs hfc-s+/sp based cards
   4  *
   5  * Author       Werner Cornelius
   6  *              based on existing driver for CCD HFC PCI cards
   7  * Copyright    by Werner Cornelius  <werner@isdn4linux.de>
   8  *
   9  * This software may be used and distributed according to the terms
  10  * of the GNU General Public License, incorporated herein by reference.
  11  *
  12  */
  13
  14 #include <linux/init.h>
  15 #include "hisax.h"
  16 #include "hfc_sx.h"
  17 #include "isdnl1.h"
  18 #include <linux/interrupt.h>
  19 #include <linux/isapnp.h>
  20
  21 extern const char *CardType[];
  22
  23 static const char *hfcsx_revision = "$Revision: 1.12.2.5 $";
  24
  25 /***************************************/
  26 /* IRQ-table for CCDs demo board       */
  27 /* IRQs 6,5,10,11,12,15 are supported  */
  28 /***************************************/
  29
  30 /* Teles 16.3c Vendor Id TAG2620, Version 1.0, Vendor version 2.1
  31  *
  32  * Thanks to Uwe Wisniewski
  33  *
  34  * ISA-SLOT  Signal      PIN
  35  * B25        IRQ3     92 IRQ_G
  36  * B23        IRQ5     94 IRQ_A
  37  * B4         IRQ2/9   95 IRQ_B
  38  * D3         IRQ10    96 IRQ_C
  39  * D4         IRQ11    97 IRQ_D
  40  * D5         IRQ12    98 IRQ_E
  41  * D6         IRQ15    99 IRQ_F
  42  */
  43
  44 #undef CCD_DEMO_BOARD
  45 #ifdef CCD_DEMO_BOARD
  46 static u_char ccd_sp_irqtab[16] = {
  47   0,0,0,0,0,2,1,0,0,0,3,4,5,0,0,6
  48 };
  49 #else /* Teles 16.3c */
  50 static u_char ccd_sp_irqtab[16] = {
  51   0,0,0,7,0,1,0,0,0,2,3,4,5,0,0,6
  52 };
  53 #endif
  54 #define NT_T1_COUNT 20          /* number of 3.125ms interrupts for G2 timeout */
  55
  56 #define byteout(addr,val) outb(val,addr)
  57 #define bytein(addr) inb(addr)
  58
  59 /******************************/
  60 /* In/Out access to registers */
  61 /******************************/
  62 static inline void
  63 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val)
  64 {
  65         byteout(cs->hw.hfcsx.base+1, regnum);
  66         byteout(cs->hw.hfcsx.base, val);
  67 }
  68
  69 static inline u_char
  70 Read_hfc(struct IsdnCardState *cs, u_char regnum)
  71 {
  72         u_char ret;
  73
  74         byteout(cs->hw.hfcsx.base+1, regnum);
  75         ret = bytein(cs->hw.hfcsx.base);
  76         return(ret);
  77 }
  78
  79
  80 /**************************************************/
  81 /* select a fifo and remember which one for reuse */
  82 /**************************************************/
  83 static void
  84 fifo_select(struct IsdnCardState *cs, u_char fifo)
  85 {
  86         if (fifo == cs->hw.hfcsx.last_fifo)
  87           return; /* still valid */
  88
  89         byteout(cs->hw.hfcsx.base+1, HFCSX_FIF_SEL);
  90         byteout(cs->hw.hfcsx.base, fifo);
  91         while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
  92         udelay(4);
  93         byteout(cs->hw.hfcsx.base, fifo);
  94         while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
  95 }
  96
  97 /******************************************/
  98 /* reset the specified fifo to defaults.  */
  99 /* If its a send fifo init needed markers */
 100 /******************************************/
 101 static void
 102 reset_fifo(struct IsdnCardState *cs, u_char fifo)
 103 {
 104         fifo_select(cs, fifo); /* first select the fifo */
 105         byteout(cs->hw.hfcsx.base+1, HFCSX_CIRM);
 106         byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */
 107         udelay(1);
 108         while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
 109 }
 110
 111
 112 /*************************************************************/
 113 /* write_fifo writes the skb contents to the desired fifo    */
 114 /* if no space is available or an error occurs 0 is returned */
 115 /* the skb is not released in any way.                       */
 116 /*************************************************************/
 117 static int
 118 write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max)
 119 {
 120        unsigned short *msp;
 121         int fifo_size, count, z1, z2;
 122         u_char f_msk, f1, f2, *src;
 123
 124         if (skb->len <= 0) return(0);
 125         if (fifo & 1) return(0); /* no write fifo */
 126
 127         fifo_select(cs, fifo);
 128         if (fifo & 4) {
 129           fifo_size = D_FIFO_SIZE; /* D-channel */
 130           f_msk = MAX_D_FRAMES;
 131           if (trans_max) return(0); /* only HDLC */
 132         }
 133         else {
 134           fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
 135           f_msk = MAX_B_FRAMES;
 136         }
 137
 138         z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 139         z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 140
 141         /* Check for transparent mode */
 142         if (trans_max) {
 143           z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 144           z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 145           count = z2 - z1;
 146           if (count <= 0)
 147             count += fifo_size; /* free bytes */
 148           if (count < skb->len+1) return(0); /* no room */
 149           count = fifo_size - count; /* bytes still not send */
 150           if (count > 2 * trans_max) return(0); /* delay to long */
 151           count = skb->len;
 152           src = skb->data;
 153           while (count--)
 154             Write_hfc(cs, HFCSX_FIF_DWR, *src++);
 155           return(1); /* success */
 156         }
 157
 158         msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker;
 159         msp += (((fifo >> 1) & 3) * (MAX_B_FRAMES+1));
 160         f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
 161         f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
 162
 163         count = f1 - f2; /* frame count actually buffered */
 164         if (count < 0)
 165                 count += (f_msk + 1);   /* if wrap around */
 166         if (count > f_msk-1) {
 167           if (cs->debug & L1_DEB_ISAC_FIFO)
 168             debugl1(cs, "hfcsx_write_fifo %d more as %d frames",fifo,f_msk-1);
 169           return(0);
 170         }
 171
 172         *(msp + f1) = z1; /* remember marker */
 173
 174         if (cs->debug & L1_DEB_ISAC_FIFO)
 175                 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)",
 176                         fifo, f1, f2, z1);
 177         /* now determine free bytes in FIFO buffer */
 178         count = *(msp + f2) - z1;
 179         if (count <= 0)
 180           count += fifo_size;   /* count now contains available bytes */
 181
 182         if (cs->debug & L1_DEB_ISAC_FIFO)
 183           debugl1(cs, "hfcsx_write_fifo %d count(%ld/%d)",
 184                   fifo, skb->len, count);
 185         if (count < skb->len) {
 186           if (cs->debug & L1_DEB_ISAC_FIFO)
 187             debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo);
 188           return(0);
 189         }
 190
 191         count = skb->len; /* get frame len */
 192         src = skb->data;        /* source pointer */
 193         while (count--)
 194           Write_hfc(cs, HFCSX_FIF_DWR, *src++);
 195
 196         Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */
 197         udelay(1);
 198         while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
 199         return(1);
 200 }
 201
 202 /***************************************************************/
 203 /* read_fifo reads data to an skb from the desired fifo        */
 204 /* if no data is available or an error occurs NULL is returned */
 205 /* the skb is not released in any way.                         */
 206 /***************************************************************/
 207 static struct sk_buff *
 208 read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max)
 209 {       int fifo_size, count, z1, z2;
 210         u_char f_msk, f1, f2, *dst;
 211         struct sk_buff *skb;
 212
 213         if (!(fifo & 1)) return(NULL); /* no read fifo */
 214         fifo_select(cs, fifo);
 215         if (fifo & 4) {
 216           fifo_size = D_FIFO_SIZE; /* D-channel */
 217           f_msk = MAX_D_FRAMES;
 218           if (trans_max) return(NULL); /* only hdlc */
 219         }
 220         else {
 221           fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */
 222           f_msk = MAX_B_FRAMES;
 223         }
 224
 225         /* transparent mode */
 226         if (trans_max) {
 227           z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 228           z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 229           z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 230           z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 231           /* now determine bytes in actual FIFO buffer */
 232           count = z1 - z2;
 233           if (count <= 0)
 234             count += fifo_size; /* count now contains buffered bytes */
 235           count++;
 236           if (count > trans_max)
 237             count = trans_max; /* limit length */
 238             if ((skb = dev_alloc_skb(count))) {
 239               dst = skb_put(skb, count);
 240               while (count--)
 241                 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
 242               return(skb);
 243             }
 244             else return(NULL); /* no memory */
 245         }
 246
 247         do {
 248           f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk;
 249           f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk;
 250
 251           if (f1 == f2) return(NULL); /* no frame available */
 252
 253           z1 = Read_hfc(cs, HFCSX_FIF_Z1H);
 254           z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L));
 255           z2 = Read_hfc(cs, HFCSX_FIF_Z2H);
 256           z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L));
 257
 258           if (cs->debug & L1_DEB_ISAC_FIFO)
 259             debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)",
 260                         fifo, f1, f2, z1, z2);
 261           /* now determine bytes in actual FIFO buffer */
 262           count = z1 - z2;
 263           if (count <= 0)
 264             count += fifo_size; /* count now contains buffered bytes */
 265           count++;
 266
 267           if (cs->debug & L1_DEB_ISAC_FIFO)
 268             debugl1(cs, "hfcsx_read_fifo %d count %ld)",
 269                     fifo, count);
 270
 271           if ((count > fifo_size) || (count < 4)) {
 272             if (cs->debug & L1_DEB_WARN)
 273               debugl1(cs, "hfcsx_read_fifo %d paket inv. len %d ", fifo , count);
 274             while (count) {
 275               count--; /* empty fifo */
 276               Read_hfc(cs, HFCSX_FIF_DRD);
 277             }
 278             skb = NULL;
 279           } else
 280             if ((skb = dev_alloc_skb(count - 3))) {
 281               count -= 3;
 282               dst = skb_put(skb, count);
 283
 284               while (count--)
 285                 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD);
 286
 287               Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */
 288               Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */
 289               if (Read_hfc(cs, HFCSX_FIF_DRD)) {
 290                 dev_kfree_skb_irq(skb);
 291                 if (cs->debug & L1_DEB_ISAC_FIFO)
 292                   debugl1(cs, "hfcsx_read_fifo %d crc error", fifo);
 293                 skb = NULL;
 294               }
 295             } else {
 296               printk(KERN_WARNING "HFC-SX: receive out of memory\n");
 297               return(NULL);
 298             }
 299
 300           Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */
 301           udelay(1);
 302           while (bytein(cs->hw.hfcsx.base+1) & 1); /* wait for busy */
 303           udelay(1);
 304         } while (!skb); /* retry in case of crc error */
 305         return(skb);
 306 }
 307
 308 /******************************************/
 309 /* free hardware resources used by driver */
 310 /******************************************/
 311 void
 312 release_io_hfcsx(struct IsdnCardState *cs)
 313 {
 314         cs->hw.hfcsx.int_m2 = 0;        /* interrupt output off ! */
 315         Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 316         Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */
 317         set_current_state(TASK_UNINTERRUPTIBLE);
 318         schedule_timeout((30 * HZ) / 1000);     /* Timeout 30ms */
 319         Write_hfc(cs, HFCSX_CIRM, 0);   /* Reset Off */
 320         del_timer(&cs->hw.hfcsx.timer);
 321         release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */
 322         kfree(cs->hw.hfcsx.extra);
 323         cs->hw.hfcsx.extra = NULL;
 324 }
 325
 326 /**********************************************************/
 327 /* set_fifo_size determines the size of the RAM and FIFOs */
 328 /* returning 0 -> need to reset the chip again.           */
 329 /**********************************************************/
 330 static int set_fifo_size(struct IsdnCardState *cs)
 331 {
 332
 333         if (cs->hw.hfcsx.b_fifo_size) return(1); /* already determined */
 334
 335         if ((cs->hw.hfcsx.chip >> 4) == 9) {
 336           cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K;
 337           return(1);
 338         }
 339
 340           cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K;
 341           cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */
 342           return(0);
 343
 344 }
 345
 346 /********************************************************************************/
 347 /* function called to reset the HFC SX chip. A complete software reset of chip */
 348 /* and fifos is done.                                                           */
 349 /********************************************************************************/
 350 static void
 351 reset_hfcsx(struct IsdnCardState *cs)
 352 {
 353         cs->hw.hfcsx.int_m2 = 0;        /* interrupt output off ! */
 354         Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 355
 356         printk(KERN_INFO "HFC_SX: resetting card\n");
 357         while (1) {
 358           Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm ); /* Reset */
 359           mdelay(30);
 360           Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */
 361           mdelay(20);
 362           if (Read_hfc(cs, HFCSX_STATUS) & 2)
 363             printk(KERN_WARNING "HFC-SX init bit busy\n");
 364           cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */
 365           if (!set_fifo_size(cs)) continue;
 366           break;
 367         }
 368
 369         cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK;  /* no echo connect , threshold */
 370         Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 371
 372         Write_hfc(cs, HFCSX_CLKDEL, 0x0e);      /* ST-Bit delay for TE-Mode */
 373         cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE;
 374         Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);     /* S/T Auto awake */
 375         cs->hw.hfcsx.bswapped = 0;      /* no exchange */
 376         cs->hw.hfcsx.nt_mode = 0;       /* we are in TE mode */
 377         cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER;
 378         Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
 379
 380         cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC |
 381             HFCSX_INTS_L1STATE | HFCSX_INTS_TIMER;
 382         Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
 383
 384         /* Clear already pending ints */
 385         if (Read_hfc(cs, HFCSX_INT_S1));
 386
 387         Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2);      /* HFC ST 2 */
 388         udelay(10);
 389         Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */
 390         cs->hw.hfcsx.mst_m = HFCSX_MASTER;      /* HFC Master Mode */
 391
 392         Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 393         cs->hw.hfcsx.sctrl = 0x40;      /* set tx_lo mode, error in datasheet ! */
 394         Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
 395         cs->hw.hfcsx.sctrl_r = 0;
 396         Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
 397
 398         /* Init GCI/IOM2 in master mode */
 399         /* Slots 0 and 1 are set for B-chan 1 and 2 */
 400         /* D- and monitor/CI channel are not enabled */
 401         /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */
 402         /* STIO2 is used as data input, B1+B2 from IOM->ST */
 403         /* ST B-channel send disabled -> continous 1s */
 404         /* The IOM slots are always enabled */
 405         cs->hw.hfcsx.conn = 0x36;       /* set data flow directions */
 406         Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 407         Write_hfc(cs, HFCSX_B1_SSL, 0x80);      /* B1-Slot 0 STIO1 out enabled */
 408         Write_hfc(cs, HFCSX_B2_SSL, 0x81);      /* B2-Slot 1 STIO1 out enabled */
 409         Write_hfc(cs, HFCSX_B1_RSL, 0x80);      /* B1-Slot 0 STIO2 in enabled */
 410         Write_hfc(cs, HFCSX_B2_RSL, 0x81);      /* B2-Slot 1 STIO2 in enabled */
 411
 412         /* Finally enable IRQ output */
 413         cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE;
 414         Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
 415         if (Read_hfc(cs, HFCSX_INT_S2));
 416 }
 417
 418 /***************************************************/
 419 /* Timer function called when kernel timer expires */
 420 /***************************************************/
 421 static void
 422 hfcsx_Timer(struct IsdnCardState *cs)
 423 {
 424         cs->hw.hfcsx.timer.expires = jiffies + 75;
 425         /* WD RESET */
 426 /*      WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcsx.ctmt | 0x80);
 427    add_timer(&cs->hw.hfcsx.timer);
 428  */
 429 }
 430
 431 /************************************************/
 432 /* select a b-channel entry matching and active */
 433 /************************************************/
 434 static
 435 struct BCState *
 436 Sel_BCS(struct IsdnCardState *cs, int channel)
 437 {
 438         if (cs->bcs[0].mode && (cs->bcs[0].channel == channel))
 439                 return (&cs->bcs[0]);
 440         else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel))
 441                 return (&cs->bcs[1]);
 442         else
 443                 return (NULL);
 444 }
 445
 446 /*******************************/
 447 /* D-channel receive procedure */
 448 /*******************************/
 449 static
 450 int
 451 receive_dmsg(struct IsdnCardState *cs)
 452 {
 453         struct sk_buff *skb;
 454         int count = 5;
 455
 456         if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 457                 debugl1(cs, "rec_dmsg blocked");
 458                 return (1);
 459         }
 460
 461         do {
 462           skb = read_fifo(cs, HFCSX_SEL_D_RX, 0);
 463           if (skb) {
 464             skb_queue_tail(&cs->rq, skb);
 465             schedule_event(cs, D_RCVBUFREADY);
 466           }
 467         } while (--count && skb);
 468
 469         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 470         return (1);
 471 }
 472
 473 /**********************************/
 474 /* B-channel main receive routine */
 475 /**********************************/
 476 void
 477 main_rec_hfcsx(struct BCState *bcs)
 478 {
 479         struct IsdnCardState *cs = bcs->cs;
 480         int count = 5;
 481         struct sk_buff *skb;
 482
 483       Begin:
 484         count--;
 485         if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 486                 debugl1(cs, "rec_data %d blocked", bcs->channel);
 487                 return;
 488         }
 489         skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
 490                         HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX,
 491                         (bcs->mode == L1_MODE_TRANS) ?
 492                         HFCSX_BTRANS_THRESHOLD : 0);
 493
 494         if (skb) {
 495           skb_queue_tail(&bcs->rqueue, skb);
 496           schedule_event(bcs, B_RCVBUFREADY);
 497         }
 498
 499         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 500         if (count && skb)
 501                 goto Begin;
 502         return;
 503 }
 504
 505 /**************************/
 506 /* D-channel send routine */
 507 /**************************/
 508 static void
 509 hfcsx_fill_dfifo(struct IsdnCardState *cs)
 510 {
 511         if (!cs->tx_skb)
 512                 return;
 513         if (cs->tx_skb->len <= 0)
 514                 return;
 515
 516         if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) {
 517           dev_kfree_skb_any(cs->tx_skb);
 518           cs->tx_skb = NULL;
 519         }
 520         return;
 521 }
 522
 523 /**************************/
 524 /* B-channel send routine */
 525 /**************************/
 526 static void
 527 hfcsx_fill_fifo(struct BCState *bcs)
 528 {
 529         struct IsdnCardState *cs = bcs->cs;
 530
 531         if (!bcs->tx_skb)
 532                 return;
 533         if (bcs->tx_skb->len <= 0)
 534                 return;
 535
 536         if (write_fifo(cs, bcs->tx_skb,
 537                        ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ?
 538                        HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX,
 539                        (bcs->mode == L1_MODE_TRANS) ?
 540                        HFCSX_BTRANS_THRESHOLD : 0)) {
 541
 542           bcs->tx_cnt -= bcs->tx_skb->len;
 543           if (test_bit(FLG_LLI_L1WAKEUP,&bcs->st->lli.flag) &&
 544                 (PACKET_NOACK != bcs->tx_skb->pkt_type)) {
 545                 u_long  flags;
 546                 spin_lock_irqsave(&bcs->aclock, flags);
 547                 bcs->ackcnt += bcs->tx_skb->len;
 548                 spin_unlock_irqrestore(&bcs->aclock, flags);
 549                 schedule_event(bcs, B_ACKPENDING);
 550           }
 551           dev_kfree_skb_any(bcs->tx_skb);
 552           bcs->tx_skb = NULL;
 553           test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
 554         }
 555 }
 556
 557 /**********************************************/
 558 /* D-channel l1 state call for leased NT-mode */
 559 /**********************************************/
 560 static void
 561 dch_nt_l2l1(struct PStack *st, int pr, void *arg)
 562 {
 563         struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
 564
 565         switch (pr) {
 566                 case (PH_DATA | REQUEST):
 567                 case (PH_PULL | REQUEST):
 568                 case (PH_PULL | INDICATION):
 569                         st->l1.l1hw(st, pr, arg);
 570                         break;
 571                 case (PH_ACTIVATE | REQUEST):
 572                         st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL);
 573                         break;
 574                 case (PH_TESTLOOP | REQUEST):
 575                         if (1 & (long) arg)
 576                                 debugl1(cs, "PH_TEST_LOOP B1");
 577                         if (2 & (long) arg)
 578                                 debugl1(cs, "PH_TEST_LOOP B2");
 579                         if (!(3 & (long) arg))
 580                                 debugl1(cs, "PH_TEST_LOOP DISABLED");
 581                         st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg);
 582                         break;
 583                 default:
 584                         if (cs->debug)
 585                                 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr);
 586                         break;
 587         }
 588 }
 589
 590
 591
 592 /***********************/
 593 /* set/reset echo mode */
 594 /***********************/
 595 static int
 596 hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl * ic)
 597 {
 598         unsigned long flags;
 599         int i = *(unsigned int *) ic->parm.num;
 600
 601         if ((ic->arg == 98) &&
 602             (!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC)))) {
 603                 spin_lock_irqsave(&cs->lock, flags);
 604                 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0);      /* HFC ST G0 */
 605                 udelay(10);
 606                 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT;
 607                 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */
 608                 udelay(10);
 609                 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1);      /* HFC ST G1 */
 610                 udelay(10);
 611                 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 612                 cs->dc.hfcsx.ph_state = 1;
 613                 cs->hw.hfcsx.nt_mode = 1;
 614                 cs->hw.hfcsx.nt_timer = 0;
 615                 spin_unlock_irqrestore(&cs->lock, flags);
 616                 cs->stlist->l2.l2l1 = dch_nt_l2l1;
 617                 debugl1(cs, "NT mode activated");
 618                 return (0);
 619         }
 620         if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) ||
 621             (cs->hw.hfcsx.nt_mode) || (ic->arg != 12))
 622                 return (-EINVAL);
 623
 624         if (i) {
 625                 cs->logecho = 1;
 626                 cs->hw.hfcsx.trm |= 0x20;       /* enable echo chan */
 627                 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC;
 628                 /* reset Channel !!!!! */
 629         } else {
 630                 cs->logecho = 0;
 631                 cs->hw.hfcsx.trm &= ~0x20;      /* disable echo chan */
 632                 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC;
 633         }
 634         cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
 635         cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
 636         cs->hw.hfcsx.conn |= 0x10;      /* B2-IOM -> B2-ST */
 637         cs->hw.hfcsx.ctmt &= ~2;
 638         spin_lock_irqsave(&cs->lock, flags);
 639         Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
 640         Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
 641         Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
 642         Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 643         Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 644         Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
 645         spin_unlock_irqrestore(&cs->lock, flags);
 646         return (0);
 647 }                               /* hfcsx_auxcmd */
 648
 649 /*****************************/
 650 /* E-channel receive routine */
 651 /*****************************/
 652 static void
 653 receive_emsg(struct IsdnCardState *cs)
 654 {
 655         int count = 5;
 656         u_char *ptr;
 657         struct sk_buff *skb;
 658
 659         if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 660                 debugl1(cs, "echo_rec_data blocked");
 661                 return;
 662         }
 663         do {
 664           skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0);
 665           if (skb) {
 666             if (cs->debug & DEB_DLOG_HEX) {
 667               ptr = cs->dlog;
 668               if ((skb->len) < MAX_DLOG_SPACE / 3 - 10) {
 669                 *ptr++ = 'E';
 670                 *ptr++ = 'C';
 671                 *ptr++ = 'H';
 672                 *ptr++ = 'O';
 673                 *ptr++ = ':';
 674                 ptr += QuickHex(ptr, skb->data, skb->len);
 675                 ptr--;
 676                 *ptr++ = '\n';
 677                 *ptr = 0;
 678                 HiSax_putstatus(cs, NULL, cs->dlog);
 679               } else
 680                 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len);
 681             }
 682             dev_kfree_skb_any(skb);
 683           }
 684         } while (--count && skb);
 685
 686         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 687         return;
 688 }                               /* receive_emsg */
 689
 690
 691 /*********************/
 692 /* Interrupt handler */
 693 /*********************/
 694 static irqreturn_t
 695 hfcsx_interrupt(int intno, void *dev_id, struct pt_regs *regs)
 696 {
 697         struct IsdnCardState *cs = dev_id;
 698         u_char exval;
 699         struct BCState *bcs;
 700         int count = 15;
 701         u_long flags;
 702         u_char val, stat;
 703
 704         if (!(cs->hw.hfcsx.int_m2 & 0x08))
 705                 return IRQ_NONE;                /* not initialised */
 706
 707         spin_lock_irqsave(&cs->lock, flags);
 708         if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) {
 709                 val = Read_hfc(cs, HFCSX_INT_S1);
 710                 if (cs->debug & L1_DEB_ISAC)
 711                         debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val);
 712         } else {
 713                 spin_unlock_irqrestore(&cs->lock, flags);
 714                 return IRQ_NONE;
 715         }
 716         if (cs->debug & L1_DEB_ISAC)
 717                 debugl1(cs, "HFC-SX irq %x %s", val,
 718                         test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ?
 719                         "locked" : "unlocked");
 720         val &= cs->hw.hfcsx.int_m1;
 721         if (val & 0x40) {       /* state machine irq */
 722                 exval = Read_hfc(cs, HFCSX_STATES) & 0xf;
 723                 if (cs->debug & L1_DEB_ISAC)
 724                         debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state,
 725                                 exval);
 726                 cs->dc.hfcsx.ph_state = exval;
 727                 schedule_event(cs, D_L1STATECHANGE);
 728                 val &= ~0x40;
 729         }
 730         if (val & 0x80) {       /* timer irq */
 731                 if (cs->hw.hfcsx.nt_mode) {
 732                         if ((--cs->hw.hfcsx.nt_timer) < 0)
 733                                 schedule_event(cs, D_L1STATECHANGE);
 734                 }
 735                 val &= ~0x80;
 736                 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
 737         }
 738         while (val) {
 739                 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 740                         cs->hw.hfcsx.int_s1 |= val;
 741                         spin_unlock_irqrestore(&cs->lock, flags);
 742                         return IRQ_HANDLED;
 743                 }
 744                 if (cs->hw.hfcsx.int_s1 & 0x18) {
 745                         exval = val;
 746                         val = cs->hw.hfcsx.int_s1;
 747                         cs->hw.hfcsx.int_s1 = exval;
 748                 }
 749                 if (val & 0x08) {
 750                         if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
 751                                 if (cs->debug)
 752                                         debugl1(cs, "hfcsx spurious 0x08 IRQ");
 753                         } else
 754                                 main_rec_hfcsx(bcs);
 755                 }
 756                 if (val & 0x10) {
 757                         if (cs->logecho)
 758                                 receive_emsg(cs);
 759                         else if (!(bcs = Sel_BCS(cs, 1))) {
 760                                 if (cs->debug)
 761                                         debugl1(cs, "hfcsx spurious 0x10 IRQ");
 762                         } else
 763                                 main_rec_hfcsx(bcs);
 764                 }
 765                 if (val & 0x01) {
 766                         if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) {
 767                                 if (cs->debug)
 768                                         debugl1(cs, "hfcsx spurious 0x01 IRQ");
 769                         } else {
 770                                 if (bcs->tx_skb) {
 771                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 772                                                 hfcsx_fill_fifo(bcs);
 773                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 774                                         } else
 775                                                 debugl1(cs, "fill_data %d blocked", bcs->channel);
 776                                 } else {
 777                                         if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 778                                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 779                                                         hfcsx_fill_fifo(bcs);
 780                                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 781                                                 } else
 782                                                         debugl1(cs, "fill_data %d blocked", bcs->channel);
 783                                         } else {
 784                                                 schedule_event(bcs, B_XMTBUFREADY);
 785                                         }
 786                                 }
 787                         }
 788                 }
 789                 if (val & 0x02) {
 790                         if (!(bcs = Sel_BCS(cs, 1))) {
 791                                 if (cs->debug)
 792                                         debugl1(cs, "hfcsx spurious 0x02 IRQ");
 793                         } else {
 794                                 if (bcs->tx_skb) {
 795                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 796                                                 hfcsx_fill_fifo(bcs);
 797                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 798                                         } else
 799                                                 debugl1(cs, "fill_data %d blocked", bcs->channel);
 800                                 } else {
 801                                         if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
 802                                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 803                                                         hfcsx_fill_fifo(bcs);
 804                                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 805                                                 } else
 806                                                         debugl1(cs, "fill_data %d blocked", bcs->channel);
 807                                         } else {
 808                                                 schedule_event(bcs, B_XMTBUFREADY);
 809                                         }
 810                                 }
 811                         }
 812                 }
 813                 if (val & 0x20) {       /* receive dframe */
 814                         receive_dmsg(cs);
 815                 }
 816                 if (val & 0x04) {       /* dframe transmitted */
 817                         if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags))
 818                                 del_timer(&cs->dbusytimer);
 819                         if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags))
 820                                 schedule_event(cs, D_CLEARBUSY);
 821                         if (cs->tx_skb) {
 822                                 if (cs->tx_skb->len) {
 823                                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 824                                                 hfcsx_fill_dfifo(cs);
 825                                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 826                                         } else {
 827                                                 debugl1(cs, "hfcsx_fill_dfifo irq blocked");
 828                                         }
 829                                         goto afterXPR;
 830                                 } else {
 831                                         dev_kfree_skb_irq(cs->tx_skb);
 832                                         cs->tx_cnt = 0;
 833                                         cs->tx_skb = NULL;
 834                                 }
 835                         }
 836                         if ((cs->tx_skb = skb_dequeue(&cs->sq))) {
 837                                 cs->tx_cnt = 0;
 838                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 839                                         hfcsx_fill_dfifo(cs);
 840                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 841                                 } else {
 842                                         debugl1(cs, "hfcsx_fill_dfifo irq blocked");
 843                                 }
 844                         } else
 845                                 schedule_event(cs, D_XMTBUFREADY);
 846                 }
 847               afterXPR:
 848                 if (cs->hw.hfcsx.int_s1 && count--) {
 849                         val = cs->hw.hfcsx.int_s1;
 850                         cs->hw.hfcsx.int_s1 = 0;
 851                         if (cs->debug & L1_DEB_ISAC)
 852                                 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count);
 853                 } else
 854                         val = 0;
 855         }
 856         spin_unlock_irqrestore(&cs->lock, flags);
 857         return IRQ_HANDLED;
 858 }
 859
 860 /********************************************************************/
 861 /* timer callback for D-chan busy resolution. Currently no function */
 862 /********************************************************************/
 863 static void
 864 hfcsx_dbusy_timer(struct IsdnCardState *cs)
 865 {
 866 }
 867
 868 /*************************************/
 869 /* Layer 1 D-channel hardware access */
 870 /*************************************/
 871 static void
 872 HFCSX_l1hw(struct PStack *st, int pr, void *arg)
 873 {
 874         struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware;
 875         struct sk_buff *skb = arg;
 876         u_long flags;
 877
 878         switch (pr) {
 879                 case (PH_DATA | REQUEST):
 880                         if (cs->debug & DEB_DLOG_HEX)
 881                                 LogFrame(cs, skb->data, skb->len);
 882                         if (cs->debug & DEB_DLOG_VERBOSE)
 883                                 dlogframe(cs, skb, 0);
 884                         spin_lock_irqsave(&cs->lock, flags);
 885                         if (cs->tx_skb) {
 886                                 skb_queue_tail(&cs->sq, skb);
 887 #ifdef L2FRAME_DEBUG            /* psa */
 888                                 if (cs->debug & L1_DEB_LAPD)
 889                                         Logl2Frame(cs, skb, "PH_DATA Queued", 0);
 890 #endif
 891                         } else {
 892                                 cs->tx_skb = skb;
 893                                 cs->tx_cnt = 0;
 894 #ifdef L2FRAME_DEBUG            /* psa */
 895                                 if (cs->debug & L1_DEB_LAPD)
 896                                         Logl2Frame(cs, skb, "PH_DATA", 0);
 897 #endif
 898                                 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 899                                         hfcsx_fill_dfifo(cs);
 900                                         test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 901                                 } else
 902                                         debugl1(cs, "hfcsx_fill_dfifo blocked");
 903
 904                         }
 905                         spin_unlock_irqrestore(&cs->lock, flags);
 906                         break;
 907                 case (PH_PULL | INDICATION):
 908                         spin_lock_irqsave(&cs->lock, flags);
 909                         if (cs->tx_skb) {
 910                                 if (cs->debug & L1_DEB_WARN)
 911                                         debugl1(cs, " l2l1 tx_skb exist this shouldn't happen");
 912                                 skb_queue_tail(&cs->sq, skb);
 913                                 spin_unlock_irqrestore(&cs->lock, flags);
 914                                 break;
 915                         }
 916                         if (cs->debug & DEB_DLOG_HEX)
 917                                 LogFrame(cs, skb->data, skb->len);
 918                         if (cs->debug & DEB_DLOG_VERBOSE)
 919                                 dlogframe(cs, skb, 0);
 920                         cs->tx_skb = skb;
 921                         cs->tx_cnt = 0;
 922 #ifdef L2FRAME_DEBUG            /* psa */
 923                         if (cs->debug & L1_DEB_LAPD)
 924                                 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0);
 925 #endif
 926                         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
 927                                 hfcsx_fill_dfifo(cs);
 928                                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
 929                         } else
 930                                 debugl1(cs, "hfcsx_fill_dfifo blocked");
 931                         spin_unlock_irqrestore(&cs->lock, flags);
 932                         break;
 933                 case (PH_PULL | REQUEST):
 934 #ifdef L2FRAME_DEBUG            /* psa */
 935                         if (cs->debug & L1_DEB_LAPD)
 936                                 debugl1(cs, "-> PH_REQUEST_PULL");
 937 #endif
 938                         if (!cs->tx_skb) {
 939                                 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 940                                 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
 941                         } else
 942                                 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
 943                         break;
 944                 case (HW_RESET | REQUEST):
 945                         spin_lock_irqsave(&cs->lock, flags);
 946                         Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3);      /* HFC ST 3 */
 947                         udelay(6);
 948                         Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */
 949                         cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
 950                         Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 951                         Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 952                         spin_unlock_irqrestore(&cs->lock, flags);
 953                         l1_msg(cs, HW_POWERUP | CONFIRM, NULL);
 954                         break;
 955                 case (HW_ENABLE | REQUEST):
 956                         spin_lock_irqsave(&cs->lock, flags);
 957                         Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION);
 958                         spin_unlock_irqrestore(&cs->lock, flags);
 959                         break;
 960                 case (HW_DEACTIVATE | REQUEST):
 961                         spin_lock_irqsave(&cs->lock, flags);
 962                         cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER;
 963                         Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 964                         spin_unlock_irqrestore(&cs->lock, flags);
 965                         break;
 966                 case (HW_INFO3 | REQUEST):
 967                         spin_lock_irqsave(&cs->lock, flags);
 968                         cs->hw.hfcsx.mst_m |= HFCSX_MASTER;
 969                         Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
 970                         spin_unlock_irqrestore(&cs->lock, flags);
 971                         break;
 972                 case (HW_TESTLOOP | REQUEST):
 973                         spin_lock_irqsave(&cs->lock, flags);
 974                         switch ((int) arg) {
 975                                 case (1):
 976                                         Write_hfc(cs, HFCSX_B1_SSL, 0x80);      /* tx slot */
 977                                         Write_hfc(cs, HFCSX_B1_RSL, 0x80);      /* rx slot */
 978                                         cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1;
 979                                         Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 980                                         break;
 981                                 case (2):
 982                                         Write_hfc(cs, HFCSX_B2_SSL, 0x81);      /* tx slot */
 983                                         Write_hfc(cs, HFCSX_B2_RSL, 0x81);      /* rx slot */
 984                                         cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08;
 985                                         Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
 986                                         break;
 987                                 default:
 988                                         spin_unlock_irqrestore(&cs->lock, flags);
 989                                         if (cs->debug & L1_DEB_WARN)
 990                                                 debugl1(cs, "hfcsx_l1hw loop invalid %4x", (int) arg);
 991                                         return;
 992                         }
 993                         cs->hw.hfcsx.trm |= 0x80;       /* enable IOM-loop */
 994                         Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm);
 995                         spin_unlock_irqrestore(&cs->lock, flags);
 996                         break;
 997                 default:
 998                         if (cs->debug & L1_DEB_WARN)
 999                                 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr);
1000                         break;
1001         }
1002 }
1003
1004 /***********************************************/
1005 /* called during init setting l1 stack pointer */
1006 /***********************************************/
1007 void
1008 setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs)
1009 {
1010         st->l1.l1hw = HFCSX_l1hw;
1011 }
1012
1013 /**************************************/
1014 /* send B-channel data if not blocked */
1015 /**************************************/
1016 static void
1017 hfcsx_send_data(struct BCState *bcs)
1018 {
1019         struct IsdnCardState *cs = bcs->cs;
1020
1021         if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) {
1022           hfcsx_fill_fifo(bcs);
1023                 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags);
1024         } else
1025                 debugl1(cs, "send_data %d blocked", bcs->channel);
1026 }
1027
1028 /***************************************************************/
1029 /* activate/deactivate hardware for selected channels and mode */
1030 /***************************************************************/
1031 void
1032 mode_hfcsx(struct BCState *bcs, int mode, int bc)
1033 {
1034         struct IsdnCardState *cs = bcs->cs;
1035         int fifo2;
1036
1037         if (cs->debug & L1_DEB_HSCX)
1038                 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d",
1039                         mode, bc, bcs->channel);
1040         bcs->mode = mode;
1041         bcs->channel = bc;
1042         fifo2 = bc;
1043         if (cs->chanlimit > 1) {
1044                 cs->hw.hfcsx.bswapped = 0;      /* B1 and B2 normal mode */
1045                 cs->hw.hfcsx.sctrl_e &= ~0x80;
1046         } else {
1047                 if (bc) {
1048                         if (mode != L1_MODE_NULL) {
1049                                 cs->hw.hfcsx.bswapped = 1;      /* B1 and B2 exchanged */
1050                                 cs->hw.hfcsx.sctrl_e |= 0x80;
1051                         } else {
1052                                 cs->hw.hfcsx.bswapped = 0;      /* B1 and B2 normal mode */
1053                                 cs->hw.hfcsx.sctrl_e &= ~0x80;
1054                         }
1055                         fifo2 = 0;
1056                 } else {
1057                         cs->hw.hfcsx.bswapped = 0;      /* B1 and B2 normal mode */
1058                         cs->hw.hfcsx.sctrl_e &= ~0x80;
1059                 }
1060         }
1061         switch (mode) {
1062                 case (L1_MODE_NULL):
1063                         if (bc) {
1064                                 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA;
1065                                 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA;
1066                         } else {
1067                                 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA;
1068                                 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA;
1069                         }
1070                         if (fifo2) {
1071                                 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1072                         } else {
1073                                 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1074                         }
1075                         break;
1076                 case (L1_MODE_TRANS):
1077                         if (bc) {
1078                                 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1079                                 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1080                         } else {
1081                                 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1082                                 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1083                         }
1084                         if (fifo2) {
1085                                 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1086                                 cs->hw.hfcsx.ctmt |= 2;
1087                                 cs->hw.hfcsx.conn &= ~0x18;
1088                         } else {
1089                                 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1090                                 cs->hw.hfcsx.ctmt |= 1;
1091                                 cs->hw.hfcsx.conn &= ~0x03;
1092                         }
1093                         break;
1094                 case (L1_MODE_HDLC):
1095                         if (bc) {
1096                                 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1097                                 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1098                         } else {
1099                                 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1100                                 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1101                         }
1102                         if (fifo2) {
1103                                 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1104                                 cs->hw.hfcsx.ctmt &= ~2;
1105                                 cs->hw.hfcsx.conn &= ~0x18;
1106                         } else {
1107                                 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1108                                 cs->hw.hfcsx.ctmt &= ~1;
1109                                 cs->hw.hfcsx.conn &= ~0x03;
1110                         }
1111                         break;
1112                 case (L1_MODE_EXTRN):
1113                         if (bc) {
1114                                 cs->hw.hfcsx.conn |= 0x10;
1115                                 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA;
1116                                 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA;
1117                                 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC);
1118                         } else {
1119                                 cs->hw.hfcsx.conn |= 0x02;
1120                                 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA;
1121                                 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA;
1122                                 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC);
1123                         }
1124                         break;
1125         }
1126         Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e);
1127         Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1128         Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl);
1129         Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r);
1130         Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt);
1131         Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn);
1132         if (mode != L1_MODE_EXTRN) {
1133           reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX);
1134           reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX);
1135         }
1136 }
1137
1138 /******************************/
1139 /* Layer2 -> Layer 1 Transfer */
1140 /******************************/
1141 static void
1142 hfcsx_l2l1(struct PStack *st, int pr, void *arg)
1143 {
1144         struct BCState *bcs = st->l1.bcs;
1145         struct sk_buff *skb = arg;
1146         u_long flags;
1147
1148         switch (pr) {
1149                 case (PH_DATA | REQUEST):
1150                         spin_lock_irqsave(&bcs->cs->lock, flags);
1151                         if (bcs->tx_skb) {
1152                                 skb_queue_tail(&bcs->squeue, skb);
1153                         } else {
1154                                 bcs->tx_skb = skb;
1155 //                              test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1156                                 bcs->cs->BC_Send_Data(bcs);
1157                         }
1158                         spin_unlock_irqrestore(&bcs->cs->lock, flags);
1159                         break;
1160                 case (PH_PULL | INDICATION):
1161                         spin_lock_irqsave(&bcs->cs->lock, flags);
1162                         if (bcs->tx_skb) {
1163                                 printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
1164                         } else {
1165 //                              test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
1166                                 bcs->tx_skb = skb;
1167                                 bcs->cs->BC_Send_Data(bcs);
1168                         }
1169                         spin_unlock_irqrestore(&bcs->cs->lock, flags);
1170                         break;
1171                 case (PH_PULL | REQUEST):
1172                         if (!bcs->tx_skb) {
1173                                 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1174                                 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
1175                         } else
1176                                 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
1177                         break;
1178                 case (PH_ACTIVATE | REQUEST):
1179                         spin_lock_irqsave(&bcs->cs->lock, flags);
1180                         test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
1181                         mode_hfcsx(bcs, st->l1.mode, st->l1.bc);
1182                         spin_unlock_irqrestore(&bcs->cs->lock, flags);
1183                         l1_msg_b(st, pr, arg);
1184                         break;
1185                 case (PH_DEACTIVATE | REQUEST):
1186                         l1_msg_b(st, pr, arg);
1187                         break;
1188                 case (PH_DEACTIVATE | CONFIRM):
1189                         spin_lock_irqsave(&bcs->cs->lock, flags);
1190                         test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
1191                         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1192                         mode_hfcsx(bcs, 0, st->l1.bc);
1193                         spin_unlock_irqrestore(&bcs->cs->lock, flags);
1194                         st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
1195                         break;
1196         }
1197 }
1198
1199 /******************************************/
1200 /* deactivate B-channel access and queues */
1201 /******************************************/
1202 static void
1203 close_hfcsx(struct BCState *bcs)
1204 {
1205         mode_hfcsx(bcs, 0, bcs->channel);
1206         if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) {
1207                 skb_queue_purge(&bcs->rqueue);
1208                 skb_queue_purge(&bcs->squeue);
1209                 if (bcs->tx_skb) {
1210                         dev_kfree_skb_any(bcs->tx_skb);
1211                         bcs->tx_skb = NULL;
1212                         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1213                 }
1214         }
1215 }
1216
1217 /*************************************/
1218 /* init B-channel queues and control */
1219 /*************************************/
1220 static int
1221 open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs)
1222 {
1223         if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
1224                 skb_queue_head_init(&bcs->rqueue);
1225                 skb_queue_head_init(&bcs->squeue);
1226         }
1227         bcs->tx_skb = NULL;
1228         test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
1229         bcs->event = 0;
1230         bcs->tx_cnt = 0;
1231         return (0);
1232 }
1233
1234 /*********************************/
1235 /* inits the stack for B-channel */
1236 /*********************************/
1237 static int
1238 setstack_2b(struct PStack *st, struct BCState *bcs)
1239 {
1240         bcs->channel = st->l1.bc;
1241         if (open_hfcsxstate(st->l1.hardware, bcs))
1242                 return (-1);
1243         st->l1.bcs = bcs;
1244         st->l2.l2l1 = hfcsx_l2l1;
1245         setstack_manager(st);
1246         bcs->st = st;
1247         setstack_l1_B(st);
1248         return (0);
1249 }
1250
1251 /***************************/
1252 /* handle L1 state changes */
1253 /***************************/
1254 static void
1255 hfcsx_bh(struct IsdnCardState *cs)
1256 {
1257         u_long flags;
1258
1259         if (!cs)
1260                 return;
1261         if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) {
1262                 if (!cs->hw.hfcsx.nt_mode)
1263                         switch (cs->dc.hfcsx.ph_state) {
1264                                 case (0):
1265                                         l1_msg(cs, HW_RESET | INDICATION, NULL);
1266                                         break;
1267                                 case (3):
1268                                         l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL);
1269                                         break;
1270                                 case (8):
1271                                         l1_msg(cs, HW_RSYNC | INDICATION, NULL);
1272                                         break;
1273                                 case (6):
1274                                         l1_msg(cs, HW_INFO2 | INDICATION, NULL);
1275                                         break;
1276                                 case (7):
1277                                         l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL);
1278                                         break;
1279                                 default:
1280                                         break;
1281                 } else {
1282                         switch (cs->dc.hfcsx.ph_state) {
1283                                 case (2):
1284                                         spin_lock_irqsave(&cs->lock, flags);
1285                                         if (cs->hw.hfcsx.nt_timer < 0) {
1286                                                 cs->hw.hfcsx.nt_timer = 0;
1287                                                 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1288                                                 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1289                                                 /* Clear already pending ints */
1290                                                 if (Read_hfc(cs, HFCSX_INT_S1));
1291
1292                                                 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE);
1293                                                 udelay(10);
1294                                                 Write_hfc(cs, HFCSX_STATES, 4);
1295                                                 cs->dc.hfcsx.ph_state = 4;
1296                                         } else {
1297                                                 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER;
1298                                                 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1299                                                 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER;
1300                                                 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125;
1301                                                 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1302                                                 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER);
1303                                                 cs->hw.hfcsx.nt_timer = NT_T1_COUNT;
1304                                                 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3);        /* allow G2 -> G3 transition */
1305                                         }
1306                                         spin_unlock_irqrestore(&cs->lock, flags);
1307                                         break;
1308                                 case (1):
1309                                 case (3):
1310                                 case (4):
1311                                         spin_lock_irqsave(&cs->lock, flags);
1312                                         cs->hw.hfcsx.nt_timer = 0;
1313                                         cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1314                                         Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1315                                         spin_unlock_irqrestore(&cs->lock, flags);
1316                                         break;
1317                                 default:
1318                                         break;
1319                         }
1320                 }
1321         }
1322         if (test_and_clear_bit(D_RCVBUFREADY, &cs->event))
1323                 DChannel_proc_rcv(cs);
1324         if (test_and_clear_bit(D_XMTBUFREADY, &cs->event))
1325                 DChannel_proc_xmt(cs);
1326 }
1327
1328
1329 /********************************/
1330 /* called for card init message */
1331 /********************************/
1332 void __devinit
1333 inithfcsx(struct IsdnCardState *cs)
1334 {
1335         cs->setstack_d = setstack_hfcsx;
1336         cs->BC_Send_Data = &hfcsx_send_data;
1337         cs->bcs[0].BC_SetStack = setstack_2b;
1338         cs->bcs[1].BC_SetStack = setstack_2b;
1339         cs->bcs[0].BC_Close = close_hfcsx;
1340         cs->bcs[1].BC_Close = close_hfcsx;
1341         mode_hfcsx(cs->bcs, 0, 0);
1342         mode_hfcsx(cs->bcs + 1, 0, 1);
1343 }
1344
1345
1346
1347 /*******************************************/
1348 /* handle card messages from control layer */
1349 /*******************************************/
1350 static int
1351 hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg)
1352 {
1353         u_long flags;
1354
1355         if (cs->debug & L1_DEB_ISAC)
1356                 debugl1(cs, "HFCSX: card_msg %x", mt);
1357         switch (mt) {
1358                 case CARD_RESET:
1359                         spin_lock_irqsave(&cs->lock, flags);
1360                         reset_hfcsx(cs);
1361                         spin_unlock_irqrestore(&cs->lock, flags);
1362                         return (0);
1363                 case CARD_RELEASE:
1364                         release_io_hfcsx(cs);
1365                         return (0);
1366                 case CARD_INIT:
1367                         spin_lock_irqsave(&cs->lock, flags);
1368                         inithfcsx(cs);
1369                         spin_unlock_irqrestore(&cs->lock, flags);
1370                         set_current_state(TASK_UNINTERRUPTIBLE);
1371                         schedule_timeout((80 * HZ) / 1000);     /* Timeout 80ms */
1372                         /* now switch timer interrupt off */
1373                         spin_lock_irqsave(&cs->lock, flags);
1374                         cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER;
1375                         Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1376                         /* reinit mode reg */
1377                         Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m);
1378                         spin_unlock_irqrestore(&cs->lock, flags);
1379                         return (0);
1380                 case CARD_TEST:
1381                         return (0);
1382         }
1383         return (0);
1384 }
1385
1386 #ifdef __ISAPNP__
1387 static struct isapnp_device_id hfc_ids[] __initdata = {
1388         { ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1389           ISAPNP_VENDOR('T', 'A', 'G'), ISAPNP_FUNCTION(0x2620),
1390           (unsigned long) "Teles 16.3c2" },
1391         { 0, }
1392 };
1393
1394 static struct isapnp_device_id *ipid __initdata = &hfc_ids[0];
1395 static struct pnp_card *pnp_c __devinitdata = NULL;
1396 #endif
1397
1398 int __devinit
1399 setup_hfcsx(struct IsdnCard *card)
1400 {
1401         struct IsdnCardState *cs = card->cs;
1402         char tmp[64];
1403
1404         strcpy(tmp, hfcsx_revision);
1405         printk(KERN_INFO "HiSax: HFC-SX driver Rev. %s\n", HiSax_getrev(tmp));
1406 #ifdef __ISAPNP__
1407         if (!card->para[1] && isapnp_present()) {
1408                 struct pnp_dev *pnp_d;
1409                 while(ipid->card_vendor) {
1410                         if ((pnp_c = pnp_find_card(ipid->card_vendor,
1411                                 ipid->card_device, pnp_c))) {
1412                                 pnp_d = NULL;
1413                                 if ((pnp_d = pnp_find_dev(pnp_c,
1414                                         ipid->vendor, ipid->function, pnp_d))) {
1415                                         int err;
1416
1417                                         printk(KERN_INFO "HiSax: %s detected\n",
1418                                                 (char *)ipid->driver_data);
1419                                         pnp_disable_dev(pnp_d);
1420                                         err = pnp_activate_dev(pnp_d);
1421                                         if (err<0) {
1422                                                 printk(KERN_WARNING "%s: pnp_activate_dev ret(%d)\n",
1423                                                         __FUNCTION__, err);
1424                                                 return(0);
1425                                         }
1426                                         card->para[1] = pnp_port_start(pnp_d, 0);
1427                                         card->para[0] = pnp_irq(pnp_d, 0);
1428                                         if (!card->para[0] || !card->para[1]) {
1429                                                 printk(KERN_ERR "HFC PnP:some resources are missing %ld/%lx\n",
1430                                                         card->para[0], card->para[1]);
1431                                                 pnp_disable_dev(pnp_d);
1432                                                 return(0);
1433                                         }
1434                                         break;
1435                                 } else {
1436                                         printk(KERN_ERR "HFC PnP: PnP error card found, no device\n");
1437                                 }
1438                         }
1439                         ipid++;
1440                         pnp_c = NULL;
1441                 }
1442                 if (!ipid->card_vendor) {
1443                         printk(KERN_INFO "HFC PnP: no ISAPnP card found\n");
1444                         return(0);
1445                 }
1446         }
1447 #endif
1448         cs->hw.hfcsx.base = card->para[1] & 0xfffe;
1449         cs->irq = card->para[0];
1450         cs->hw.hfcsx.int_s1 = 0;
1451         cs->dc.hfcsx.ph_state = 0;
1452         cs->hw.hfcsx.fifo = 255;
1453         if ((cs->typ == ISDN_CTYPE_HFC_SX) ||
1454             (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) {
1455                 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) {
1456                   printk(KERN_WARNING
1457                          "HiSax: HFC-SX io-base %#lx already in use\n",
1458                           cs->hw.hfcsx.base);
1459                   return(0);
1460                 }
1461                 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF);
1462                 byteout(cs->hw.hfcsx.base + 1,
1463                         ((cs->hw.hfcsx.base >> 8) & 3) | 0x54);
1464                 udelay(10);
1465                 cs->hw.hfcsx.chip = Read_hfc(cs,HFCSX_CHIP_ID);
1466                 switch (cs->hw.hfcsx.chip >> 4) {
1467                   case 1:
1468                     tmp[0] ='+';
1469                     break;
1470                   case 9:
1471                     tmp[0] ='P';
1472                     break;
1473                   default:
1474                     printk(KERN_WARNING
1475                            "HFC-SX: invalid chip id 0x%x\n",
1476                            cs->hw.hfcsx.chip >> 4);
1477                     release_region(cs->hw.hfcsx.base, 2);
1478                     return(0);
1479                 }
1480                 if (!ccd_sp_irqtab[cs->irq & 0xF]) {
1481                   printk(KERN_WARNING
1482                          "HFC_SX: invalid irq %d specified\n",cs->irq & 0xF);
1483                   release_region(cs->hw.hfcsx.base, 2);
1484                   return(0);
1485                 }
1486                 if (!(cs->hw.hfcsx.extra = (void *)
1487                       kmalloc(sizeof(struct hfcsx_extra), GFP_ATOMIC))) {
1488                   release_region(cs->hw.hfcsx.base, 2);
1489                   printk(KERN_WARNING "HFC-SX: unable to allocate memory\n");
1490                   return(0);
1491                 }
1492                 printk(KERN_INFO "HFC-S%c chip detected at base 0x%x IRQ %d HZ %d\n",
1493                         tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ);
1494                 cs->hw.hfcsx.int_m2 = 0;        /* disable alle interrupts */
1495                 cs->hw.hfcsx.int_m1 = 0;
1496                 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1);
1497                 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2);
1498         } else
1499                 return (0);     /* no valid card type */
1500
1501         cs->dbusytimer.function = (void *) hfcsx_dbusy_timer;
1502         cs->dbusytimer.data = (long) cs;
1503         init_timer(&cs->dbusytimer);
1504         INIT_WORK(&cs->tqueue, (void *)(void *) hfcsx_bh, cs);
1505         cs->readisac = NULL;
1506         cs->writeisac = NULL;
1507         cs->readisacfifo = NULL;
1508         cs->writeisacfifo = NULL;
1509         cs->BC_Read_Reg = NULL;
1510         cs->BC_Write_Reg = NULL;
1511         cs->irq_func = &hfcsx_interrupt;
1512
1513         cs->hw.hfcsx.timer.function = (void *) hfcsx_Timer;
1514         cs->hw.hfcsx.timer.data = (long) cs;
1515         cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */
1516         cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */
1517         init_timer(&cs->hw.hfcsx.timer);
1518
1519         reset_hfcsx(cs);
1520         cs->cardmsg = &hfcsx_card_msg;
1521         cs->auxcmd = &hfcsx_auxcmd;
1522         return (1);
1523 }