2 cx24110 - Single Chip Satellite Channel Receiver driver module
4 Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@t-online.de> based on
6 Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/slab.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
31 #include "dvb_frontend.h"
35 struct cx24110_state {
37 struct i2c_adapter* i2c;
39 struct dvb_frontend_ops ops;
41 const struct cx24110_config* config;
43 struct dvb_frontend frontend;
51 #define dprintk(args...) \
53 if (debug) printk(KERN_DEBUG "cx24110: " args); \
56 static struct {u8 reg; u8 data;} cx24110_regdata[]=
57 /* Comments beginning with @ denote this value should
59 {{0x09,0x01}, /* SoftResetAll */
60 {0x09,0x00}, /* release reset */
61 {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
62 {0x02,0x17}, /* middle byte " */
63 {0x03,0x29}, /* LSB " */
64 {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
65 {0x06,0xa5}, /* @ PLL 60MHz */
66 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
67 {0x0a,0x00}, /* @ partial chip disables, do not set */
68 {0x0b,0x01}, /* set output clock in gapped mode, start signal low
69 active for first byte */
70 {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
71 {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
72 {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
73 to avoid starting the BER counter. Reset the
74 CRC test bit. Finite counting selected */
75 {0x15,0xff}, /* @ size of the limited time window for RS BER
76 estimation. It is <value>*256 RS blocks, this
77 gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
78 {0x16,0x00}, /* @ enable all RS output ports */
79 {0x17,0x04}, /* @ time window allowed for the RS to sync */
80 {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
82 /* leave the current code rate and normalization
83 registers as they are after reset... */
84 {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
86 {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
87 estimation. It is <value>*65536 channel bits, i.e.
88 approx. 38ms at 27.5MS/s, rate 3/4 */
89 {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
90 /* leave front-end AGC parameters at default values */
91 /* leave decimation AGC parameters at default values */
92 {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
93 {0x36,0xff}, /* clear all interrupt pending flags */
94 {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
95 {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
96 /* leave the equalizer parameters on their default values */
97 /* leave the final AGC parameters on their default values */
98 {0x41,0x00}, /* @ MSB of front-end derotator frequency */
99 {0x42,0x00}, /* @ middle bytes " */
100 {0x43,0x00}, /* @ LSB " */
101 /* leave the carrier tracking loop parameters on default */
102 /* leave the bit timing loop parameters at gefault */
103 {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
104 /* the cx24108 data sheet for symbol rates above 15MS/s */
105 {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
106 {0x61,0x95}, /* GPIO pins 1-4 have special function */
107 {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
108 {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
109 {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
110 {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
111 {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
112 {0x73,0x00}, /* @ disable several demod bypasses */
113 {0x74,0x00}, /* @ " */
114 {0x75,0x00} /* @ " */
115 /* the remaining registers are for SEC */
119 static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
121 u8 buf [] = { reg, data };
122 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
125 if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
126 dprintk ("%s: writereg error (err == %i, reg == 0x%02x,"
127 " data == 0x%02x)\n", __FUNCTION__, err, reg, data);
135 static int cx24110_readreg (struct cx24110_state* state, u8 reg)
140 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
141 { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
143 ret = i2c_transfer(state->i2c, msg, 2);
145 if (ret != 2) return ret;
150 static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inversion_t inversion)
152 /* fixme (low): error handling */
156 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
157 /* AcqSpectrInvDis on. No idea why someone should want this */
158 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
159 /* Initial value 0 at start of acq */
160 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
161 /* current value 0 */
162 /* The cx24110 manual tells us this reg is read-only.
163 But what the heck... set it ayways */
166 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
167 /* AcqSpectrInvDis on. No idea why someone should want this */
168 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
169 /* Initial value 1 at start of acq */
170 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
171 /* current value 1 */
174 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
175 /* AcqSpectrInvDis off. Leave initial & current states as is */
185 static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
187 /* fixme (low): error handling */
189 static const int rate[]={-1,1,2,3,5,7,-1};
190 static const int g1[]={-1,0x01,0x02,0x05,0x15,0x45,-1};
191 static const int g2[]={-1,0x01,0x03,0x06,0x1a,0x7a,-1};
193 /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
194 searches all enabled viterbi rates, and can handle non-standard
200 if (fec==FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
201 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xdf);
202 /* clear AcqVitDis bit */
203 cx24110_writereg(state,0x18,0xae);
204 /* allow all DVB standard code rates */
205 cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|0x3);
206 /* set nominal Viterbi rate 3/4 */
207 cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|0x3);
208 /* set current Viterbi rate 3/4 */
209 cx24110_writereg(state,0x1a,0x05); cx24110_writereg(state,0x1b,0x06);
210 /* set the puncture registers for code rate 3/4 */
213 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x20);
214 /* set AcqVitDis bit */
216 cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|rate[fec]);
217 /* set nominal Viterbi rate */
218 cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|rate[fec]);
219 /* set current Viterbi rate */
220 cx24110_writereg(state,0x1a,g1[fec]);
221 cx24110_writereg(state,0x1b,g2[fec]);
222 /* not sure if this is the right way: I always used AutoAcq mode */
225 /* fixme (low): which is the correct return code? */
231 static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state)
235 i=cx24110_readreg(state,0x22)&0x0f;
237 return FEC_1_2 + i - 1;
239 /* fixme (low): a special code rate has been selected. In theory, we need to
240 return a denominator value, a numerator value, and a pair of puncture
241 maps to correctly describe this mode. But this should never happen in
242 practice, because it cannot be set by cx24110_get_fec. */
248 static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
250 /* fixme (low): add error handling */
254 static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
257 dprintk("cx24110 debug: entering %s(%d)\n",__FUNCTION__,srate);
258 if (srate>90999000UL/2)
263 for(i=0;(i<sizeof(bands)/sizeof(bands[0]))&&(srate>bands[i]);i++)
265 /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
266 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
267 R06[3:0] PLLphaseDetGain */
268 tmp=cx24110_readreg(state,0x07)&0xfc;
269 if(srate<90999000UL/4) { /* sample rate 45MHz*/
270 cx24110_writereg(state,0x07,tmp);
271 cx24110_writereg(state,0x06,0x78);
273 } else if(srate<60666000UL/2) { /* sample rate 60MHz */
274 cx24110_writereg(state,0x07,tmp|0x1);
275 cx24110_writereg(state,0x06,0xa5);
277 } else if(srate<80888000UL/2) { /* sample rate 80MHz */
278 cx24110_writereg(state,0x07,tmp|0x2);
279 cx24110_writereg(state,0x06,0x87);
281 } else { /* sample rate 90MHz */
282 cx24110_writereg(state,0x07,tmp|0x3);
283 cx24110_writereg(state,0x06,0x78);
286 dprintk("cx24110 debug: fclk %d Hz\n",fclk);
287 /* we need to divide two integers with approx. 27 bits in 32 bit
288 arithmetic giving a 25 bit result */
289 /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
290 also the most complex divisor. Hence, the dividend has,
291 assuming 32bit unsigned arithmetic, 6 clear bits on top, the
292 divisor 2 unused bits at the bottom. Also, the quotient is
293 always less than 1/2. Borrowed from VES1893.c, of course */
300 ratio=(ratio<<8)+(tmp/BDRI);
303 ratio=(ratio<<8)+(tmp/BDRI);
306 ratio=(ratio<<1)+(tmp/BDRI);
308 dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
309 dprintk("fclk = %d\n", fclk);
310 dprintk("ratio= %08x\n", ratio);
312 cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
313 cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
314 cx24110_writereg(state, 0x3, (ratio)&0xff);
331 int cx24110_pll_write (struct dvb_frontend* fe, u32 data)
333 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
335 /* tuner data is 21 bits long, must be left-aligned in data */
336 /* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
337 /* FIXME (low): add error handling, avoid infinite loops if HW fails... */
339 dprintk("cx24110 debug: cx24108_write(%8.8x)\n",data);
341 cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
342 cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
344 /* if the auto tuner writer is still busy, clear it out */
345 while (cx24110_readreg(state,0x6d)&0x80)
346 cx24110_writereg(state,0x72,0);
348 /* write the topmost 8 bits */
349 cx24110_writereg(state,0x72,(data>>24)&0xff);
351 /* wait for the send to be completed */
352 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
355 /* send another 8 bytes */
356 cx24110_writereg(state,0x72,(data>>16)&0xff);
357 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
360 /* and the topmost 5 bits of this byte */
361 cx24110_writereg(state,0x72,(data>>8)&0xff);
362 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
365 /* now strobe the enable line once */
366 cx24110_writereg(state,0x6d,0x32);
367 cx24110_writereg(state,0x6d,0x30);
374 static int cx24110_initfe(struct dvb_frontend* fe)
376 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
377 /* fixme (low): error handling */
380 dprintk("%s: init chip\n", __FUNCTION__);
382 for(i=0;i<sizeof(cx24110_regdata)/sizeof(cx24110_regdata[0]);i++) {
383 cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
386 if (state->config->pll_init) state->config->pll_init(fe);
392 static int cx24110_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
394 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
398 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
400 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
406 static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
407 struct dvb_diseqc_master_cmd *cmd)
410 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
412 for (i = 0; i < cmd->msg_len; i++)
413 cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
415 rv = cx24110_readreg(state, 0x76);
417 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
418 for (i=500; i-- > 0 && !(cx24110_readreg(state,0x76)&0x40);)
419 ; /* wait for LNB ready */
424 static int cx24110_read_status(struct dvb_frontend* fe, fe_status_t* status)
426 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
428 int sync = cx24110_readreg (state, 0x55);
433 *status |= FE_HAS_SIGNAL;
436 *status |= FE_HAS_CARRIER;
438 sync = cx24110_readreg (state, 0x08);
441 *status |= FE_HAS_VITERBI;
444 *status |= FE_HAS_SYNC;
446 if ((sync & 0x60) == 0x60)
447 *status |= FE_HAS_LOCK;
452 static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
454 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
456 /* fixme (maybe): value range is 16 bit. Scale? */
457 if(cx24110_readreg(state,0x24)&0x10) {
458 /* the Viterbi error counter has finished one counting window */
459 cx24110_writereg(state,0x24,0x04); /* select the ber reg */
460 state->lastber=cx24110_readreg(state,0x25)|
461 (cx24110_readreg(state,0x26)<<8);
462 cx24110_writereg(state,0x24,0x04); /* start new count window */
463 cx24110_writereg(state,0x24,0x14);
465 *ber = state->lastber;
470 static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
472 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
474 /* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
475 u8 signal = cx24110_readreg (state, 0x27)+128;
476 *signal_strength = (signal << 8) | signal;
481 static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
483 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
485 /* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
486 if(cx24110_readreg(state,0x6a)&0x80) {
487 /* the Es/N0 error counter has finished one counting window */
488 state->lastesn0=cx24110_readreg(state,0x69)|
489 (cx24110_readreg(state,0x68)<<8);
490 cx24110_writereg(state,0x6a,0x84); /* start new count window */
492 *snr = state->lastesn0;
497 static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
499 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
502 if(cx24110_readreg(state,0x10)&0x40) {
503 /* the RS error counter has finished one counting window */
504 cx24110_writereg(state,0x10,0x60); /* select the byer reg */
505 lastbyer=cx24110_readreg(state,0x12)|
506 (cx24110_readreg(state,0x13)<<8)|
507 (cx24110_readreg(state,0x14)<<16);
508 cx24110_writereg(state,0x10,0x70); /* select the bler reg */
509 state->lastbler=cx24110_readreg(state,0x12)|
510 (cx24110_readreg(state,0x13)<<8)|
511 (cx24110_readreg(state,0x14)<<16);
512 cx24110_writereg(state,0x10,0x20); /* start new count window */
514 *ucblocks = state->lastbler;
519 static int cx24110_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
521 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
523 state->config->pll_set(fe, p);
524 cx24110_set_inversion (state, p->inversion);
525 cx24110_set_fec (state, p->u.qpsk.fec_inner);
526 cx24110_set_symbolrate (state, p->u.qpsk.symbol_rate);
527 cx24110_writereg(state,0x04,0x05); /* start aquisition */
532 static int cx24110_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
534 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
535 s32 afc; unsigned sclk;
537 /* cannot read back tuner settings (freq). Need to have some private storage */
539 sclk = cx24110_readreg (state, 0x07) & 0x03;
540 /* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
541 * Need 64 bit arithmetic. Is thiss possible in the kernel? */
542 if (sclk==0) sclk=90999000L/2L;
543 else if (sclk==1) sclk=60666000L;
544 else if (sclk==2) sclk=80888000L;
547 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
548 ((sclk*cx24110_readreg (state, 0x45))>>8)+
549 ((sclk*cx24110_readreg (state, 0x46))>>16);
552 p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
553 INVERSION_ON : INVERSION_OFF;
554 p->u.qpsk.fec_inner = cx24110_get_fec (state);
559 static int cx24110_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
561 struct cx24110_state *state = (struct cx24110_state*) fe->demodulator_priv;
563 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
566 static void cx24110_release(struct dvb_frontend* fe)
568 struct cx24110_state* state = (struct cx24110_state*) fe->demodulator_priv;
572 static struct dvb_frontend_ops cx24110_ops;
574 struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
575 struct i2c_adapter* i2c)
577 struct cx24110_state* state = NULL;
580 /* allocate memory for the internal state */
581 state = (struct cx24110_state*) kmalloc(sizeof(struct cx24110_state), GFP_KERNEL);
582 if (state == NULL) goto error;
584 /* setup the state */
585 state->config = config;
587 memcpy(&state->ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
592 /* check if the demod is there */
593 ret = cx24110_readreg(state, 0x00);
594 if ((ret != 0x5a) && (ret != 0x69)) goto error;
596 /* create dvb_frontend */
597 state->frontend.ops = &state->ops;
598 state->frontend.demodulator_priv = state;
599 return &state->frontend;
602 if (state) kfree(state);
606 static struct dvb_frontend_ops cx24110_ops = {
609 .name = "Conexant CX24110 DVB-S",
611 .frequency_min = 950000,
612 .frequency_max = 2150000,
613 .frequency_stepsize = 1011, /* kHz for QPSK frontends */
614 .frequency_tolerance = 29500,
615 .symbol_rate_min = 1000000,
616 .symbol_rate_max = 45000000,
617 .caps = FE_CAN_INVERSION_AUTO |
618 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
619 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
620 FE_CAN_QPSK | FE_CAN_RECOVER
623 .release = cx24110_release,
625 .init = cx24110_initfe,
626 .set_frontend = cx24110_set_frontend,
627 .get_frontend = cx24110_get_frontend,
628 .read_status = cx24110_read_status,
629 .read_ber = cx24110_read_ber,
630 .read_signal_strength = cx24110_read_signal_strength,
631 .read_snr = cx24110_read_snr,
632 .read_ucblocks = cx24110_read_ucblocks,
634 .diseqc_send_master_cmd = cx24110_send_diseqc_msg,
635 .set_tone = cx24110_set_tone,
636 .set_voltage = cx24110_set_voltage,
639 module_param(debug, int, 0644);
640 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
642 MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
643 MODULE_AUTHOR("Peter Hettkamp");
644 MODULE_LICENSE("GPL");
646 EXPORT_SYMBOL(cx24110_attach);
647 EXPORT_SYMBOL(cx24110_pll_write);