drivers/media/dvb/frontends/dib3000mb.c

   1 /*
   2  * Frontend driver for mobile DVB-T demodulator DiBcom 3000-MB
   3  * DiBcom (http://www.dibcom.fr/)
   4  *
   5  * Copyright (C) 2004-5 Patrick Boettcher (patrick.boettcher@desy.de)
   6  *
   7  * based on GPL code from DibCom, which has
   8  *
   9  * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
  10  *
  11  *      This program is free software; you can redistribute it and/or
  12  *      modify it under the terms of the GNU General Public License as
  13  *      published by the Free Software Foundation, version 2.
  14  *
  15  * Acknowledgements
  16  *
  17  *  Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
  18  *  sources, on which this driver (and the dvb-dibusb) are based.
  19  *
  20  * see Documentation/dvb/README.dibusb for more information
  21  *
  22  */
  23
  24 #include <linux/config.h>
  25 #include <linux/kernel.h>
  26 #include <linux/version.h>
  27 #include <linux/module.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/init.h>
  30 #include <linux/delay.h>
  31
  32 #include "dib3000-common.h"
  33 #include "dib3000mb_priv.h"
  34 #include "dib3000.h"
  35
  36 /* Version information */
  37 #define DRIVER_VERSION "0.1"
  38 #define DRIVER_DESC "DiBcom 3000-MB DVB-T demodulator driver"
  39 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
  40
  41 #ifdef CONFIG_DVB_DIBCOM_DEBUG
  42 static int debug;
  43 module_param(debug, int, 0644);
  44 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
  45 #endif
  46 #define deb_info(args...) dprintk(0x01,args)
  47 #define deb_xfer(args...) dprintk(0x02,args)
  48 #define deb_setf(args...) dprintk(0x04,args)
  49 #define deb_getf(args...) dprintk(0x08,args)
  50
  51 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr);
  52
  53 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
  54                                   struct dvb_frontend_parameters *fep);
  55
  56 static int dib3000mb_set_frontend(struct dvb_frontend* fe,
  57                 struct dvb_frontend_parameters *fep, int tuner)
  58 {
  59         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
  60         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
  61         fe_code_rate_t fe_cr = FEC_NONE;
  62         int search_state,seq;
  63
  64         if (tuner) {
  65                 dib3000mb_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));
  66                 state->config.pll_set(fe, fep, NULL);
  67                 dib3000mb_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));
  68
  69                 deb_setf("bandwidth: ");
  70                 switch (ofdm->bandwidth) {
  71                         case BANDWIDTH_8_MHZ:
  72                                 deb_setf("8 MHz\n");
  73                                 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
  74                                 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
  75                                 break;
  76                         case BANDWIDTH_7_MHZ:
  77                                 deb_setf("7 MHz\n");
  78                                 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[1]);
  79                                 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_7mhz);
  80                                 break;
  81                         case BANDWIDTH_6_MHZ:
  82                                 deb_setf("6 MHz\n");
  83                                 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[0]);
  84                                 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_6mhz);
  85                                 break;
  86                         case BANDWIDTH_AUTO:
  87                                 return -EOPNOTSUPP;
  88                         default:
  89                                 err("unkown bandwidth value.");
  90                                 return -EINVAL;
  91                 }
  92         }
  93         wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
  94
  95         deb_setf("transmission mode: ");
  96         switch (ofdm->transmission_mode) {
  97                 case TRANSMISSION_MODE_2K:
  98                         deb_setf("2k\n");
  99                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
 100                         break;
 101                 case TRANSMISSION_MODE_8K:
 102                         deb_setf("8k\n");
 103                         wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
 104                         break;
 105                 case TRANSMISSION_MODE_AUTO:
 106                         deb_setf("auto\n");
 107                         break;
 108                 default:
 109                         return -EINVAL;
 110         }
 111
 112         deb_setf("guard: ");
 113         switch (ofdm->guard_interval) {
 114                 case GUARD_INTERVAL_1_32:
 115                         deb_setf("1_32\n");
 116                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
 117                         break;
 118                 case GUARD_INTERVAL_1_16:
 119                         deb_setf("1_16\n");
 120                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
 121                         break;
 122                 case GUARD_INTERVAL_1_8:
 123                         deb_setf("1_8\n");
 124                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
 125                         break;
 126                 case GUARD_INTERVAL_1_4:
 127                         deb_setf("1_4\n");
 128                         wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
 129                         break;
 130                 case GUARD_INTERVAL_AUTO:
 131                         deb_setf("auto\n");
 132                         break;
 133                 default:
 134                         return -EINVAL;
 135         }
 136
 137         deb_setf("inversion: ");
 138         switch (fep->inversion) {
 139                 case INVERSION_OFF:
 140                         deb_setf("off\n");
 141                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
 142                         break;
 143                 case INVERSION_AUTO:
 144                         deb_setf("auto ");
 145                         break;
 146                 case INVERSION_ON:
 147                         deb_setf("on\n");
 148                         wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
 149                         break;
 150                 default:
 151                         return -EINVAL;
 152         }
 153
 154         deb_setf("constellation: ");
 155         switch (ofdm->constellation) {
 156                 case QPSK:
 157                         deb_setf("qpsk\n");
 158                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
 159                         break;
 160                 case QAM_16:
 161                         deb_setf("qam16\n");
 162                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
 163                         break;
 164                 case QAM_64:
 165                         deb_setf("qam64\n");
 166                         wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
 167                         break;
 168                 case QAM_AUTO:
 169                         break;
 170                 default:
 171                         return -EINVAL;
 172         }
 173         deb_setf("hierachy: ");
 174         switch (ofdm->hierarchy_information) {
 175                 case HIERARCHY_NONE:
 176                         deb_setf("none ");
 177                         /* fall through */
 178                 case HIERARCHY_1:
 179                         deb_setf("alpha=1\n");
 180                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
 181                         break;
 182                 case HIERARCHY_2:
 183                         deb_setf("alpha=2\n");
 184                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
 185                         break;
 186                 case HIERARCHY_4:
 187                         deb_setf("alpha=4\n");
 188                         wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
 189                         break;
 190                 case HIERARCHY_AUTO:
 191                         deb_setf("alpha=auto\n");
 192                         break;
 193                 default:
 194                         return -EINVAL;
 195         }
 196
 197         deb_setf("hierarchy: ");
 198         if (ofdm->hierarchy_information == HIERARCHY_NONE) {
 199                 deb_setf("none\n");
 200                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
 201                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
 202                 fe_cr = ofdm->code_rate_HP;
 203         } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
 204                 deb_setf("on\n");
 205                 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
 206                 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
 207                 fe_cr = ofdm->code_rate_LP;
 208         }
 209         deb_setf("fec: ");
 210         switch (fe_cr) {
 211                 case FEC_1_2:
 212                         deb_setf("1_2\n");
 213                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
 214                         break;
 215                 case FEC_2_3:
 216                         deb_setf("2_3\n");
 217                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
 218                         break;
 219                 case FEC_3_4:
 220                         deb_setf("3_4\n");
 221                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
 222                         break;
 223                 case FEC_5_6:
 224                         deb_setf("5_6\n");
 225                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
 226                         break;
 227                 case FEC_7_8:
 228                         deb_setf("7_8\n");
 229                         wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
 230                         break;
 231                 case FEC_NONE:
 232                         deb_setf("none ");
 233                         break;
 234                 case FEC_AUTO:
 235                         deb_setf("auto\n");
 236                         break;
 237                 default:
 238                         return -EINVAL;
 239         }
 240
 241         seq = dib3000_seq
 242                 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
 243                 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
 244                 [fep->inversion == INVERSION_AUTO];
 245
 246         deb_setf("seq? %d\n",seq);
 247
 248         wr(DIB3000MB_REG_SEQ,seq);
 249
 250         wr(DIB3000MB_REG_ISI,seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
 251
 252         if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
 253                 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
 254                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_2K_1_8);
 255                 } else {
 256                         wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_DEFAULT);
 257                 }
 258
 259                 wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_2K);
 260         } else {
 261                 wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_DEFAULT);
 262         }
 263
 264         wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_OFF);
 265         wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
 266         wr(DIB3000MB_REG_MOBILE_MODE,DIB3000MB_MOBILE_MODE_OFF);
 267
 268         wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_high);
 269
 270         wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_ACTIVATE);
 271
 272         wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AGC+DIB3000MB_RESTART_CTRL);
 273         wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
 274
 275         /* wait for AGC lock */
 276         msleep(70);
 277
 278         wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
 279
 280         /* something has to be auto searched */
 281         if (ofdm->constellation == QAM_AUTO ||
 282                 ofdm->hierarchy_information == HIERARCHY_AUTO ||
 283                 fe_cr == FEC_AUTO ||
 284                 fep->inversion == INVERSION_AUTO) {
 285                 int as_count=0;
 286
 287                 deb_setf("autosearch enabled.\n");
 288
 289                 wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
 290
 291                 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AUTO_SEARCH);
 292                 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
 293
 294                 while ((search_state =
 295                                 dib3000_search_status(
 296                                         rd(DIB3000MB_REG_AS_IRQ_PENDING),
 297                                         rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
 298                         msleep(1);
 299
 300                 deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
 301
 302                 if (search_state == 1) {
 303                         struct dvb_frontend_parameters feps;
 304                         if (dib3000mb_get_frontend(fe, &feps) == 0) {
 305                                 deb_setf("reading tuning data from frontend succeeded.\n");
 306                                 return dib3000mb_set_frontend(fe, &feps, 0);
 307                         }
 308                 }
 309
 310         } else {
 311                 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_CTRL);
 312                 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
 313         }
 314
 315         return 0;
 316 }
 317
 318 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
 319 {
 320         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
 321
 322         wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_UP);
 323
 324         wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
 325
 326         wr(DIB3000MB_REG_RESET_DEVICE,DIB3000MB_RESET_DEVICE);
 327         wr(DIB3000MB_REG_RESET_DEVICE,DIB3000MB_RESET_DEVICE_RST);
 328
 329         wr(DIB3000MB_REG_CLOCK,DIB3000MB_CLOCK_DEFAULT);
 330
 331         wr(DIB3000MB_REG_ELECT_OUT_MODE,DIB3000MB_ELECT_OUT_MODE_ON);
 332
 333         wr(DIB3000MB_REG_DDS_FREQ_MSB,DIB3000MB_DDS_FREQ_MSB);
 334         wr(DIB3000MB_REG_DDS_FREQ_LSB,DIB3000MB_DDS_FREQ_LSB);
 335
 336         wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
 337
 338         wr_foreach(dib3000mb_reg_impulse_noise,
 339                         dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
 340
 341         wr_foreach(dib3000mb_reg_agc_gain,dib3000mb_default_agc_gain);
 342
 343         wr(DIB3000MB_REG_PHASE_NOISE,DIB3000MB_PHASE_NOISE_DEFAULT);
 344
 345         wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
 346
 347         wr_foreach(dib3000mb_reg_lock_duration,dib3000mb_default_lock_duration);
 348
 349         wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
 350
 351         wr(DIB3000MB_REG_LOCK0_MASK,DIB3000MB_LOCK0_DEFAULT);
 352         wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
 353         wr(DIB3000MB_REG_LOCK2_MASK,DIB3000MB_LOCK2_DEFAULT);
 354         wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
 355
 356         wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
 357
 358         wr(DIB3000MB_REG_UNK_68,DIB3000MB_UNK_68);
 359         wr(DIB3000MB_REG_UNK_69,DIB3000MB_UNK_69);
 360         wr(DIB3000MB_REG_UNK_71,DIB3000MB_UNK_71);
 361         wr(DIB3000MB_REG_UNK_77,DIB3000MB_UNK_77);
 362         wr(DIB3000MB_REG_UNK_78,DIB3000MB_UNK_78);
 363         wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
 364         wr(DIB3000MB_REG_UNK_92,DIB3000MB_UNK_92);
 365         wr(DIB3000MB_REG_UNK_96,DIB3000MB_UNK_96);
 366         wr(DIB3000MB_REG_UNK_97,DIB3000MB_UNK_97);
 367         wr(DIB3000MB_REG_UNK_106,DIB3000MB_UNK_106);
 368         wr(DIB3000MB_REG_UNK_107,DIB3000MB_UNK_107);
 369         wr(DIB3000MB_REG_UNK_108,DIB3000MB_UNK_108);
 370         wr(DIB3000MB_REG_UNK_122,DIB3000MB_UNK_122);
 371         wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
 372         wr(DIB3000MB_REG_BERLEN,DIB3000MB_BERLEN_DEFAULT);
 373
 374         wr_foreach(dib3000mb_reg_filter_coeffs,dib3000mb_filter_coeffs);
 375
 376         wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_ON);
 377         wr(DIB3000MB_REG_MULTI_DEMOD_MSB,DIB3000MB_MULTI_DEMOD_MSB);
 378         wr(DIB3000MB_REG_MULTI_DEMOD_LSB,DIB3000MB_MULTI_DEMOD_LSB);
 379
 380         wr(DIB3000MB_REG_OUTPUT_MODE,DIB3000MB_OUTPUT_MODE_SLAVE);
 381
 382         wr(DIB3000MB_REG_FIFO_142,DIB3000MB_FIFO_142);
 383         wr(DIB3000MB_REG_MPEG2_OUT_MODE,DIB3000MB_MPEG2_OUT_MODE_188);
 384         wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
 385         wr(DIB3000MB_REG_FIFO,DIB3000MB_FIFO_INHIBIT);
 386         wr(DIB3000MB_REG_FIFO_146,DIB3000MB_FIFO_146);
 387         wr(DIB3000MB_REG_FIFO_147,DIB3000MB_FIFO_147);
 388
 389         wr(DIB3000MB_REG_DATA_IN_DIVERSITY,DIB3000MB_DATA_DIVERSITY_IN_OFF);
 390
 391         if (state->config.pll_init) {
 392                 dib3000mb_tuner_pass_ctrl(fe,1,state->config.pll_addr(fe));
 393                 state->config.pll_init(fe,NULL);
 394                 dib3000mb_tuner_pass_ctrl(fe,0,state->config.pll_addr(fe));
 395         }
 396
 397         return 0;
 398 }
 399
 400 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
 401                                   struct dvb_frontend_parameters *fep)
 402 {
 403         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
 404         struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
 405         fe_code_rate_t *cr;
 406         u16 tps_val;
 407         int inv_test1,inv_test2;
 408         u32 dds_val, threshold = 0x800000;
 409
 410         if (!rd(DIB3000MB_REG_TPS_LOCK))
 411                 return 0;
 412
 413         dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
 414         deb_getf("DDS_VAL: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_VALUE_MSB), rd(DIB3000MB_REG_DDS_VALUE_LSB));
 415         if (dds_val < threshold)
 416                 inv_test1 = 0;
 417         else if (dds_val == threshold)
 418                 inv_test1 = 1;
 419         else
 420                 inv_test1 = 2;
 421
 422         dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
 423         deb_getf("DDS_FREQ: %x %x %x",dds_val, rd(DIB3000MB_REG_DDS_FREQ_MSB), rd(DIB3000MB_REG_DDS_FREQ_LSB));
 424         if (dds_val < threshold)
 425                 inv_test2 = 0;
 426         else if (dds_val == threshold)
 427                 inv_test2 = 1;
 428         else
 429                 inv_test2 = 2;
 430
 431         fep->inversion =
 432                 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
 433                 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
 434                 INVERSION_ON : INVERSION_OFF;
 435
 436         deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
 437
 438         switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
 439                 case DIB3000_CONSTELLATION_QPSK:
 440                         deb_getf("QPSK ");
 441                         ofdm->constellation = QPSK;
 442                         break;
 443                 case DIB3000_CONSTELLATION_16QAM:
 444                         deb_getf("QAM16 ");
 445                         ofdm->constellation = QAM_16;
 446                         break;
 447                 case DIB3000_CONSTELLATION_64QAM:
 448                         deb_getf("QAM64 ");
 449                         ofdm->constellation = QAM_64;
 450                         break;
 451                 default:
 452                         err("Unexpected constellation returned by TPS (%d)", tps_val);
 453                         break;
 454         }
 455         deb_getf("TPS: %d\n", tps_val);
 456
 457         if (rd(DIB3000MB_REG_TPS_HRCH)) {
 458                 deb_getf("HRCH ON\n");
 459                 cr = &ofdm->code_rate_LP;
 460                 ofdm->code_rate_HP = FEC_NONE;
 461                 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
 462                         case DIB3000_ALPHA_0:
 463                                 deb_getf("HIERARCHY_NONE ");
 464                                 ofdm->hierarchy_information = HIERARCHY_NONE;
 465                                 break;
 466                         case DIB3000_ALPHA_1:
 467                                 deb_getf("HIERARCHY_1 ");
 468                                 ofdm->hierarchy_information = HIERARCHY_1;
 469                                 break;
 470                         case DIB3000_ALPHA_2:
 471                                 deb_getf("HIERARCHY_2 ");
 472                                 ofdm->hierarchy_information = HIERARCHY_2;
 473                                 break;
 474                         case DIB3000_ALPHA_4:
 475                                 deb_getf("HIERARCHY_4 ");
 476                                 ofdm->hierarchy_information = HIERARCHY_4;
 477                                 break;
 478                         default:
 479                                 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
 480                                 break;
 481                 }
 482                 deb_getf("TPS: %d\n", tps_val);
 483
 484                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
 485         } else {
 486                 deb_getf("HRCH OFF\n");
 487                 cr = &ofdm->code_rate_HP;
 488                 ofdm->code_rate_LP = FEC_NONE;
 489                 ofdm->hierarchy_information = HIERARCHY_NONE;
 490
 491                 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
 492         }
 493
 494         switch (tps_val) {
 495                 case DIB3000_FEC_1_2:
 496                         deb_getf("FEC_1_2 ");
 497                         *cr = FEC_1_2;
 498                         break;
 499                 case DIB3000_FEC_2_3:
 500                         deb_getf("FEC_2_3 ");
 501                         *cr = FEC_2_3;
 502                         break;
 503                 case DIB3000_FEC_3_4:
 504                         deb_getf("FEC_3_4 ");
 505                         *cr = FEC_3_4;
 506                         break;
 507                 case DIB3000_FEC_5_6:
 508                         deb_getf("FEC_5_6 ");
 509                         *cr = FEC_4_5;
 510                         break;
 511                 case DIB3000_FEC_7_8:
 512                         deb_getf("FEC_7_8 ");
 513                         *cr = FEC_7_8;
 514                         break;
 515                 default:
 516                         err("Unexpected FEC returned by TPS (%d)", tps_val);
 517                         break;
 518         }
 519         deb_getf("TPS: %d\n",tps_val);
 520
 521         switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
 522                 case DIB3000_GUARD_TIME_1_32:
 523                         deb_getf("GUARD_INTERVAL_1_32 ");
 524                         ofdm->guard_interval = GUARD_INTERVAL_1_32;
 525                         break;
 526                 case DIB3000_GUARD_TIME_1_16:
 527                         deb_getf("GUARD_INTERVAL_1_16 ");
 528                         ofdm->guard_interval = GUARD_INTERVAL_1_16;
 529                         break;
 530                 case DIB3000_GUARD_TIME_1_8:
 531                         deb_getf("GUARD_INTERVAL_1_8 ");
 532                         ofdm->guard_interval = GUARD_INTERVAL_1_8;
 533                         break;
 534                 case DIB3000_GUARD_TIME_1_4:
 535                         deb_getf("GUARD_INTERVAL_1_4 ");
 536                         ofdm->guard_interval = GUARD_INTERVAL_1_4;
 537                         break;
 538                 default:
 539                         err("Unexpected Guard Time returned by TPS (%d)", tps_val);
 540                         break;
 541         }
 542         deb_getf("TPS: %d\n", tps_val);
 543
 544         switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
 545                 case DIB3000_TRANSMISSION_MODE_2K:
 546                         deb_getf("TRANSMISSION_MODE_2K ");
 547                         ofdm->transmission_mode = TRANSMISSION_MODE_2K;
 548                         break;
 549                 case DIB3000_TRANSMISSION_MODE_8K:
 550                         deb_getf("TRANSMISSION_MODE_8K ");
 551                         ofdm->transmission_mode = TRANSMISSION_MODE_8K;
 552                         break;
 553                 default:
 554                         err("unexpected transmission mode return by TPS (%d)", tps_val);
 555                         break;
 556         }
 557         deb_getf("TPS: %d\n", tps_val);
 558
 559         return 0;
 560 }
 561
 562 static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
 563 {
 564         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
 565
 566         *stat = 0;
 567
 568         if (rd(DIB3000MB_REG_AGC_LOCK))
 569                 *stat |= FE_HAS_SIGNAL;
 570         if (rd(DIB3000MB_REG_CARRIER_LOCK))
 571                 *stat |= FE_HAS_CARRIER;
 572         if (rd(DIB3000MB_REG_VIT_LCK))
 573                 *stat |= FE_HAS_VITERBI;
 574         if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
 575                 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
 576
 577         deb_info("actual status is %2x\n",*stat);
 578
 579         deb_getf("tps %x %x %x %x %x\n",
 580                         rd(DIB3000MB_REG_TPS_1),
 581                         rd(DIB3000MB_REG_TPS_2),
 582                         rd(DIB3000MB_REG_TPS_3),
 583                         rd(DIB3000MB_REG_TPS_4),
 584                         rd(DIB3000MB_REG_TPS_5));
 585
 586         deb_info("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
 587                         rd(DIB3000MB_REG_TPS_LOCK),
 588                         rd(DIB3000MB_REG_TPS_QAM),
 589                         rd(DIB3000MB_REG_TPS_HRCH),
 590                         rd(DIB3000MB_REG_TPS_VIT_ALPHA),
 591                         rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
 592                         rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
 593                         rd(DIB3000MB_REG_TPS_GUARD_TIME),
 594                         rd(DIB3000MB_REG_TPS_FFT),
 595                         rd(DIB3000MB_REG_TPS_CELL_ID));
 596
 597         //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 598         return 0;
 599 }
 600
 601 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
 602 {
 603         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
 604
 605         *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB) );
 606         return 0;
 607 }
 608 /*
 609  * Amaury:
 610  * signal strength is measured with dBm (power compared to mW)
 611  * the standard range is -90dBm(low power) to -10 dBm (strong power),
 612  * but the calibration is done for -100 dBm to 0dBm
 613  */
 614
 615 #define DIB3000MB_AGC_REF_dBm           -14
 616 #define DIB3000MB_GAIN_SLOPE_dBm        100
 617 #define DIB3000MB_GAIN_DELTA_dBm        -2
 618 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
 619 {
 620         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
 621
 622 /* TODO log10
 623         u16 sigpow = rd(DIB3000MB_REG_SIGNAL_POWER),
 624                 n_agc_power = rd(DIB3000MB_REG_AGC_POWER),
 625                 rf_power = rd(DIB3000MB_REG_RF_POWER);
 626         double rf_power_dBm, ad_power_dBm, minar_power_dBm;
 627
 628         if (n_agc_power == 0 )
 629                 n_agc_power = 1 ;
 630
 631         ad_power_dBm    = 10 * log10 ( (float)n_agc_power / (float)(1<<16) );
 632         minor_power_dBm = ad_power_dBm - DIB3000MB_AGC_REF_dBm;
 633         rf_power_dBm = (-DIB3000MB_GAIN_SLOPE_dBm * (float)rf_power / (float)(1<<16) +
 634                         DIB3000MB_GAIN_DELTA_dBm) + minor_power_dBm;
 635         // relative rf_power
 636         *strength = (u16) ((rf_power_dBm + 100) / 100 * 0xffff);
 637 */
 638         *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
 639         return 0;
 640 }
 641
 642 /*
 643  * Amaury:
 644  * snr is the signal quality measured in dB.
 645  * snr = 10*log10(signal power / noise power)
 646  * the best quality is near 35dB (cable transmission & good modulator)
 647  * the minimum without errors depend of transmission parameters
 648  * some indicative values are given in en300744 Annex A
 649  * ex : 16QAM 2/3 (Gaussian)  = 11.1 dB
 650  *
 651  * If SNR is above 20dB, BER should be always 0.
 652  * choose 0dB as the minimum
 653  */
 654 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
 655 {
 656         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
 657         short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
 658         int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
 659                 rd(DIB3000MB_REG_NOISE_POWER_LSB);
 660 /*
 661         float snr_dBm=0;
 662
 663         if (sigpow > 0 && icipow > 0)
 664                 snr_dBm = 10.0 * log10( (float) (sigpow<<8) / (float)icipow )  ;
 665         else if (sigpow > 0)
 666                 snr_dBm = 35;
 667
 668         *snr = (u16) ((snr_dBm / 35) * 0xffff);
 669 */
 670         *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
 671         return 0;
 672 }
 673
 674 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
 675 {
 676         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
 677
 678         *unc = rd(DIB3000MB_REG_UNC);
 679         return 0;
 680 }
 681
 682 static int dib3000mb_sleep(struct dvb_frontend* fe)
 683 {
 684         struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
 685
 686         wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_DOWN);
 687         return 0;
 688 }
 689
 690 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
 691 {
 692         tune->min_delay_ms = 800;
 693         tune->step_size = 166667;
 694         tune->max_drift = 166667*2;
 695
 696         return 0;
 697 }
 698
 699 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
 700 {
 701         return dib3000mb_fe_init(fe, 0);
 702 }
 703
 704 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
 705 {
 706         return dib3000mb_set_frontend(fe, fep, 1);
 707 }
 708
 709 static void dib3000mb_release(struct dvb_frontend* fe)
 710 {
 711         struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
 712         kfree(state);
 713 }
 714
 715 /* pid filter and transfer stuff */
 716 static int dib3000mb_pid_control(struct dvb_frontend *fe,int index, int pid,int onoff)
 717 {
 718         struct dib3000_state *state = fe->demodulator_priv;
 719         pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
 720                 wr(index+DIB3000MB_REG_FIRST_PID,pid);
 721         return 0;
 722 }
 723
 724 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
 725 {
 726         struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
 727
 728         deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
 729         if (onoff) {
 730                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
 731         } else {
 732                 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
 733         }
 734         return 0;
 735         }
 736
 737 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
 738 {
 739         //struct dib3000_state *state = fe->demodulator_priv;
 740         /* switch it off and on */
 741         return 0;
 742         }
 743
 744 static int dib3000mb_tuner_pass_ctrl(struct dvb_frontend *fe, int onoff, u8 pll_addr)
 745 {
 746         struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
 747         if (onoff) {
 748                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));
 749         } else {
 750                 wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));
 751         }
 752         return 0;
 753 }
 754
 755 static struct dvb_frontend_ops dib3000mb_ops;
 756
 757 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
 758                                       struct i2c_adapter* i2c, struct dib_fe_xfer_ops *xfer_ops)
 759 {
 760         struct dib3000_state* state = NULL;
 761
 762         /* allocate memory for the internal state */
 763         state = (struct dib3000_state*) kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
 764         if (state == NULL)
 765                 goto error;
 766
 767         /* setup the state */
 768         state->i2c = i2c;
 769         memcpy(&state->config,config,sizeof(struct dib3000_config));
 770         memcpy(&state->ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
 771
 772         /* check for the correct demod */
 773         if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
 774                 goto error;
 775
 776         if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
 777                 goto error;
 778
 779         /* create dvb_frontend */
 780         state->frontend.ops = &state->ops;
 781         state->frontend.demodulator_priv = state;
 782
 783         /* set the xfer operations */
 784         xfer_ops->pid_parse = dib3000mb_pid_parse;
 785         xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
 786         xfer_ops->pid_ctrl = dib3000mb_pid_control;
 787         xfer_ops->tuner_pass_ctrl = dib3000mb_tuner_pass_ctrl;
 788
 789         return &state->frontend;
 790
 791 error:
 792         if (state)
 793         kfree(state);
 794         return NULL;
 795         }
 796
 797 static struct dvb_frontend_ops dib3000mb_ops = {
 798
 799         .info = {
 800                 .name                   = "DiBcom 3000-MB DVB-T",
 801                 .type                   = FE_OFDM,
 802                 .frequency_min          = 44250000,
 803                 .frequency_max          = 867250000,
 804                 .frequency_stepsize     = 62500,
 805                 .caps = FE_CAN_INVERSION_AUTO |
 806                                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 807                                 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 808                                 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 809                                 FE_CAN_TRANSMISSION_MODE_AUTO |
 810                                 FE_CAN_GUARD_INTERVAL_AUTO |
 811                                 FE_CAN_RECOVER |
 812                                 FE_CAN_HIERARCHY_AUTO,
 813         },
 814
 815         .release = dib3000mb_release,
 816
 817         .init = dib3000mb_fe_init_nonmobile,
 818         .sleep = dib3000mb_sleep,
 819
 820         .set_frontend = dib3000mb_set_frontend_and_tuner,
 821         .get_frontend = dib3000mb_get_frontend,
 822         .get_tune_settings = dib3000mb_fe_get_tune_settings,
 823
 824         .read_status = dib3000mb_read_status,
 825         .read_ber = dib3000mb_read_ber,
 826         .read_signal_strength = dib3000mb_read_signal_strength,
 827         .read_snr = dib3000mb_read_snr,
 828         .read_ucblocks = dib3000mb_read_unc_blocks,
 829 };
 830
 831 MODULE_AUTHOR(DRIVER_AUTHOR);
 832 MODULE_DESCRIPTION(DRIVER_DESC);
 833 MODULE_LICENSE("GPL");
 834
 835 EXPORT_SYMBOL(dib3000mb_attach);