2 * Frontend driver for mobile DVB-T demodulator DiBcom 3000-MB
3 * DiBcom (http://www.dibcom.fr/)
5 * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
7 * based on GPL code from DibCom, which has
9 * Copyright (C) 2004 Amaury Demol for DiBcom (ademol@dibcom.fr)
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation, version 2.
17 * Amaury Demol (ademol@dibcom.fr) from DiBcom for providing specs and driver
18 * sources, on which this driver (and the dvb-dibusb) are based.
20 * see Documentation/dvb/README.dibusb for more information
24 #include <linux/config.h>
25 #include <linux/kernel.h>
26 #include <linux/version.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
32 #include "dvb_frontend.h"
33 #include "dib3000-common.h"
34 #include "dib3000mb_priv.h"
37 /* Version information */
38 #define DRIVER_VERSION "0.1"
39 #define DRIVER_DESC "DiBcom 3000-MB DVB-T demodulator driver"
40 #define DRIVER_AUTHOR "Patrick Boettcher, patrick.boettcher@desy.de"
42 #ifdef CONFIG_DVB_DIBCOM_DEBUG
44 module_param(debug, int, 0x644);
45 MODULE_PARM_DESC(debug, "set debugging level (1=info,2=xfer,4=setfe,8=getfe (|-able)).");
47 #define deb_info(args...) dprintk(0x01,args)
48 #define deb_xfer(args...) dprintk(0x02,args)
49 #define deb_setf(args...) dprintk(0x04,args)
50 #define deb_getf(args...) dprintk(0x08,args)
52 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
53 struct dvb_frontend_parameters *fep);
55 static int dib3000mb_set_frontend(struct dvb_frontend* fe,
56 struct dvb_frontend_parameters *fep, int tuner)
58 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
59 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
60 fe_code_rate_t fe_cr = FEC_NONE;
64 wr(DIB3000MB_REG_TUNER,
65 DIB3000_TUNER_WRITE_ENABLE(state->config.pll_addr));
66 state->config.pll_set(fe, fep);
67 wr(DIB3000MB_REG_TUNER,
68 DIB3000_TUNER_WRITE_DISABLE(state->config.pll_addr));
70 deb_setf("bandwidth: ");
71 switch (ofdm->bandwidth) {
74 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
75 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
79 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[1]);
80 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_7mhz);
84 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[0]);
85 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_6mhz);
90 err("unkown bandwidth value.");
94 wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
96 deb_setf("transmission mode: ");
97 switch (ofdm->transmission_mode) {
98 case TRANSMISSION_MODE_2K:
100 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);
102 case TRANSMISSION_MODE_8K:
104 wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);
106 case TRANSMISSION_MODE_AUTO:
114 switch (ofdm->guard_interval) {
115 case GUARD_INTERVAL_1_32:
117 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);
119 case GUARD_INTERVAL_1_16:
121 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);
123 case GUARD_INTERVAL_1_8:
125 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);
127 case GUARD_INTERVAL_1_4:
129 wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);
131 case GUARD_INTERVAL_AUTO:
138 deb_setf("inversion: ");
139 switch (fep->inversion) {
142 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);
149 wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);
155 deb_setf("constellation: ");
156 switch (ofdm->constellation) {
159 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);
163 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);
167 wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);
174 deb_setf("hierachy: ");
175 switch (ofdm->hierarchy_information) {
180 deb_setf("alpha=1\n");
181 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);
184 deb_setf("alpha=2\n");
185 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);
188 deb_setf("alpha=4\n");
189 wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);
192 deb_setf("alpha=auto\n");
198 deb_setf("hierarchy: ");
199 if (ofdm->hierarchy_information == HIERARCHY_NONE) {
201 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);
202 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);
203 fe_cr = ofdm->code_rate_HP;
204 } else if (ofdm->hierarchy_information != HIERARCHY_AUTO) {
206 wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);
207 wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);
208 fe_cr = ofdm->code_rate_LP;
214 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);
218 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);
222 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);
226 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);
230 wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);
243 [ofdm->transmission_mode == TRANSMISSION_MODE_AUTO]
244 [ofdm->guard_interval == GUARD_INTERVAL_AUTO]
245 [fep->inversion == INVERSION_AUTO];
247 deb_setf("seq? %d\n",seq);
249 wr(DIB3000MB_REG_SEQ,seq);
251 wr(DIB3000MB_REG_ISI,seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);
253 if (ofdm->transmission_mode == TRANSMISSION_MODE_2K) {
254 if (ofdm->guard_interval == GUARD_INTERVAL_1_8) {
255 wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_2K_1_8);
257 wr(DIB3000MB_REG_SYNC_IMPROVEMENT,DIB3000MB_SYNC_IMPROVE_DEFAULT);
260 wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_2K);
262 wr(DIB3000MB_REG_UNK_121,DIB3000MB_UNK_121_DEFAULT);
265 wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_OFF);
266 wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
267 wr(DIB3000MB_REG_MOBILE_MODE,DIB3000MB_MOBILE_MODE_OFF);
269 wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_high);
271 wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_ACTIVATE);
273 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AGC+DIB3000MB_RESTART_CTRL);
274 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
276 /* wait for AGC lock */
279 wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
281 /* something has to be auto searched */
282 if (ofdm->constellation == QAM_AUTO ||
283 ofdm->hierarchy_information == HIERARCHY_AUTO ||
285 fep->inversion == INVERSION_AUTO) {
288 deb_setf("autosearch enabled.\n");
290 wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
292 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_AUTO_SEARCH);
293 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
295 while ((search_state =
296 dib3000_search_status(
297 rd(DIB3000MB_REG_AS_IRQ_PENDING),
298 rd(DIB3000MB_REG_LOCK2_VALUE))) < 0 && as_count++ < 100)
301 deb_info("search_state after autosearch %d after %d checks\n",search_state,as_count);
303 if (search_state == 1) {
304 struct dvb_frontend_parameters feps;
305 if (dib3000mb_get_frontend(fe, &feps) == 0) {
306 deb_setf("reading tuning data from frontend succeeded.\n");
307 return dib3000mb_set_frontend(fe, &feps, 0);
312 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_CTRL);
313 wr(DIB3000MB_REG_RESTART,DIB3000MB_RESTART_OFF);
319 static int dib3000mb_fe_init(struct dvb_frontend* fe, int mobile_mode)
321 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
323 wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_UP);
325 wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);
327 wr(DIB3000MB_REG_RESET_DEVICE,DIB3000MB_RESET_DEVICE);
328 wr(DIB3000MB_REG_RESET_DEVICE,DIB3000MB_RESET_DEVICE_RST);
330 wr(DIB3000MB_REG_CLOCK,DIB3000MB_CLOCK_DEFAULT);
332 wr(DIB3000MB_REG_ELECT_OUT_MODE,DIB3000MB_ELECT_OUT_MODE_ON);
334 wr(DIB3000MB_REG_DDS_FREQ_MSB,DIB3000MB_DDS_FREQ_MSB);
335 wr(DIB3000MB_REG_DDS_FREQ_LSB,DIB3000MB_DDS_FREQ_LSB);
337 wr_foreach(dib3000mb_reg_timing_freq,dib3000mb_timing_freq[2]);
339 wr_foreach(dib3000mb_reg_impulse_noise,
340 dib3000mb_impulse_noise_values[DIB3000MB_IMPNOISE_OFF]);
342 wr_foreach(dib3000mb_reg_agc_gain,dib3000mb_default_agc_gain);
344 wr(DIB3000MB_REG_PHASE_NOISE,DIB3000MB_PHASE_NOISE_DEFAULT);
346 wr_foreach(dib3000mb_reg_phase_noise, dib3000mb_default_noise_phase);
348 wr_foreach(dib3000mb_reg_lock_duration,dib3000mb_default_lock_duration);
350 wr_foreach(dib3000mb_reg_agc_bandwidth,dib3000mb_agc_bandwidth_low);
352 wr(DIB3000MB_REG_LOCK0_MASK,DIB3000MB_LOCK0_DEFAULT);
353 wr(DIB3000MB_REG_LOCK1_MASK,DIB3000MB_LOCK1_SEARCH_4);
354 wr(DIB3000MB_REG_LOCK2_MASK,DIB3000MB_LOCK2_DEFAULT);
355 wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);
357 wr_foreach(dib3000mb_reg_bandwidth,dib3000mb_bandwidth_8mhz);
359 wr(DIB3000MB_REG_UNK_68,DIB3000MB_UNK_68);
360 wr(DIB3000MB_REG_UNK_69,DIB3000MB_UNK_69);
361 wr(DIB3000MB_REG_UNK_71,DIB3000MB_UNK_71);
362 wr(DIB3000MB_REG_UNK_77,DIB3000MB_UNK_77);
363 wr(DIB3000MB_REG_UNK_78,DIB3000MB_UNK_78);
364 wr(DIB3000MB_REG_ISI,DIB3000MB_ISI_INHIBIT);
365 wr(DIB3000MB_REG_UNK_92,DIB3000MB_UNK_92);
366 wr(DIB3000MB_REG_UNK_96,DIB3000MB_UNK_96);
367 wr(DIB3000MB_REG_UNK_97,DIB3000MB_UNK_97);
368 wr(DIB3000MB_REG_UNK_106,DIB3000MB_UNK_106);
369 wr(DIB3000MB_REG_UNK_107,DIB3000MB_UNK_107);
370 wr(DIB3000MB_REG_UNK_108,DIB3000MB_UNK_108);
371 wr(DIB3000MB_REG_UNK_122,DIB3000MB_UNK_122);
372 wr(DIB3000MB_REG_MOBILE_MODE_QAM,DIB3000MB_MOBILE_MODE_QAM_OFF);
373 wr(DIB3000MB_REG_BERLEN,DIB3000MB_BERLEN_DEFAULT);
375 wr_foreach(dib3000mb_reg_filter_coeffs,dib3000mb_filter_coeffs);
377 wr(DIB3000MB_REG_MOBILE_ALGO,DIB3000MB_MOBILE_ALGO_ON);
378 wr(DIB3000MB_REG_MULTI_DEMOD_MSB,DIB3000MB_MULTI_DEMOD_MSB);
379 wr(DIB3000MB_REG_MULTI_DEMOD_LSB,DIB3000MB_MULTI_DEMOD_LSB);
381 wr(DIB3000MB_REG_OUTPUT_MODE,DIB3000MB_OUTPUT_MODE_SLAVE);
383 wr(DIB3000MB_REG_FIFO_142,DIB3000MB_FIFO_142);
384 wr(DIB3000MB_REG_MPEG2_OUT_MODE,DIB3000MB_MPEG2_OUT_MODE_188);
385 wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);
386 wr(DIB3000MB_REG_FIFO,DIB3000MB_FIFO_INHIBIT);
387 wr(DIB3000MB_REG_FIFO_146,DIB3000MB_FIFO_146);
388 wr(DIB3000MB_REG_FIFO_147,DIB3000MB_FIFO_147);
390 wr(DIB3000MB_REG_DATA_IN_DIVERSITY,DIB3000MB_DATA_DIVERSITY_IN_OFF);
392 if (state->config.pll_init) {
393 wr(DIB3000MB_REG_TUNER,
394 DIB3000_TUNER_WRITE_ENABLE(state->config.pll_addr));
395 state->config.pll_init(fe);
396 wr(DIB3000MB_REG_TUNER,
397 DIB3000_TUNER_WRITE_DISABLE(state->config.pll_addr));
403 static int dib3000mb_get_frontend(struct dvb_frontend* fe,
404 struct dvb_frontend_parameters *fep)
406 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
407 struct dvb_ofdm_parameters *ofdm = &fep->u.ofdm;
410 int inv_test1,inv_test2;
411 u32 dds_val, threshold = 0x800000;
413 if (!rd(DIB3000MB_REG_TPS_LOCK))
416 dds_val = ((rd(DIB3000MB_REG_DDS_VALUE_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_VALUE_LSB);
417 if (dds_val < threshold)
419 else if (dds_val == threshold)
424 dds_val = ((rd(DIB3000MB_REG_DDS_FREQ_MSB) & 0xff) << 16) + rd(DIB3000MB_REG_DDS_FREQ_LSB);
425 if (dds_val < threshold)
427 else if (dds_val == threshold)
433 ((inv_test2 == 2) && (inv_test1==1 || inv_test1==0)) ||
434 ((inv_test2 == 0) && (inv_test1==1 || inv_test1==2)) ?
435 INVERSION_ON : INVERSION_OFF;
437 deb_getf("inversion %d %d, %d\n", inv_test2, inv_test1, fep->inversion);
439 switch ((tps_val = rd(DIB3000MB_REG_TPS_QAM))) {
440 case DIB3000_CONSTELLATION_QPSK:
442 ofdm->constellation = QPSK;
444 case DIB3000_CONSTELLATION_16QAM:
446 ofdm->constellation = QAM_16;
448 case DIB3000_CONSTELLATION_64QAM:
450 ofdm->constellation = QAM_64;
453 err("Unexpected constellation returned by TPS (%d)", tps_val);
456 deb_getf("TPS: %d\n", tps_val);
458 if (rd(DIB3000MB_REG_TPS_HRCH)) {
459 deb_getf("HRCH ON\n");
460 cr = &ofdm->code_rate_LP;
461 ofdm->code_rate_HP = FEC_NONE;
462 switch ((tps_val = rd(DIB3000MB_REG_TPS_VIT_ALPHA))) {
463 case DIB3000_ALPHA_0:
464 deb_getf("HIERARCHY_NONE ");
465 ofdm->hierarchy_information = HIERARCHY_NONE;
467 case DIB3000_ALPHA_1:
468 deb_getf("HIERARCHY_1 ");
469 ofdm->hierarchy_information = HIERARCHY_1;
471 case DIB3000_ALPHA_2:
472 deb_getf("HIERARCHY_2 ");
473 ofdm->hierarchy_information = HIERARCHY_2;
475 case DIB3000_ALPHA_4:
476 deb_getf("HIERARCHY_4 ");
477 ofdm->hierarchy_information = HIERARCHY_4;
480 err("Unexpected ALPHA value returned by TPS (%d)", tps_val);
483 deb_getf("TPS: %d\n", tps_val);
485 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_LP);
487 deb_getf("HRCH OFF\n");
488 cr = &ofdm->code_rate_HP;
489 ofdm->code_rate_LP = FEC_NONE;
490 ofdm->hierarchy_information = HIERARCHY_NONE;
492 tps_val = rd(DIB3000MB_REG_TPS_CODE_RATE_HP);
496 case DIB3000_FEC_1_2:
497 deb_getf("FEC_1_2 ");
500 case DIB3000_FEC_2_3:
501 deb_getf("FEC_2_3 ");
504 case DIB3000_FEC_3_4:
505 deb_getf("FEC_3_4 ");
508 case DIB3000_FEC_5_6:
509 deb_getf("FEC_5_6 ");
512 case DIB3000_FEC_7_8:
513 deb_getf("FEC_7_8 ");
517 err("Unexpected FEC returned by TPS (%d)", tps_val);
520 deb_getf("TPS: %d\n",tps_val);
522 switch ((tps_val = rd(DIB3000MB_REG_TPS_GUARD_TIME))) {
523 case DIB3000_GUARD_TIME_1_32:
524 deb_getf("GUARD_INTERVAL_1_32 ");
525 ofdm->guard_interval = GUARD_INTERVAL_1_32;
527 case DIB3000_GUARD_TIME_1_16:
528 deb_getf("GUARD_INTERVAL_1_16 ");
529 ofdm->guard_interval = GUARD_INTERVAL_1_16;
531 case DIB3000_GUARD_TIME_1_8:
532 deb_getf("GUARD_INTERVAL_1_8 ");
533 ofdm->guard_interval = GUARD_INTERVAL_1_8;
535 case DIB3000_GUARD_TIME_1_4:
536 deb_getf("GUARD_INTERVAL_1_4 ");
537 ofdm->guard_interval = GUARD_INTERVAL_1_4;
540 err("Unexpected Guard Time returned by TPS (%d)", tps_val);
543 deb_getf("TPS: %d\n", tps_val);
545 switch ((tps_val = rd(DIB3000MB_REG_TPS_FFT))) {
546 case DIB3000_TRANSMISSION_MODE_2K:
547 deb_getf("TRANSMISSION_MODE_2K ");
548 ofdm->transmission_mode = TRANSMISSION_MODE_2K;
550 case DIB3000_TRANSMISSION_MODE_8K:
551 deb_getf("TRANSMISSION_MODE_8K ");
552 ofdm->transmission_mode = TRANSMISSION_MODE_8K;
555 err("unexpected transmission mode return by TPS (%d)", tps_val);
558 deb_getf("TPS: %d\n", tps_val);
563 static int dib3000mb_read_status(struct dvb_frontend* fe, fe_status_t *stat)
565 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
569 if (rd(DIB3000MB_REG_AGC_LOCK))
570 *stat |= FE_HAS_SIGNAL;
571 if (rd(DIB3000MB_REG_CARRIER_LOCK))
572 *stat |= FE_HAS_CARRIER;
573 if (rd(DIB3000MB_REG_VIT_LCK))
574 *stat |= FE_HAS_VITERBI;
575 if (rd(DIB3000MB_REG_TS_SYNC_LOCK))
576 *stat |= (FE_HAS_SYNC | FE_HAS_LOCK);
578 deb_info("actual status is %2x\n",*stat);
580 deb_getf("tps %x %x %x %x %x\n",
581 rd(DIB3000MB_REG_TPS_1),
582 rd(DIB3000MB_REG_TPS_2),
583 rd(DIB3000MB_REG_TPS_3),
584 rd(DIB3000MB_REG_TPS_4),
585 rd(DIB3000MB_REG_TPS_5));
587 deb_info("autoval: tps: %d, qam: %d, hrch: %d, alpha: %d, hp: %d, lp: %d, guard: %d, fft: %d cell: %d\n",
588 rd(DIB3000MB_REG_TPS_LOCK),
589 rd(DIB3000MB_REG_TPS_QAM),
590 rd(DIB3000MB_REG_TPS_HRCH),
591 rd(DIB3000MB_REG_TPS_VIT_ALPHA),
592 rd(DIB3000MB_REG_TPS_CODE_RATE_HP),
593 rd(DIB3000MB_REG_TPS_CODE_RATE_LP),
594 rd(DIB3000MB_REG_TPS_GUARD_TIME),
595 rd(DIB3000MB_REG_TPS_FFT),
596 rd(DIB3000MB_REG_TPS_CELL_ID));
598 //*stat = FE_HAS_SIGNAL | FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
602 static int dib3000mb_read_ber(struct dvb_frontend* fe, u32 *ber)
604 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
606 *ber = ((rd(DIB3000MB_REG_BER_MSB) << 16) | rd(DIB3000MB_REG_BER_LSB) );
611 * signal strength is measured with dBm (power compared to mW)
612 * the standard range is -90dBm(low power) to -10 dBm (strong power),
613 * but the calibration is done for -100 dBm to 0dBm
616 #define DIB3000MB_AGC_REF_dBm -14
617 #define DIB3000MB_GAIN_SLOPE_dBm 100
618 #define DIB3000MB_GAIN_DELTA_dBm -2
619 static int dib3000mb_read_signal_strength(struct dvb_frontend* fe, u16 *strength)
621 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
624 u16 sigpow = rd(DIB3000MB_REG_SIGNAL_POWER),
625 n_agc_power = rd(DIB3000MB_REG_AGC_POWER),
626 rf_power = rd(DIB3000MB_REG_RF_POWER);
627 double rf_power_dBm, ad_power_dBm, minar_power_dBm;
629 if (n_agc_power == 0 )
632 ad_power_dBm = 10 * log10 ( (float)n_agc_power / (float)(1<<16) );
633 minor_power_dBm = ad_power_dBm - DIB3000MB_AGC_REF_dBm;
634 rf_power_dBm = (-DIB3000MB_GAIN_SLOPE_dBm * (float)rf_power / (float)(1<<16) +
635 DIB3000MB_GAIN_DELTA_dBm) + minor_power_dBm;
637 *strength = (u16) ((rf_power_dBm + 100) / 100 * 0xffff);
639 *strength = rd(DIB3000MB_REG_SIGNAL_POWER) * 0xffff / 0x170;
645 * snr is the signal quality measured in dB.
646 * snr = 10*log10(signal power / noise power)
647 * the best quality is near 35dB (cable transmission & good modulator)
648 * the minimum without errors depend of transmission parameters
649 * some indicative values are given in en300744 Annex A
650 * ex : 16QAM 2/3 (Gaussian) = 11.1 dB
652 * If SNR is above 20dB, BER should be always 0.
653 * choose 0dB as the minimum
655 static int dib3000mb_read_snr(struct dvb_frontend* fe, u16 *snr)
657 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
658 short sigpow = rd(DIB3000MB_REG_SIGNAL_POWER);
659 int icipow = ((rd(DIB3000MB_REG_NOISE_POWER_MSB) & 0xff) << 16) |
660 rd(DIB3000MB_REG_NOISE_POWER_LSB);
664 if (sigpow > 0 && icipow > 0)
665 snr_dBm = 10.0 * log10( (float) (sigpow<<8) / (float)icipow ) ;
669 *snr = (u16) ((snr_dBm / 35) * 0xffff);
671 *snr = (sigpow << 8) / ((icipow > 0) ? icipow : 1);
675 static int dib3000mb_read_unc_blocks(struct dvb_frontend* fe, u32 *unc)
677 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
679 *unc = rd(DIB3000MB_REG_UNC);
683 static int dib3000mb_sleep(struct dvb_frontend* fe)
685 struct dib3000_state* state = (struct dib3000_state*) fe->demodulator_priv;
687 wr(DIB3000MB_REG_POWER_CONTROL,DIB3000MB_POWER_DOWN);
691 static int dib3000mb_fe_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings *tune)
693 tune->min_delay_ms = 800;
694 tune->step_size = 166667;
695 tune->max_drift = 166667*2;
700 static int dib3000mb_fe_init_nonmobile(struct dvb_frontend* fe)
702 return dib3000mb_fe_init(fe, 0);
705 static int dib3000mb_set_frontend_and_tuner(struct dvb_frontend* fe, struct dvb_frontend_parameters *fep)
707 return dib3000mb_set_frontend(fe, fep, 1);
710 static void dib3000mb_release(struct dvb_frontend* fe)
712 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
716 /* pid filter and transfer stuff */
717 static int dib3000mb_pid_control(struct dvb_frontend *fe,int pid,int onoff)
719 struct dib3000_state *state = fe->demodulator_priv;
720 int index = dib3000_get_pid_index(state->pid_list, DIB3000MB_NUM_PIDS, pid, &state->pid_list_lock,onoff);
721 pid = (onoff ? pid | DIB3000_ACTIVATE_PID_FILTERING : 0);
724 wr(index+DIB3000MB_REG_FIRST_PID,pid);
726 err("no more pids for filtering.");
732 static int dib3000mb_fifo_control(struct dvb_frontend *fe, int onoff)
734 struct dib3000_state *state = (struct dib3000_state*) fe->demodulator_priv;
736 deb_xfer("%s fifo\n",onoff ? "enabling" : "disabling");
738 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);
740 wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);
745 static int dib3000mb_pid_parse(struct dvb_frontend *fe, int onoff)
747 //struct dib3000_state *state = fe->demodulator_priv;
748 /* switch it off and on */
752 static struct dvb_frontend_ops dib3000mb_ops;
754 struct dvb_frontend* dib3000mb_attach(const struct dib3000_config* config,
755 struct i2c_adapter* i2c, struct dib3000_xfer_ops *xfer_ops)
757 struct dib3000_state* state = NULL;
759 /* allocate memory for the internal state */
760 state = (struct dib3000_state*) kmalloc(sizeof(struct dib3000_state), GFP_KERNEL);
764 /* setup the state */
766 memcpy(&state->config,config,sizeof(struct dib3000_config));
767 memcpy(&state->ops, &dib3000mb_ops, sizeof(struct dvb_frontend_ops));
769 /* check for the correct demod */
770 if (rd(DIB3000_REG_MANUFACTOR_ID) != DIB3000_I2C_ID_DIBCOM)
773 if (rd(DIB3000_REG_DEVICE_ID) != DIB3000MB_DEVICE_ID)
776 if (dib3000_init_pid_list(state,DIB3000MB_NUM_PIDS))
779 /* create dvb_frontend */
780 state->frontend.ops = &state->ops;
781 state->frontend.demodulator_priv = state;
783 /* set the xfer operations */
784 xfer_ops->pid_parse = dib3000mb_pid_parse;
785 xfer_ops->fifo_ctrl = dib3000mb_fifo_control;
786 xfer_ops->pid_ctrl = dib3000mb_pid_control;
788 return &state->frontend;
796 static struct dvb_frontend_ops dib3000mb_ops = {
799 .name = "DiBcom 3000-MB DVB-T",
801 .frequency_min = 44250000,
802 .frequency_max = 867250000,
803 .frequency_stepsize = 62500,
804 .caps = FE_CAN_INVERSION_AUTO |
805 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
806 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
807 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
808 FE_CAN_TRANSMISSION_MODE_AUTO |
809 FE_CAN_GUARD_INTERVAL_AUTO |
810 FE_CAN_HIERARCHY_AUTO,
813 .release = dib3000mb_release,
815 .init = dib3000mb_fe_init_nonmobile,
816 .sleep = dib3000mb_sleep,
818 .set_frontend = dib3000mb_set_frontend_and_tuner,
819 .get_frontend = dib3000mb_get_frontend,
820 .get_tune_settings = dib3000mb_fe_get_tune_settings,
822 .read_status = dib3000mb_read_status,
823 .read_ber = dib3000mb_read_ber,
824 .read_signal_strength = dib3000mb_read_signal_strength,
825 .read_snr = dib3000mb_read_snr,
826 .read_ucblocks = dib3000mb_read_unc_blocks,
829 MODULE_AUTHOR(DRIVER_AUTHOR);
830 MODULE_DESCRIPTION(DRIVER_DESC);
831 MODULE_LICENSE("GPL");
833 EXPORT_SYMBOL(dib3000mb_attach);