drivers/media/dvb/frontends/dib3000mc_priv.h

   1 /*
   2  * dib3000mc_priv.h
   3  *
   4  * Copyright (C) 2004 Patrick Boettcher (patrick.boettcher@desy.de)
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License as
   8  *      published by the Free Software Foundation, version 2.
   9  *
  10  * for more information see dib3000mc.c .
  11  */
  12
  13 #ifndef __DIB3000MC_PRIV_H__
  14 #define __DIB3000MC_PRIV_H__
  15
  16 /* info and err, taken from usb.h, if there is anything available like by default,
  17  * please change !
  18  */
  19 #define err(format, arg...) printk(KERN_ERR "%s: " format "\n" , __FILE__ , ## arg)
  20 #define info(format, arg...) printk(KERN_INFO "%s: " format "\n" , __FILE__ , ## arg)
  21 #define warn(format, arg...) printk(KERN_WARNING "%s: " format "\n" , __FILE__ , ## arg)
  22
  23 // defines the phase noise algorithm to be used (O:Inhib, 1:CPE on)
  24 #define DEF_PHASE_NOISE_MODE                0
  25
  26 // define Mobille algorithms
  27 #define DEF_MOBILE_MODE      Auto_Reception
  28
  29 // defines the tuner type
  30 #define DEF_TUNER_TYPE   TUNER_PANASONIC_ENV57H13D5
  31
  32 // defines the impule noise algorithm to be used
  33 #define DEF_IMPULSE_NOISE_MODE      0
  34
  35 // defines the MPEG2 data output format
  36 #define DEF_MPEG2_OUTPUT_188       0
  37
  38 // defines the MPEG2 data output format
  39 #define DEF_OUTPUT_MODE       MPEG2_PARALLEL_CONTINUOUS_CLOCK
  40
  41 /*
  42  * Demodulator parameters
  43  * reg: 0  1 1  1 11 11 111
  44  *         | |  |  |  |  |
  45  *         | |  |  |  |  +-- alpha (000=0, 001=1, 010=2, 100=4)
  46  *         | |  |  |  +----- constellation (00=QPSK, 01=16QAM, 10=64QAM)
  47  *         | |  |  +-------- guard (00=1/32, 01=1/16, 10=1/8, 11=1/4)
  48  *         | |  +----------- transmission mode (0=2k, 1=8k)
  49  *         | |
  50  *         | +-------------- restart autosearch for parameters
  51  *         +---------------- restart the demodulator
  52  * reg: 181      1 111 1
  53  *               |  |  |
  54  *               |  |  +- FEC applies for HP or LP (0=LP, 1=HP)
  55  *               |  +---- FEC rate (001=1/2, 010=2/3, 011=3/4, 101=5/6, 111=7/8)
  56  *               +------- hierarchy on (0=no, 1=yes)
  57  */
  58
  59 /* demodulator tuning parameter and restart options */
  60 #define DIB3000MC_REG_DEMOD_PARM                (     0)
  61 #define DIB3000MC_DEMOD_PARM(a,c,g,t)   ( \
  62                  (0x7 & a) | \
  63                 ((0x3 & c) << 3) | \
  64                 ((0x3 & g) << 5) | \
  65                 ((0x1 & t) << 7) )
  66 #define DIB3000MC_DEMOD_RST_AUTO_SRCH_ON        (1 << 8)
  67 #define DIB3000MC_DEMOD_RST_AUTO_SRCH_OFF       (0 << 8)
  68 #define DIB3000MC_DEMOD_RST_DEMOD_ON            (1 << 9)
  69 #define DIB3000MC_DEMOD_RST_DEMOD_OFF           (0 << 9)
  70
  71 /* register for hierarchy parameters */
  72 #define DIB3000MC_REG_HRCH_PARM                 (   181)
  73 #define DIB3000MC_HRCH_PARM(s,f,h)              ( \
  74                  (0x1 & s) | \
  75                 ((0x7 & f) << 1) | \
  76                 ((0x1 & h) << 4) )
  77
  78 /* timeout ??? */
  79 #define DIB3000MC_REG_UNK_1                             (     1)
  80 #define DIB3000MC_UNK_1                                 (  0x04)
  81
  82 /* timeout ??? */
  83 #define DIB3000MC_REG_UNK_2                             (     2)
  84 #define DIB3000MC_UNK_2                                 (  0x04)
  85
  86 /* timeout ??? */
  87 #define DIB3000MC_REG_UNK_3                             (     3)
  88 #define DIB3000MC_UNK_3                                 (0x1000)
  89
  90 #define DIB3000MC_REG_UNK_4                             (     4)
  91 #define DIB3000MC_UNK_4                                 (0x0814)
  92
  93 /* timeout ??? */
  94 #define DIB3000MC_REG_SEQ_TPS                   (     5)
  95 #define DIB3000MC_SEQ_TPS_DEFAULT               (     1)
  96 #define DIB3000MC_SEQ_TPS(s,t)                  ( \
  97                 ((s & 0x0f) << 4) | \
  98                 ((t & 0x01) << 8) )
  99 #define DIB3000MC_IS_TPS(v)                             ((v << 8) & 0x1)
 100 #define DIB3000MC_IS_AS(v)                              ((v >> 4) & 0xf)
 101
 102 /* parameters for the bandwidth */
 103 #define DIB3000MC_REG_BW_TIMOUT_MSB             (     6)
 104 #define DIB3000MC_REG_BW_TIMOUT_LSB             (     7)
 105
 106 static u16 dib3000mc_reg_bandwidth[] = { 6,7,8,9,10,11,16,17 };
 107
 108 /*static u16 dib3000mc_bandwidth_5mhz[] =
 109         { 0x28, 0x9380, 0x87, 0x4100, 0x2a4, 0x4500, 0x1, 0xb0d0 };*/
 110
 111 static u16 dib3000mc_bandwidth_6mhz[] =
 112         { 0x21, 0xd040, 0x70, 0xb62b, 0x233, 0x8ed5, 0x1, 0xb0d0 };
 113
 114 static u16 dib3000mc_bandwidth_7mhz[] =
 115         { 0x1c, 0xfba5, 0x60, 0x9c25, 0x1e3, 0x0cb7, 0x1, 0xb0d0 };
 116
 117 static u16 dib3000mc_bandwidth_8mhz[] =
 118         { 0x19, 0x5c30, 0x54, 0x88a0, 0x1a6, 0xab20, 0x1, 0xb0b0 };
 119
 120 static u16 dib3000mc_reg_bandwidth_general[] = { 12,13,14,15 };
 121 static u16 dib3000mc_bandwidth_general[] = { 0x0000, 0x03e8, 0x0000, 0x03f2 };
 122
 123 /* lock mask */
 124 #define DIB3000MC_REG_LOCK_MASK                 (    15)
 125 #define DIB3000MC_ACTIVATE_LOCK_MASK    (0x0800)
 126
 127 /* reset the uncorrected packet count (??? do it 5 times) */
 128 #define DIB3000MC_REG_RST_UNC                   (    18)
 129 #define DIB3000MC_RST_UNC_ON                    (     1)
 130 #define DIB3000MC_RST_UNC_OFF                   (     0)
 131
 132 #define DIB3000MC_REG_UNK_19                    (    19)
 133 #define DIB3000MC_UNK_19                                (     0)
 134
 135 /* DDS frequency value (IF position) and inversion bit */
 136 #define DIB3000MC_REG_INVERSION                 (    21)
 137 #define DIB3000MC_REG_SET_DDS_FREQ_MSB  (    21)
 138 #define DIB3000MC_DDS_FREQ_MSB_INV_OFF  (0x0164)
 139 #define DIB3000MC_DDS_FREQ_MSB_INV_ON   (0x0364)
 140
 141 #define DIB3000MC_REG_SET_DDS_FREQ_LSB  (    22)
 142 #define DIB3000MC_DDS_FREQ_LSB                  (0x463d)
 143
 144 /* timing frequencies setting */
 145 #define DIB3000MC_REG_TIMING_FREQ_MSB   (    23)
 146 #define DIB3000MC_REG_TIMING_FREQ_LSB   (    24)
 147 #define DIB3000MC_CLOCK_REF                             (0x151fd1)
 148
 149 //static u16 dib3000mc_reg_timing_freq[] = { 23,24 };
 150
 151 //static u16 dib3000mc_timing_freq[][2] = {
 152 //      { 0x69, 0x9f18 }, /* 5 MHz */
 153 //      { 0x7e ,0xbee9 }, /* 6 MHz */
 154 //      { 0x93 ,0xdebb }, /* 7 MHz */
 155 //      { 0xa8 ,0xfe8c }, /* 8 MHz */
 156 //};
 157
 158 /* timeout ??? */
 159 static u16 dib3000mc_reg_offset[] = { 26,33 };
 160
 161 static u16 dib3000mc_offset[][2] = {
 162         { 26240, 5 }, /* default */
 163         { 30336, 6 }, /* 8K */
 164         { 38528, 8 }, /* 2K */
 165 };
 166
 167 #define DIB3000MC_REG_ISI                               (    29)
 168 #define DIB3000MC_ISI_DEFAULT                   (0x1073)
 169 #define DIB3000MC_ISI_ACTIVATE                  (0x0000)
 170 #define DIB3000MC_ISI_INHIBIT                   (0x0200)
 171
 172 /* impulse noise control */
 173 static u16 dib3000mc_reg_imp_noise_ctl[] = { 34,35 };
 174
 175 static u16 dib3000mc_imp_noise_ctl[][2] = {
 176         { 0x1294, 0xfff8 }, /* mode 0 */
 177         { 0x1294, 0xfff8 }, /* mode 1 */
 178         { 0x1294, 0xfff8 }, /* mode 2 */
 179         { 0x1294, 0xfff8 }, /* mode 3 */
 180         { 0x1294, 0xfff8 }, /* mode 4 */
 181 };
 182
 183 /* AGC registers */
 184 static u16 dib3000mc_reg_agc[] = {
 185         36,37,38,39,42,43,44,45,46,47,48,49
 186 };
 187
 188 static u16 dib3000mc_agc_tuner[][12] = {
 189         {       0x0051, 0x301d, 0x0000, 0x1cc7, 0xcf5c, 0x6666,
 190                 0xbae1, 0xa148, 0x3b5e, 0x3c1c, 0x001a, 0x2019
 191         }, /* TUNER_PANASONIC_ENV77H04D5, */
 192
 193         {       0x0051, 0x301d, 0x0000, 0x1cc7, 0xdc29, 0x570a,
 194                 0xbae1, 0x8ccd, 0x3b6d, 0x551d, 0x000a, 0x951e
 195         }, /* TUNER_PANASONIC_ENV57H13D5, TUNER_PANASONIC_ENV57H12D5 */
 196
 197         {       0x0051, 0x301d, 0x0000, 0x1cc7, 0xffff, 0xffff,
 198                 0xffff, 0x0000, 0xfdfd, 0x4040, 0x00fd, 0x4040
 199         }, /* TUNER_SAMSUNG_DTOS333IH102, TUNER_RFAGCIN_UNKNOWN */
 200
 201         {       0x0196, 0x301d, 0x0000, 0x1cc7, 0xbd71, 0x5c29,
 202                 0xb5c3, 0x6148, 0x6569, 0x5127, 0x0033, 0x3537
 203         }, /* TUNER_PROVIDER_X */
 204         /* TODO TUNER_PANASONIC_ENV57H10D8, TUNER_PANASONIC_ENV57H11D8 */
 205 };
 206
 207 /* AGC loop bandwidth */
 208 static u16 dib3000mc_reg_agc_bandwidth[] = { 40,41 };
 209 static u16 dib3000mc_agc_bandwidth[]  = { 0x119,0x330 };
 210
 211 static u16 dib3000mc_reg_agc_bandwidth_general[] = { 50,51,52,53,54 };
 212 static u16 dib3000mc_agc_bandwidth_general[] =
 213         { 0x8000, 0x91ca, 0x01ba, 0x0087, 0x0087 };
 214
 215 #define DIB3000MC_REG_IMP_NOISE_55              (    55)
 216 #define DIB3000MC_IMP_NEW_ALGO(w)               (w | (1<<10))
 217
 218 /* Impulse noise params */
 219 static u16 dib3000mc_reg_impulse_noise[] = { 55,56,57 };
 220 static u16 dib3000mc_impluse_noise[][3] = {
 221         { 0x489, 0x89, 0x72 }, /* 5 MHz */
 222         { 0x4a5, 0xa5, 0x89 }, /* 6 MHz */
 223         { 0x4c0, 0xc0, 0xa0 }, /* 7 MHz */
 224         { 0x4db, 0xdb, 0xb7 }, /* 8 Mhz */
 225 };
 226
 227 static u16 dib3000mc_reg_fft[] = {
 228         58,59,60,61,62,63,64,65,66,67,68,69,
 229         70,71,72,73,74,75,76,77,78,79,80,81,
 230         82,83,84,85,86
 231 };
 232
 233 static u16 dib3000mc_fft_modes[][29] = {
 234         {       0x38, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c,
 235                 0x3ffe, 0x7f3, 0x2d94, 0x76, 0x53d,
 236                 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3,
 237                 0x3feb, 0x7d2, 0x365e, 0x76, 0x48c,
 238                 0x3ffe, 0x5b3, 0x3feb, 0x76,   0x0, 0xd
 239         }, /* fft mode 0 */
 240         {       0x3b, 0x6d9, 0x3f28, 0x7a7, 0x3a74, 0x196, 0x32a, 0x48c,
 241                 0x3ffe, 0x7f3, 0x2d94, 0x76, 0x53d,
 242                 0x3ff8, 0x7e3, 0x3320, 0x76, 0x5b3,
 243                 0x3feb, 0x7d2, 0x365e, 0x76, 0x48c,
 244                 0x3ffe, 0x5b3, 0x3feb, 0x0,  0x8200, 0xd
 245         }, /* fft mode 1 */
 246 };
 247
 248 #define DIB3000MC_REG_UNK_88                    (    88)
 249 #define DIB3000MC_UNK_88                                (0x0410)
 250
 251 static u16 dib3000mc_reg_bw[] = { 93,94,95,96,97,98 };
 252 static u16 dib3000mc_bw[][6] = {
 253         { 0,0,0,0,0,0 }, /* 5 MHz */
 254         { 0,0,0,0,0,0 }, /* 6 MHz */
 255         { 0,0,0,0,0,0 }, /* 7 MHz */
 256         { 0x20, 0x21, 0x20, 0x23, 0x20, 0x27 }, /* 8 MHz */
 257 };
 258
 259
 260 /* phase noise control */
 261 #define DIB3000MC_REG_UNK_99                    (    99)
 262 #define DIB3000MC_UNK_99                                (0x0220)
 263
 264 #define DIB3000MC_REG_SCAN_BOOST                (   100)
 265 #define DIB3000MC_SCAN_BOOST_ON                 ((11 << 6) + 6)
 266 #define DIB3000MC_SCAN_BOOST_OFF                ((16 << 6) + 9)
 267
 268 /* timeout ??? */
 269 #define DIB3000MC_REG_UNK_110                   (   110)
 270 #define DIB3000MC_UNK_110                               (  3277)
 271
 272 #define DIB3000MC_REG_UNK_111                   (   111)
 273 #define DIB3000MC_UNK_111_PH_N_MODE_0   (     0)
 274 #define DIB3000MC_UNK_111_PH_N_MODE_1   (1 << 1)
 275
 276 /* superious rm config */
 277 #define DIB3000MC_REG_UNK_120                   (   120)
 278 #define DIB3000MC_UNK_120                               (  8207)
 279
 280 #define DIB3000MC_REG_UNK_133                   (   133)
 281 #define DIB3000MC_UNK_133                               ( 15564)
 282
 283 #define DIB3000MC_REG_UNK_134                   (   134)
 284 #define DIB3000MC_UNK_134                               (     0)
 285
 286 /* adapter config for constellation */
 287 static u16 dib3000mc_reg_adp_cfg[] = { 129, 130, 131, 132 };
 288
 289 static u16 dib3000mc_adp_cfg[][4] = {
 290         { 0x99a, 0x7fae, 0x333, 0x7ff0 }, /* QPSK  */
 291         { 0x23d, 0x7fdf, 0x0a4, 0x7ff0 }, /* 16-QAM */
 292         { 0x148, 0x7ff0, 0x0a4, 0x7ff8 }, /* 64-QAM */
 293 };
 294
 295 static u16 dib3000mc_reg_mobile_mode[] = { 139, 140, 141, 175, 1032 };
 296
 297 static u16 dib3000mc_mobile_mode[][5] = {
 298         { 0x01, 0x0, 0x0, 0x00, 0x12c }, /* fixed */
 299         { 0x01, 0x0, 0x0, 0x00, 0x12c }, /* portable */
 300         { 0x00, 0x0, 0x0, 0x02, 0x000 }, /* mobile */
 301         { 0x00, 0x0, 0x0, 0x02, 0x000 }, /* auto */
 302 };
 303
 304 #define DIB3000MC_REG_DIVERSITY1                (   177)
 305 #define DIB3000MC_DIVERSITY1_DEFAULT    (     1)
 306
 307 #define DIB3000MC_REG_DIVERSITY2                (   178)
 308 #define DIB3000MC_DIVERSITY2_DEFAULT    (     1)
 309
 310 #define DIB3000MC_REG_DIVERSITY3                (   180)
 311 #define DIB3000MC_DIVERSITY3_IN_OFF             (0xfff0)
 312 #define DIB3000MC_DIVERSITY3_IN_ON              (0xfff6)
 313
 314 #define DIB3000MC_REG_FEC_CFG                   (   195)
 315 #define DIB3000MC_FEC_CFG                               (  0x10)
 316
 317 #define DIB3000MC_REG_SMO_MODE                  (   206)
 318 #define DIB3000MC_SMO_MODE_DEFAULT              (1 << 2)
 319 #define DIB3000MC_SMO_MODE_FIFO_FLUSH   (1 << 3)
 320 #define DIB3000MC_SMO_MODE_FIFO_UNFLUSH ~DIB3000MC_SMO_MODE_FIFO_FLUSH
 321 #define DIB3000MC_SMO_MODE_PID_PARSE    (1 << 4)
 322 #define DIB3000MC_SMO_MODE_NO_PID_PARSE ~DIB3000MC_SMO_MODE_PID_PARSE
 323 #define DIB3000MC_SMO_MODE_188                  (1 << 5)
 324 #define DIB3000MC_SMO_MODE_SLAVE                (DIB3000MC_SMO_MODE_DEFAULT | \
 325                         DIB3000MC_SMO_MODE_188 | DIB3000MC_SMO_MODE_PID_PARSE | (1<<1))
 326
 327 #define DIB3000MC_REG_FIFO_THRESHOLD    (   207)
 328 #define DIB3000MC_FIFO_THRESHOLD_DEFAULT        (  1792)
 329 #define DIB3000MC_FIFO_THRESHOLD_SLAVE  (   512)
 330 /*
 331  * pidfilter
 332  * it is not a hardware pidfilter but a filter which drops all pids
 333  * except the ones set. When connected to USB1.1 bandwidth this is important.
 334  * DiB3000-MC/P can filter up to 32 PIDs
 335  */
 336 #define DIB3000MC_REG_FIRST_PID                 (   212)
 337 #define DIB3000MC_NUM_PIDS                              (    32)
 338
 339 #define DIB3000MC_REG_OUTMODE                   (   244)
 340 #define DIB3000MC_OM_PARALLEL_GATED_CLK (     0)
 341 #define DIB3000MC_OM_PAR_CONT_CLK               (1 << 11)
 342 #define DIB3000MC_OM_SERIAL                             (2 << 11)
 343 #define DIB3000MC_OM_DIVOUT_ON                  (4 << 11)
 344 #define DIB3000MC_OM_SLAVE                              (DIB3000MC_OM_DIVOUT_ON | DIB3000MC_OM_PAR_CONT_CLK)
 345
 346 #define DIB3000MC_REG_RF_POWER                  (   392)
 347
 348 #define DIB3000MC_REG_FFT_POSITION              (   407)
 349
 350 #define DIB3000MC_REG_DDS_FREQ_MSB              (   414)
 351 #define DIB3000MC_REG_DDS_FREQ_LSB              (   415)
 352
 353 #define DIB3000MC_REG_TIMING_OFFS_MSB   (   416)
 354 #define DIB3000MC_REG_TIMING_OFFS_LSB   (   417)
 355
 356 #define DIB3000MC_REG_TUNING_PARM               (   458)
 357 #define DIB3000MC_TP_QAM(v)                             ((v >> 13) & 0x03)
 358 #define DIB3000MC_TP_HRCH(v)                    ((v >> 12) & 0x01)
 359 #define DIB3000MC_TP_ALPHA(v)                   ((v >> 9) & 0x07)
 360 #define DIB3000MC_TP_FFT(v)                             ((v >> 8) & 0x01)
 361 #define DIB3000MC_TP_FEC_CR_HP(v)               ((v >> 5) & 0x07)
 362 #define DIB3000MC_TP_FEC_CR_LP(v)               ((v >> 2) & 0x07)
 363 #define DIB3000MC_TP_GUARD(v)                   (v & 0x03)
 364
 365 #define DIB3000MC_REG_SIGNAL_NOISE_MSB  (   483)
 366 #define DIB3000MC_REG_SIGNAL_NOISE_LSB  (   484)
 367
 368 #define DIB3000MC_REG_MER                               (   485)
 369
 370 #define DIB3000MC_REG_BER_MSB                   (   500)
 371 #define DIB3000MC_REG_BER_LSB                   (   501)
 372
 373 #define DIB3000MC_REG_PACKET_ERRORS             (   503)
 374
 375 #define DIB3000MC_REG_PACKET_ERROR_COUNT        (   506)
 376
 377 #define DIB3000MC_REG_LOCK_507                  (   507)
 378 #define DIB3000MC_LOCK_507                              (0x0002) // ? name correct ?
 379
 380 #define DIB3000MC_REG_LOCKING                   (   509)
 381 #define DIB3000MC_AGC_LOCK(v)                   (v & 0x8000)
 382 #define DIB3000MC_CARRIER_LOCK(v)               (v & 0x2000)
 383 #define DIB3000MC_MPEG_SYNC_LOCK(v)             (v & 0x0080)
 384 #define DIB3000MC_MPEG_DATA_LOCK(v)             (v & 0x0040)
 385 #define DIB3000MC_TPS_LOCK(v)                   (v & 0x0004)
 386
 387 #define DIB3000MC_REG_AS_IRQ                    (   511)
 388 #define DIB3000MC_AS_IRQ_SUCCESS                (1 << 1)
 389 #define DIB3000MC_AS_IRQ_FAIL                   (     1)
 390
 391 #define DIB3000MC_REG_TUNER                             (   769)
 392
 393 #define DIB3000MC_REG_RST_I2C_ADDR              (  1024)
 394 #define DIB3000MC_DEMOD_ADDR_ON                 (     1)
 395 #define DIB3000MC_DEMOD_ADDR(a)                 ((a << 3) & 0x03F0)
 396
 397 #define DIB3000MC_REG_RESTART                   (  1027)
 398 #define DIB3000MC_RESTART_OFF                   (0x0000)
 399 #define DIB3000MC_RESTART_AGC                   (0x0800)
 400 #define DIB3000MC_RESTART_CONFIG                (0x8000)
 401
 402 #define DIB3000MC_REG_RESTART_VIT               (  1028)
 403 #define DIB3000MC_RESTART_VIT_OFF               (     0)
 404 #define DIB3000MC_RESTART_VIT_ON                (     1)
 405
 406 #define DIB3000MC_REG_CLK_CFG_1                 (  1031)
 407 #define DIB3000MC_CLK_CFG_1_POWER_UP    (     0)
 408 #define DIB3000MC_CLK_CFG_1_POWER_DOWN  (0xffff)
 409
 410 #define DIB3000MC_REG_CLK_CFG_2                 (  1032)
 411 #define DIB3000MC_CLK_CFG_2_PUP_FIXED   (0x012c)
 412 #define DIB3000MC_CLK_CFG_2_PUP_PORT    (0x0104)
 413 #define DIB3000MC_CLK_CFG_2_PUP_MOBILE  (0x0000)
 414 #define DIB3000MC_CLK_CFG_2_POWER_DOWN  (0xffff)
 415
 416 #define DIB3000MC_REG_CLK_CFG_3                 (  1033)
 417 #define DIB3000MC_CLK_CFG_3_POWER_UP    (     0)
 418 #define DIB3000MC_CLK_CFG_3_POWER_DOWN  (0xfff5)
 419
 420 #define DIB3000MC_REG_CLK_CFG_7                 (  1037)
 421 #define DIB3000MC_CLK_CFG_7_INIT                ( 12592)
 422 #define DIB3000MC_CLK_CFG_7_POWER_UP    (~0x0003)
 423 #define DIB3000MC_CLK_CFG_7_PWR_DOWN    (0x0003)
 424 #define DIB3000MC_CLK_CFG_7_DIV_IN_OFF  (1 << 8)
 425
 426 /* was commented out ??? */
 427 #define DIB3000MC_REG_CLK_CFG_8                 (  1038)
 428 #define DIB3000MC_CLK_CFG_8_POWER_UP    (0x160c)
 429
 430 #define DIB3000MC_REG_CLK_CFG_9                 (  1039)
 431 #define DIB3000MC_CLK_CFG_9_POWER_UP    (     0)
 432
 433 /* also clock ??? */
 434 #define DIB3000MC_REG_ELEC_OUT                  (  1040)
 435 #define DIB3000MC_ELEC_OUT_HIGH_Z               (     0)
 436 #define DIB3000MC_ELEC_OUT_DIV_OUT_ON   (     1)
 437 #define DIB3000MC_ELEC_OUT_SLAVE                (     3)
 438
 439 #endif