2 * Driver for Zarlink DVB-T MT352 demodulator
4 * Written by Holger Waechtler <holger@qanu.de>
5 * and Daniel Mack <daniel@qanu.de>
7 * AVerMedia AVerTV DVB-T 771 support by
8 * Wolfram Joost <dbox2@frokaschwei.de>
10 * Support for Samsung TDTC9251DH01C(M) tuner
11 * Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
12 * Amauri Celani <acelani@essegi.net>
14 * DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
15 * Christopher Pascoe <c.pascoe@itee.uq.edu.au>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/init.h>
37 #include <linux/delay.h>
39 #include "dvb_frontend.h"
40 #include "mt352_priv.h"
45 struct i2c_adapter* i2c;
47 struct dvb_frontend_ops ops;
49 /* configuration settings */
50 const struct mt352_config* config;
52 struct dvb_frontend frontend;
56 #define dprintk(args...) \
58 if (debug) printk(KERN_DEBUG "mt352: " args); \
61 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
63 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
64 u8 buf[2] = { reg, val };
65 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0,
66 .buf = buf, .len = 2 };
67 int err = i2c_transfer(state->i2c, &msg, 1);
69 dprintk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
75 int mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
78 for (i=0; i < ilen-1; i++)
79 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
85 static u8 mt352_read_register(struct mt352_state* state, u8 reg)
90 struct i2c_msg msg [] = { { .addr = state->config->demod_address,
92 .buf = b0, .len = 1 },
93 { .addr = state->config->demod_address,
95 .buf = b1, .len = 1 } };
97 ret = i2c_transfer(state->i2c, msg, 2);
100 dprintk("%s: readreg error (ret == %i)\n", __FUNCTION__, ret);
105 u8 mt352_read(struct dvb_frontend *fe, u8 reg)
107 return mt352_read_register(fe->demodulator_priv,reg);
117 static int mt352_sleep(struct dvb_frontend* fe)
119 static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
121 mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
126 static int mt352_set_parameters(struct dvb_frontend* fe,
127 struct dvb_frontend_parameters *param)
129 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
130 unsigned char buf[14];
131 unsigned int tps = 0;
132 struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
135 switch (op->code_rate_HP) {
155 switch (op->code_rate_LP) {
172 if (op->hierarchy_information == HIERARCHY_AUTO ||
173 op->hierarchy_information == HIERARCHY_NONE)
179 switch (op->constellation) {
193 switch (op->transmission_mode) {
194 case TRANSMISSION_MODE_2K:
195 case TRANSMISSION_MODE_AUTO:
197 case TRANSMISSION_MODE_8K:
204 switch (op->guard_interval) {
205 case GUARD_INTERVAL_1_32:
206 case GUARD_INTERVAL_AUTO:
208 case GUARD_INTERVAL_1_16:
211 case GUARD_INTERVAL_1_8:
214 case GUARD_INTERVAL_1_4:
221 switch (op->hierarchy_information) {
239 buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
241 buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */
247 * these settings assume 20.48MHz f_ADC, for other tuners you might
248 * need other values. See p. 33 in the MT352 Design Manual.
250 if (op->bandwidth == BANDWIDTH_8_MHZ) {
251 buf[4] = 0x72; /* TRL_NOMINAL_RATE_(1|0) */
253 } else if (op->bandwidth == BANDWIDTH_7_MHZ) {
261 buf[6] = 0x31; /* INPUT_FREQ_(1|0), 20.48MHz clock, 36.166667MHz IF */
262 buf[7] = 0x05; /* see MT352 Design Manual page 32 for details */
264 state->config->pll_set(fe, param, buf+8);
266 buf[13] = 0x01; /* TUNER_GO!! */
268 /* Only send the tuning request if the tuner doesn't have the requested
269 * parameters already set. Enhances tuning time and prevents stream
270 * breakup when retuning the same transponder. */
271 for (i = 1; i < 13; i++)
272 if (buf[i] != mt352_read_register(state, i + 0x50)) {
273 mt352_write(fe, buf, sizeof(buf));
280 static int mt352_get_parameters(struct dvb_frontend* fe,
281 struct dvb_frontend_parameters *param)
283 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
287 struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
288 static const u8 tps_fec_to_api[8] =
300 if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
305 /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
306 * the mt352 sometimes works with the wrong parameters
308 tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
309 div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
310 trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
312 op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
313 op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
315 switch ( (tps >> 13) & 3)
318 op->constellation = QPSK;
321 op->constellation = QAM_16;
324 op->constellation = QAM_64;
327 op->constellation = QAM_AUTO;
331 op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
333 switch ( (tps >> 2) & 3)
336 op->guard_interval = GUARD_INTERVAL_1_32;
339 op->guard_interval = GUARD_INTERVAL_1_16;
342 op->guard_interval = GUARD_INTERVAL_1_8;
345 op->guard_interval = GUARD_INTERVAL_1_4;
348 op->guard_interval = GUARD_INTERVAL_AUTO;
352 switch ( (tps >> 10) & 7)
355 op->hierarchy_information = HIERARCHY_NONE;
358 op->hierarchy_information = HIERARCHY_1;
361 op->hierarchy_information = HIERARCHY_2;
364 op->hierarchy_information = HIERARCHY_4;
367 op->hierarchy_information = HIERARCHY_AUTO;
371 param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;
375 op->bandwidth = BANDWIDTH_8_MHZ;
377 else if (trl == 0x64)
379 op->bandwidth = BANDWIDTH_7_MHZ;
383 op->bandwidth = BANDWIDTH_6_MHZ;
387 if (mt352_read_register(state, STATUS_2) & 0x02)
388 param->inversion = INVERSION_OFF;
390 param->inversion = INVERSION_ON;
395 static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
397 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
401 r = mt352_read_register (state, STATUS_0);
403 *status = FE_HAS_CARRIER;
405 *status |= FE_HAS_VITERBI;
407 *status |= FE_HAS_LOCK;
409 r = mt352_read_register (state, STATUS_1);
411 *status |= FE_HAS_SYNC;
413 r = mt352_read_register (state, STATUS_3);
415 *status |= FE_HAS_SIGNAL;
417 if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
418 (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
419 *status &= ~FE_HAS_LOCK;
424 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
426 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
428 *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
429 (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
430 (mt352_read_register (state, RS_ERR_CNT_0));
435 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
437 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
439 u16 signal = (mt352_read_register (state, AGC_GAIN_3) << 8) |
440 (mt352_read_register (state, AGC_GAIN_2));
446 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
448 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
450 u8 _snr = mt352_read_register (state, SNR);
451 *snr = (_snr << 8) | _snr;
456 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
458 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
460 *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
461 (mt352_read_register (state, RS_UBC_0));
466 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
468 fe_tune_settings->min_delay_ms = 800;
469 fe_tune_settings->step_size = 0;
470 fe_tune_settings->max_drift = 0;
475 static int mt352_init(struct dvb_frontend* fe)
477 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
479 static u8 mt352_reset_attach [] = { RESET, 0xC0 };
481 if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
482 (mt352_read_register(state, CONFIG) & 0x20) == 0) {
484 /* Do a "hard" reset */
485 mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
486 return state->config->demod_init(fe);
492 static void mt352_release(struct dvb_frontend* fe)
494 struct mt352_state* state = (struct mt352_state*) fe->demodulator_priv;
498 static struct dvb_frontend_ops mt352_ops;
500 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
501 struct i2c_adapter* i2c)
503 struct mt352_state* state = NULL;
505 /* allocate memory for the internal state */
506 state = (struct mt352_state*) kmalloc(sizeof(struct mt352_state), GFP_KERNEL);
507 if (state == NULL) goto error;
509 /* setup the state */
510 state->config = config;
512 memcpy(&state->ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
514 /* check if the demod is there */
515 if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
517 /* create dvb_frontend */
518 state->frontend.ops = &state->ops;
519 state->frontend.demodulator_priv = state;
520 return &state->frontend;
523 if (state) kfree(state);
527 static struct dvb_frontend_ops mt352_ops = {
530 .name = "Zarlink MT352 DVB-T",
532 .frequency_min = 174000000,
533 .frequency_max = 862000000,
534 .frequency_stepsize = 166667,
535 .frequency_tolerance = 0,
536 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
537 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
539 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
540 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
541 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
545 .release = mt352_release,
548 .sleep = mt352_sleep,
550 .set_frontend = mt352_set_parameters,
551 .get_frontend = mt352_get_parameters,
552 .get_tune_settings = mt352_get_tune_settings,
554 .read_status = mt352_read_status,
555 .read_ber = mt352_read_ber,
556 .read_signal_strength = mt352_read_signal_strength,
557 .read_snr = mt352_read_snr,
558 .read_ucblocks = mt352_read_ucblocks,
561 module_param(debug, int, 0644);
562 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
564 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
565 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
566 MODULE_LICENSE("GPL");
568 EXPORT_SYMBOL(mt352_attach);
569 EXPORT_SYMBOL(mt352_write);
570 EXPORT_SYMBOL(mt352_read);