drivers/media/dvb/frontends/s5h1420.c

   1 /*
   2 Driver for Samsung S5H1420 QPSK Demodulator
   3
   4 Copyright (C) 2005 Andrew de Quincey <adq_dvb@lidskialf.net>
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 2 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with this program; if not, write to the Free Software
  19 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21 */
  22
  23 #include <linux/kernel.h>
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/string.h>
  27 #include <linux/slab.h>
  28 #include <linux/delay.h>
  29 #include <linux/jiffies.h>
  30 #include <asm/div64.h>
  31
  32 #include "dvb_frontend.h"
  33 #include "s5h1420.h"
  34
  35
  36
  37 #define TONE_FREQ 22000
  38
  39 struct s5h1420_state {
  40         struct i2c_adapter* i2c;
  41         struct dvb_frontend_ops ops;
  42         const struct s5h1420_config* config;
  43         struct dvb_frontend frontend;
  44
  45         u8 postlocked:1;
  46         u32 fclk;
  47         u32 tunedfreq;
  48         fe_code_rate_t fec_inner;
  49         u32 symbol_rate;
  50 };
  51
  52 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state);
  53 static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
  54                                      struct dvb_frontend_tune_settings* fesettings);
  55
  56
  57 static int debug = 0;
  58 #define dprintk if (debug) printk
  59
  60 static int s5h1420_writereg (struct s5h1420_state* state, u8 reg, u8 data)
  61 {
  62         u8 buf [] = { reg, data };
  63         struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
  64         int err;
  65
  66         if ((err = i2c_transfer (state->i2c, &msg, 1)) != 1) {
  67                 dprintk ("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", __FUNCTION__, err, reg, data);
  68                 return -EREMOTEIO;
  69         }
  70
  71         return 0;
  72 }
  73
  74 static u8 s5h1420_readreg (struct s5h1420_state* state, u8 reg)
  75 {
  76         int ret;
  77         u8 b0 [] = { reg };
  78         u8 b1 [] = { 0 };
  79         struct i2c_msg msg1 = { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 };
  80         struct i2c_msg msg2 = { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 };
  81
  82         if ((ret = i2c_transfer (state->i2c, &msg1, 1)) != 1)
  83                 return ret;
  84
  85         if ((ret = i2c_transfer (state->i2c, &msg2, 1)) != 1)
  86                 return ret;
  87
  88         return b1[0];
  89 }
  90
  91 static int s5h1420_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
  92 {
  93         struct s5h1420_state* state = fe->demodulator_priv;
  94
  95         switch(voltage) {
  96         case SEC_VOLTAGE_13:
  97                 s5h1420_writereg(state, 0x3c,
  98                                  (s5h1420_readreg(state, 0x3c) & 0xfe) | 0x02);
  99                 break;
 100
 101         case SEC_VOLTAGE_18:
 102                 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) | 0x03);
 103                 break;
 104
 105         case SEC_VOLTAGE_OFF:
 106                 s5h1420_writereg(state, 0x3c, s5h1420_readreg(state, 0x3c) & 0xfd);
 107                 break;
 108         }
 109
 110         return 0;
 111 }
 112
 113 static int s5h1420_set_tone (struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
 114 {
 115         struct s5h1420_state* state = fe->demodulator_priv;
 116
 117         switch(tone) {
 118         case SEC_TONE_ON:
 119                 s5h1420_writereg(state, 0x3b,
 120                                  (s5h1420_readreg(state, 0x3b) & 0x74) | 0x08);
 121                 break;
 122
 123         case SEC_TONE_OFF:
 124                 s5h1420_writereg(state, 0x3b,
 125                                  (s5h1420_readreg(state, 0x3b) & 0x74) | 0x01);
 126                 break;
 127         }
 128
 129         return 0;
 130 }
 131
 132 static int s5h1420_send_master_cmd (struct dvb_frontend* fe,
 133                                     struct dvb_diseqc_master_cmd* cmd)
 134 {
 135         struct s5h1420_state* state = fe->demodulator_priv;
 136         u8 val;
 137         int i;
 138         unsigned long timeout;
 139         int result = 0;
 140
 141         if (cmd->msg_len > 8)
 142                 return -EINVAL;
 143
 144         /* setup for DISEQC */
 145         val = s5h1420_readreg(state, 0x3b);
 146         s5h1420_writereg(state, 0x3b, 0x02);
 147         msleep(15);
 148
 149         /* write the DISEQC command bytes */
 150         for(i=0; i< cmd->msg_len; i++) {
 151                 s5h1420_writereg(state, 0x3d + i, cmd->msg[i]);
 152         }
 153
 154         /* kick off transmission */
 155         s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) |
 156                                       ((cmd->msg_len-1) << 4) | 0x08);
 157
 158         /* wait for transmission to complete */
 159         timeout = jiffies + ((100*HZ) / 1000);
 160         while(time_before(jiffies, timeout)) {
 161                 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
 162                         break;
 163
 164                 msleep(5);
 165         }
 166         if (time_after(jiffies, timeout))
 167                 result = -ETIMEDOUT;
 168
 169         /* restore original settings */
 170         s5h1420_writereg(state, 0x3b, val);
 171         msleep(15);
 172         return result;
 173 }
 174
 175 static int s5h1420_recv_slave_reply (struct dvb_frontend* fe,
 176                                      struct dvb_diseqc_slave_reply* reply)
 177 {
 178         struct s5h1420_state* state = fe->demodulator_priv;
 179         u8 val;
 180         int i;
 181         int length;
 182         unsigned long timeout;
 183         int result = 0;
 184
 185         /* setup for DISEQC recieve */
 186         val = s5h1420_readreg(state, 0x3b);
 187         s5h1420_writereg(state, 0x3b, 0x82); /* FIXME: guess - do we need to set DIS_RDY(0x08) in receive mode? */
 188         msleep(15);
 189
 190         /* wait for reception to complete */
 191         timeout = jiffies + ((reply->timeout*HZ) / 1000);
 192         while(time_before(jiffies, timeout)) {
 193                 if (!(s5h1420_readreg(state, 0x3b) & 0x80)) /* FIXME: do we test DIS_RDY(0x08) or RCV_EN(0x80)? */
 194                         break;
 195
 196                 msleep(5);
 197         }
 198         if (time_after(jiffies, timeout)) {
 199                 result = -ETIMEDOUT;
 200                 goto exit;
 201         }
 202
 203         /* check error flag - FIXME: not sure what this does - docs do not describe
 204          * beyond "error flag for diseqc receive data :( */
 205         if (s5h1420_readreg(state, 0x49)) {
 206                 result = -EIO;
 207                 goto exit;
 208         }
 209
 210         /* check length */
 211         length = (s5h1420_readreg(state, 0x3b) & 0x70) >> 4;
 212         if (length > sizeof(reply->msg)) {
 213                 result = -EOVERFLOW;
 214                 goto exit;
 215         }
 216         reply->msg_len = length;
 217
 218         /* extract data */
 219         for(i=0; i< length; i++) {
 220                 reply->msg[i] = s5h1420_readreg(state, 0x3d + i);
 221         }
 222
 223 exit:
 224         /* restore original settings */
 225         s5h1420_writereg(state, 0x3b, val);
 226         msleep(15);
 227         return result;
 228 }
 229
 230 static int s5h1420_send_burst (struct dvb_frontend* fe, fe_sec_mini_cmd_t minicmd)
 231 {
 232         struct s5h1420_state* state = fe->demodulator_priv;
 233         u8 val;
 234         int result = 0;
 235         unsigned long timeout;
 236
 237         /* setup for tone burst */
 238         val = s5h1420_readreg(state, 0x3b);
 239         s5h1420_writereg(state, 0x3b, (s5h1420_readreg(state, 0x3b) & 0x70) | 0x01);
 240
 241         /* set value for B position if requested */
 242         if (minicmd == SEC_MINI_B) {
 243                 s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x04);
 244         }
 245         msleep(15);
 246
 247         /* start transmission */
 248         s5h1420_writereg(state, 0x3b, s5h1420_readreg(state, 0x3b) | 0x08);
 249
 250         /* wait for transmission to complete */
 251         timeout = jiffies + ((100*HZ) / 1000);
 252         while(time_before(jiffies, timeout)) {
 253                 if (!(s5h1420_readreg(state, 0x3b) & 0x08))
 254                         break;
 255
 256                 msleep(5);
 257         }
 258         if (time_after(jiffies, timeout))
 259                 result = -ETIMEDOUT;
 260
 261         /* restore original settings */
 262         s5h1420_writereg(state, 0x3b, val);
 263         msleep(15);
 264         return result;
 265 }
 266
 267 static fe_status_t s5h1420_get_status_bits(struct s5h1420_state* state)
 268 {
 269         u8 val;
 270         fe_status_t status = 0;
 271
 272         val = s5h1420_readreg(state, 0x14);
 273         if (val & 0x02)
 274                 status |=  FE_HAS_SIGNAL;
 275         if (val & 0x01)
 276                 status |=  FE_HAS_CARRIER;
 277         val = s5h1420_readreg(state, 0x36);
 278         if (val & 0x01)
 279                 status |=  FE_HAS_VITERBI;
 280         if (val & 0x20)
 281                 status |=  FE_HAS_SYNC;
 282         if (status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI|FE_HAS_SYNC))
 283                 status |=  FE_HAS_LOCK;
 284
 285         return status;
 286 }
 287
 288 static int s5h1420_read_status(struct dvb_frontend* fe, fe_status_t* status)
 289 {
 290         struct s5h1420_state* state = fe->demodulator_priv;
 291         u8 val;
 292
 293         if (status == NULL)
 294                 return -EINVAL;
 295
 296         /* determine lock state */
 297         *status = s5h1420_get_status_bits(state);
 298
 299         /* fix for FEC 5/6 inversion issue - if it doesn't quite lock, invert
 300         the inversion, wait a bit and check again */
 301         if (*status == (FE_HAS_SIGNAL|FE_HAS_CARRIER|FE_HAS_VITERBI)) {
 302                 val = s5h1420_readreg(state, 0x32);
 303                 if ((val & 0x07) == 0x03) {
 304                         if (val & 0x08)
 305                                 s5h1420_writereg(state, 0x31, 0x13);
 306                         else
 307                                 s5h1420_writereg(state, 0x31, 0x1b);
 308
 309                         /* wait a bit then update lock status */
 310                         mdelay(200);
 311                         *status = s5h1420_get_status_bits(state);
 312                 }
 313         }
 314
 315         /* perform post lock setup */
 316         if ((*status & FE_HAS_LOCK) && (!state->postlocked)) {
 317
 318                 /* calculate the data rate */
 319                 u32 tmp = s5h1420_getsymbolrate(state);
 320                 switch(s5h1420_readreg(state, 0x32) & 0x07) {
 321                 case 0:
 322                         tmp = (tmp * 2 * 1) / 2;
 323                         break;
 324
 325                 case 1:
 326                         tmp = (tmp * 2 * 2) / 3;
 327                         break;
 328
 329                 case 2:
 330                         tmp = (tmp * 2 * 3) / 4;
 331                         break;
 332
 333                 case 3:
 334                         tmp = (tmp * 2 * 5) / 6;
 335                         break;
 336
 337                 case 4:
 338                         tmp = (tmp * 2 * 6) / 7;
 339                         break;
 340
 341                 case 5:
 342                         tmp = (tmp * 2 * 7) / 8;
 343                         break;
 344                 }
 345                 if (tmp == 0) {
 346                         printk("s5h1420: avoided division by 0\n");
 347                         tmp = 1;
 348                 }
 349                 tmp = state->fclk / tmp;
 350
 351                 /* set the MPEG_CLK_INTL for the calculated data rate */
 352                 if (tmp < 4)
 353                         val = 0x00;
 354                 else if (tmp < 8)
 355                         val = 0x01;
 356                 else if (tmp < 12)
 357                         val = 0x02;
 358                 else if (tmp < 16)
 359                         val = 0x03;
 360                 else if (tmp < 24)
 361                         val = 0x04;
 362                 else if (tmp < 32)
 363                         val = 0x05;
 364                 else
 365                         val = 0x06;
 366                 s5h1420_writereg(state, 0x22, val);
 367
 368                 /* DC freeze */
 369                 s5h1420_writereg(state, 0x1f, s5h1420_readreg(state, 0x1f) | 0x01);
 370
 371                 /* kicker disable + remove DC offset */
 372                 s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) & 0x6f);
 373
 374                 /* post-lock processing has been done! */
 375                 state->postlocked = 1;
 376         }
 377
 378         return 0;
 379 }
 380
 381 static int s5h1420_read_ber(struct dvb_frontend* fe, u32* ber)
 382 {
 383         struct s5h1420_state* state = fe->demodulator_priv;
 384
 385         s5h1420_writereg(state, 0x46, 0x1d);
 386         mdelay(25);
 387
 388         *ber = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
 389
 390         return 0;
 391 }
 392
 393 static int s5h1420_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 394 {
 395         struct s5h1420_state* state = fe->demodulator_priv;
 396
 397         u8 val = s5h1420_readreg(state, 0x15);
 398
 399         *strength =  (u16) ((val << 8) | val);
 400
 401         return 0;
 402 }
 403
 404 static int s5h1420_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 405 {
 406         struct s5h1420_state* state = fe->demodulator_priv;
 407
 408         s5h1420_writereg(state, 0x46, 0x1f);
 409         mdelay(25);
 410
 411         *ucblocks = (s5h1420_readreg(state, 0x48) << 8) | s5h1420_readreg(state, 0x47);
 412
 413         return 0;
 414 }
 415
 416 static void s5h1420_reset(struct s5h1420_state* state)
 417 {
 418         s5h1420_writereg (state, 0x01, 0x08);
 419         s5h1420_writereg (state, 0x01, 0x00);
 420         udelay(10);
 421 }
 422
 423 static void s5h1420_setsymbolrate(struct s5h1420_state* state,
 424                                   struct dvb_frontend_parameters *p)
 425 {
 426         u64 val;
 427
 428         val = ((u64) p->u.qpsk.symbol_rate / 1000ULL) * (1ULL<<24);
 429         if (p->u.qpsk.symbol_rate <= 21000000) {
 430                 val *= 2;
 431         }
 432         do_div(val, (state->fclk / 1000));
 433
 434         s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0x7f);
 435         s5h1420_writereg(state, 0x11, val >> 16);
 436         s5h1420_writereg(state, 0x12, val >> 8);
 437         s5h1420_writereg(state, 0x13, val & 0xff);
 438         s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x80);
 439 }
 440
 441 static u32 s5h1420_getsymbolrate(struct s5h1420_state* state)
 442 {
 443         u64 val = 0;
 444         int sampling = 2;
 445
 446         if (s5h1420_readreg(state, 0x05) & 0x2)
 447                 sampling = 1;
 448
 449         s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
 450         val  = s5h1420_readreg(state, 0x11) << 16;
 451         val |= s5h1420_readreg(state, 0x12) << 8;
 452         val |= s5h1420_readreg(state, 0x13);
 453         s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
 454
 455         val *= (state->fclk / 1000ULL);
 456         do_div(val, ((1<<24) * sampling));
 457
 458         return (u32) (val * 1000ULL);
 459 }
 460
 461 static void s5h1420_setfreqoffset(struct s5h1420_state* state, int freqoffset)
 462 {
 463         int val;
 464
 465         /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
 466          * divide fclk by 1000000 to get the correct value. */
 467         val = -(int) ((freqoffset * (1<<24)) / (state->fclk / 1000000));
 468
 469         s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) & 0xbf);
 470         s5h1420_writereg(state, 0x0e, val >> 16);
 471         s5h1420_writereg(state, 0x0f, val >> 8);
 472         s5h1420_writereg(state, 0x10, val & 0xff);
 473         s5h1420_writereg(state, 0x09, s5h1420_readreg(state, 0x09) | 0x40);
 474 }
 475
 476 static int s5h1420_getfreqoffset(struct s5h1420_state* state)
 477 {
 478         int val;
 479
 480         s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) | 0x08);
 481         val  = s5h1420_readreg(state, 0x0e) << 16;
 482         val |= s5h1420_readreg(state, 0x0f) << 8;
 483         val |= s5h1420_readreg(state, 0x10);
 484         s5h1420_writereg(state, 0x06, s5h1420_readreg(state, 0x06) & 0xf7);
 485
 486         if (val & 0x800000)
 487                 val |= 0xff000000;
 488
 489         /* remember freqoffset is in kHz, but the chip wants the offset in Hz, so
 490          * divide fclk by 1000000 to get the correct value. */
 491         val = (((-val) * (state->fclk/1000000)) / (1<<24));
 492
 493         return val;
 494 }
 495
 496 static void s5h1420_setfec_inversion(struct s5h1420_state* state,
 497                                      struct dvb_frontend_parameters *p)
 498 {
 499         u8 inversion = 0;
 500
 501         if (p->inversion == INVERSION_OFF) {
 502                 inversion = state->config->invert ? 0x08 : 0;
 503         } else if (p->inversion == INVERSION_ON) {
 504                 inversion = state->config->invert ? 0 : 0x08;
 505         }
 506
 507         if ((p->u.qpsk.fec_inner == FEC_AUTO) || (p->inversion == INVERSION_AUTO)) {
 508                 s5h1420_writereg(state, 0x30, 0x3f);
 509                 s5h1420_writereg(state, 0x31, 0x00 | inversion);
 510         } else {
 511                 switch(p->u.qpsk.fec_inner) {
 512                 case FEC_1_2:
 513                         s5h1420_writereg(state, 0x30, 0x01);
 514                         s5h1420_writereg(state, 0x31, 0x10 | inversion);
 515                         break;
 516
 517                 case FEC_2_3:
 518                         s5h1420_writereg(state, 0x30, 0x02);
 519                         s5h1420_writereg(state, 0x31, 0x11 | inversion);
 520                         break;
 521
 522                 case FEC_3_4:
 523                         s5h1420_writereg(state, 0x30, 0x04);
 524                         s5h1420_writereg(state, 0x31, 0x12 | inversion);
 525                         break;
 526
 527                 case FEC_5_6:
 528                         s5h1420_writereg(state, 0x30, 0x08);
 529                         s5h1420_writereg(state, 0x31, 0x13 | inversion);
 530                         break;
 531
 532                 case FEC_6_7:
 533                         s5h1420_writereg(state, 0x30, 0x10);
 534                         s5h1420_writereg(state, 0x31, 0x14 | inversion);
 535                         break;
 536
 537                 case FEC_7_8:
 538                         s5h1420_writereg(state, 0x30, 0x20);
 539                         s5h1420_writereg(state, 0x31, 0x15 | inversion);
 540                         break;
 541
 542                 default:
 543                         return;
 544                 }
 545         }
 546 }
 547
 548 static fe_code_rate_t s5h1420_getfec(struct s5h1420_state* state)
 549 {
 550         switch(s5h1420_readreg(state, 0x32) & 0x07) {
 551         case 0:
 552                 return FEC_1_2;
 553
 554         case 1:
 555                 return FEC_2_3;
 556
 557         case 2:
 558                 return FEC_3_4;
 559
 560         case 3:
 561                 return FEC_5_6;
 562
 563         case 4:
 564                 return FEC_6_7;
 565
 566         case 5:
 567                 return FEC_7_8;
 568         }
 569
 570         return FEC_NONE;
 571 }
 572
 573 static fe_spectral_inversion_t s5h1420_getinversion(struct s5h1420_state* state)
 574 {
 575         if (s5h1420_readreg(state, 0x32) & 0x08)
 576                 return INVERSION_ON;
 577
 578         return INVERSION_OFF;
 579 }
 580
 581 static int s5h1420_set_frontend(struct dvb_frontend* fe,
 582                                 struct dvb_frontend_parameters *p)
 583 {
 584         struct s5h1420_state* state = fe->demodulator_priv;
 585         int frequency_delta;
 586         struct dvb_frontend_tune_settings fesettings;
 587         u32 tmp;
 588
 589         /* check if we should do a fast-tune */
 590         memcpy(&fesettings.parameters, p, sizeof(struct dvb_frontend_parameters));
 591         s5h1420_get_tune_settings(fe, &fesettings);
 592         frequency_delta = p->frequency - state->tunedfreq;
 593         if ((frequency_delta > -fesettings.max_drift) &&
 594             (frequency_delta < fesettings.max_drift) &&
 595             (frequency_delta != 0) &&
 596             (state->fec_inner == p->u.qpsk.fec_inner) &&
 597             (state->symbol_rate == p->u.qpsk.symbol_rate)) {
 598
 599                 if (state->config->pll_set) {
 600                         s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
 601                         state->config->pll_set(fe, p, &tmp);
 602                         s5h1420_setfreqoffset(state, p->frequency - tmp);
 603                 }
 604                 return 0;
 605         }
 606
 607         /* first of all, software reset */
 608         s5h1420_reset(state);
 609
 610         /* set s5h1420 fclk PLL according to desired symbol rate */
 611         if (p->u.qpsk.symbol_rate > 28000000) {
 612                 state->fclk = 88000000;
 613                 s5h1420_writereg(state, 0x03, 0x50);
 614                 s5h1420_writereg(state, 0x04, 0x40);
 615                 s5h1420_writereg(state, 0x05, 0xae);
 616         } else if (p->u.qpsk.symbol_rate > 21000000) {
 617                 state->fclk = 59000000;
 618                 s5h1420_writereg(state, 0x03, 0x33);
 619                 s5h1420_writereg(state, 0x04, 0x40);
 620                 s5h1420_writereg(state, 0x05, 0xae);
 621         } else {
 622                 state->fclk = 88000000;
 623                 s5h1420_writereg(state, 0x03, 0x50);
 624                 s5h1420_writereg(state, 0x04, 0x40);
 625                 s5h1420_writereg(state, 0x05, 0xac);
 626         }
 627
 628         /* set misc registers */
 629         s5h1420_writereg(state, 0x02, 0x00);
 630         s5h1420_writereg(state, 0x06, 0x00);
 631         s5h1420_writereg(state, 0x07, 0xb0);
 632         s5h1420_writereg(state, 0x0a, 0xe7);
 633         s5h1420_writereg(state, 0x0b, 0x78);
 634         s5h1420_writereg(state, 0x0c, 0x48);
 635         s5h1420_writereg(state, 0x0d, 0x6b);
 636         s5h1420_writereg(state, 0x2e, 0x8e);
 637         s5h1420_writereg(state, 0x35, 0x33);
 638         s5h1420_writereg(state, 0x38, 0x01);
 639         s5h1420_writereg(state, 0x39, 0x7d);
 640         s5h1420_writereg(state, 0x3a, (state->fclk + (TONE_FREQ * 32) - 1) / (TONE_FREQ * 32));
 641         s5h1420_writereg(state, 0x3c, 0x00);
 642         s5h1420_writereg(state, 0x45, 0x61);
 643         s5h1420_writereg(state, 0x46, 0x1d);
 644
 645         /* start QPSK */
 646         s5h1420_writereg(state, 0x05, s5h1420_readreg(state, 0x05) | 1);
 647
 648         /* set tuner PLL */
 649         if (state->config->pll_set) {
 650                 s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
 651                 state->config->pll_set(fe, p, &tmp);
 652                 s5h1420_setfreqoffset(state, 0);
 653         }
 654
 655         /* set the reset of the parameters */
 656         s5h1420_setsymbolrate(state, p);
 657         s5h1420_setfec_inversion(state, p);
 658
 659         state->fec_inner = p->u.qpsk.fec_inner;
 660         state->symbol_rate = p->u.qpsk.symbol_rate;
 661         state->postlocked = 0;
 662         state->tunedfreq = p->frequency;
 663         return 0;
 664 }
 665
 666 static int s5h1420_get_frontend(struct dvb_frontend* fe,
 667                                 struct dvb_frontend_parameters *p)
 668 {
 669         struct s5h1420_state* state = fe->demodulator_priv;
 670
 671         p->frequency = state->tunedfreq + s5h1420_getfreqoffset(state);
 672         p->inversion = s5h1420_getinversion(state);
 673         p->u.qpsk.symbol_rate = s5h1420_getsymbolrate(state);
 674         p->u.qpsk.fec_inner = s5h1420_getfec(state);
 675
 676         return 0;
 677 }
 678
 679 static int s5h1420_get_tune_settings(struct dvb_frontend* fe,
 680                                      struct dvb_frontend_tune_settings* fesettings)
 681 {
 682         if (fesettings->parameters.u.qpsk.symbol_rate > 20000000) {
 683                 fesettings->min_delay_ms = 50;
 684                 fesettings->step_size = 2000;
 685                 fesettings->max_drift = 8000;
 686         } else if (fesettings->parameters.u.qpsk.symbol_rate > 12000000) {
 687                 fesettings->min_delay_ms = 100;
 688                 fesettings->step_size = 1500;
 689                 fesettings->max_drift = 9000;
 690         } else if (fesettings->parameters.u.qpsk.symbol_rate > 8000000) {
 691                 fesettings->min_delay_ms = 100;
 692                 fesettings->step_size = 1000;
 693                 fesettings->max_drift = 8000;
 694         } else if (fesettings->parameters.u.qpsk.symbol_rate > 4000000) {
 695                 fesettings->min_delay_ms = 100;
 696                 fesettings->step_size = 500;
 697                 fesettings->max_drift = 7000;
 698         } else if (fesettings->parameters.u.qpsk.symbol_rate > 2000000) {
 699                 fesettings->min_delay_ms = 200;
 700                 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000);
 701                 fesettings->max_drift = 14 * fesettings->step_size;
 702         } else {
 703                 fesettings->min_delay_ms = 200;
 704                 fesettings->step_size = (fesettings->parameters.u.qpsk.symbol_rate / 8000);
 705                 fesettings->max_drift = 18 * fesettings->step_size;
 706         }
 707
 708         return 0;
 709 }
 710
 711 static int s5h1420_init (struct dvb_frontend* fe)
 712 {
 713         struct s5h1420_state* state = fe->demodulator_priv;
 714
 715         /* disable power down and do reset */
 716         s5h1420_writereg(state, 0x02, 0x10);
 717         msleep(10);
 718         s5h1420_reset(state);
 719
 720         /* init PLL */
 721         if (state->config->pll_init) {
 722                 s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) | 1);
 723                 state->config->pll_init(fe);
 724                 s5h1420_writereg (state, 0x02, s5h1420_readreg(state,0x02) & 0xfe);
 725         }
 726
 727         return 0;
 728 }
 729
 730 static int s5h1420_sleep(struct dvb_frontend* fe)
 731 {
 732         struct s5h1420_state* state = fe->demodulator_priv;
 733
 734         return s5h1420_writereg(state, 0x02, 0x12);
 735 }
 736
 737 static void s5h1420_release(struct dvb_frontend* fe)
 738 {
 739         struct s5h1420_state* state = fe->demodulator_priv;
 740         kfree(state);
 741 }
 742
 743 static struct dvb_frontend_ops s5h1420_ops;
 744
 745 struct dvb_frontend* s5h1420_attach(const struct s5h1420_config* config,
 746                                     struct i2c_adapter* i2c)
 747 {
 748         struct s5h1420_state* state = NULL;
 749         u8 identity;
 750
 751         /* allocate memory for the internal state */
 752         state = kmalloc(sizeof(struct s5h1420_state), GFP_KERNEL);
 753         if (state == NULL)
 754                 goto error;
 755
 756         /* setup the state */
 757         state->config = config;
 758         state->i2c = i2c;
 759         memcpy(&state->ops, &s5h1420_ops, sizeof(struct dvb_frontend_ops));
 760         state->postlocked = 0;
 761         state->fclk = 88000000;
 762         state->tunedfreq = 0;
 763         state->fec_inner = FEC_NONE;
 764         state->symbol_rate = 0;
 765
 766         /* check if the demod is there + identify it */
 767         identity = s5h1420_readreg(state, 0x00);
 768         if (identity != 0x03)
 769                 goto error;
 770
 771         /* create dvb_frontend */
 772         state->frontend.ops = &state->ops;
 773         state->frontend.demodulator_priv = state;
 774         return &state->frontend;
 775
 776 error:
 777         kfree(state);
 778         return NULL;
 779 }
 780
 781 static struct dvb_frontend_ops s5h1420_ops = {
 782
 783         .info = {
 784                 .name     = "Samsung S5H1420 DVB-S",
 785                 .type     = FE_QPSK,
 786                 .frequency_min    = 950000,
 787                 .frequency_max    = 2150000,
 788                 .frequency_stepsize = 125,     /* kHz for QPSK frontends */
 789                 .frequency_tolerance  = 29500,
 790                 .symbol_rate_min  = 1000000,
 791                 .symbol_rate_max  = 45000000,
 792                 /*  .symbol_rate_tolerance  = ???,*/
 793                 .caps = FE_CAN_INVERSION_AUTO |
 794                 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 795                 FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 796                 FE_CAN_QPSK
 797         },
 798
 799         .release = s5h1420_release,
 800
 801         .init = s5h1420_init,
 802         .sleep = s5h1420_sleep,
 803
 804         .set_frontend = s5h1420_set_frontend,
 805         .get_frontend = s5h1420_get_frontend,
 806         .get_tune_settings = s5h1420_get_tune_settings,
 807
 808         .read_status = s5h1420_read_status,
 809         .read_ber = s5h1420_read_ber,
 810         .read_signal_strength = s5h1420_read_signal_strength,
 811         .read_ucblocks = s5h1420_read_ucblocks,
 812
 813         .diseqc_send_master_cmd = s5h1420_send_master_cmd,
 814         .diseqc_recv_slave_reply = s5h1420_recv_slave_reply,
 815         .diseqc_send_burst = s5h1420_send_burst,
 816         .set_tone = s5h1420_set_tone,
 817         .set_voltage = s5h1420_set_voltage,
 818 };
 819
 820 module_param(debug, int, 0644);
 821
 822 MODULE_DESCRIPTION("Samsung S5H1420 DVB-S Demodulator driver");
 823 MODULE_AUTHOR("Andrew de Quincey");
 824 MODULE_LICENSE("GPL");
 825
 826 EXPORT_SYMBOL(s5h1420_attach);