drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Frontend
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22
  23 /*
  24     This driver needs a copy of the DLL "ttlcdacc.dll" from the Haupauge or Technotrend
  25     windows driver saved as '/usr/lib/hotplug/firmware/tda1004x.bin'.
  26     You can also pass the complete file name with the module parameter 'tda1004x_firmware'.
  27
  28     Currently the DLL from v2.15a of the technotrend driver is supported. Other versions can
  29     be added reasonably painlessly.
  30
  31     Windows driver URL: http://www.technotrend.de/
  32  */
  33
  34
  35 #define __KERNEL_SYSCALLS__
  36 #include <linux/kernel.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/module.h>
  39 #include <linux/init.h>
  40 #include <linux/string.h>
  41 #include <linux/slab.h>
  42 #include <linux/fs.h>
  43 #include <linux/unistd.h>
  44 #include <linux/fcntl.h>
  45 #include <linux/errno.h>
  46 #include <linux/syscalls.h>
  47
  48 #include "dvb_frontend.h"
  49 #include "dvb_functions.h"
  50
  51 #ifndef DVB_TDA1004X_FIRMWARE_FILE
  52 #define DVB_TDA1004X_FIRMWARE_FILE "/usr/lib/hotplug/firmware/tda1004x.bin"
  53 #endif
  54
  55 static int tda1004x_debug = 0;
  56 static char *tda1004x_firmware = DVB_TDA1004X_FIRMWARE_FILE;
  57
  58 #define MC44BC374_ADDRESS        0x65
  59
  60 #define TDA1004X_CHIPID          0x00
  61 #define TDA1004X_AUTO            0x01
  62 #define TDA1004X_IN_CONF1        0x02
  63 #define TDA1004X_IN_CONF2        0x03
  64 #define TDA1004X_OUT_CONF1       0x04
  65 #define TDA1004X_OUT_CONF2       0x05
  66 #define TDA1004X_STATUS_CD       0x06
  67 #define TDA1004X_CONFC4          0x07
  68 #define TDA1004X_DSSPARE2        0x0C
  69 #define TDA10045H_CODE_IN        0x0D
  70 #define TDA10045H_FWPAGE         0x0E
  71 #define TDA1004X_SCAN_CPT        0x10
  72 #define TDA1004X_DSP_CMD         0x11
  73 #define TDA1004X_DSP_ARG         0x12
  74 #define TDA1004X_DSP_DATA1       0x13
  75 #define TDA1004X_DSP_DATA2       0x14
  76 #define TDA1004X_CONFADC1        0x15
  77 #define TDA1004X_CONFC1          0x16
  78 #define TDA10045H_S_AGC          0x1a
  79 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  80 #define TDA1004X_SNR             0x1c
  81 #define TDA1004X_CONF_TS1        0x1e
  82 #define TDA1004X_CONF_TS2        0x1f
  83 #define TDA1004X_CBER_RESET      0x20
  84 #define TDA1004X_CBER_MSB        0x21
  85 #define TDA1004X_CBER_LSB        0x22
  86 #define TDA1004X_CVBER_LUT       0x23
  87 #define TDA1004X_VBER_MSB        0x24
  88 #define TDA1004X_VBER_MID        0x25
  89 #define TDA1004X_VBER_LSB        0x26
  90 #define TDA1004X_UNCOR           0x27
  91
  92 #define TDA10045H_CONFPLL_P      0x2D
  93 #define TDA10045H_CONFPLL_M_MSB  0x2E
  94 #define TDA10045H_CONFPLL_M_LSB  0x2F
  95 #define TDA10045H_CONFPLL_N      0x30
  96
  97 #define TDA10046H_CONFPLL1       0x2D
  98 #define TDA10046H_CONFPLL2       0x2F
  99 #define TDA10046H_CONFPLL3       0x30
 100 #define TDA10046H_TIME_WREF1     0x31
 101 #define TDA10046H_TIME_WREF2     0x32
 102 #define TDA10046H_TIME_WREF3     0x33
 103 #define TDA10046H_TIME_WREF4     0x34
 104 #define TDA10046H_TIME_WREF5     0x35
 105
 106 #define TDA10045H_UNSURW_MSB     0x31
 107 #define TDA10045H_UNSURW_LSB     0x32
 108 #define TDA10045H_WREF_MSB       0x33
 109 #define TDA10045H_WREF_MID       0x34
 110 #define TDA10045H_WREF_LSB       0x35
 111 #define TDA10045H_MUXOUT         0x36
 112 #define TDA1004X_CONFADC2        0x37
 113
 114 #define TDA10045H_IOFFSET        0x38
 115
 116 #define TDA10046H_CONF_TRISTATE1 0x3B
 117 #define TDA10046H_CONF_TRISTATE2 0x3C
 118 #define TDA10046H_CONF_POLARITY  0x3D
 119 #define TDA10046H_FREQ_OFFSET    0x3E
 120 #define TDA10046H_GPIO_OUT_SEL   0x41
 121 #define TDA10046H_GPIO_SELECT    0x42
 122 #define TDA10046H_AGC_CONF       0x43
 123 #define TDA10046H_AGC_GAINS      0x46
 124 #define TDA10046H_AGC_TUN_MIN    0x47
 125 #define TDA10046H_AGC_TUN_MAX    0x48
 126 #define TDA10046H_AGC_IF_MIN     0x49
 127 #define TDA10046H_AGC_IF_MAX     0x4A
 128
 129 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 130 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 131
 132 #define TDA10046H_CVBER_CTRL     0x4F
 133 #define TDA10046H_AGC_IF_LEVEL   0x52
 134 #define TDA10046H_CODE_CPT       0x57
 135 #define TDA10046H_CODE_IN        0x58
 136
 137
 138 #define FE_TYPE_TDA10045H     0
 139 #define FE_TYPE_TDA10046H     1
 140
 141 #define TUNER_TYPE_TD1344     0
 142 #define TUNER_TYPE_TD1316     1
 143
 144 #define dprintk if (tda1004x_debug) printk
 145
 146 static struct dvb_frontend_info tda10045h_info = {
 147         .name = "Philips TDA10045H",
 148         .type = FE_OFDM,
 149         .frequency_min = 51000000,
 150         .frequency_max = 858000000,
 151         .frequency_stepsize = 166667,
 152         .caps =
 153             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 154             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 155             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 156             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
 157 };
 158
 159 static struct dvb_frontend_info tda10046h_info = {
 160         .name = "Philips TDA10046H",
 161         .type = FE_OFDM,
 162         .frequency_min = 51000000,
 163         .frequency_max = 858000000,
 164         .frequency_stepsize = 166667,
 165         .caps =
 166             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 167             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 168             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 169             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
 170 };
 171
 172
 173 struct tda1004x_state {
 174         u8 tda1004x_address;
 175         u8 tuner_address;
 176         u8 initialised:1;
 177         u8 tuner_type:2;
 178         u8 fe_type:2;
 179 };
 180
 181
 182 struct fwinfo {
 183         int file_size;
 184         int fw_offset;
 185         int fw_size;
 186 };
 187 static struct fwinfo tda10045h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x34cc5,.fw_size = 30555} };
 188 static int tda10045h_fwinfo_count = sizeof(tda10045h_fwinfo) / sizeof(struct fwinfo);
 189
 190 static struct fwinfo tda10046h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x3c4f9,.fw_size = 24479} };
 191 static int tda10046h_fwinfo_count = sizeof(tda10046h_fwinfo) / sizeof(struct fwinfo);
 192
 193
 194
 195 static int tda1004x_write_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int data)
 196 {
 197         int ret;
 198         u8 buf[] = { reg, data };
 199         struct i2c_msg msg = { .addr=0, .flags=0, .buf=buf, .len=2 };
 200
 201         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 202
 203         msg.addr = tda_state->tda1004x_address;
 204         ret = i2c->xfer(i2c, &msg, 1);
 205
 206         if (ret != 1)
 207                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 208                        __FUNCTION__, reg, data, ret);
 209
 210         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 211                 reg, data, ret);
 212         return (ret != 1) ? -1 : 0;
 213 }
 214
 215 static int tda1004x_read_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg)
 216 {
 217         int ret;
 218         u8 b0[] = { reg };
 219         u8 b1[] = { 0 };
 220         struct i2c_msg msg[] = {{ .addr=0, .flags=0, .buf=b0, .len=1},
 221                                 { .addr=0, .flags=I2C_M_RD, .buf=b1, .len = 1}};
 222
 223         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 224
 225         msg[0].addr = tda_state->tda1004x_address;
 226         msg[1].addr = tda_state->tda1004x_address;
 227         ret = i2c->xfer(i2c, msg, 2);
 228
 229         if (ret != 2) {
 230                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 231                        ret);
 232                 return -1;
 233         }
 234
 235         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 236                 reg, b1[0], ret);
 237         return b1[0];
 238 }
 239
 240 static int tda1004x_write_mask(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int mask, int data)
 241 {
 242         int val;
 243         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 244                 mask, data);
 245
 246         // read a byte and check
 247         val = tda1004x_read_byte(i2c, tda_state, reg);
 248         if (val < 0)
 249                 return val;
 250
 251         // mask if off
 252         val = val & ~mask;
 253         val |= data & 0xff;
 254
 255         // write it out again
 256         return tda1004x_write_byte(i2c, tda_state, reg, val);
 257 }
 258
 259 static int tda1004x_write_buf(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, unsigned char *buf, int len)
 260 {
 261         int i;
 262         int result;
 263
 264         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 265
 266         result = 0;
 267         for (i = 0; i < len; i++) {
 268                 result = tda1004x_write_byte(i2c, tda_state, reg + i, buf[i]);
 269                 if (result != 0)
 270                         break;
 271         }
 272
 273         return result;
 274 }
 275
 276 static int tda1004x_enable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 277 {
 278         int result;
 279         dprintk("%s\n", __FUNCTION__);
 280
 281         result = tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 2);
 282         dvb_delay(1);
 283         return result;
 284 }
 285
 286 static int tda1004x_disable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 287 {
 288
 289         dprintk("%s\n", __FUNCTION__);
 290
 291         return tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 0);
 292 }
 293
 294
 295 static int tda10045h_set_bandwidth(struct dvb_i2c_bus *i2c,
 296                                    struct tda1004x_state *tda_state,
 297                                    fe_bandwidth_t bandwidth)
 298 {
 299         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 300         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 301         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 302
 303         switch (bandwidth) {
 304         case BANDWIDTH_6_MHZ:
 305                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
 306                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 307                 break;
 308
 309         case BANDWIDTH_7_MHZ:
 310                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x80);
 311                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 312                 break;
 313
 314         case BANDWIDTH_8_MHZ:
 315                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
 316                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 317                 break;
 318
 319         default:
 320                 return -EINVAL;
 321         }
 322
 323         tda1004x_write_byte(i2c, tda_state, TDA10045H_IOFFSET, 0);
 324
 325         // done
 326         return 0;
 327 }
 328
 329
 330 static int tda10046h_set_bandwidth(struct dvb_i2c_bus *i2c,
 331                                    struct tda1004x_state *tda_state,
 332                                    fe_bandwidth_t bandwidth)
 333 {
 334         static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
 335         static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
 336         static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
 337
 338         switch (bandwidth) {
 339         case BANDWIDTH_6_MHZ:
 340                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 341                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
 342                 break;
 343
 344         case BANDWIDTH_7_MHZ:
 345                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 346                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
 347                 break;
 348
 349         case BANDWIDTH_8_MHZ:
 350                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 351                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0xFF);
 352                 break;
 353
 354         default:
 355                 return -EINVAL;
 356         }
 357
 358         // done
 359         return 0;
 360 }
 361
 362
 363 static int tda1004x_fwupload(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 364 {
 365         u8 fw_buf[65];
 366         struct i2c_msg fw_msg = {.addr = 0,.flags = 0,.buf = fw_buf,.len = 0 };
 367         unsigned char *firmware = NULL;
 368         int filesize;
 369         int fd;
 370         int fwinfo_idx;
 371         int fw_size = 0;
 372         int fw_pos, fw_offset;
 373         int tx_size;
 374         mm_segment_t fs = get_fs();
 375         int dspCodeCounterReg=0, dspCodeInReg=0, dspVersion=0;
 376         int fwInfoCount=0;
 377         struct fwinfo* fwInfo = NULL;
 378         unsigned long timeout;
 379
 380         // DSP parameters
 381         switch(tda_state->fe_type) {
 382         case FE_TYPE_TDA10045H:
 383                 dspCodeCounterReg = TDA10045H_FWPAGE;
 384                 dspCodeInReg = TDA10045H_CODE_IN;
 385                 dspVersion = 0x2c;
 386                 fwInfoCount = tda10045h_fwinfo_count;
 387                 fwInfo = tda10045h_fwinfo;
 388                 break;
 389
 390         case FE_TYPE_TDA10046H:
 391                 dspCodeCounterReg = TDA10046H_CODE_CPT;
 392                 dspCodeInReg = TDA10046H_CODE_IN;
 393                 dspVersion = 0x20;
 394                 fwInfoCount = tda10046h_fwinfo_count;
 395                 fwInfo = tda10046h_fwinfo;
 396                 break;
 397         }
 398
 399         // Load the firmware
 400         set_fs(get_ds());
 401         fd = open(tda1004x_firmware, 0, 0);
 402         if (fd < 0) {
 403                 printk("%s: Unable to open firmware %s\n", __FUNCTION__,
 404                        tda1004x_firmware);
 405                 return -EIO;
 406         }
 407         filesize = lseek(fd, 0L, 2);
 408         if (filesize <= 0) {
 409                 printk("%s: Firmware %s is empty\n", __FUNCTION__,
 410                        tda1004x_firmware);
 411                 sys_close(fd);
 412                 return -EIO;
 413         }
 414
 415         // find extraction parameters for firmware
 416         for (fwinfo_idx = 0; fwinfo_idx < fwInfoCount; fwinfo_idx++) {
 417                 if (fwInfo[fwinfo_idx].file_size == filesize)
 418                         break;
 419         }
 420         if (fwinfo_idx >= fwInfoCount) {
 421                 printk("%s: Unsupported firmware %s\n", __FUNCTION__, tda1004x_firmware);
 422                 sys_close(fd);
 423                 return -EIO;
 424         }
 425         fw_size = fwInfo[fwinfo_idx].fw_size;
 426         fw_offset = fwInfo[fwinfo_idx].fw_offset;
 427
 428         // allocate buffer for it
 429         firmware = vmalloc(fw_size);
 430         if (firmware == NULL) {
 431                 printk("%s: Out of memory loading firmware\n",
 432                        __FUNCTION__);
 433                 sys_close(fd);
 434                 return -EIO;
 435         }
 436
 437         // read it!
 438         lseek(fd, fw_offset, 0);
 439         if (read(fd, firmware, fw_size) != fw_size) {
 440                 printk("%s: Failed to read firmware\n", __FUNCTION__);
 441                 vfree(firmware);
 442                 sys_close(fd);
 443                 return -EIO;
 444         }
 445         sys_close(fd);
 446         set_fs(fs);
 447
 448         // set some valid bandwith parameters before uploading
 449         switch(tda_state->fe_type) {
 450         case FE_TYPE_TDA10045H:
 451                 // reset chip
 452                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0);
 453                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
 454                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
 455                 dvb_delay(10);
 456
 457                 // set parameters
 458                 tda10045h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ);
 459                 break;
 460
 461         case FE_TYPE_TDA10046H:
 462                 // reset chip
 463                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0);
 464                 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 1, 0);
 465                 dvb_delay(10);
 466
 467                 // set parameters
 468                 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10);
 469                 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0);
 470                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99);
 471                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 472                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
 473                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 474                 break;
 475         }
 476
 477         // do the firmware upload
 478         tda1004x_write_byte(i2c, tda_state, dspCodeCounterReg, 0); // clear code counter
 479         fw_msg.addr = tda_state->tda1004x_address;
 480         fw_pos = 0;
 481         while (fw_pos != fw_size) {
 482
 483                 // work out how much to send this time
 484                 tx_size = fw_size - fw_pos;
 485                 if (tx_size > 0x10) {
 486                         tx_size = 0x10;
 487                 }
 488
 489                 // send the chunk
 490                 fw_buf[0] = dspCodeInReg;
 491                 memcpy(fw_buf + 1, firmware + fw_pos, tx_size);
 492                 fw_msg.len = tx_size + 1;
 493                 if (i2c->xfer(i2c, &fw_msg, 1) != 1) {
 494                         printk("tda1004x: Error during firmware upload\n");
 495                         vfree(firmware);
 496                         return -EIO;
 497                 }
 498                 fw_pos += tx_size;
 499
 500                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, fw_pos);
 501         }
 502         vfree(firmware);
 503
 504         // wait for DSP to initialise
 505         switch(tda_state->fe_type) {
 506         case FE_TYPE_TDA10045H:
 507                 // DSPREADY doesn't seem to work on the TDA10045H
 508                 dvb_delay(100);
 509                 break;
 510
 511         case FE_TYPE_TDA10046H:
 512                 timeout = jiffies + HZ;
 513                 while(!(tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD) & 0x20)) {
 514                         if (time_after(jiffies, timeout)) {
 515                                 printk("tda1004x: DSP failed to initialised.\n");
 516                                 return -EIO;
 517                         }
 518
 519                         dvb_delay(1);
 520                 }
 521                 break;
 522         }
 523
 524         // check upload was OK
 525         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 526         tda1004x_write_byte(i2c, tda_state, TDA1004X_DSP_CMD, 0x67);
 527         if ((tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA1) != 0x67) ||
 528             (tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA2) != dspVersion)) {
 529                 printk("%s: firmware upload failed!\n", __FUNCTION__);
 530                 return -EIO;
 531         }
 532
 533         // success
 534         return 0;
 535 }
 536
 537
 538 static int tda10045h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 539 {
 540         struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = 0,.len = 0 };
 541         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 542
 543         dprintk("%s\n", __FUNCTION__);
 544
 545         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 546
 547         // Disable the MC44BC374C
 548         tda1004x_enable_tuner_i2c(i2c, tda_state);
 549         tuner_msg.addr = MC44BC374_ADDRESS;
 550         tuner_msg.buf = disable_mc44BC374c;
 551         tuner_msg.len = sizeof(disable_mc44BC374c);
 552         if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 553                 i2c->xfer(i2c, &tuner_msg, 1);
 554         }
 555         tda1004x_disable_tuner_i2c(i2c, tda_state);
 556
 557         // tda setup
 558         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 559         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
 560         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0); // no frequency inversion
 561         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 562         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 563         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 564         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 565         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 566         tda1004x_write_mask(i2c, tda_state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 567         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 568         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONFADC1, 0x2e);
 569
 570         // done
 571         return 0;
 572 }
 573
 574
 575
 576 static int tda10046h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 577 {
 578         struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = 0,.len = 0 };
 579         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 580
 581         dprintk("%s\n", __FUNCTION__);
 582
 583         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0); // wake up the chip
 584
 585         // Disable the MC44BC374C
 586         tda1004x_enable_tuner_i2c(i2c, tda_state);
 587         tuner_msg.addr = MC44BC374_ADDRESS;
 588         tuner_msg.buf = disable_mc44BC374c;
 589         tuner_msg.len = sizeof(disable_mc44BC374c);
 590         if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 591                 i2c->xfer(i2c, &tuner_msg, 1);
 592         }
 593         tda1004x_disable_tuner_i2c(i2c, tda_state);
 594
 595         // tda setup
 596         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 597         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0x40); // TT TDA10046H needs inversion ON
 598         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
 599         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
 600         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10); // PLL M = 10
 601         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 602         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
 603         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
 604         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
 605         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_CONF, 0); // AGC setup
 606         tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
 607         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MIN, 0);    // }
 608         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 609         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MIN, 0);     // }
 610         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 611         tda1004x_write_mask(i2c, tda_state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
 612         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
 613         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
 614         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 615         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
 616         tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
 617         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
 618         tda1004x_write_byte(i2c, tda_state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
 619         tda1004x_write_mask(i2c, tda_state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
 620         tda10046h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 621
 622         // done
 623         return 0;
 624 }
 625
 626
 627
 628 static int tda1004x_encode_fec(int fec)
 629 {
 630         // convert known FEC values
 631         switch (fec) {
 632         case FEC_1_2:
 633                 return 0;
 634         case FEC_2_3:
 635                 return 1;
 636         case FEC_3_4:
 637                 return 2;
 638         case FEC_5_6:
 639                 return 3;
 640         case FEC_7_8:
 641                 return 4;
 642         }
 643
 644         // unsupported
 645         return -EINVAL;
 646 }
 647
 648 static int tda1004x_decode_fec(int tdafec)
 649 {
 650         // convert known FEC values
 651         switch (tdafec) {
 652         case 0:
 653                 return FEC_1_2;
 654         case 1:
 655                 return FEC_2_3;
 656         case 2:
 657                 return FEC_3_4;
 658         case 3:
 659                 return FEC_5_6;
 660         case 4:
 661                 return FEC_7_8;
 662         }
 663
 664         // unsupported
 665         return -1;
 666 }
 667
 668 static int tda1004x_set_frequency(struct dvb_i2c_bus *i2c,
 669                            struct tda1004x_state *tda_state,
 670                            struct dvb_frontend_parameters *fe_params)
 671 {
 672         u8 tuner_buf[4];
 673         struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=tuner_buf, .len=sizeof(tuner_buf) };
 674         int tuner_frequency = 0;
 675         u8 band, cp, filter;
 676         int counter, counter2;
 677
 678         dprintk("%s\n", __FUNCTION__);
 679
 680         // setup the frequency buffer
 681         switch (tda_state->tuner_type) {
 682         case TUNER_TYPE_TD1344:
 683
 684                 // setup tuner buffer
 685                 // ((Fif+((1000000/6)/2)) + Finput)/(1000000/6)
 686                 tuner_frequency =
 687                         (((fe_params->frequency / 1000) * 6) + 217502) / 1000;
 688                 tuner_buf[0] = tuner_frequency >> 8;
 689                 tuner_buf[1] = tuner_frequency & 0xff;
 690                 tuner_buf[2] = 0x88;
 691                 if (fe_params->frequency < 550000000) {
 692                         tuner_buf[3] = 0xab;
 693                 } else {
 694                         tuner_buf[3] = 0xeb;
 695                 }
 696
 697                 // tune it
 698                 tda1004x_enable_tuner_i2c(i2c, tda_state);
 699                 tuner_msg.addr = tda_state->tuner_address;
 700                 tuner_msg.len = 4;
 701                 i2c->xfer(i2c, &tuner_msg, 1);
 702
 703                 // wait for it to finish
 704                 tuner_msg.len = 1;
 705                 tuner_msg.flags = I2C_M_RD;
 706                 counter = 0;
 707                 counter2 = 0;
 708                 while (counter++ < 100) {
 709                         if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
 710                                 if (tuner_buf[0] & 0x40) {
 711                                         counter2++;
 712                                 } else {
 713                                         counter2 = 0;
 714                                 }
 715                         }
 716
 717                         if (counter2 > 10) {
 718                                 break;
 719                         }
 720                 }
 721                 tda1004x_disable_tuner_i2c(i2c, tda_state);
 722                 break;
 723
 724         case TUNER_TYPE_TD1316:
 725                 // determine charge pump
 726                 tuner_frequency = fe_params->frequency + 36130000;
 727                 if (tuner_frequency < 87000000) {
 728                         return -EINVAL;
 729                 } else if (tuner_frequency < 130000000) {
 730                         cp = 3;
 731                 } else if (tuner_frequency < 160000000) {
 732                         cp = 5;
 733                 } else if (tuner_frequency < 200000000) {
 734                         cp = 6;
 735                 } else if (tuner_frequency < 290000000) {
 736                         cp = 3;
 737                 } else if (tuner_frequency < 420000000) {
 738                         cp = 5;
 739                 } else if (tuner_frequency < 480000000) {
 740                         cp = 6;
 741                 } else if (tuner_frequency < 620000000) {
 742                         cp = 3;
 743                 } else if (tuner_frequency < 830000000) {
 744                         cp = 5;
 745                 } else if (tuner_frequency < 895000000) {
 746                         cp = 7;
 747                 } else {
 748                         return -EINVAL;
 749                 }
 750
 751                 // determine band
 752                 if (fe_params->frequency < 49000000) {
 753                         return -EINVAL;
 754                 } else if (fe_params->frequency < 159000000) {
 755                         band = 1;
 756                 } else if (fe_params->frequency < 444000000) {
 757                         band = 2;
 758                 } else if (fe_params->frequency < 861000000) {
 759                         band = 4;
 760                 } else {
 761                         return -EINVAL;
 762                 }
 763
 764                 // work out filter
 765                 switch (fe_params->u.ofdm.bandwidth) {
 766                 case BANDWIDTH_6_MHZ:
 767                         filter = 0;
 768                         break;
 769
 770                 case BANDWIDTH_7_MHZ:
 771                         filter = 0;
 772                         break;
 773
 774                 case BANDWIDTH_8_MHZ:
 775                         filter = 1;
 776                         break;
 777
 778                 default:
 779                         return -EINVAL;
 780                 }
 781
 782                 // calculate divisor
 783                 // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
 784                 tuner_frequency =
 785                         (((fe_params->frequency / 1000) * 6) + 217280) / 1000;
 786
 787                 // setup tuner buffer
 788                 tuner_buf[0] = tuner_frequency >> 8;
 789                 tuner_buf[1] = tuner_frequency & 0xff;
 790                 tuner_buf[2] = 0xca;
 791                 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
 792
 793                 // tune it
 794                 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
 795                         // setup auto offset
 796                         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10);
 797                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x80, 0);
 798                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0);
 799
 800                         // disable agc_conf[2]
 801                         tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 0);
 802                 }
 803                 tda1004x_enable_tuner_i2c(i2c, tda_state);
 804                 tuner_msg.addr = tda_state->tuner_address;
 805                 tuner_msg.len = 4;
 806                 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 807                         return -EIO;
 808                 }
 809                 dvb_delay(1);
 810                 tda1004x_disable_tuner_i2c(i2c, tda_state);
 811                 if (tda_state->fe_type == FE_TYPE_TDA10046H)
 812                         tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 4);
 813                 break;
 814
 815         default:
 816                 return -EINVAL;
 817         }
 818
 819         dprintk("%s: success\n", __FUNCTION__);
 820
 821         // done
 822         return 0;
 823 }
 824
 825 static int tda1004x_set_fe(struct dvb_i2c_bus *i2c,
 826                            struct tda1004x_state *tda_state,
 827                            struct dvb_frontend_parameters *fe_params)
 828 {
 829         int tmp;
 830         int inversion;
 831
 832         dprintk("%s\n", __FUNCTION__);
 833
 834         // set frequency
 835         if ((tmp = tda1004x_set_frequency(i2c, tda_state, fe_params)) < 0)
 836                 return tmp;
 837
 838         // hardcoded to use auto as much as possible
 839         fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 840         fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 841         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 842
 843         // Set standard params.. or put them to auto
 844         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 845             (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 846             (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 847             (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 848                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 1);       // enable auto
 849                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x03, 0);        // turn off constellation bits
 850                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0);        // turn off hierarchy bits
 851                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x3f, 0);        // turn off FEC bits
 852         } else {
 853                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 0);       // disable auto
 854
 855                 // set HP FEC
 856                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 857                 if (tmp < 0) return tmp;
 858                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 7, tmp);
 859
 860                 // set LP FEC
 861                 if (fe_params->u.ofdm.code_rate_LP != FEC_NONE) {
 862                         tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 863                         if (tmp < 0) return tmp;
 864                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 865                 }
 866
 867                 // set constellation
 868                 switch (fe_params->u.ofdm.constellation) {
 869                 case QPSK:
 870                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 0);
 871                         break;
 872
 873                 case QAM_16:
 874                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 1);
 875                         break;
 876
 877                 case QAM_64:
 878                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 2);
 879                         break;
 880
 881                 default:
 882                         return -EINVAL;
 883                 }
 884
 885                 // set hierarchy
 886                 switch (fe_params->u.ofdm.hierarchy_information) {
 887                 case HIERARCHY_NONE:
 888                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 889                         break;
 890
 891                 case HIERARCHY_1:
 892                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 893                         break;
 894
 895                 case HIERARCHY_2:
 896                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 897                         break;
 898
 899                 case HIERARCHY_4:
 900                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 901                         break;
 902
 903                 default:
 904                         return -EINVAL;
 905                 }
 906         }
 907
 908         // set bandwidth
 909         switch(tda_state->fe_type) {
 910         case FE_TYPE_TDA10045H:
 911                 tda10045h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
 912                 break;
 913
 914         case FE_TYPE_TDA10046H:
 915                 tda10046h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
 916                 break;
 917         }
 918
 919         // need to invert the inversion for TT TDA10046H
 920         inversion = fe_params->inversion;
 921         if (tda_state->fe_type == FE_TYPE_TDA10046H) {
 922                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 923         }
 924
 925         // set inversion
 926         switch (inversion) {
 927         case INVERSION_OFF:
 928                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0);
 929                 break;
 930
 931         case INVERSION_ON:
 932                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0x20);
 933                 break;
 934
 935         default:
 936                 return -EINVAL;
 937         }
 938
 939         // set guard interval
 940         switch (fe_params->u.ofdm.guard_interval) {
 941         case GUARD_INTERVAL_1_32:
 942                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 943                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 944                 break;
 945
 946         case GUARD_INTERVAL_1_16:
 947                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 948                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 949                 break;
 950
 951         case GUARD_INTERVAL_1_8:
 952                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 953                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 954                 break;
 955
 956         case GUARD_INTERVAL_1_4:
 957                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 958                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 959                 break;
 960
 961         case GUARD_INTERVAL_AUTO:
 962                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 2);
 963                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 964                 break;
 965
 966         default:
 967                 return -EINVAL;
 968         }
 969
 970         // set transmission mode
 971         switch (fe_params->u.ofdm.transmission_mode) {
 972         case TRANSMISSION_MODE_2K:
 973                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
 974                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 975                 break;
 976
 977         case TRANSMISSION_MODE_8K:
 978                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
 979                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 980                 break;
 981
 982         case TRANSMISSION_MODE_AUTO:
 983                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 4);
 984                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0);
 985                 break;
 986
 987         default:
 988                 return -EINVAL;
 989         }
 990
 991         // start the lock
 992         switch(tda_state->fe_type) {
 993         case FE_TYPE_TDA10045H:
 994         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
 995         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
 996         dvb_delay(10);
 997                 break;
 998
 999         case FE_TYPE_TDA10046H:
1000                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x40, 0x40);
1001                 dvb_delay(10);
1002                 break;
1003         }
1004
1005         // done
1006         return 0;
1007 }
1008
1009
1010 static int tda1004x_get_fe(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, struct dvb_frontend_parameters *fe_params)
1011 {
1012
1013         dprintk("%s\n", __FUNCTION__);
1014
1015         // inversion status
1016         fe_params->inversion = INVERSION_OFF;
1017         if (tda1004x_read_byte(i2c, tda_state, TDA1004X_CONFC1) & 0x20) {
1018                 fe_params->inversion = INVERSION_ON;
1019         }
1020
1021         // need to invert the inversion for TT TDA10046H
1022         if (tda_state->fe_type == FE_TYPE_TDA10046H) {
1023                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
1024         }
1025
1026         // bandwidth
1027         switch(tda_state->fe_type) {
1028         case FE_TYPE_TDA10045H:
1029                 switch (tda1004x_read_byte(i2c, tda_state, TDA10045H_WREF_LSB)) {
1030         case 0x14:
1031                 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1032                 break;
1033         case 0xdb:
1034                 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1035                 break;
1036         case 0x4f:
1037                 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1038                 break;
1039         }
1040                 break;
1041
1042         case FE_TYPE_TDA10046H:
1043                 switch (tda1004x_read_byte(i2c, tda_state, TDA10046H_TIME_WREF1)) {
1044                 case 0x60:
1045                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1046                         break;
1047                 case 0x6e:
1048                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1049                         break;
1050                 case 0x80:
1051                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1052                         break;
1053                 }
1054                 break;
1055         }
1056
1057         // FEC
1058         fe_params->u.ofdm.code_rate_HP =
1059             tda1004x_decode_fec(tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) & 7);
1060         fe_params->u.ofdm.code_rate_LP =
1061             tda1004x_decode_fec((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) >> 3) & 7);
1062
1063         // constellation
1064         switch (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 3) {
1065         case 0:
1066                 fe_params->u.ofdm.constellation = QPSK;
1067                 break;
1068         case 1:
1069                 fe_params->u.ofdm.constellation = QAM_16;
1070                 break;
1071         case 2:
1072                 fe_params->u.ofdm.constellation = QAM_64;
1073                 break;
1074         }
1075
1076         // transmission mode
1077         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1078         if (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x10) {
1079                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1080         }
1081
1082         // guard interval
1083         switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
1084         case 0:
1085                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1086                 break;
1087         case 1:
1088                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1089                 break;
1090         case 2:
1091                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1092                 break;
1093         case 3:
1094                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1095                 break;
1096         }
1097
1098         // hierarchy
1099         switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
1100         case 0:
1101                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1102                 break;
1103         case 1:
1104                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
1105                 break;
1106         case 2:
1107                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
1108                 break;
1109         case 3:
1110                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
1111                 break;
1112         }
1113
1114         // done
1115         return 0;
1116 }
1117
1118
1119 static int tda1004x_read_status(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, fe_status_t * fe_status)
1120 {
1121         int status;
1122         int cber;
1123         int vber;
1124
1125         dprintk("%s\n", __FUNCTION__);
1126
1127         // read status
1128         status = tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD);
1129         if (status == -1) {
1130                 return -EIO;
1131         }
1132
1133         // decode
1134         *fe_status = 0;
1135         if (status & 4) *fe_status |= FE_HAS_SIGNAL;
1136         if (status & 2) *fe_status |= FE_HAS_CARRIER;
1137         if (status & 8) *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1138
1139         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1140         // is getting anything valid
1141         if (!(*fe_status & FE_HAS_VITERBI)) {
1142                 // read the CBER
1143                 cber = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1144                 if (cber == -1) return -EIO;
1145                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1146                 if (status == -1) return -EIO;
1147                 cber |= (status << 8);
1148                 tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1149
1150                 if (cber != 65535) {
1151                         *fe_status |= FE_HAS_VITERBI;
1152                 }
1153         }
1154
1155         // if we DO have some valid VITERBI output, but don't already have SYNC
1156         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1157         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1158                 // read the VBER
1159                 vber = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_LSB);
1160                 if (vber == -1) return -EIO;
1161                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MID);
1162                 if (status == -1) return -EIO;
1163                 vber |= (status << 8);
1164                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MSB);
1165                 if (status == -1) return -EIO;
1166                 vber |= ((status << 16) & 0x0f);
1167                 tda1004x_read_byte(i2c, tda_state, TDA1004X_CVBER_LUT);
1168
1169                 // if RS has passed some valid TS packets, then we must be
1170                 // getting some SYNC bytes
1171                 if (vber < 16632) {
1172                         *fe_status |= FE_HAS_SYNC;
1173                 }
1174         }
1175
1176         // success
1177         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1178         return 0;
1179 }
1180
1181 static int tda1004x_read_signal_strength(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * signal)
1182 {
1183         int tmp;
1184         int reg = 0;
1185
1186         dprintk("%s\n", __FUNCTION__);
1187
1188         // determine the register to use
1189         switch(tda_state->fe_type) {
1190         case FE_TYPE_TDA10045H:
1191                 reg = TDA10045H_S_AGC;
1192                 break;
1193
1194         case FE_TYPE_TDA10046H:
1195                 reg = TDA10046H_AGC_IF_LEVEL;
1196                 break;
1197         }
1198
1199         // read it
1200         tmp = tda1004x_read_byte(i2c, tda_state, reg);
1201         if (tmp < 0)
1202                 return -EIO;
1203
1204         // done
1205         *signal = (tmp << 8) | tmp;
1206         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1207         return 0;
1208 }
1209
1210
1211 static int tda1004x_read_snr(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * snr)
1212 {
1213         int tmp;
1214
1215         dprintk("%s\n", __FUNCTION__);
1216
1217         // read it
1218         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_SNR);
1219         if (tmp < 0)
1220                 return -EIO;
1221         if (tmp) {
1222                 tmp = 255 - tmp;
1223         }
1224
1225         // done
1226         *snr = ((tmp << 8) | tmp);
1227         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1228         return 0;
1229 }
1230
1231 static int tda1004x_read_ucblocks(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ucblocks)
1232 {
1233         int tmp;
1234         int tmp2;
1235         int counter;
1236
1237         dprintk("%s\n", __FUNCTION__);
1238
1239         // read the UCBLOCKS and reset
1240         counter = 0;
1241         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1242         if (tmp < 0)
1243                 return -EIO;
1244         tmp &= 0x7f;
1245         while (counter++ < 5) {
1246                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1247                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1248                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1249
1250                 tmp2 = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1251                 if (tmp2 < 0)
1252                         return -EIO;
1253                 tmp2 &= 0x7f;
1254                 if ((tmp2 < tmp) || (tmp2 == 0))
1255                         break;
1256         }
1257
1258         // done
1259         if (tmp != 0x7f) {
1260                 *ucblocks = tmp;
1261         } else {
1262                 *ucblocks = 0xffffffff;
1263         }
1264         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1265         return 0;
1266 }
1267
1268 static int tda1004x_read_ber(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ber)
1269 {
1270         int tmp;
1271
1272         dprintk("%s\n", __FUNCTION__);
1273
1274         // read it in
1275         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1276         if (tmp < 0) return -EIO;
1277         *ber = tmp << 1;
1278         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1279         if (tmp < 0) return -EIO;
1280         *ber |= (tmp << 9);
1281         tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1282
1283         // done
1284         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1285         return 0;
1286 }
1287
1288 static int tda1004x_sleep(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state)
1289 {
1290         switch(tda_state->fe_type) {
1291         case FE_TYPE_TDA10045H:
1292                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0x10);
1293                 break;
1294
1295         case FE_TYPE_TDA10046H:
1296                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 1);
1297                 break;
1298         }
1299
1300         return 0;
1301 }
1302
1303
1304 static int tda1004x_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
1305 {
1306         int status = 0;
1307         struct dvb_i2c_bus *i2c = fe->i2c;
1308         struct tda1004x_state *tda_state = (struct tda1004x_state *) fe->data;
1309
1310         dprintk("%s: cmd=0x%x\n", __FUNCTION__, cmd);
1311
1312         switch (cmd) {
1313         case FE_GET_INFO:
1314                 switch(tda_state->fe_type) {
1315                 case FE_TYPE_TDA10045H:
1316                         memcpy(arg, &tda10045h_info, sizeof(struct dvb_frontend_info));
1317                         break;
1318
1319                 case FE_TYPE_TDA10046H:
1320                         memcpy(arg, &tda10046h_info, sizeof(struct dvb_frontend_info));
1321                         break;
1322                 }
1323                 break;
1324
1325         case FE_READ_STATUS:
1326                 return tda1004x_read_status(i2c, tda_state, (fe_status_t *) arg);
1327
1328         case FE_READ_BER:
1329                 return tda1004x_read_ber(i2c, tda_state, (u32 *) arg);
1330
1331         case FE_READ_SIGNAL_STRENGTH:
1332                 return tda1004x_read_signal_strength(i2c, tda_state, (u16 *) arg);
1333
1334         case FE_READ_SNR:
1335                 return tda1004x_read_snr(i2c, tda_state, (u16 *) arg);
1336
1337         case FE_READ_UNCORRECTED_BLOCKS:
1338                 return tda1004x_read_ucblocks(i2c, tda_state, (u32 *) arg);
1339
1340         case FE_SET_FRONTEND:
1341                 return tda1004x_set_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1342
1343         case FE_GET_FRONTEND:
1344                 return tda1004x_get_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1345
1346         case FE_SLEEP:
1347                 tda_state->initialised = 0;
1348                 return tda1004x_sleep(i2c, tda_state);
1349
1350         case FE_INIT:
1351
1352                 // don't bother reinitialising
1353                 if (tda_state->initialised)
1354                         return 0;
1355
1356                 // OK, perform initialisation
1357                 switch(tda_state->fe_type) {
1358                 case FE_TYPE_TDA10045H:
1359                         status = tda10045h_init(i2c, tda_state);
1360                         break;
1361
1362                 case FE_TYPE_TDA10046H:
1363                         status = tda10046h_init(i2c, tda_state);
1364                         break;
1365                 }
1366                 if (status == 0)
1367                         tda_state->initialised = 1;
1368                 return status;
1369
1370         case FE_GET_TUNE_SETTINGS:
1371         {
1372                 struct dvb_frontend_tune_settings* fesettings = (struct dvb_frontend_tune_settings*) arg;
1373                 fesettings->min_delay_ms = 800;
1374                 fesettings->step_size = 166667;
1375                 fesettings->max_drift = 166667*2;
1376                 return 0;
1377         }
1378
1379         default:
1380                 return -EOPNOTSUPP;
1381         }
1382
1383         return 0;
1384 }
1385
1386
1387 static int tda1004x_attach(struct dvb_i2c_bus *i2c, void **data)
1388 {
1389         int tda1004x_address = -1;
1390         int tuner_address = -1;
1391         int fe_type = -1;
1392         int tuner_type = -1;
1393         struct tda1004x_state tda_state;
1394         struct tda1004x_state* ptda_state;
1395         struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=0, .len=0 };
1396         static u8 td1344_init[] = { 0x0b, 0xf5, 0x88, 0xab };
1397         static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
1398         static u8 td1316_init_tda10046h[] = { 0x0b, 0xf5, 0x80, 0xab };
1399         int status;
1400
1401         dprintk("%s\n", __FUNCTION__);
1402
1403         // probe for tda10045h
1404         if (tda1004x_address == -1) {
1405                 tda_state.tda1004x_address = 0x08;
1406         if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x25) {
1407                         tda1004x_address = 0x08;
1408                         fe_type = FE_TYPE_TDA10045H;
1409                 printk("tda1004x: Detected Philips TDA10045H.\n");
1410         }
1411         }
1412
1413         // probe for tda10046h
1414         if (tda1004x_address == -1) {
1415                 tda_state.tda1004x_address = 0x08;
1416                 if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x46) {
1417                         tda1004x_address = 0x08;
1418                         fe_type = FE_TYPE_TDA10046H;
1419                         printk("tda1004x: Detected Philips TDA10046H.\n");
1420                 }
1421         }
1422
1423         // did we find a frontend?
1424         if (tda1004x_address == -1) {
1425                 return -ENODEV;
1426         }
1427
1428         // enable access to the tuner
1429         tda1004x_enable_tuner_i2c(i2c, &tda_state);
1430
1431         // check for a TD1344 first
1432         if (tuner_address == -1) {
1433                 tuner_msg.addr = 0x61;
1434         tuner_msg.buf = td1344_init;
1435         tuner_msg.len = sizeof(td1344_init);
1436         if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1437                 dvb_delay(1);
1438                         tuner_address = 0x61;
1439                         tuner_type = TUNER_TYPE_TD1344;
1440                         printk("tda1004x: Detected Philips TD1344 tuner.\n");
1441                 }
1442         }
1443
1444         // OK, try a TD1316 on address 0x63
1445         if (tuner_address == -1) {
1446                 tuner_msg.addr = 0x63;
1447                 tuner_msg.buf = td1316_init;
1448                 tuner_msg.len = sizeof(td1316_init);
1449                 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1450                         dvb_delay(1);
1451                         tuner_address = 0x63;
1452                         tuner_type = TUNER_TYPE_TD1316;
1453                         printk("tda1004x: Detected Philips TD1316 tuner.\n");
1454                 }
1455         }
1456
1457         // OK, TD1316 again, on address 0x60 (TDA10046H)
1458         if (tuner_address == -1) {
1459                 tuner_msg.addr = 0x60;
1460                 tuner_msg.buf = td1316_init_tda10046h;
1461                 tuner_msg.len = sizeof(td1316_init_tda10046h);
1462                 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1463                         dvb_delay(1);
1464                         tuner_address = 0x60;
1465                         tuner_type = TUNER_TYPE_TD1316;
1466                         printk("tda1004x: Detected Philips TD1316 tuner.\n");
1467                 }
1468         }
1469         tda1004x_disable_tuner_i2c(i2c, &tda_state);
1470
1471         // did we find a tuner?
1472         if (tuner_address == -1) {
1473                 printk("tda1004x: Detected, but with unknown tuner.\n");
1474                 return -ENODEV;
1475         }
1476
1477         // create state
1478         tda_state.tda1004x_address = tda1004x_address;
1479         tda_state.fe_type = fe_type;
1480         tda_state.tuner_address = tuner_address;
1481         tda_state.tuner_type = tuner_type;
1482         tda_state.initialised = 0;
1483
1484         // upload firmware
1485         if ((status = tda1004x_fwupload(i2c, &tda_state)) != 0) return status;
1486
1487         // create the real state we'll be passing about
1488         if ((ptda_state = (struct tda1004x_state*) kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL)) == NULL) {
1489                 return -ENOMEM;
1490         }
1491         memcpy(ptda_state, &tda_state, sizeof(struct tda1004x_state));
1492         *data = ptda_state;
1493
1494         // register
1495         switch(tda_state.fe_type) {
1496         case FE_TYPE_TDA10045H:
1497                 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10045h_info);
1498
1499         case FE_TYPE_TDA10046H:
1500                 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10046h_info);
1501         }
1502
1503         // should not get here
1504         return -EINVAL;
1505 }
1506
1507
1508 static
1509 void tda1004x_detach(struct dvb_i2c_bus *i2c, void *data)
1510 {
1511         dprintk("%s\n", __FUNCTION__);
1512
1513         kfree(data);
1514         dvb_unregister_frontend(tda1004x_ioctl, i2c);
1515 }
1516
1517
1518 static
1519 int __init init_tda1004x(void)
1520 {
1521         return dvb_register_i2c_device(THIS_MODULE, tda1004x_attach, tda1004x_detach);
1522 }
1523
1524
1525 static
1526 void __exit exit_tda1004x(void)
1527 {
1528         dvb_unregister_i2c_device(tda1004x_attach);
1529 }
1530
1531 module_init(init_tda1004x);
1532 module_exit(exit_tda1004x);
1533
1534 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Frontend");
1535 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1536 MODULE_LICENSE("GPL");
1537
1538 MODULE_PARM(tda1004x_debug, "i");
1539 MODULE_PARM_DESC(tda1004x_debug, "enable verbose debug messages");
1540
1541 MODULE_PARM(tda1004x_firmware, "s");
1542 MODULE_PARM_DESC(tda1004x_firmware, "Where to find the firmware file");