drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware.
  27  */
  28 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  29 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  30
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include "dvb_frontend.h"
  36 #include "tda1004x.h"
  37
  38 enum tda1004x_demod {
  39         TDA1004X_DEMOD_TDA10045,
  40         TDA1004X_DEMOD_TDA10046,
  41 };
  42
  43 struct tda1004x_state {
  44         struct i2c_adapter* i2c;
  45         struct dvb_frontend_ops ops;
  46         const struct tda1004x_config* config;
  47         struct dvb_frontend frontend;
  48
  49         /* private demod data */
  50         u8 initialised;
  51         enum tda1004x_demod demod_type;
  52         u8 fw_version;
  53 };
  54
  55
  56 static int debug;
  57 #define dprintk(args...) \
  58         do { \
  59                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  60         } while (0)
  61
  62 #define TDA1004X_CHIPID          0x00
  63 #define TDA1004X_AUTO            0x01
  64 #define TDA1004X_IN_CONF1        0x02
  65 #define TDA1004X_IN_CONF2        0x03
  66 #define TDA1004X_OUT_CONF1       0x04
  67 #define TDA1004X_OUT_CONF2       0x05
  68 #define TDA1004X_STATUS_CD       0x06
  69 #define TDA1004X_CONFC4          0x07
  70 #define TDA1004X_DSSPARE2        0x0C
  71 #define TDA10045H_CODE_IN        0x0D
  72 #define TDA10045H_FWPAGE         0x0E
  73 #define TDA1004X_SCAN_CPT        0x10
  74 #define TDA1004X_DSP_CMD         0x11
  75 #define TDA1004X_DSP_ARG         0x12
  76 #define TDA1004X_DSP_DATA1       0x13
  77 #define TDA1004X_DSP_DATA2       0x14
  78 #define TDA1004X_CONFADC1        0x15
  79 #define TDA1004X_CONFC1          0x16
  80 #define TDA10045H_S_AGC          0x1a
  81 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  82 #define TDA1004X_SNR             0x1c
  83 #define TDA1004X_CONF_TS1        0x1e
  84 #define TDA1004X_CONF_TS2        0x1f
  85 #define TDA1004X_CBER_RESET      0x20
  86 #define TDA1004X_CBER_MSB        0x21
  87 #define TDA1004X_CBER_LSB        0x22
  88 #define TDA1004X_CVBER_LUT       0x23
  89 #define TDA1004X_VBER_MSB        0x24
  90 #define TDA1004X_VBER_MID        0x25
  91 #define TDA1004X_VBER_LSB        0x26
  92 #define TDA1004X_UNCOR           0x27
  93
  94 #define TDA10045H_CONFPLL_P      0x2D
  95 #define TDA10045H_CONFPLL_M_MSB  0x2E
  96 #define TDA10045H_CONFPLL_M_LSB  0x2F
  97 #define TDA10045H_CONFPLL_N      0x30
  98
  99 #define TDA10046H_CONFPLL1       0x2D
 100 #define TDA10046H_CONFPLL2       0x2F
 101 #define TDA10046H_CONFPLL3       0x30
 102 #define TDA10046H_TIME_WREF1     0x31
 103 #define TDA10046H_TIME_WREF2     0x32
 104 #define TDA10046H_TIME_WREF3     0x33
 105 #define TDA10046H_TIME_WREF4     0x34
 106 #define TDA10046H_TIME_WREF5     0x35
 107
 108 #define TDA10045H_UNSURW_MSB     0x31
 109 #define TDA10045H_UNSURW_LSB     0x32
 110 #define TDA10045H_WREF_MSB       0x33
 111 #define TDA10045H_WREF_MID       0x34
 112 #define TDA10045H_WREF_LSB       0x35
 113 #define TDA10045H_MUXOUT         0x36
 114 #define TDA1004X_CONFADC2        0x37
 115
 116 #define TDA10045H_IOFFSET        0x38
 117
 118 #define TDA10046H_CONF_TRISTATE1 0x3B
 119 #define TDA10046H_CONF_TRISTATE2 0x3C
 120 #define TDA10046H_CONF_POLARITY  0x3D
 121 #define TDA10046H_FREQ_OFFSET    0x3E
 122 #define TDA10046H_GPIO_OUT_SEL   0x41
 123 #define TDA10046H_GPIO_SELECT    0x42
 124 #define TDA10046H_AGC_CONF       0x43
 125 #define TDA10046H_AGC_GAINS      0x46
 126 #define TDA10046H_AGC_TUN_MIN    0x47
 127 #define TDA10046H_AGC_TUN_MAX    0x48
 128 #define TDA10046H_AGC_IF_MIN     0x49
 129 #define TDA10046H_AGC_IF_MAX     0x4A
 130
 131 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 132 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 133
 134 #define TDA10046H_CVBER_CTRL     0x4F
 135 #define TDA10046H_AGC_IF_LEVEL   0x52
 136 #define TDA10046H_CODE_CPT       0x57
 137 #define TDA10046H_CODE_IN        0x58
 138
 139
 140 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 141 {
 142         int ret;
 143         u8 buf[] = { reg, data };
 144         struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
 145
 146         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 147
 148         msg.addr = state->config->demod_address;
 149         ret = i2c_transfer(state->i2c, &msg, 1);
 150
 151         if (ret != 1)
 152                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 153                         __FUNCTION__, reg, data, ret);
 154
 155         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 156                 reg, data, ret);
 157         return (ret != 1) ? -1 : 0;
 158 }
 159
 160 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 161 {
 162         int ret;
 163         u8 b0[] = { reg };
 164         u8 b1[] = { 0 };
 165         struct i2c_msg msg[] = {{ .flags = 0, .buf = b0, .len = 1 },
 166                                 { .flags = I2C_M_RD, .buf = b1, .len = 1 }};
 167
 168         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 169
 170         msg[0].addr = state->config->demod_address;
 171         msg[1].addr = state->config->demod_address;
 172         ret = i2c_transfer(state->i2c, msg, 2);
 173
 174         if (ret != 2) {
 175                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 176                         ret);
 177                 return -1;
 178         }
 179
 180         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 181                 reg, b1[0], ret);
 182         return b1[0];
 183 }
 184
 185 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 186 {
 187         int val;
 188         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 189                 mask, data);
 190
 191         // read a byte and check
 192         val = tda1004x_read_byte(state, reg);
 193         if (val < 0)
 194                 return val;
 195
 196         // mask if off
 197         val = val & ~mask;
 198         val |= data & 0xff;
 199
 200         // write it out again
 201         return tda1004x_write_byteI(state, reg, val);
 202 }
 203
 204 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 205 {
 206         int i;
 207         int result;
 208
 209         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 210
 211         result = 0;
 212         for (i = 0; i < len; i++) {
 213                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 214                 if (result != 0)
 215                         break;
 216         }
 217
 218         return result;
 219 }
 220
 221 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 222 {
 223         int result;
 224         dprintk("%s\n", __FUNCTION__);
 225
 226         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 227         msleep(1);
 228         return result;
 229 }
 230
 231 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 232 {
 233         dprintk("%s\n", __FUNCTION__);
 234
 235         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 236 }
 237
 238 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 239                                    fe_bandwidth_t bandwidth)
 240 {
 241         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 242         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 243         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 244
 245         switch (bandwidth) {
 246         case BANDWIDTH_6_MHZ:
 247                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 248                 break;
 249
 250         case BANDWIDTH_7_MHZ:
 251                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 252                 break;
 253
 254         case BANDWIDTH_8_MHZ:
 255                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 256                 break;
 257
 258         default:
 259                 return -EINVAL;
 260         }
 261
 262         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 263
 264         return 0;
 265 }
 266
 267 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 268                                    fe_bandwidth_t bandwidth)
 269 {
 270         static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
 271         static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
 272         static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
 273
 274         switch (bandwidth) {
 275         case BANDWIDTH_6_MHZ:
 276                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 277                 break;
 278
 279         case BANDWIDTH_7_MHZ:
 280                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 281                 break;
 282
 283         case BANDWIDTH_8_MHZ:
 284                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 285                 break;
 286
 287         default:
 288                 return -EINVAL;
 289         }
 290
 291         return 0;
 292 }
 293
 294 static int tda1004x_do_upload(struct tda1004x_state *state,
 295                               unsigned char *mem, unsigned int len,
 296                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 297 {
 298         u8 buf[65];
 299         struct i2c_msg fw_msg = { .flags = 0, .buf = buf, .len = 0 };
 300         int tx_size;
 301         int pos = 0;
 302
 303         /* clear code counter */
 304         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 305         fw_msg.addr = state->config->demod_address;
 306
 307         buf[0] = dspCodeInReg;
 308         while (pos != len) {
 309                 // work out how much to send this time
 310                 tx_size = len - pos;
 311                 if (tx_size > 0x10)
 312                         tx_size = 0x10;
 313
 314                 // send the chunk
 315                 memcpy(buf + 1, mem + pos, tx_size);
 316                 fw_msg.len = tx_size + 1;
 317                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 318                         printk("tda1004x: Error during firmware upload\n");
 319                         return -EIO;
 320                 }
 321                 pos += tx_size;
 322
 323                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
 324         }
 325
 326         return 0;
 327 }
 328
 329 static int tda1004x_check_upload_ok(struct tda1004x_state *state, u8 dspVersion)
 330 {
 331         u8 data1, data2;
 332
 333         // check upload was OK
 334         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 335         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 336
 337         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 338         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 339         if ((data1 != 0x67) || (data2 != dspVersion))
 340                 return -EIO;
 341
 342         return 0;
 343 }
 344
 345 static int tda10045_fwupload(struct dvb_frontend* fe)
 346 {
 347         struct tda1004x_state* state = fe->demodulator_priv;
 348         int ret;
 349         const struct firmware *fw;
 350
 351         /* don't re-upload unless necessary */
 352         if (tda1004x_check_upload_ok(state, 0x2c) == 0)
 353                 return 0;
 354
 355         /* request the firmware, this will block until someone uploads it */
 356         printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10045_DEFAULT_FIRMWARE);
 357         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 358         if (ret) {
 359                 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
 360                 return ret;
 361         }
 362
 363         /* reset chip */
 364         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 365         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 366         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 367         msleep(10);
 368
 369         /* set parameters */
 370         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 371
 372         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 373         if (ret)
 374                 return ret;
 375         printk("tda1004x: firmware upload complete\n");
 376
 377         /* wait for DSP to initialise */
 378         /* DSPREADY doesn't seem to work on the TDA10045H */
 379         msleep(100);
 380
 381         return tda1004x_check_upload_ok(state, 0x2c);
 382 }
 383
 384 static int tda10046_get_fw_version(struct tda1004x_state *state,
 385                                    const struct firmware *fw)
 386 {
 387         const unsigned char pattern[] = { 0x67, 0x00, 0x50, 0x62, 0x5e, 0x18, 0x67 };
 388         unsigned int i;
 389
 390         /* area guessed from firmware v20, v21 and v25 */
 391         for (i = 0x660; i < 0x700; i++) {
 392                 if (!memcmp(&fw->data[i], pattern, sizeof(pattern))) {
 393                         state->fw_version = fw->data[i + sizeof(pattern)];
 394                         printk(KERN_INFO "tda1004x: using firmware v%02x\n",
 395                                         state->fw_version);
 396                         return 0;
 397                 }
 398         }
 399
 400         return -EINVAL;
 401 }
 402
 403 static int tda10046_fwupload(struct dvb_frontend* fe)
 404 {
 405         struct tda1004x_state* state = fe->demodulator_priv;
 406         unsigned long timeout;
 407         int ret;
 408         const struct firmware *fw;
 409
 410         /* reset + wake up chip */
 411         tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0);
 412         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 413         msleep(100);
 414
 415         /* don't re-upload unless necessary */
 416         if (tda1004x_check_upload_ok(state, state->fw_version) == 0)
 417                 return 0;
 418
 419         /* request the firmware, this will block until someone uploads it */
 420         printk("tda1004x: waiting for firmware upload (%s)...\n", TDA10046_DEFAULT_FIRMWARE);
 421         ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 422         if (ret) {
 423                 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
 424                 return ret;
 425         }
 426
 427         if (fw->size < 24478) { /* size of firmware v20, which is the smallest of v20, v21 and v25 */
 428                 printk("tda1004x: firmware file seems to be too small (%d bytes)\n", fw->size);
 429                 return -EINVAL;
 430         }
 431
 432         ret = tda10046_get_fw_version(state, fw);
 433         if (ret < 0) {
 434                 printk("tda1004x: unable to find firmware version\n");
 435                 return ret;
 436         }
 437
 438         /* set parameters */
 439         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10);
 440         tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c);
 441         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
 442         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 443         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
 444         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 445
 446         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 447         if (ret)
 448                 return ret;
 449         printk("tda1004x: firmware upload complete\n");
 450
 451         /* wait for DSP to initialise */
 452         timeout = jiffies + HZ;
 453         while (!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 454                 if (time_after(jiffies, timeout)) {
 455                         printk("tda1004x: DSP failed to initialised.\n");
 456                         return -EIO;
 457                 }
 458                 msleep(1);
 459         }
 460
 461         return tda1004x_check_upload_ok(state, state->fw_version);
 462 }
 463
 464 static int tda1004x_encode_fec(int fec)
 465 {
 466         // convert known FEC values
 467         switch (fec) {
 468         case FEC_1_2:
 469                 return 0;
 470         case FEC_2_3:
 471                 return 1;
 472         case FEC_3_4:
 473                 return 2;
 474         case FEC_5_6:
 475                 return 3;
 476         case FEC_7_8:
 477                 return 4;
 478         }
 479
 480         // unsupported
 481         return -EINVAL;
 482 }
 483
 484 static int tda1004x_decode_fec(int tdafec)
 485 {
 486         // convert known FEC values
 487         switch (tdafec) {
 488         case 0:
 489                 return FEC_1_2;
 490         case 1:
 491                 return FEC_2_3;
 492         case 2:
 493                 return FEC_3_4;
 494         case 3:
 495                 return FEC_5_6;
 496         case 4:
 497                 return FEC_7_8;
 498         }
 499
 500         // unsupported
 501         return -1;
 502 }
 503
 504 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
 505 {
 506         struct tda1004x_state* state = fe->demodulator_priv;
 507
 508         return tda1004x_write_byteI(state, reg, data);
 509 }
 510
 511 static int tda10045_init(struct dvb_frontend* fe)
 512 {
 513         struct tda1004x_state* state = fe->demodulator_priv;
 514
 515         dprintk("%s\n", __FUNCTION__);
 516
 517         if (state->initialised)
 518                 return 0;
 519
 520         if (tda10045_fwupload(fe)) {
 521                 printk("tda1004x: firmware upload failed\n");
 522                 return -EIO;
 523         }
 524
 525         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 526
 527         // Init the PLL
 528         if (state->config->pll_init) {
 529                 tda1004x_enable_tuner_i2c(state);
 530                 state->config->pll_init(fe);
 531                 tda1004x_disable_tuner_i2c(state);
 532         }
 533
 534         // tda setup
 535         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 536         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 537         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 538         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 539         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 540         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 541         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 542         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 543         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 544         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 545         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 546
 547         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 548
 549         state->initialised = 1;
 550         return 0;
 551 }
 552
 553 static int tda10046_init(struct dvb_frontend* fe)
 554 {
 555         struct tda1004x_state* state = fe->demodulator_priv;
 556         dprintk("%s\n", __FUNCTION__);
 557
 558         if (state->initialised)
 559                 return 0;
 560
 561         if (tda10046_fwupload(fe)) {
 562                 printk("tda1004x: firmware upload failed\n");
 563                 return -EIO;
 564         }
 565
 566         tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0); // wake up the chip
 567
 568         // Init the PLL
 569         if (state->config->pll_init) {
 570                 tda1004x_enable_tuner_i2c(state);
 571                 state->config->pll_init(fe);
 572                 tda1004x_disable_tuner_i2c(state);
 573         }
 574
 575         // tda setup
 576         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 577         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0x40);
 578         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 579         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
 580         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
 581         tda1004x_write_byteI(state, TDA10046H_CONFPLL3, state->config->n_i2c); // PLL P = N = 0
 582         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
 583         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
 584         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
 585         tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0); // AGC setup
 586         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
 587         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 588         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 589         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 590         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 591         tda1004x_write_mask(state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
 592         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
 593         tda1004x_write_mask(state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
 594         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 595         tda1004x_write_mask(state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
 596         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
 597         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
 598         tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
 599         tda1004x_write_mask(state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
 600         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 601
 602         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 603
 604         state->initialised = 1;
 605         return 0;
 606 }
 607
 608 static int tda1004x_set_fe(struct dvb_frontend* fe,
 609                            struct dvb_frontend_parameters *fe_params)
 610 {
 611         struct tda1004x_state* state = fe->demodulator_priv;
 612         int tmp;
 613         int inversion;
 614
 615         dprintk("%s\n", __FUNCTION__);
 616
 617         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 618                 // setup auto offset
 619                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 620                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 621                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 622
 623                 // disable agc_conf[2]
 624                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 625         }
 626
 627         // set frequency
 628         tda1004x_enable_tuner_i2c(state);
 629         state->config->pll_set(fe, fe_params);
 630         tda1004x_disable_tuner_i2c(state);
 631
 632         if (state->demod_type == TDA1004X_DEMOD_TDA10046)
 633                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 4);
 634
 635         // Hardcoded to use auto as much as possible on the TDA10045 as it
 636         // is very unreliable if AUTO mode is _not_ used.
 637         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 638                 fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 639                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 640                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 641         }
 642
 643         // Set standard params.. or put them to auto
 644         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 645             (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 646             (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 647             (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 648                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 649                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 650                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 651                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 652         } else {
 653                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 654
 655                 // set HP FEC
 656                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 657                 if (tmp < 0)
 658                         return tmp;
 659                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 660
 661                 // set LP FEC
 662                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 663                 if (tmp < 0)
 664                         return tmp;
 665                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 666
 667                 // set constellation
 668                 switch (fe_params->u.ofdm.constellation) {
 669                 case QPSK:
 670                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 671                         break;
 672
 673                 case QAM_16:
 674                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 675                         break;
 676
 677                 case QAM_64:
 678                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 679                         break;
 680
 681                 default:
 682                         return -EINVAL;
 683                 }
 684
 685                 // set hierarchy
 686                 switch (fe_params->u.ofdm.hierarchy_information) {
 687                 case HIERARCHY_NONE:
 688                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 689                         break;
 690
 691                 case HIERARCHY_1:
 692                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 693                         break;
 694
 695                 case HIERARCHY_2:
 696                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 697                         break;
 698
 699                 case HIERARCHY_4:
 700                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 701                         break;
 702
 703                 default:
 704                         return -EINVAL;
 705                 }
 706         }
 707
 708         // set bandwidth
 709         switch (state->demod_type) {
 710         case TDA1004X_DEMOD_TDA10045:
 711                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 712                 break;
 713
 714         case TDA1004X_DEMOD_TDA10046:
 715                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 716                 break;
 717         }
 718
 719         // set inversion
 720         inversion = fe_params->inversion;
 721         if (state->config->invert)
 722                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 723         switch (inversion) {
 724         case INVERSION_OFF:
 725                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 726                 break;
 727
 728         case INVERSION_ON:
 729                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 730                 break;
 731
 732         default:
 733                 return -EINVAL;
 734         }
 735
 736         // set guard interval
 737         switch (fe_params->u.ofdm.guard_interval) {
 738         case GUARD_INTERVAL_1_32:
 739                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 740                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 741                 break;
 742
 743         case GUARD_INTERVAL_1_16:
 744                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 745                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 746                 break;
 747
 748         case GUARD_INTERVAL_1_8:
 749                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 750                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 751                 break;
 752
 753         case GUARD_INTERVAL_1_4:
 754                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 755                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 756                 break;
 757
 758         case GUARD_INTERVAL_AUTO:
 759                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 760                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 761                 break;
 762
 763         default:
 764                 return -EINVAL;
 765         }
 766
 767         // set transmission mode
 768         switch (fe_params->u.ofdm.transmission_mode) {
 769         case TRANSMISSION_MODE_2K:
 770                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 771                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 772                 break;
 773
 774         case TRANSMISSION_MODE_8K:
 775                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 776                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 777                 break;
 778
 779         case TRANSMISSION_MODE_AUTO:
 780                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 781                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 782                 break;
 783
 784         default:
 785                 return -EINVAL;
 786         }
 787
 788         // start the lock
 789         switch (state->demod_type) {
 790         case TDA1004X_DEMOD_TDA10045:
 791                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 792                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 793                 break;
 794
 795         case TDA1004X_DEMOD_TDA10046:
 796                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 797                 break;
 798         }
 799
 800         msleep(10);
 801
 802         return 0;
 803 }
 804
 805 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 806 {
 807         struct tda1004x_state* state = fe->demodulator_priv;
 808         dprintk("%s\n", __FUNCTION__);
 809
 810         // inversion status
 811         fe_params->inversion = INVERSION_OFF;
 812         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20)
 813                 fe_params->inversion = INVERSION_ON;
 814         if (state->config->invert)
 815                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 816
 817         // bandwidth
 818         switch (state->demod_type) {
 819         case TDA1004X_DEMOD_TDA10045:
 820                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 821                 case 0x14:
 822                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 823                         break;
 824                 case 0xdb:
 825                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 826                         break;
 827                 case 0x4f:
 828                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 829                         break;
 830                 }
 831                 break;
 832
 833         case TDA1004X_DEMOD_TDA10046:
 834                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 835                 case 0x60:
 836                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 837                         break;
 838                 case 0x6e:
 839                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 840                         break;
 841                 case 0x80:
 842                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 843                         break;
 844                 }
 845                 break;
 846         }
 847
 848         // FEC
 849         fe_params->u.ofdm.code_rate_HP =
 850             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 851         fe_params->u.ofdm.code_rate_LP =
 852             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 853
 854         // constellation
 855         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 856         case 0:
 857                 fe_params->u.ofdm.constellation = QPSK;
 858                 break;
 859         case 1:
 860                 fe_params->u.ofdm.constellation = QAM_16;
 861                 break;
 862         case 2:
 863                 fe_params->u.ofdm.constellation = QAM_64;
 864                 break;
 865         }
 866
 867         // transmission mode
 868         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 869         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10)
 870                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 871
 872         // guard interval
 873         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 874         case 0:
 875                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 876                 break;
 877         case 1:
 878                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 879                 break;
 880         case 2:
 881                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 882                 break;
 883         case 3:
 884                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 885                 break;
 886         }
 887
 888         // hierarchy
 889         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 890         case 0:
 891                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 892                 break;
 893         case 1:
 894                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 895                 break;
 896         case 2:
 897                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 898                 break;
 899         case 3:
 900                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
 901                 break;
 902         }
 903
 904         return 0;
 905 }
 906
 907 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
 908 {
 909         struct tda1004x_state* state = fe->demodulator_priv;
 910         int status;
 911         int cber;
 912         int vber;
 913
 914         dprintk("%s\n", __FUNCTION__);
 915
 916         // read status
 917         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 918         if (status == -1)
 919                 return -EIO;
 920
 921         // decode
 922         *fe_status = 0;
 923         if (status & 4)
 924                 *fe_status |= FE_HAS_SIGNAL;
 925         if (status & 2)
 926                 *fe_status |= FE_HAS_CARRIER;
 927         if (status & 8)
 928                 *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 929
 930         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
 931         // is getting anything valid
 932         if (!(*fe_status & FE_HAS_VITERBI)) {
 933                 // read the CBER
 934                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
 935                 if (cber == -1)
 936                         return -EIO;
 937                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
 938                 if (status == -1)
 939                         return -EIO;
 940                 cber |= (status << 8);
 941                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
 942
 943                 if (cber != 65535)
 944                         *fe_status |= FE_HAS_VITERBI;
 945         }
 946
 947         // if we DO have some valid VITERBI output, but don't already have SYNC
 948         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
 949         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
 950                 // read the VBER
 951                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
 952                 if (vber == -1)
 953                         return -EIO;
 954                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
 955                 if (status == -1)
 956                         return -EIO;
 957                 vber |= (status << 8);
 958                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
 959                 if (status == -1)
 960                         return -EIO;
 961                 vber |= ((status << 16) & 0x0f);
 962                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
 963
 964                 // if RS has passed some valid TS packets, then we must be
 965                 // getting some SYNC bytes
 966                 if (vber < 16632)
 967                         *fe_status |= FE_HAS_SYNC;
 968         }
 969
 970         // success
 971         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
 972         return 0;
 973 }
 974
 975 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
 976 {
 977         struct tda1004x_state* state = fe->demodulator_priv;
 978         int tmp;
 979         int reg = 0;
 980
 981         dprintk("%s\n", __FUNCTION__);
 982
 983         // determine the register to use
 984         switch (state->demod_type) {
 985         case TDA1004X_DEMOD_TDA10045:
 986                 reg = TDA10045H_S_AGC;
 987                 break;
 988
 989         case TDA1004X_DEMOD_TDA10046:
 990                 reg = TDA10046H_AGC_IF_LEVEL;
 991                 break;
 992         }
 993
 994         // read it
 995         tmp = tda1004x_read_byte(state, reg);
 996         if (tmp < 0)
 997                 return -EIO;
 998
 999         *signal = (tmp << 8) | tmp;
1000         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1001         return 0;
1002 }
1003
1004 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
1005 {
1006         struct tda1004x_state* state = fe->demodulator_priv;
1007         int tmp;
1008
1009         dprintk("%s\n", __FUNCTION__);
1010
1011         // read it
1012         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
1013         if (tmp < 0)
1014                 return -EIO;
1015         if (tmp)
1016                 tmp = 255 - tmp;
1017
1018         *snr = ((tmp << 8) | tmp);
1019         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1020         return 0;
1021 }
1022
1023 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1024 {
1025         struct tda1004x_state* state = fe->demodulator_priv;
1026         int tmp;
1027         int tmp2;
1028         int counter;
1029
1030         dprintk("%s\n", __FUNCTION__);
1031
1032         // read the UCBLOCKS and reset
1033         counter = 0;
1034         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1035         if (tmp < 0)
1036                 return -EIO;
1037         tmp &= 0x7f;
1038         while (counter++ < 5) {
1039                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1040                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1041                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1042
1043                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1044                 if (tmp2 < 0)
1045                         return -EIO;
1046                 tmp2 &= 0x7f;
1047                 if ((tmp2 < tmp) || (tmp2 == 0))
1048                         break;
1049         }
1050
1051         if (tmp != 0x7f)
1052                 *ucblocks = tmp;
1053         else
1054                 *ucblocks = 0xffffffff;
1055
1056         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1057         return 0;
1058 }
1059
1060 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1061 {
1062         struct tda1004x_state* state = fe->demodulator_priv;
1063         int tmp;
1064
1065         dprintk("%s\n", __FUNCTION__);
1066
1067         // read it in
1068         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1069         if (tmp < 0)
1070                 return -EIO;
1071         *ber = tmp << 1;
1072         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1073         if (tmp < 0)
1074                 return -EIO;
1075         *ber |= (tmp << 9);
1076         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1077
1078         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1079         return 0;
1080 }
1081
1082 static int tda1004x_sleep(struct dvb_frontend* fe)
1083 {
1084         struct tda1004x_state* state = fe->demodulator_priv;
1085
1086         switch (state->demod_type) {
1087         case TDA1004X_DEMOD_TDA10045:
1088                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1089                 break;
1090
1091         case TDA1004X_DEMOD_TDA10046:
1092                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1093                 break;
1094         }
1095         state->initialised = 0;
1096
1097         return 0;
1098 }
1099
1100 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1101 {
1102         fesettings->min_delay_ms = 800;
1103         fesettings->step_size = 166667;
1104         fesettings->max_drift = 166667*2;
1105         return 0;
1106 }
1107
1108 static void tda1004x_release(struct dvb_frontend* fe)
1109 {
1110         struct tda1004x_state *state = fe->demodulator_priv;
1111         kfree(state);
1112 }
1113
1114 static struct dvb_frontend_ops tda10045_ops = {
1115         .info = {
1116                 .name = "Philips TDA10045H DVB-T",
1117                 .type = FE_OFDM,
1118                 .frequency_min = 51000000,
1119                 .frequency_max = 858000000,
1120                 .frequency_stepsize = 166667,
1121                 .caps =
1122                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1123                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1124                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1125                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1126         },
1127
1128         .release = tda1004x_release,
1129
1130         .init = tda10045_init,
1131         .sleep = tda1004x_sleep,
1132
1133         .set_frontend = tda1004x_set_fe,
1134         .get_frontend = tda1004x_get_fe,
1135         .get_tune_settings = tda1004x_get_tune_settings,
1136
1137         .read_status = tda1004x_read_status,
1138         .read_ber = tda1004x_read_ber,
1139         .read_signal_strength = tda1004x_read_signal_strength,
1140         .read_snr = tda1004x_read_snr,
1141         .read_ucblocks = tda1004x_read_ucblocks,
1142 };
1143
1144 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1145                                      struct i2c_adapter* i2c)
1146 {
1147         struct tda1004x_state *state;
1148
1149         /* allocate memory for the internal state */
1150         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1151         if (!state)
1152                 return NULL;
1153
1154         /* setup the state */
1155         state->config = config;
1156         state->i2c = i2c;
1157         memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1158         state->initialised = 0;
1159         state->demod_type = TDA1004X_DEMOD_TDA10045;
1160
1161         /* check if the demod is there */
1162         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) {
1163                 kfree(state);
1164                 return NULL;
1165         }
1166
1167         /* create dvb_frontend */
1168         state->frontend.ops = &state->ops;
1169         state->frontend.demodulator_priv = state;
1170         return &state->frontend;
1171 }
1172
1173 static struct dvb_frontend_ops tda10046_ops = {
1174         .info = {
1175                 .name = "Philips TDA10046H DVB-T",
1176                 .type = FE_OFDM,
1177                 .frequency_min = 51000000,
1178                 .frequency_max = 858000000,
1179                 .frequency_stepsize = 166667,
1180                 .caps =
1181                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1182                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1183                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1184                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1185         },
1186
1187         .release = tda1004x_release,
1188
1189         .init = tda10046_init,
1190         .sleep = tda1004x_sleep,
1191
1192         .set_frontend = tda1004x_set_fe,
1193         .get_frontend = tda1004x_get_fe,
1194         .get_tune_settings = tda1004x_get_tune_settings,
1195
1196         .read_status = tda1004x_read_status,
1197         .read_ber = tda1004x_read_ber,
1198         .read_signal_strength = tda1004x_read_signal_strength,
1199         .read_snr = tda1004x_read_snr,
1200         .read_ucblocks = tda1004x_read_ucblocks,
1201 };
1202
1203 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1204                                      struct i2c_adapter* i2c)
1205 {
1206         struct tda1004x_state *state;
1207
1208         /* allocate memory for the internal state */
1209         state = kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1210         if (!state)
1211                 return NULL;
1212
1213         /* setup the state */
1214         state->config = config;
1215         state->i2c = i2c;
1216         memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1217         state->initialised = 0;
1218         state->demod_type = TDA1004X_DEMOD_TDA10046;
1219         state->fw_version = 0x20;       /* dummy default value */
1220
1221         /* check if the demod is there */
1222         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) {
1223                 kfree(state);
1224                 return NULL;
1225         }
1226
1227         /* create dvb_frontend */
1228         state->frontend.ops = &state->ops;
1229         state->frontend.demodulator_priv = state;
1230         return &state->frontend;
1231 }
1232
1233 module_param(debug, int, 0644);
1234 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1235
1236 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1237 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1238 MODULE_LICENSE("GPL");
1239
1240 EXPORT_SYMBOL(tda10045_attach);
1241 EXPORT_SYMBOL(tda10046_attach);
1242 EXPORT_SYMBOL(tda1004x_write_byte);