drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Demodulator
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22 /*
  23  * This driver needs external firmware. Please use the commands
  24  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10045",
  25  * "<kerneldir>/Documentation/dvb/get_dvb_firmware tda10046" to
  26  * download/extract them, and then copy them to /usr/lib/hotplug/firmware.
  27  */
  28 #define TDA10045_DEFAULT_FIRMWARE "dvb-fe-tda10045.fw"
  29 #define TDA10046_DEFAULT_FIRMWARE "dvb-fe-tda10046.fw"
  30
  31 #include <linux/init.h>
  32 #include <linux/module.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/device.h>
  35 #include "dvb_frontend.h"
  36 #include "tda1004x.h"
  37
  38 #define TDA1004X_DEMOD_TDA10045 0
  39 #define TDA1004X_DEMOD_TDA10046 1
  40
  41
  42 struct tda1004x_state
  43 {
  44         struct i2c_adapter* i2c;
  45
  46         struct dvb_frontend_ops ops;
  47
  48         const struct tda1004x_config* config;
  49
  50         struct dvb_frontend frontend;
  51
  52         /* private demod data */
  53         u8 initialised:1;
  54
  55         u8 demod_type;
  56 };
  57
  58
  59 static int debug;
  60 #define dprintk(args...) \
  61         do { \
  62                 if (debug) printk(KERN_DEBUG "tda1004x: " args); \
  63         } while (0)
  64
  65 #define TDA1004X_CHIPID          0x00
  66 #define TDA1004X_AUTO            0x01
  67 #define TDA1004X_IN_CONF1        0x02
  68 #define TDA1004X_IN_CONF2        0x03
  69 #define TDA1004X_OUT_CONF1       0x04
  70 #define TDA1004X_OUT_CONF2       0x05
  71 #define TDA1004X_STATUS_CD       0x06
  72 #define TDA1004X_CONFC4          0x07
  73 #define TDA1004X_DSSPARE2        0x0C
  74 #define TDA10045H_CODE_IN        0x0D
  75 #define TDA10045H_FWPAGE         0x0E
  76 #define TDA1004X_SCAN_CPT        0x10
  77 #define TDA1004X_DSP_CMD         0x11
  78 #define TDA1004X_DSP_ARG         0x12
  79 #define TDA1004X_DSP_DATA1       0x13
  80 #define TDA1004X_DSP_DATA2       0x14
  81 #define TDA1004X_CONFADC1        0x15
  82 #define TDA1004X_CONFC1          0x16
  83 #define TDA10045H_S_AGC          0x1a
  84 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  85 #define TDA1004X_SNR             0x1c
  86 #define TDA1004X_CONF_TS1        0x1e
  87 #define TDA1004X_CONF_TS2        0x1f
  88 #define TDA1004X_CBER_RESET      0x20
  89 #define TDA1004X_CBER_MSB        0x21
  90 #define TDA1004X_CBER_LSB        0x22
  91 #define TDA1004X_CVBER_LUT       0x23
  92 #define TDA1004X_VBER_MSB        0x24
  93 #define TDA1004X_VBER_MID        0x25
  94 #define TDA1004X_VBER_LSB        0x26
  95 #define TDA1004X_UNCOR           0x27
  96
  97 #define TDA10045H_CONFPLL_P      0x2D
  98 #define TDA10045H_CONFPLL_M_MSB  0x2E
  99 #define TDA10045H_CONFPLL_M_LSB  0x2F
 100 #define TDA10045H_CONFPLL_N      0x30
 101
 102 #define TDA10046H_CONFPLL1       0x2D
 103 #define TDA10046H_CONFPLL2       0x2F
 104 #define TDA10046H_CONFPLL3       0x30
 105 #define TDA10046H_TIME_WREF1     0x31
 106 #define TDA10046H_TIME_WREF2     0x32
 107 #define TDA10046H_TIME_WREF3     0x33
 108 #define TDA10046H_TIME_WREF4     0x34
 109 #define TDA10046H_TIME_WREF5     0x35
 110
 111 #define TDA10045H_UNSURW_MSB     0x31
 112 #define TDA10045H_UNSURW_LSB     0x32
 113 #define TDA10045H_WREF_MSB       0x33
 114 #define TDA10045H_WREF_MID       0x34
 115 #define TDA10045H_WREF_LSB       0x35
 116 #define TDA10045H_MUXOUT         0x36
 117 #define TDA1004X_CONFADC2        0x37
 118
 119 #define TDA10045H_IOFFSET        0x38
 120
 121 #define TDA10046H_CONF_TRISTATE1 0x3B
 122 #define TDA10046H_CONF_TRISTATE2 0x3C
 123 #define TDA10046H_CONF_POLARITY  0x3D
 124 #define TDA10046H_FREQ_OFFSET    0x3E
 125 #define TDA10046H_GPIO_OUT_SEL   0x41
 126 #define TDA10046H_GPIO_SELECT    0x42
 127 #define TDA10046H_AGC_CONF       0x43
 128 #define TDA10046H_AGC_GAINS      0x46
 129 #define TDA10046H_AGC_TUN_MIN    0x47
 130 #define TDA10046H_AGC_TUN_MAX    0x48
 131 #define TDA10046H_AGC_IF_MIN     0x49
 132 #define TDA10046H_AGC_IF_MAX     0x4A
 133
 134 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 135 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 136
 137 #define TDA10046H_CVBER_CTRL     0x4F
 138 #define TDA10046H_AGC_IF_LEVEL   0x52
 139 #define TDA10046H_CODE_CPT       0x57
 140 #define TDA10046H_CODE_IN        0x58
 141
 142
 143 static int tda1004x_write_byteI(struct tda1004x_state *state, int reg, int data)
 144 {
 145         int ret;
 146         u8 buf[] = { reg, data };
 147         struct i2c_msg msg = { .addr=0, .flags=0, .buf=buf, .len=2 };
 148
 149         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 150
 151         msg.addr = state->config->demod_address;
 152         ret = i2c_transfer(state->i2c, &msg, 1);
 153
 154         if (ret != 1)
 155                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 156                         __FUNCTION__, reg, data, ret);
 157
 158         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 159                 reg, data, ret);
 160         return (ret != 1) ? -1 : 0;
 161 }
 162
 163 static int tda1004x_read_byte(struct tda1004x_state *state, int reg)
 164 {
 165         int ret;
 166         u8 b0[] = { reg };
 167         u8 b1[] = { 0 };
 168         struct i2c_msg msg[] = {{ .addr=0, .flags=0, .buf=b0, .len=1},
 169                                 { .addr=0, .flags=I2C_M_RD, .buf=b1, .len = 1}};
 170
 171         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 172
 173         msg[0].addr = state->config->demod_address;
 174         msg[1].addr = state->config->demod_address;
 175         ret = i2c_transfer(state->i2c, msg, 2);
 176
 177         if (ret != 2) {
 178                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 179                         ret);
 180                 return -1;
 181         }
 182
 183         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 184                 reg, b1[0], ret);
 185         return b1[0];
 186 }
 187
 188 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data)
 189 {
 190         int val;
 191         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 192                 mask, data);
 193
 194         // read a byte and check
 195         val = tda1004x_read_byte(state, reg);
 196         if (val < 0)
 197                 return val;
 198
 199         // mask if off
 200         val = val & ~mask;
 201         val |= data & 0xff;
 202
 203         // write it out again
 204         return tda1004x_write_byteI(state, reg, val);
 205 }
 206
 207 static int tda1004x_write_buf(struct tda1004x_state *state, int reg, unsigned char *buf, int len)
 208 {
 209         int i;
 210         int result;
 211
 212         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 213
 214         result = 0;
 215         for (i = 0; i < len; i++) {
 216                 result = tda1004x_write_byteI(state, reg + i, buf[i]);
 217                 if (result != 0)
 218                         break;
 219         }
 220
 221         return result;
 222 }
 223
 224 static int tda1004x_enable_tuner_i2c(struct tda1004x_state *state)
 225 {
 226         int result;
 227         dprintk("%s\n", __FUNCTION__);
 228
 229         result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2);
 230         msleep(1);
 231         return result;
 232 }
 233
 234 static int tda1004x_disable_tuner_i2c(struct tda1004x_state *state)
 235 {
 236         dprintk("%s\n", __FUNCTION__);
 237
 238         return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0);
 239 }
 240
 241 static int tda10045h_set_bandwidth(struct tda1004x_state *state,
 242                                    fe_bandwidth_t bandwidth)
 243 {
 244         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 245         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 246         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 247
 248         switch (bandwidth) {
 249         case BANDWIDTH_6_MHZ:
 250                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 251                 break;
 252
 253         case BANDWIDTH_7_MHZ:
 254                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 255                 break;
 256
 257         case BANDWIDTH_8_MHZ:
 258                 tda1004x_write_buf(state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 259                 break;
 260
 261         default:
 262                 return -EINVAL;
 263         }
 264
 265         tda1004x_write_byteI(state, TDA10045H_IOFFSET, 0);
 266
 267         return 0;
 268 }
 269
 270 static int tda10046h_set_bandwidth(struct tda1004x_state *state,
 271                                    fe_bandwidth_t bandwidth)
 272 {
 273         static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
 274         static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
 275         static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
 276
 277         switch (bandwidth) {
 278         case BANDWIDTH_6_MHZ:
 279                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 280                 break;
 281
 282         case BANDWIDTH_7_MHZ:
 283                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 284                 break;
 285
 286         case BANDWIDTH_8_MHZ:
 287                 tda1004x_write_buf(state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 288                 break;
 289
 290         default:
 291                 return -EINVAL;
 292         }
 293
 294         return 0;
 295 }
 296
 297 static int tda1004x_do_upload(struct tda1004x_state *state,
 298                               unsigned char *mem, unsigned int len,
 299                               u8 dspCodeCounterReg, u8 dspCodeInReg)
 300 {
 301         u8 buf[65];
 302         struct i2c_msg fw_msg = {.addr = 0,.flags = 0,.buf = buf,.len = 0 };
 303         int tx_size;
 304         int pos = 0;
 305
 306         /* clear code counter */
 307         tda1004x_write_byteI(state, dspCodeCounterReg, 0);
 308         fw_msg.addr = state->config->demod_address;
 309
 310         buf[0] = dspCodeInReg;
 311         while (pos != len) {
 312
 313                 // work out how much to send this time
 314                 tx_size = len - pos;
 315                 if (tx_size > 0x10) {
 316                         tx_size = 0x10;
 317                 }
 318
 319                 // send the chunk
 320                 memcpy(buf + 1, mem + pos, tx_size);
 321                 fw_msg.len = tx_size + 1;
 322                 if (i2c_transfer(state->i2c, &fw_msg, 1) != 1) {
 323                         printk("tda1004x: Error during firmware upload\n");
 324                         return -EIO;
 325                 }
 326                 pos += tx_size;
 327
 328                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, pos);
 329         }
 330         return 0;
 331 }
 332
 333 static int tda1004x_check_upload_ok(struct tda1004x_state *state, u8 dspVersion)
 334 {
 335         u8 data1, data2;
 336
 337         // check upload was OK
 338         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 339         tda1004x_write_byteI(state, TDA1004X_DSP_CMD, 0x67);
 340
 341         data1 = tda1004x_read_byte(state, TDA1004X_DSP_DATA1);
 342         data2 = tda1004x_read_byte(state, TDA1004X_DSP_DATA2);
 343         if (data1 != 0x67 || data2 != dspVersion) {
 344                 return -EIO;
 345         }
 346
 347         return 0;
 348 }
 349
 350
 351 static int tda10045_fwupload(struct dvb_frontend* fe)
 352 {
 353         struct tda1004x_state* state = fe->demodulator_priv;
 354         int ret;
 355         const struct firmware *fw;
 356
 357
 358         /* don't re-upload unless necessary */
 359         if (tda1004x_check_upload_ok(state, 0x2c) == 0) return 0;
 360
 361         /* request the firmware, this will block until someone uploads it */
 362         printk("tda1004x: waiting for firmware upload...\n");
 363         ret = state->config->request_firmware(fe, &fw, TDA10045_DEFAULT_FIRMWARE);
 364         if (ret) {
 365                 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
 366                 return ret;
 367         }
 368
 369         /* reset chip */
 370         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0);
 371         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 372         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 373         msleep(10);
 374
 375         /* set parameters */
 376         tda10045h_set_bandwidth(state, BANDWIDTH_8_MHZ);
 377
 378         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10045H_FWPAGE, TDA10045H_CODE_IN);
 379         if (ret)
 380                 return ret;
 381
 382         /* wait for DSP to initialise */
 383         /* DSPREADY doesn't seem to work on the TDA10045H */
 384         msleep(100);
 385
 386         return tda1004x_check_upload_ok(state, 0x2c);
 387 }
 388
 389 static int tda10046_fwupload(struct dvb_frontend* fe)
 390 {
 391         struct tda1004x_state* state = fe->demodulator_priv;
 392         unsigned long timeout;
 393         int ret;
 394         const struct firmware *fw;
 395
 396         /* reset + wake up chip */
 397         tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0);
 398         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0);
 399         msleep(100);
 400
 401         /* don't re-upload unless necessary */
 402         if (tda1004x_check_upload_ok(state, 0x20) == 0) return 0;
 403
 404         /* request the firmware, this will block until someone uploads it */
 405         printk("tda1004x: waiting for firmware upload...\n");
 406         ret = state->config->request_firmware(fe, &fw, TDA10046_DEFAULT_FIRMWARE);
 407         if (ret) {
 408                 printk("tda1004x: no firmware upload (timeout or file not found?)\n");
 409                 return ret;
 410         }
 411
 412         /* set parameters */
 413         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10);
 414         tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0);
 415         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99);
 416         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 417         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
 418         tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 419
 420         ret = tda1004x_do_upload(state, fw->data, fw->size, TDA10046H_CODE_CPT, TDA10046H_CODE_IN);
 421         if (ret)
 422                 return ret;
 423
 424         /* wait for DSP to initialise */
 425         timeout = jiffies + HZ;
 426         while(!(tda1004x_read_byte(state, TDA1004X_STATUS_CD) & 0x20)) {
 427                 if (time_after(jiffies, timeout)) {
 428                         printk("tda1004x: DSP failed to initialised.\n");
 429                         return -EIO;
 430                 }
 431                 msleep(1);
 432         }
 433
 434         return tda1004x_check_upload_ok(state, 0x20);
 435 }
 436
 437 static int tda1004x_encode_fec(int fec)
 438 {
 439         // convert known FEC values
 440         switch (fec) {
 441         case FEC_1_2:
 442                 return 0;
 443         case FEC_2_3:
 444                 return 1;
 445         case FEC_3_4:
 446                 return 2;
 447         case FEC_5_6:
 448                 return 3;
 449         case FEC_7_8:
 450                 return 4;
 451         }
 452
 453         // unsupported
 454         return -EINVAL;
 455 }
 456
 457 static int tda1004x_decode_fec(int tdafec)
 458 {
 459         // convert known FEC values
 460         switch (tdafec) {
 461         case 0:
 462                 return FEC_1_2;
 463         case 1:
 464                 return FEC_2_3;
 465         case 2:
 466                 return FEC_3_4;
 467         case 3:
 468                 return FEC_5_6;
 469         case 4:
 470                 return FEC_7_8;
 471         }
 472
 473         // unsupported
 474         return -1;
 475 }
 476
 477
 478
 479
 480
 481
 482
 483
 484
 485
 486
 487
 488
 489
 490
 491
 492
 493
 494 int tda1004x_write_byte(struct dvb_frontend* fe, int reg, int data)
 495 {
 496         struct tda1004x_state* state = fe->demodulator_priv;
 497
 498         return tda1004x_write_byteI(state, reg, data);
 499                 }
 500
 501 static int tda10045_init(struct dvb_frontend* fe)
 502 {
 503         struct tda1004x_state* state = fe->demodulator_priv;
 504
 505         dprintk("%s\n", __FUNCTION__);
 506
 507         if (state->initialised) return 0;
 508
 509         if (tda10045_fwupload(fe)) {
 510                 printk("tda1004x: firmware upload failed\n");
 511                 return -EIO;
 512                 }
 513
 514         tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 515
 516         // Init the PLL
 517         if (state->config->pll_init) {
 518                 tda1004x_enable_tuner_i2c(state);
 519                 state->config->pll_init(fe);
 520                 tda1004x_disable_tuner_i2c(state);
 521         }
 522
 523         // tda setup
 524         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 525         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 526         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal
 527         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 528         tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 529         tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 530         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 531         tda1004x_write_byteI(state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 532         tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 533         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 534         tda1004x_write_byteI(state, TDA1004X_CONFADC1, 0x2e);
 535
 536         tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk);
 537
 538         state->initialised = 1;
 539         return 0;
 540                 }
 541
 542 static int tda10046_init(struct dvb_frontend* fe)
 543 {
 544         struct tda1004x_state* state = fe->demodulator_priv;
 545         dprintk("%s\n", __FUNCTION__);
 546
 547         if (state->initialised) return 0;
 548
 549         if (tda10046_fwupload(fe)) {
 550                 printk("tda1004x: firmware upload failed\n");
 551                         return -EIO;
 552                 }
 553
 554         tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 0); // wake up the chip
 555
 556         // Init the PLL
 557         if (state->config->pll_init) {
 558                 tda1004x_enable_tuner_i2c(state);
 559                 state->config->pll_init(fe);
 560                 tda1004x_disable_tuner_i2c(state);
 561         }
 562
 563         // tda setup
 564         tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 565         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0x40);
 566         tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream
 567         tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
 568         tda1004x_write_byteI(state, TDA10046H_CONFPLL2, 10); // PLL M = 10
 569         tda1004x_write_byteI(state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 570         tda1004x_write_byteI(state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
 571         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
 572         tda1004x_write_byteI(state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
 573         tda1004x_write_byteI(state, TDA10046H_AGC_CONF, 0); // AGC setup
 574         tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
 575         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MIN, 0);    // }
 576         tda1004x_write_byteI(state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 577         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MIN, 0);     // }
 578         tda1004x_write_byteI(state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 579         tda1004x_write_mask(state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
 580         tda1004x_write_byteI(state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
 581         tda1004x_write_mask(state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
 582         tda1004x_write_byteI(state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 583         tda1004x_write_mask(state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
 584         tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
 585         tda1004x_write_byteI(state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
 586         tda1004x_write_byteI(state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
 587         tda1004x_write_mask(state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
 588         tda10046h_set_bandwidth(state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 589
 590         tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7);
 591
 592         state->initialised = 1;
 593         return 0;
 594 }
 595
 596 static int tda1004x_set_fe(struct dvb_frontend* fe,
 597                            struct dvb_frontend_parameters *fe_params)
 598 {
 599         struct tda1004x_state* state = fe->demodulator_priv;
 600         int tmp;
 601         int inversion;
 602
 603         dprintk("%s\n", __FUNCTION__);
 604
 605         if (state->demod_type == TDA1004X_DEMOD_TDA10046) {
 606                 // setup auto offset
 607                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10);
 608                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0);
 609                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0);
 610
 611                 // disable agc_conf[2]
 612                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0);
 613         }
 614
 615         // set frequency
 616         tda1004x_enable_tuner_i2c(state);
 617         state->config->pll_set(fe, fe_params);
 618         tda1004x_disable_tuner_i2c(state);
 619
 620         if (state->demod_type == TDA1004X_DEMOD_TDA10046)
 621                 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 4);
 622
 623         // Hardcoded to use auto as much as possible on the TDA10045 as it
 624         // is very unreliable if AUTO mode is _not_ used.
 625         if (state->demod_type == TDA1004X_DEMOD_TDA10045) {
 626         fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 627         fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 628         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 629         }
 630
 631         // Set standard params.. or put them to auto
 632         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 633             (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 634             (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 635             (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 636                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1);        // enable auto
 637                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); // turn off constellation bits
 638                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits
 639                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits
 640         } else {
 641                 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0);        // disable auto
 642
 643                 // set HP FEC
 644                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 645                 if (tmp < 0) return tmp;
 646                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp);
 647
 648                 // set LP FEC
 649                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 650                 if (tmp < 0) return tmp;
 651                 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 652
 653                 // set constellation
 654                 switch (fe_params->u.ofdm.constellation) {
 655                 case QPSK:
 656                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0);
 657                         break;
 658
 659                 case QAM_16:
 660                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1);
 661                         break;
 662
 663                 case QAM_64:
 664                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2);
 665                         break;
 666
 667                 default:
 668                         return -EINVAL;
 669                 }
 670
 671                 // set hierarchy
 672                 switch (fe_params->u.ofdm.hierarchy_information) {
 673                 case HIERARCHY_NONE:
 674                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 675                         break;
 676
 677                 case HIERARCHY_1:
 678                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 679                         break;
 680
 681                 case HIERARCHY_2:
 682                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 683                         break;
 684
 685                 case HIERARCHY_4:
 686                         tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 687                         break;
 688
 689                 default:
 690                         return -EINVAL;
 691                 }
 692         }
 693
 694         // set bandwidth
 695         switch(state->demod_type) {
 696         case TDA1004X_DEMOD_TDA10045:
 697                 tda10045h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 698                 break;
 699
 700         case TDA1004X_DEMOD_TDA10046:
 701                 tda10046h_set_bandwidth(state, fe_params->u.ofdm.bandwidth);
 702                 break;
 703         }
 704
 705         // set inversion
 706         inversion = fe_params->inversion;
 707         if (state->config->invert) inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 708         switch (inversion) {
 709         case INVERSION_OFF:
 710                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0);
 711                 break;
 712
 713         case INVERSION_ON:
 714                 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20);
 715                 break;
 716
 717         default:
 718                 return -EINVAL;
 719         }
 720
 721         // set guard interval
 722         switch (fe_params->u.ofdm.guard_interval) {
 723         case GUARD_INTERVAL_1_32:
 724                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 725                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 726                 break;
 727
 728         case GUARD_INTERVAL_1_16:
 729                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 730                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 731                 break;
 732
 733         case GUARD_INTERVAL_1_8:
 734                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 735                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 736                 break;
 737
 738         case GUARD_INTERVAL_1_4:
 739                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0);
 740                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 741                 break;
 742
 743         case GUARD_INTERVAL_AUTO:
 744                 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2);
 745                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 746                 break;
 747
 748         default:
 749                 return -EINVAL;
 750         }
 751
 752         // set transmission mode
 753         switch (fe_params->u.ofdm.transmission_mode) {
 754         case TRANSMISSION_MODE_2K:
 755                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 756                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 757                 break;
 758
 759         case TRANSMISSION_MODE_8K:
 760                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0);
 761                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 762                 break;
 763
 764         case TRANSMISSION_MODE_AUTO:
 765                 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4);
 766                 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0);
 767                 break;
 768
 769         default:
 770                 return -EINVAL;
 771         }
 772
 773         // start the lock
 774         switch(state->demod_type) {
 775         case TDA1004X_DEMOD_TDA10045:
 776                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8);
 777                 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0);
 778                 msleep(10);
 779                 break;
 780
 781         case TDA1004X_DEMOD_TDA10046:
 782                 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40);
 783                 msleep(10);
 784                 break;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static int tda1004x_get_fe(struct dvb_frontend* fe, struct dvb_frontend_parameters *fe_params)
 791 {
 792         struct tda1004x_state* state = fe->demodulator_priv;
 793         dprintk("%s\n", __FUNCTION__);
 794
 795         // inversion status
 796         fe_params->inversion = INVERSION_OFF;
 797         if (tda1004x_read_byte(state, TDA1004X_CONFC1) & 0x20) {
 798                 fe_params->inversion = INVERSION_ON;
 799         }
 800         if (state->config->invert) fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
 801
 802         // bandwidth
 803         switch(state->demod_type) {
 804         case TDA1004X_DEMOD_TDA10045:
 805                 switch (tda1004x_read_byte(state, TDA10045H_WREF_LSB)) {
 806                 case 0x14:
 807                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 808                         break;
 809                 case 0xdb:
 810                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 811                         break;
 812                 case 0x4f:
 813                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 814                         break;
 815                 }
 816                 break;
 817
 818         case TDA1004X_DEMOD_TDA10046:
 819                 switch (tda1004x_read_byte(state, TDA10046H_TIME_WREF1)) {
 820                 case 0x60:
 821                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
 822                         break;
 823                 case 0x6e:
 824                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
 825                         break;
 826                 case 0x80:
 827                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
 828                         break;
 829                 }
 830                 break;
 831         }
 832
 833         // FEC
 834         fe_params->u.ofdm.code_rate_HP =
 835             tda1004x_decode_fec(tda1004x_read_byte(state, TDA1004X_OUT_CONF2) & 7);
 836         fe_params->u.ofdm.code_rate_LP =
 837             tda1004x_decode_fec((tda1004x_read_byte(state, TDA1004X_OUT_CONF2) >> 3) & 7);
 838
 839         // constellation
 840         switch (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 3) {
 841         case 0:
 842                 fe_params->u.ofdm.constellation = QPSK;
 843                 break;
 844         case 1:
 845                 fe_params->u.ofdm.constellation = QAM_16;
 846                 break;
 847         case 2:
 848                 fe_params->u.ofdm.constellation = QAM_64;
 849                 break;
 850         }
 851
 852         // transmission mode
 853         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
 854         if (tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x10) {
 855                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
 856         }
 857
 858         // guard interval
 859         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
 860         case 0:
 861                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
 862                 break;
 863         case 1:
 864                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
 865                 break;
 866         case 2:
 867                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
 868                 break;
 869         case 3:
 870                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
 871                 break;
 872         }
 873
 874         // hierarchy
 875         switch ((tda1004x_read_byte(state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
 876         case 0:
 877                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
 878                 break;
 879         case 1:
 880                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
 881                 break;
 882         case 2:
 883                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
 884                 break;
 885         case 3:
 886                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
 887                 break;
 888         }
 889
 890         return 0;
 891 }
 892
 893 static int tda1004x_read_status(struct dvb_frontend* fe, fe_status_t * fe_status)
 894 {
 895         struct tda1004x_state* state = fe->demodulator_priv;
 896         int status;
 897         int cber;
 898         int vber;
 899
 900         dprintk("%s\n", __FUNCTION__);
 901
 902         // read status
 903         status = tda1004x_read_byte(state, TDA1004X_STATUS_CD);
 904         if (status == -1) {
 905                 return -EIO;
 906         }
 907
 908         // decode
 909         *fe_status = 0;
 910         if (status & 4) *fe_status |= FE_HAS_SIGNAL;
 911         if (status & 2) *fe_status |= FE_HAS_CARRIER;
 912         if (status & 8) *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
 913
 914         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
 915         // is getting anything valid
 916         if (!(*fe_status & FE_HAS_VITERBI)) {
 917                 // read the CBER
 918                 cber = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
 919                 if (cber == -1) return -EIO;
 920                 status = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
 921                 if (status == -1) return -EIO;
 922                 cber |= (status << 8);
 923                 tda1004x_read_byte(state, TDA1004X_CBER_RESET);
 924
 925                 if (cber != 65535) {
 926                         *fe_status |= FE_HAS_VITERBI;
 927                 }
 928         }
 929
 930         // if we DO have some valid VITERBI output, but don't already have SYNC
 931         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
 932         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
 933                 // read the VBER
 934                 vber = tda1004x_read_byte(state, TDA1004X_VBER_LSB);
 935                 if (vber == -1) return -EIO;
 936                 status = tda1004x_read_byte(state, TDA1004X_VBER_MID);
 937                 if (status == -1) return -EIO;
 938                 vber |= (status << 8);
 939                 status = tda1004x_read_byte(state, TDA1004X_VBER_MSB);
 940                 if (status == -1) return -EIO;
 941                 vber |= ((status << 16) & 0x0f);
 942                 tda1004x_read_byte(state, TDA1004X_CVBER_LUT);
 943
 944                 // if RS has passed some valid TS packets, then we must be
 945                 // getting some SYNC bytes
 946                 if (vber < 16632) {
 947                         *fe_status |= FE_HAS_SYNC;
 948                 }
 949         }
 950
 951         // success
 952         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
 953         return 0;
 954 }
 955
 956 static int tda1004x_read_signal_strength(struct dvb_frontend* fe, u16 * signal)
 957 {
 958         struct tda1004x_state* state = fe->demodulator_priv;
 959         int tmp;
 960         int reg = 0;
 961
 962         dprintk("%s\n", __FUNCTION__);
 963
 964         // determine the register to use
 965         switch(state->demod_type) {
 966         case TDA1004X_DEMOD_TDA10045:
 967                 reg = TDA10045H_S_AGC;
 968                 break;
 969
 970         case TDA1004X_DEMOD_TDA10046:
 971                 reg = TDA10046H_AGC_IF_LEVEL;
 972                 break;
 973         }
 974
 975         // read it
 976         tmp = tda1004x_read_byte(state, reg);
 977         if (tmp < 0)
 978                 return -EIO;
 979
 980         *signal = (tmp << 8) | tmp;
 981         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
 982         return 0;
 983 }
 984
 985 static int tda1004x_read_snr(struct dvb_frontend* fe, u16 * snr)
 986 {
 987         struct tda1004x_state* state = fe->demodulator_priv;
 988         int tmp;
 989
 990         dprintk("%s\n", __FUNCTION__);
 991
 992         // read it
 993         tmp = tda1004x_read_byte(state, TDA1004X_SNR);
 994         if (tmp < 0)
 995                 return -EIO;
 996         if (tmp) {
 997                 tmp = 255 - tmp;
 998         }
 999
1000         *snr = ((tmp << 8) | tmp);
1001         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1002         return 0;
1003 }
1004
1005 static int tda1004x_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
1006 {
1007         struct tda1004x_state* state = fe->demodulator_priv;
1008         int tmp;
1009         int tmp2;
1010         int counter;
1011
1012         dprintk("%s\n", __FUNCTION__);
1013
1014         // read the UCBLOCKS and reset
1015         counter = 0;
1016         tmp = tda1004x_read_byte(state, TDA1004X_UNCOR);
1017         if (tmp < 0)
1018                 return -EIO;
1019         tmp &= 0x7f;
1020         while (counter++ < 5) {
1021                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1022                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1023                 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0);
1024
1025                 tmp2 = tda1004x_read_byte(state, TDA1004X_UNCOR);
1026                 if (tmp2 < 0)
1027                         return -EIO;
1028                 tmp2 &= 0x7f;
1029                 if ((tmp2 < tmp) || (tmp2 == 0))
1030                         break;
1031         }
1032
1033         if (tmp != 0x7f) {
1034                 *ucblocks = tmp;
1035         } else {
1036                 *ucblocks = 0xffffffff;
1037         }
1038         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1039         return 0;
1040 }
1041
1042 static int tda1004x_read_ber(struct dvb_frontend* fe, u32* ber)
1043 {
1044         struct tda1004x_state* state = fe->demodulator_priv;
1045         int tmp;
1046
1047         dprintk("%s\n", __FUNCTION__);
1048
1049         // read it in
1050         tmp = tda1004x_read_byte(state, TDA1004X_CBER_LSB);
1051         if (tmp < 0) return -EIO;
1052         *ber = tmp << 1;
1053         tmp = tda1004x_read_byte(state, TDA1004X_CBER_MSB);
1054         if (tmp < 0) return -EIO;
1055         *ber |= (tmp << 9);
1056         tda1004x_read_byte(state, TDA1004X_CBER_RESET);
1057
1058         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1059         return 0;
1060 }
1061
1062 static int tda1004x_sleep(struct dvb_frontend* fe)
1063 {
1064         struct tda1004x_state* state = fe->demodulator_priv;
1065
1066         switch(state->demod_type) {
1067         case TDA1004X_DEMOD_TDA10045:
1068                 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10);
1069                         break;
1070
1071         case TDA1004X_DEMOD_TDA10046:
1072                 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1);
1073                         break;
1074                 }
1075         state->initialised = 0;
1076
1077                         return 0;
1078                 }
1079
1080 static int tda1004x_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
1081         {
1082                 fesettings->min_delay_ms = 800;
1083                 fesettings->step_size = 166667;
1084                 fesettings->max_drift = 166667*2;
1085                 return 0;
1086         }
1087
1088 static void tda1004x_release(struct dvb_frontend* fe)
1089 {
1090         struct tda1004x_state* state = (struct tda1004x_state*) fe->demodulator_priv;
1091         kfree(state);
1092         }
1093
1094 static struct dvb_frontend_ops tda10045_ops;
1095
1096 struct dvb_frontend* tda10045_attach(const struct tda1004x_config* config,
1097                                      struct i2c_adapter* i2c)
1098 {
1099         struct tda1004x_state* state = NULL;
1100
1101         /* allocate memory for the internal state */
1102         state = (struct tda1004x_state*) kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1103         if (state == NULL) goto error;
1104
1105         /* setup the state */
1106         state->config = config;
1107         state->i2c = i2c;
1108         memcpy(&state->ops, &tda10045_ops, sizeof(struct dvb_frontend_ops));
1109         state->initialised = 0;
1110         state->demod_type = TDA1004X_DEMOD_TDA10045;
1111
1112         /* check if the demod is there */
1113         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x25) goto error;
1114
1115         /* create dvb_frontend */
1116         state->frontend.ops = &state->ops;
1117         state->frontend.demodulator_priv = state;
1118         return &state->frontend;
1119
1120 error:
1121         if (state) kfree(state);
1122         return NULL;
1123         }
1124
1125 static struct dvb_frontend_ops tda10046_ops;
1126
1127 struct dvb_frontend* tda10046_attach(const struct tda1004x_config* config,
1128                                      struct i2c_adapter* i2c)
1129 {
1130         struct tda1004x_state* state = NULL;
1131
1132         /* allocate memory for the internal state */
1133         state = (struct tda1004x_state*) kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL);
1134         if (state == NULL) goto error;
1135
1136         /* setup the state */
1137         state->config = config;
1138         state->i2c = i2c;
1139         memcpy(&state->ops, &tda10046_ops, sizeof(struct dvb_frontend_ops));
1140         state->initialised = 0;
1141         state->demod_type = TDA1004X_DEMOD_TDA10046;
1142
1143         /* check if the demod is there */
1144         if (tda1004x_read_byte(state, TDA1004X_CHIPID) != 0x46) goto error;
1145
1146         /* create dvb_frontend */
1147         state->frontend.ops = &state->ops;
1148         state->frontend.demodulator_priv = state;
1149         return &state->frontend;
1150
1151 error:
1152         if (state) kfree(state);
1153         return NULL;
1154                 }
1155
1156 static struct dvb_frontend_ops tda10045_ops = {
1157
1158         .info = {
1159                 .name = "Philips TDA10045H DVB-T",
1160                 .type = FE_OFDM,
1161                 .frequency_min = 51000000,
1162                 .frequency_max = 858000000,
1163                 .frequency_stepsize = 166667,
1164                 .caps =
1165                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1166                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1167                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1168                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1169         },
1170
1171         .release = tda1004x_release,
1172
1173         .init = tda10045_init,
1174         .sleep = tda1004x_sleep,
1175
1176         .set_frontend = tda1004x_set_fe,
1177         .get_frontend = tda1004x_get_fe,
1178         .get_tune_settings = tda1004x_get_tune_settings,
1179
1180         .read_status = tda1004x_read_status,
1181         .read_ber = tda1004x_read_ber,
1182         .read_signal_strength = tda1004x_read_signal_strength,
1183         .read_snr = tda1004x_read_snr,
1184         .read_ucblocks = tda1004x_read_ucblocks,
1185 };
1186
1187 static struct dvb_frontend_ops tda10046_ops = {
1188
1189         .info = {
1190                 .name = "Philips TDA10046H DVB-T",
1191                 .type = FE_OFDM,
1192                 .frequency_min = 51000000,
1193                 .frequency_max = 858000000,
1194                 .frequency_stepsize = 166667,
1195                 .caps =
1196                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1197                     FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1198                     FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
1199                     FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
1200         },
1201
1202         .release = tda1004x_release,
1203
1204         .init = tda10046_init,
1205         .sleep = tda1004x_sleep,
1206
1207         .set_frontend = tda1004x_set_fe,
1208         .get_frontend = tda1004x_get_fe,
1209         .get_tune_settings = tda1004x_get_tune_settings,
1210
1211         .read_status = tda1004x_read_status,
1212         .read_ber = tda1004x_read_ber,
1213         .read_signal_strength = tda1004x_read_signal_strength,
1214         .read_snr = tda1004x_read_snr,
1215         .read_ucblocks = tda1004x_read_ucblocks,
1216 };
1217
1218 module_param(debug, int, 0644);
1219 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
1220
1221 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Demodulator");
1222 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1223 MODULE_LICENSE("GPL");
1224
1225 EXPORT_SYMBOL(tda10045_attach);
1226 EXPORT_SYMBOL(tda10046_attach);
1227 EXPORT_SYMBOL(tda1004x_write_byte);