drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Frontend
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22
  23 /*
  24     This driver needs a copy of the DLL "ttlcdacc.dll" from the Haupauge or Technotrend
  25     windows driver saved as '/usr/lib/hotplug/firmware/tda1004x.bin'.
  26     You can also pass the complete file name with the module parameter 'tda1004x_firmware'.
  27
  28     Currently the DLL from v2.15a of the technotrend driver is supported. Other versions can
  29     be added reasonably painlessly.
  30
  31     Windows driver URL: http://www.technotrend.de/
  32  */
  33
  34
  35 #define __KERNEL_SYSCALLS__
  36 #include <linux/kernel.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/module.h>
  39 #include <linux/init.h>
  40 #include <linux/string.h>
  41 #include <linux/slab.h>
  42 #include <linux/fs.h>
  43 #include <linux/unistd.h>
  44 #include <linux/fcntl.h>
  45 #include <linux/errno.h>
  46 #include <linux/syscalls.h>
  47
  48 #include "dvb_frontend.h"
  49 #include "dvb_functions.h"
  50
  51 #ifndef DVB_TDA1004X_FIRMWARE_FILE
  52 #define DVB_TDA1004X_FIRMWARE_FILE "/usr/lib/hotplug/firmware/tda1004x.bin"
  53 #endif
  54
  55 static int tda1004x_debug = 0;
  56 static char *tda1004x_firmware = DVB_TDA1004X_FIRMWARE_FILE;
  57
  58 #define MC44BC374_ADDRESS        0x65
  59
  60 #define TDA1004X_CHIPID          0x00
  61 #define TDA1004X_AUTO            0x01
  62 #define TDA1004X_IN_CONF1        0x02
  63 #define TDA1004X_IN_CONF2        0x03
  64 #define TDA1004X_OUT_CONF1       0x04
  65 #define TDA1004X_OUT_CONF2       0x05
  66 #define TDA1004X_STATUS_CD       0x06
  67 #define TDA1004X_CONFC4          0x07
  68 #define TDA1004X_DSSPARE2        0x0C
  69 #define TDA10045H_CODE_IN        0x0D
  70 #define TDA10045H_FWPAGE         0x0E
  71 #define TDA1004X_SCAN_CPT        0x10
  72 #define TDA1004X_DSP_CMD         0x11
  73 #define TDA1004X_DSP_ARG         0x12
  74 #define TDA1004X_DSP_DATA1       0x13
  75 #define TDA1004X_DSP_DATA2       0x14
  76 #define TDA1004X_CONFADC1        0x15
  77 #define TDA1004X_CONFC1          0x16
  78 #define TDA10045H_S_AGC          0x1a
  79 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  80 #define TDA1004X_SNR             0x1c
  81 #define TDA1004X_CONF_TS1        0x1e
  82 #define TDA1004X_CONF_TS2        0x1f
  83 #define TDA1004X_CBER_RESET      0x20
  84 #define TDA1004X_CBER_MSB        0x21
  85 #define TDA1004X_CBER_LSB        0x22
  86 #define TDA1004X_CVBER_LUT       0x23
  87 #define TDA1004X_VBER_MSB        0x24
  88 #define TDA1004X_VBER_MID        0x25
  89 #define TDA1004X_VBER_LSB        0x26
  90 #define TDA1004X_UNCOR           0x27
  91
  92 #define TDA10045H_CONFPLL_P      0x2D
  93 #define TDA10045H_CONFPLL_M_MSB  0x2E
  94 #define TDA10045H_CONFPLL_M_LSB  0x2F
  95 #define TDA10045H_CONFPLL_N      0x30
  96
  97 #define TDA10046H_CONFPLL1       0x2D
  98 #define TDA10046H_CONFPLL2       0x2F
  99 #define TDA10046H_CONFPLL3       0x30
 100 #define TDA10046H_TIME_WREF1     0x31
 101 #define TDA10046H_TIME_WREF2     0x32
 102 #define TDA10046H_TIME_WREF3     0x33
 103 #define TDA10046H_TIME_WREF4     0x34
 104 #define TDA10046H_TIME_WREF5     0x35
 105
 106 #define TDA10045H_UNSURW_MSB     0x31
 107 #define TDA10045H_UNSURW_LSB     0x32
 108 #define TDA10045H_WREF_MSB       0x33
 109 #define TDA10045H_WREF_MID       0x34
 110 #define TDA10045H_WREF_LSB       0x35
 111 #define TDA10045H_MUXOUT         0x36
 112 #define TDA1004X_CONFADC2        0x37
 113
 114 #define TDA10045H_IOFFSET        0x38
 115
 116 #define TDA10046H_CONF_TRISTATE1 0x3B
 117 #define TDA10046H_CONF_TRISTATE2 0x3C
 118 #define TDA10046H_CONF_POLARITY  0x3D
 119 #define TDA10046H_FREQ_OFFSET    0x3E
 120 #define TDA10046H_GPIO_OUT_SEL   0x41
 121 #define TDA10046H_GPIO_SELECT    0x42
 122 #define TDA10046H_AGC_CONF       0x43
 123 #define TDA10046H_AGC_GAINS      0x46
 124 #define TDA10046H_AGC_TUN_MIN    0x47
 125 #define TDA10046H_AGC_TUN_MAX    0x48
 126 #define TDA10046H_AGC_IF_MIN     0x49
 127 #define TDA10046H_AGC_IF_MAX     0x4A
 128
 129 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 130 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 131
 132 #define TDA10046H_CVBER_CTRL     0x4F
 133 #define TDA10046H_AGC_IF_LEVEL   0x52
 134 #define TDA10046H_CODE_CPT       0x57
 135 #define TDA10046H_CODE_IN        0x58
 136
 137
 138 #define FE_TYPE_TDA10045H     0
 139 #define FE_TYPE_TDA10046H     1
 140
 141 #define TUNER_TYPE_TD1344     0
 142 #define TUNER_TYPE_TD1316     1
 143
 144 #define dprintk if (tda1004x_debug) printk
 145
 146 static struct dvb_frontend_info tda10045h_info = {
 147         .name = "Philips TDA10045H",
 148         .type = FE_OFDM,
 149         .frequency_min = 51000000,
 150         .frequency_max = 858000000,
 151         .frequency_stepsize = 166667,
 152         .caps =
 153             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 154             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 155             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 156             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
 157 };
 158
 159 static struct dvb_frontend_info tda10046h_info = {
 160         .name = "Philips TDA10046H",
 161         .type = FE_OFDM,
 162         .frequency_min = 51000000,
 163         .frequency_max = 858000000,
 164         .frequency_stepsize = 166667,
 165         .caps =
 166             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 167             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 168             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 169             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
 170 };
 171
 172
 173 struct tda1004x_state {
 174         u8 tda1004x_address;
 175         u8 tuner_address;
 176         u8 initialised:1;
 177         u8 tuner_type:2;
 178         u8 fe_type:2;
 179 };
 180
 181
 182 struct fwinfo {
 183         int file_size;
 184         int fw_offset;
 185         int fw_size;
 186 };
 187 static struct fwinfo tda10045h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x34cc5,.fw_size = 30555} };
 188 static int tda10045h_fwinfo_count = sizeof(tda10045h_fwinfo) / sizeof(struct fwinfo);
 189
 190 static struct fwinfo tda10046h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x3c4f9,.fw_size = 24479} };
 191 static int tda10046h_fwinfo_count = sizeof(tda10046h_fwinfo) / sizeof(struct fwinfo);
 192
 193 static int errno;
 194
 195
 196 static int tda1004x_write_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int data)
 197 {
 198         int ret;
 199         u8 buf[] = { reg, data };
 200         struct i2c_msg msg = { .addr=0, .flags=0, .buf=buf, .len=2 };
 201
 202         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 203
 204         msg.addr = tda_state->tda1004x_address;
 205         ret = i2c->xfer(i2c, &msg, 1);
 206
 207         if (ret != 1)
 208                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 209                        __FUNCTION__, reg, data, ret);
 210
 211         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 212                 reg, data, ret);
 213         return (ret != 1) ? -1 : 0;
 214 }
 215
 216 static int tda1004x_read_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg)
 217 {
 218         int ret;
 219         u8 b0[] = { reg };
 220         u8 b1[] = { 0 };
 221         struct i2c_msg msg[] = {{ .addr=0, .flags=0, .buf=b0, .len=1},
 222                                 { .addr=0, .flags=I2C_M_RD, .buf=b1, .len = 1}};
 223
 224         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 225
 226         msg[0].addr = tda_state->tda1004x_address;
 227         msg[1].addr = tda_state->tda1004x_address;
 228         ret = i2c->xfer(i2c, msg, 2);
 229
 230         if (ret != 2) {
 231                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 232                        ret);
 233                 return -1;
 234         }
 235
 236         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 237                 reg, b1[0], ret);
 238         return b1[0];
 239 }
 240
 241 static int tda1004x_write_mask(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int mask, int data)
 242 {
 243         int val;
 244         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 245                 mask, data);
 246
 247         // read a byte and check
 248         val = tda1004x_read_byte(i2c, tda_state, reg);
 249         if (val < 0)
 250                 return val;
 251
 252         // mask if off
 253         val = val & ~mask;
 254         val |= data & 0xff;
 255
 256         // write it out again
 257         return tda1004x_write_byte(i2c, tda_state, reg, val);
 258 }
 259
 260 static int tda1004x_write_buf(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, unsigned char *buf, int len)
 261 {
 262         int i;
 263         int result;
 264
 265         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 266
 267         result = 0;
 268         for (i = 0; i < len; i++) {
 269                 result = tda1004x_write_byte(i2c, tda_state, reg + i, buf[i]);
 270                 if (result != 0)
 271                         break;
 272         }
 273
 274         return result;
 275 }
 276
 277 static int tda1004x_enable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 278 {
 279         int result;
 280         dprintk("%s\n", __FUNCTION__);
 281
 282         result = tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 2);
 283         dvb_delay(1);
 284         return result;
 285 }
 286
 287 static int tda1004x_disable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 288 {
 289
 290         dprintk("%s\n", __FUNCTION__);
 291
 292         return tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 0);
 293 }
 294
 295
 296 static int tda10045h_set_bandwidth(struct dvb_i2c_bus *i2c,
 297                                    struct tda1004x_state *tda_state,
 298                                    fe_bandwidth_t bandwidth)
 299 {
 300         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 301         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 302         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 303
 304         switch (bandwidth) {
 305         case BANDWIDTH_6_MHZ:
 306                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
 307                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 308                 break;
 309
 310         case BANDWIDTH_7_MHZ:
 311                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x80);
 312                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 313                 break;
 314
 315         case BANDWIDTH_8_MHZ:
 316                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
 317                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 318                 break;
 319
 320         default:
 321                 return -EINVAL;
 322         }
 323
 324         tda1004x_write_byte(i2c, tda_state, TDA10045H_IOFFSET, 0);
 325
 326         // done
 327         return 0;
 328 }
 329
 330
 331 static int tda10046h_set_bandwidth(struct dvb_i2c_bus *i2c,
 332                                    struct tda1004x_state *tda_state,
 333                                    fe_bandwidth_t bandwidth)
 334 {
 335         static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
 336         static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
 337         static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
 338
 339         switch (bandwidth) {
 340         case BANDWIDTH_6_MHZ:
 341                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 342                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
 343                 break;
 344
 345         case BANDWIDTH_7_MHZ:
 346                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 347                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
 348                 break;
 349
 350         case BANDWIDTH_8_MHZ:
 351                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 352                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0xFF);
 353                 break;
 354
 355         default:
 356                 return -EINVAL;
 357         }
 358
 359         // done
 360         return 0;
 361 }
 362
 363
 364 static int tda1004x_fwupload(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 365 {
 366         u8 fw_buf[65];
 367         struct i2c_msg fw_msg = {.addr = 0,.flags = 0,.buf = fw_buf,.len = 0 };
 368         unsigned char *firmware = NULL;
 369         int filesize;
 370         int fd;
 371         int fwinfo_idx;
 372         int fw_size = 0;
 373         int fw_pos, fw_offset;
 374         int tx_size;
 375         mm_segment_t fs = get_fs();
 376         int dspCodeCounterReg=0, dspCodeInReg=0, dspVersion=0;
 377         int fwInfoCount=0;
 378         struct fwinfo* fwInfo = NULL;
 379         unsigned long timeout;
 380
 381         // DSP parameters
 382         switch(tda_state->fe_type) {
 383         case FE_TYPE_TDA10045H:
 384                 dspCodeCounterReg = TDA10045H_FWPAGE;
 385                 dspCodeInReg = TDA10045H_CODE_IN;
 386                 dspVersion = 0x2c;
 387                 fwInfoCount = tda10045h_fwinfo_count;
 388                 fwInfo = tda10045h_fwinfo;
 389                 break;
 390
 391         case FE_TYPE_TDA10046H:
 392                 dspCodeCounterReg = TDA10046H_CODE_CPT;
 393                 dspCodeInReg = TDA10046H_CODE_IN;
 394                 dspVersion = 0x20;
 395                 fwInfoCount = tda10046h_fwinfo_count;
 396                 fwInfo = tda10046h_fwinfo;
 397                 break;
 398         }
 399
 400         // Load the firmware
 401         set_fs(get_ds());
 402         fd = open(tda1004x_firmware, 0, 0);
 403         if (fd < 0) {
 404                 printk("%s: Unable to open firmware %s\n", __FUNCTION__,
 405                        tda1004x_firmware);
 406                 return -EIO;
 407         }
 408         filesize = lseek(fd, 0L, 2);
 409         if (filesize <= 0) {
 410                 printk("%s: Firmware %s is empty\n", __FUNCTION__,
 411                        tda1004x_firmware);
 412                 sys_close(fd);
 413                 return -EIO;
 414         }
 415
 416         // find extraction parameters for firmware
 417         for (fwinfo_idx = 0; fwinfo_idx < fwInfoCount; fwinfo_idx++) {
 418                 if (fwInfo[fwinfo_idx].file_size == filesize)
 419                         break;
 420         }
 421         if (fwinfo_idx >= fwInfoCount) {
 422                 printk("%s: Unsupported firmware %s\n", __FUNCTION__, tda1004x_firmware);
 423                 sys_close(fd);
 424                 return -EIO;
 425         }
 426         fw_size = fwInfo[fwinfo_idx].fw_size;
 427         fw_offset = fwInfo[fwinfo_idx].fw_offset;
 428
 429         // allocate buffer for it
 430         firmware = vmalloc(fw_size);
 431         if (firmware == NULL) {
 432                 printk("%s: Out of memory loading firmware\n",
 433                        __FUNCTION__);
 434                 sys_close(fd);
 435                 return -EIO;
 436         }
 437
 438         // read it!
 439         lseek(fd, fw_offset, 0);
 440         if (read(fd, firmware, fw_size) != fw_size) {
 441                 printk("%s: Failed to read firmware\n", __FUNCTION__);
 442                 vfree(firmware);
 443                 sys_close(fd);
 444                 return -EIO;
 445         }
 446         sys_close(fd);
 447         set_fs(fs);
 448
 449         // set some valid bandwith parameters before uploading
 450         switch(tda_state->fe_type) {
 451         case FE_TYPE_TDA10045H:
 452                 // reset chip
 453                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0);
 454                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
 455                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
 456                 dvb_delay(10);
 457
 458                 // set parameters
 459                 tda10045h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ);
 460                 break;
 461
 462         case FE_TYPE_TDA10046H:
 463                 // reset chip
 464                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0);
 465                 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 1, 0);
 466                 dvb_delay(10);
 467
 468                 // set parameters
 469                 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10);
 470                 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0);
 471                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99);
 472                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 473                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
 474                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 475                 break;
 476         }
 477
 478         // do the firmware upload
 479         tda1004x_write_byte(i2c, tda_state, dspCodeCounterReg, 0); // clear code counter
 480         fw_msg.addr = tda_state->tda1004x_address;
 481         fw_pos = 0;
 482         while (fw_pos != fw_size) {
 483
 484                 // work out how much to send this time
 485                 tx_size = fw_size - fw_pos;
 486                 if (tx_size > 0x10) {
 487                         tx_size = 0x10;
 488                 }
 489
 490                 // send the chunk
 491                 fw_buf[0] = dspCodeInReg;
 492                 memcpy(fw_buf + 1, firmware + fw_pos, tx_size);
 493                 fw_msg.len = tx_size + 1;
 494                 if (i2c->xfer(i2c, &fw_msg, 1) != 1) {
 495                         printk("tda1004x: Error during firmware upload\n");
 496                         vfree(firmware);
 497                         return -EIO;
 498                 }
 499                 fw_pos += tx_size;
 500
 501                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, fw_pos);
 502         }
 503         vfree(firmware);
 504
 505         // wait for DSP to initialise
 506         switch(tda_state->fe_type) {
 507         case FE_TYPE_TDA10045H:
 508                 // DSPREADY doesn't seem to work on the TDA10045H
 509                 dvb_delay(100);
 510                 break;
 511
 512         case FE_TYPE_TDA10046H:
 513                 timeout = jiffies + HZ;
 514                 while(!(tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD) & 0x20)) {
 515                         if (time_after(jiffies, timeout)) {
 516                                 printk("tda1004x: DSP failed to initialised.\n");
 517                                 return -EIO;
 518                         }
 519
 520                         dvb_delay(1);
 521                 }
 522                 break;
 523         }
 524
 525         // check upload was OK
 526         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 527         tda1004x_write_byte(i2c, tda_state, TDA1004X_DSP_CMD, 0x67);
 528         if ((tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA1) != 0x67) ||
 529             (tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA2) != dspVersion)) {
 530                 printk("%s: firmware upload failed!\n", __FUNCTION__);
 531                 return -EIO;
 532         }
 533
 534         // success
 535         return 0;
 536 }
 537
 538
 539 static int tda10045h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 540 {
 541         struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = 0,.len = 0 };
 542         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 543
 544         dprintk("%s\n", __FUNCTION__);
 545
 546         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 547
 548         // Disable the MC44BC374C
 549         tda1004x_enable_tuner_i2c(i2c, tda_state);
 550         tuner_msg.addr = MC44BC374_ADDRESS;
 551         tuner_msg.buf = disable_mc44BC374c;
 552         tuner_msg.len = sizeof(disable_mc44BC374c);
 553         if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 554                 i2c->xfer(i2c, &tuner_msg, 1);
 555         }
 556         tda1004x_disable_tuner_i2c(i2c, tda_state);
 557
 558         // tda setup
 559         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 560         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
 561         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0); // no frequency inversion
 562         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 563         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 564         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 565         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 566         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 567         tda1004x_write_mask(i2c, tda_state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 568         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 569         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONFADC1, 0x2e);
 570
 571         // done
 572         return 0;
 573 }
 574
 575
 576
 577 static int tda10046h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 578 {
 579         struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = 0,.len = 0 };
 580         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 581
 582         dprintk("%s\n", __FUNCTION__);
 583
 584         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0); // wake up the chip
 585
 586         // Disable the MC44BC374C
 587         tda1004x_enable_tuner_i2c(i2c, tda_state);
 588         tuner_msg.addr = MC44BC374_ADDRESS;
 589         tuner_msg.buf = disable_mc44BC374c;
 590         tuner_msg.len = sizeof(disable_mc44BC374c);
 591         if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 592                 i2c->xfer(i2c, &tuner_msg, 1);
 593         }
 594         tda1004x_disable_tuner_i2c(i2c, tda_state);
 595
 596         // tda setup
 597         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 598         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0x40); // TT TDA10046H needs inversion ON
 599         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
 600         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
 601         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10); // PLL M = 10
 602         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 603         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
 604         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
 605         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
 606         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_CONF, 0); // AGC setup
 607         tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
 608         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MIN, 0);    // }
 609         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 610         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MIN, 0);     // }
 611         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 612         tda1004x_write_mask(i2c, tda_state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
 613         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
 614         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
 615         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 616         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
 617         tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
 618         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
 619         tda1004x_write_byte(i2c, tda_state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
 620         tda1004x_write_mask(i2c, tda_state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
 621         tda10046h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 622
 623         // done
 624         return 0;
 625 }
 626
 627
 628
 629 static int tda1004x_encode_fec(int fec)
 630 {
 631         // convert known FEC values
 632         switch (fec) {
 633         case FEC_1_2:
 634                 return 0;
 635         case FEC_2_3:
 636                 return 1;
 637         case FEC_3_4:
 638                 return 2;
 639         case FEC_5_6:
 640                 return 3;
 641         case FEC_7_8:
 642                 return 4;
 643         }
 644
 645         // unsupported
 646         return -EINVAL;
 647 }
 648
 649 static int tda1004x_decode_fec(int tdafec)
 650 {
 651         // convert known FEC values
 652         switch (tdafec) {
 653         case 0:
 654                 return FEC_1_2;
 655         case 1:
 656                 return FEC_2_3;
 657         case 2:
 658                 return FEC_3_4;
 659         case 3:
 660                 return FEC_5_6;
 661         case 4:
 662                 return FEC_7_8;
 663         }
 664
 665         // unsupported
 666         return -1;
 667 }
 668
 669 static int tda1004x_set_frequency(struct dvb_i2c_bus *i2c,
 670                            struct tda1004x_state *tda_state,
 671                            struct dvb_frontend_parameters *fe_params)
 672 {
 673         u8 tuner_buf[4];
 674         struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=tuner_buf, .len=sizeof(tuner_buf) };
 675         int tuner_frequency = 0;
 676         u8 band, cp, filter;
 677         int counter, counter2;
 678
 679         dprintk("%s\n", __FUNCTION__);
 680
 681         // setup the frequency buffer
 682         switch (tda_state->tuner_type) {
 683         case TUNER_TYPE_TD1344:
 684
 685                 // setup tuner buffer
 686                 // ((Fif+((1000000/6)/2)) + Finput)/(1000000/6)
 687                 tuner_frequency =
 688                         (((fe_params->frequency / 1000) * 6) + 217502) / 1000;
 689                 tuner_buf[0] = tuner_frequency >> 8;
 690                 tuner_buf[1] = tuner_frequency & 0xff;
 691                 tuner_buf[2] = 0x88;
 692                 if (fe_params->frequency < 550000000) {
 693                         tuner_buf[3] = 0xab;
 694                 } else {
 695                         tuner_buf[3] = 0xeb;
 696                 }
 697
 698                 // tune it
 699                 tda1004x_enable_tuner_i2c(i2c, tda_state);
 700                 tuner_msg.addr = tda_state->tuner_address;
 701                 tuner_msg.len = 4;
 702                 i2c->xfer(i2c, &tuner_msg, 1);
 703
 704                 // wait for it to finish
 705                 tuner_msg.len = 1;
 706                 tuner_msg.flags = I2C_M_RD;
 707                 counter = 0;
 708                 counter2 = 0;
 709                 while (counter++ < 100) {
 710                         if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
 711                                 if (tuner_buf[0] & 0x40) {
 712                                         counter2++;
 713                                 } else {
 714                                         counter2 = 0;
 715                                 }
 716                         }
 717
 718                         if (counter2 > 10) {
 719                                 break;
 720                         }
 721                 }
 722                 tda1004x_disable_tuner_i2c(i2c, tda_state);
 723                 break;
 724
 725         case TUNER_TYPE_TD1316:
 726                 // determine charge pump
 727                 tuner_frequency = fe_params->frequency + 36130000;
 728                 if (tuner_frequency < 87000000) {
 729                         return -EINVAL;
 730                 } else if (tuner_frequency < 130000000) {
 731                         cp = 3;
 732                 } else if (tuner_frequency < 160000000) {
 733                         cp = 5;
 734                 } else if (tuner_frequency < 200000000) {
 735                         cp = 6;
 736                 } else if (tuner_frequency < 290000000) {
 737                         cp = 3;
 738                 } else if (tuner_frequency < 420000000) {
 739                         cp = 5;
 740                 } else if (tuner_frequency < 480000000) {
 741                         cp = 6;
 742                 } else if (tuner_frequency < 620000000) {
 743                         cp = 3;
 744                 } else if (tuner_frequency < 830000000) {
 745                         cp = 5;
 746                 } else if (tuner_frequency < 895000000) {
 747                         cp = 7;
 748                 } else {
 749                         return -EINVAL;
 750                 }
 751
 752                 // determine band
 753                 if (fe_params->frequency < 49000000) {
 754                         return -EINVAL;
 755                 } else if (fe_params->frequency < 159000000) {
 756                         band = 1;
 757                 } else if (fe_params->frequency < 444000000) {
 758                         band = 2;
 759                 } else if (fe_params->frequency < 861000000) {
 760                         band = 4;
 761                 } else {
 762                         return -EINVAL;
 763                 }
 764
 765                 // work out filter
 766                 switch (fe_params->u.ofdm.bandwidth) {
 767                 case BANDWIDTH_6_MHZ:
 768                         filter = 0;
 769                         break;
 770
 771                 case BANDWIDTH_7_MHZ:
 772                         filter = 0;
 773                         break;
 774
 775                 case BANDWIDTH_8_MHZ:
 776                         filter = 1;
 777                         break;
 778
 779                 default:
 780                         return -EINVAL;
 781                 }
 782
 783                 // calculate divisor
 784                 // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
 785                 tuner_frequency =
 786                         (((fe_params->frequency / 1000) * 6) + 217280) / 1000;
 787
 788                 // setup tuner buffer
 789                 tuner_buf[0] = tuner_frequency >> 8;
 790                 tuner_buf[1] = tuner_frequency & 0xff;
 791                 tuner_buf[2] = 0xca;
 792                 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
 793
 794                 // tune it
 795                 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
 796                         // setup auto offset
 797                         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10);
 798                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x80, 0);
 799                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0);
 800
 801                         // disable agc_conf[2]
 802                         tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 0);
 803                 }
 804                 tda1004x_enable_tuner_i2c(i2c, tda_state);
 805                 tuner_msg.addr = tda_state->tuner_address;
 806                 tuner_msg.len = 4;
 807                 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 808                         return -EIO;
 809                 }
 810                 dvb_delay(1);
 811                 tda1004x_disable_tuner_i2c(i2c, tda_state);
 812                 if (tda_state->fe_type == FE_TYPE_TDA10046H)
 813                         tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 4);
 814                 break;
 815
 816         default:
 817                 return -EINVAL;
 818         }
 819
 820         dprintk("%s: success\n", __FUNCTION__);
 821
 822         // done
 823         return 0;
 824 }
 825
 826 static int tda1004x_set_fe(struct dvb_i2c_bus *i2c,
 827                            struct tda1004x_state *tda_state,
 828                            struct dvb_frontend_parameters *fe_params)
 829 {
 830         int tmp;
 831         int inversion;
 832
 833         dprintk("%s\n", __FUNCTION__);
 834
 835         // set frequency
 836         if ((tmp = tda1004x_set_frequency(i2c, tda_state, fe_params)) < 0)
 837                 return tmp;
 838
 839         // hardcoded to use auto as much as possible
 840         fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 841         fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 842         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 843
 844         // Set standard params.. or put them to auto
 845         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 846             (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 847             (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 848             (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 849                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 1);       // enable auto
 850                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x03, 0);        // turn off constellation bits
 851                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0);        // turn off hierarchy bits
 852                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x3f, 0);        // turn off FEC bits
 853         } else {
 854                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 0);       // disable auto
 855
 856                 // set HP FEC
 857                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 858                 if (tmp < 0) return tmp;
 859                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 7, tmp);
 860
 861                 // set LP FEC
 862                 if (fe_params->u.ofdm.code_rate_LP != FEC_NONE) {
 863                         tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 864                         if (tmp < 0) return tmp;
 865                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 866                 }
 867
 868                 // set constellation
 869                 switch (fe_params->u.ofdm.constellation) {
 870                 case QPSK:
 871                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 0);
 872                         break;
 873
 874                 case QAM_16:
 875                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 1);
 876                         break;
 877
 878                 case QAM_64:
 879                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 2);
 880                         break;
 881
 882                 default:
 883                         return -EINVAL;
 884                 }
 885
 886                 // set hierarchy
 887                 switch (fe_params->u.ofdm.hierarchy_information) {
 888                 case HIERARCHY_NONE:
 889                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 890                         break;
 891
 892                 case HIERARCHY_1:
 893                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 894                         break;
 895
 896                 case HIERARCHY_2:
 897                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 898                         break;
 899
 900                 case HIERARCHY_4:
 901                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 902                         break;
 903
 904                 default:
 905                         return -EINVAL;
 906                 }
 907         }
 908
 909         // set bandwidth
 910         switch(tda_state->fe_type) {
 911         case FE_TYPE_TDA10045H:
 912                 tda10045h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
 913                 break;
 914
 915         case FE_TYPE_TDA10046H:
 916                 tda10046h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
 917                 break;
 918         }
 919
 920         // need to invert the inversion for TT TDA10046H
 921         inversion = fe_params->inversion;
 922         if (tda_state->fe_type == FE_TYPE_TDA10046H) {
 923                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 924         }
 925
 926         // set inversion
 927         switch (inversion) {
 928         case INVERSION_OFF:
 929                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0);
 930                 break;
 931
 932         case INVERSION_ON:
 933                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0x20);
 934                 break;
 935
 936         default:
 937                 return -EINVAL;
 938         }
 939
 940         // set guard interval
 941         switch (fe_params->u.ofdm.guard_interval) {
 942         case GUARD_INTERVAL_1_32:
 943                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 944                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 945                 break;
 946
 947         case GUARD_INTERVAL_1_16:
 948                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 949                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 950                 break;
 951
 952         case GUARD_INTERVAL_1_8:
 953                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 954                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 955                 break;
 956
 957         case GUARD_INTERVAL_1_4:
 958                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 959                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 960                 break;
 961
 962         case GUARD_INTERVAL_AUTO:
 963                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 2);
 964                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 965                 break;
 966
 967         default:
 968                 return -EINVAL;
 969         }
 970
 971         // set transmission mode
 972         switch (fe_params->u.ofdm.transmission_mode) {
 973         case TRANSMISSION_MODE_2K:
 974                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
 975                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 976                 break;
 977
 978         case TRANSMISSION_MODE_8K:
 979                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
 980                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 981                 break;
 982
 983         case TRANSMISSION_MODE_AUTO:
 984                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 4);
 985                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0);
 986                 break;
 987
 988         default:
 989                 return -EINVAL;
 990         }
 991
 992         // start the lock
 993         switch(tda_state->fe_type) {
 994         case FE_TYPE_TDA10045H:
 995         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
 996         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
 997         dvb_delay(10);
 998                 break;
 999
1000         case FE_TYPE_TDA10046H:
1001                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x40, 0x40);
1002                 dvb_delay(10);
1003                 break;
1004         }
1005
1006         // done
1007         return 0;
1008 }
1009
1010
1011 static int tda1004x_get_fe(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, struct dvb_frontend_parameters *fe_params)
1012 {
1013
1014         dprintk("%s\n", __FUNCTION__);
1015
1016         // inversion status
1017         fe_params->inversion = INVERSION_OFF;
1018         if (tda1004x_read_byte(i2c, tda_state, TDA1004X_CONFC1) & 0x20) {
1019                 fe_params->inversion = INVERSION_ON;
1020         }
1021
1022         // need to invert the inversion for TT TDA10046H
1023         if (tda_state->fe_type == FE_TYPE_TDA10046H) {
1024                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
1025         }
1026
1027         // bandwidth
1028         switch(tda_state->fe_type) {
1029         case FE_TYPE_TDA10045H:
1030                 switch (tda1004x_read_byte(i2c, tda_state, TDA10045H_WREF_LSB)) {
1031         case 0x14:
1032                 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1033                 break;
1034         case 0xdb:
1035                 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1036                 break;
1037         case 0x4f:
1038                 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1039                 break;
1040         }
1041                 break;
1042
1043         case FE_TYPE_TDA10046H:
1044                 switch (tda1004x_read_byte(i2c, tda_state, TDA10046H_TIME_WREF1)) {
1045                 case 0x60:
1046                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1047                         break;
1048                 case 0x6e:
1049                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1050                         break;
1051                 case 0x80:
1052                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1053                         break;
1054                 }
1055                 break;
1056         }
1057
1058         // FEC
1059         fe_params->u.ofdm.code_rate_HP =
1060             tda1004x_decode_fec(tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) & 7);
1061         fe_params->u.ofdm.code_rate_LP =
1062             tda1004x_decode_fec((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) >> 3) & 7);
1063
1064         // constellation
1065         switch (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 3) {
1066         case 0:
1067                 fe_params->u.ofdm.constellation = QPSK;
1068                 break;
1069         case 1:
1070                 fe_params->u.ofdm.constellation = QAM_16;
1071                 break;
1072         case 2:
1073                 fe_params->u.ofdm.constellation = QAM_64;
1074                 break;
1075         }
1076
1077         // transmission mode
1078         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1079         if (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x10) {
1080                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1081         }
1082
1083         // guard interval
1084         switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
1085         case 0:
1086                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1087                 break;
1088         case 1:
1089                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1090                 break;
1091         case 2:
1092                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1093                 break;
1094         case 3:
1095                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1096                 break;
1097         }
1098
1099         // hierarchy
1100         switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
1101         case 0:
1102                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1103                 break;
1104         case 1:
1105                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
1106                 break;
1107         case 2:
1108                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
1109                 break;
1110         case 3:
1111                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
1112                 break;
1113         }
1114
1115         // done
1116         return 0;
1117 }
1118
1119
1120 static int tda1004x_read_status(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, fe_status_t * fe_status)
1121 {
1122         int status;
1123         int cber;
1124         int vber;
1125
1126         dprintk("%s\n", __FUNCTION__);
1127
1128         // read status
1129         status = tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD);
1130         if (status == -1) {
1131                 return -EIO;
1132         }
1133
1134         // decode
1135         *fe_status = 0;
1136         if (status & 4) *fe_status |= FE_HAS_SIGNAL;
1137         if (status & 2) *fe_status |= FE_HAS_CARRIER;
1138         if (status & 8) *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1139
1140         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1141         // is getting anything valid
1142         if (!(*fe_status & FE_HAS_VITERBI)) {
1143                 // read the CBER
1144                 cber = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1145                 if (cber == -1) return -EIO;
1146                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1147                 if (status == -1) return -EIO;
1148                 cber |= (status << 8);
1149                 tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1150
1151                 if (cber != 65535) {
1152                         *fe_status |= FE_HAS_VITERBI;
1153                 }
1154         }
1155
1156         // if we DO have some valid VITERBI output, but don't already have SYNC
1157         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1158         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1159                 // read the VBER
1160                 vber = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_LSB);
1161                 if (vber == -1) return -EIO;
1162                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MID);
1163                 if (status == -1) return -EIO;
1164                 vber |= (status << 8);
1165                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MSB);
1166                 if (status == -1) return -EIO;
1167                 vber |= ((status << 16) & 0x0f);
1168                 tda1004x_read_byte(i2c, tda_state, TDA1004X_CVBER_LUT);
1169
1170                 // if RS has passed some valid TS packets, then we must be
1171                 // getting some SYNC bytes
1172                 if (vber < 16632) {
1173                         *fe_status |= FE_HAS_SYNC;
1174                 }
1175         }
1176
1177         // success
1178         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1179         return 0;
1180 }
1181
1182 static int tda1004x_read_signal_strength(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * signal)
1183 {
1184         int tmp;
1185         int reg = 0;
1186
1187         dprintk("%s\n", __FUNCTION__);
1188
1189         // determine the register to use
1190         switch(tda_state->fe_type) {
1191         case FE_TYPE_TDA10045H:
1192                 reg = TDA10045H_S_AGC;
1193                 break;
1194
1195         case FE_TYPE_TDA10046H:
1196                 reg = TDA10046H_AGC_IF_LEVEL;
1197                 break;
1198         }
1199
1200         // read it
1201         tmp = tda1004x_read_byte(i2c, tda_state, reg);
1202         if (tmp < 0)
1203                 return -EIO;
1204
1205         // done
1206         *signal = (tmp << 8) | tmp;
1207         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1208         return 0;
1209 }
1210
1211
1212 static int tda1004x_read_snr(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * snr)
1213 {
1214         int tmp;
1215
1216         dprintk("%s\n", __FUNCTION__);
1217
1218         // read it
1219         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_SNR);
1220         if (tmp < 0)
1221                 return -EIO;
1222         if (tmp) {
1223                 tmp = 255 - tmp;
1224         }
1225
1226         // done
1227         *snr = ((tmp << 8) | tmp);
1228         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1229         return 0;
1230 }
1231
1232 static int tda1004x_read_ucblocks(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ucblocks)
1233 {
1234         int tmp;
1235         int tmp2;
1236         int counter;
1237
1238         dprintk("%s\n", __FUNCTION__);
1239
1240         // read the UCBLOCKS and reset
1241         counter = 0;
1242         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1243         if (tmp < 0)
1244                 return -EIO;
1245         tmp &= 0x7f;
1246         while (counter++ < 5) {
1247                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1248                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1249                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1250
1251                 tmp2 = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1252                 if (tmp2 < 0)
1253                         return -EIO;
1254                 tmp2 &= 0x7f;
1255                 if ((tmp2 < tmp) || (tmp2 == 0))
1256                         break;
1257         }
1258
1259         // done
1260         if (tmp != 0x7f) {
1261                 *ucblocks = tmp;
1262         } else {
1263                 *ucblocks = 0xffffffff;
1264         }
1265         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1266         return 0;
1267 }
1268
1269 static int tda1004x_read_ber(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ber)
1270 {
1271         int tmp;
1272
1273         dprintk("%s\n", __FUNCTION__);
1274
1275         // read it in
1276         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1277         if (tmp < 0) return -EIO;
1278         *ber = tmp << 1;
1279         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1280         if (tmp < 0) return -EIO;
1281         *ber |= (tmp << 9);
1282         tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1283
1284         // done
1285         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1286         return 0;
1287 }
1288
1289 static int tda1004x_sleep(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state)
1290 {
1291         switch(tda_state->fe_type) {
1292         case FE_TYPE_TDA10045H:
1293                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0x10);
1294                 break;
1295
1296         case FE_TYPE_TDA10046H:
1297                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 1);
1298                 break;
1299         }
1300
1301         return 0;
1302 }
1303
1304
1305 static int tda1004x_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
1306 {
1307         int status = 0;
1308         struct dvb_i2c_bus *i2c = fe->i2c;
1309         struct tda1004x_state *tda_state = (struct tda1004x_state *) fe->data;
1310
1311         dprintk("%s: cmd=0x%x\n", __FUNCTION__, cmd);
1312
1313         switch (cmd) {
1314         case FE_GET_INFO:
1315                 switch(tda_state->fe_type) {
1316                 case FE_TYPE_TDA10045H:
1317                         memcpy(arg, &tda10045h_info, sizeof(struct dvb_frontend_info));
1318                         break;
1319
1320                 case FE_TYPE_TDA10046H:
1321                         memcpy(arg, &tda10046h_info, sizeof(struct dvb_frontend_info));
1322                         break;
1323                 }
1324                 break;
1325
1326         case FE_READ_STATUS:
1327                 return tda1004x_read_status(i2c, tda_state, (fe_status_t *) arg);
1328
1329         case FE_READ_BER:
1330                 return tda1004x_read_ber(i2c, tda_state, (u32 *) arg);
1331
1332         case FE_READ_SIGNAL_STRENGTH:
1333                 return tda1004x_read_signal_strength(i2c, tda_state, (u16 *) arg);
1334
1335         case FE_READ_SNR:
1336                 return tda1004x_read_snr(i2c, tda_state, (u16 *) arg);
1337
1338         case FE_READ_UNCORRECTED_BLOCKS:
1339                 return tda1004x_read_ucblocks(i2c, tda_state, (u32 *) arg);
1340
1341         case FE_SET_FRONTEND:
1342                 return tda1004x_set_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1343
1344         case FE_GET_FRONTEND:
1345                 return tda1004x_get_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1346
1347         case FE_SLEEP:
1348                 tda_state->initialised = 0;
1349                 return tda1004x_sleep(i2c, tda_state);
1350
1351         case FE_INIT:
1352
1353                 // don't bother reinitialising
1354                 if (tda_state->initialised)
1355                         return 0;
1356
1357                 // OK, perform initialisation
1358                 switch(tda_state->fe_type) {
1359                 case FE_TYPE_TDA10045H:
1360                         status = tda10045h_init(i2c, tda_state);
1361                         break;
1362
1363                 case FE_TYPE_TDA10046H:
1364                         status = tda10046h_init(i2c, tda_state);
1365                         break;
1366                 }
1367                 if (status == 0)
1368                         tda_state->initialised = 1;
1369                 return status;
1370
1371         case FE_GET_TUNE_SETTINGS:
1372         {
1373                 struct dvb_frontend_tune_settings* fesettings = (struct dvb_frontend_tune_settings*) arg;
1374                 fesettings->min_delay_ms = 800;
1375                 fesettings->step_size = 166667;
1376                 fesettings->max_drift = 166667*2;
1377                 return 0;
1378         }
1379
1380         default:
1381                 return -EOPNOTSUPP;
1382         }
1383
1384         return 0;
1385 }
1386
1387
1388 static int tda1004x_attach(struct dvb_i2c_bus *i2c, void **data)
1389 {
1390         int tda1004x_address = -1;
1391         int tuner_address = -1;
1392         int fe_type = -1;
1393         int tuner_type = -1;
1394         struct tda1004x_state tda_state;
1395         struct tda1004x_state* ptda_state;
1396         struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=0, .len=0 };
1397         static u8 td1344_init[] = { 0x0b, 0xf5, 0x88, 0xab };
1398         static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
1399         static u8 td1316_init_tda10046h[] = { 0x0b, 0xf5, 0x80, 0xab };
1400         int status;
1401
1402         dprintk("%s\n", __FUNCTION__);
1403
1404         // probe for tda10045h
1405         if (tda1004x_address == -1) {
1406                 tda_state.tda1004x_address = 0x08;
1407         if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x25) {
1408                         tda1004x_address = 0x08;
1409                         fe_type = FE_TYPE_TDA10045H;
1410                 printk("tda1004x: Detected Philips TDA10045H.\n");
1411         }
1412         }
1413
1414         // probe for tda10046h
1415         if (tda1004x_address == -1) {
1416                 tda_state.tda1004x_address = 0x08;
1417                 if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x46) {
1418                         tda1004x_address = 0x08;
1419                         fe_type = FE_TYPE_TDA10046H;
1420                         printk("tda1004x: Detected Philips TDA10046H.\n");
1421                 }
1422         }
1423
1424         // did we find a frontend?
1425         if (tda1004x_address == -1) {
1426                 return -ENODEV;
1427         }
1428
1429         // enable access to the tuner
1430         tda1004x_enable_tuner_i2c(i2c, &tda_state);
1431
1432         // check for a TD1344 first
1433         if (tuner_address == -1) {
1434                 tuner_msg.addr = 0x61;
1435         tuner_msg.buf = td1344_init;
1436         tuner_msg.len = sizeof(td1344_init);
1437         if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1438                 dvb_delay(1);
1439                         tuner_address = 0x61;
1440                         tuner_type = TUNER_TYPE_TD1344;
1441                         printk("tda1004x: Detected Philips TD1344 tuner.\n");
1442                 }
1443         }
1444
1445         // OK, try a TD1316 on address 0x63
1446         if (tuner_address == -1) {
1447                 tuner_msg.addr = 0x63;
1448                 tuner_msg.buf = td1316_init;
1449                 tuner_msg.len = sizeof(td1316_init);
1450                 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1451                         dvb_delay(1);
1452                         tuner_address = 0x63;
1453                         tuner_type = TUNER_TYPE_TD1316;
1454                         printk("tda1004x: Detected Philips TD1316 tuner.\n");
1455                 }
1456         }
1457
1458         // OK, TD1316 again, on address 0x60 (TDA10046H)
1459         if (tuner_address == -1) {
1460                 tuner_msg.addr = 0x60;
1461                 tuner_msg.buf = td1316_init_tda10046h;
1462                 tuner_msg.len = sizeof(td1316_init_tda10046h);
1463                 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1464                         dvb_delay(1);
1465                         tuner_address = 0x60;
1466                         tuner_type = TUNER_TYPE_TD1316;
1467                         printk("tda1004x: Detected Philips TD1316 tuner.\n");
1468                 }
1469         }
1470         tda1004x_disable_tuner_i2c(i2c, &tda_state);
1471
1472         // did we find a tuner?
1473         if (tuner_address == -1) {
1474                 printk("tda1004x: Detected, but with unknown tuner.\n");
1475                 return -ENODEV;
1476         }
1477
1478         // create state
1479         tda_state.tda1004x_address = tda1004x_address;
1480         tda_state.fe_type = fe_type;
1481         tda_state.tuner_address = tuner_address;
1482         tda_state.tuner_type = tuner_type;
1483         tda_state.initialised = 0;
1484
1485         // upload firmware
1486         if ((status = tda1004x_fwupload(i2c, &tda_state)) != 0) return status;
1487
1488         // create the real state we'll be passing about
1489         if ((ptda_state = (struct tda1004x_state*) kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL)) == NULL) {
1490                 return -ENOMEM;
1491         }
1492         memcpy(ptda_state, &tda_state, sizeof(struct tda1004x_state));
1493         *data = ptda_state;
1494
1495         // register
1496         switch(tda_state.fe_type) {
1497         case FE_TYPE_TDA10045H:
1498                 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10045h_info);
1499
1500         case FE_TYPE_TDA10046H:
1501                 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10046h_info);
1502         }
1503
1504         // should not get here
1505         return -EINVAL;
1506 }
1507
1508
1509 static
1510 void tda1004x_detach(struct dvb_i2c_bus *i2c, void *data)
1511 {
1512         dprintk("%s\n", __FUNCTION__);
1513
1514         kfree(data);
1515         dvb_unregister_frontend(tda1004x_ioctl, i2c);
1516 }
1517
1518
1519 static
1520 int __init init_tda1004x(void)
1521 {
1522         return dvb_register_i2c_device(THIS_MODULE, tda1004x_attach, tda1004x_detach);
1523 }
1524
1525
1526 static
1527 void __exit exit_tda1004x(void)
1528 {
1529         dvb_unregister_i2c_device(tda1004x_attach);
1530 }
1531
1532 module_init(init_tda1004x);
1533 module_exit(exit_tda1004x);
1534
1535 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Frontend");
1536 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1537 MODULE_LICENSE("GPL");
1538
1539 MODULE_PARM(tda1004x_debug, "i");
1540 MODULE_PARM_DESC(tda1004x_debug, "enable verbose debug messages");
1541
1542 MODULE_PARM(tda1004x_firmware, "s");
1543 MODULE_PARM_DESC(tda1004x_firmware, "Where to find the firmware file");