drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Frontend
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22
  23 /*
  24     This driver needs a copy of the DLL "ttlcdacc.dll" from the Haupauge or Technotrend
  25     windows driver saved as '/usr/lib/hotplug/firmware/tda1004x.bin'.
  26     You can also pass the complete file name with the module parameter 'tda1004x_firmware'.
  27
  28     Currently the DLL from v2.15a of the technotrend driver is supported. Other versions can
  29     be added reasonably painlessly.
  30
  31     Windows driver URL: http://www.technotrend.de/
  32  */
  33
  34
  35 #include <linux/kernel.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41 #include <linux/fs.h>
  42 #include <linux/fcntl.h>
  43 #include <linux/errno.h>
  44 #include <linux/syscalls.h>
  45
  46 #include "dvb_frontend.h"
  47 #include "dvb_functions.h"
  48
  49 #ifndef DVB_TDA1004X_FIRMWARE_FILE
  50 #define DVB_TDA1004X_FIRMWARE_FILE "/usr/lib/hotplug/firmware/tda1004x.bin"
  51 #endif
  52
  53 static int tda1004x_debug = 0;
  54 static char *tda1004x_firmware = DVB_TDA1004X_FIRMWARE_FILE;
  55
  56 #define MC44BC374_ADDRESS        0x65
  57
  58 #define TDA1004X_CHIPID          0x00
  59 #define TDA1004X_AUTO            0x01
  60 #define TDA1004X_IN_CONF1        0x02
  61 #define TDA1004X_IN_CONF2        0x03
  62 #define TDA1004X_OUT_CONF1       0x04
  63 #define TDA1004X_OUT_CONF2       0x05
  64 #define TDA1004X_STATUS_CD       0x06
  65 #define TDA1004X_CONFC4          0x07
  66 #define TDA1004X_DSSPARE2        0x0C
  67 #define TDA10045H_CODE_IN        0x0D
  68 #define TDA10045H_FWPAGE         0x0E
  69 #define TDA1004X_SCAN_CPT        0x10
  70 #define TDA1004X_DSP_CMD         0x11
  71 #define TDA1004X_DSP_ARG         0x12
  72 #define TDA1004X_DSP_DATA1       0x13
  73 #define TDA1004X_DSP_DATA2       0x14
  74 #define TDA1004X_CONFADC1        0x15
  75 #define TDA1004X_CONFC1          0x16
  76 #define TDA10045H_S_AGC          0x1a
  77 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  78 #define TDA1004X_SNR             0x1c
  79 #define TDA1004X_CONF_TS1        0x1e
  80 #define TDA1004X_CONF_TS2        0x1f
  81 #define TDA1004X_CBER_RESET      0x20
  82 #define TDA1004X_CBER_MSB        0x21
  83 #define TDA1004X_CBER_LSB        0x22
  84 #define TDA1004X_CVBER_LUT       0x23
  85 #define TDA1004X_VBER_MSB        0x24
  86 #define TDA1004X_VBER_MID        0x25
  87 #define TDA1004X_VBER_LSB        0x26
  88 #define TDA1004X_UNCOR           0x27
  89
  90 #define TDA10045H_CONFPLL_P      0x2D
  91 #define TDA10045H_CONFPLL_M_MSB  0x2E
  92 #define TDA10045H_CONFPLL_M_LSB  0x2F
  93 #define TDA10045H_CONFPLL_N      0x30
  94
  95 #define TDA10046H_CONFPLL1       0x2D
  96 #define TDA10046H_CONFPLL2       0x2F
  97 #define TDA10046H_CONFPLL3       0x30
  98 #define TDA10046H_TIME_WREF1     0x31
  99 #define TDA10046H_TIME_WREF2     0x32
 100 #define TDA10046H_TIME_WREF3     0x33
 101 #define TDA10046H_TIME_WREF4     0x34
 102 #define TDA10046H_TIME_WREF5     0x35
 103
 104 #define TDA10045H_UNSURW_MSB     0x31
 105 #define TDA10045H_UNSURW_LSB     0x32
 106 #define TDA10045H_WREF_MSB       0x33
 107 #define TDA10045H_WREF_MID       0x34
 108 #define TDA10045H_WREF_LSB       0x35
 109 #define TDA10045H_MUXOUT         0x36
 110 #define TDA1004X_CONFADC2        0x37
 111
 112 #define TDA10045H_IOFFSET        0x38
 113
 114 #define TDA10046H_CONF_TRISTATE1 0x3B
 115 #define TDA10046H_CONF_TRISTATE2 0x3C
 116 #define TDA10046H_CONF_POLARITY  0x3D
 117 #define TDA10046H_FREQ_OFFSET    0x3E
 118 #define TDA10046H_GPIO_OUT_SEL   0x41
 119 #define TDA10046H_GPIO_SELECT    0x42
 120 #define TDA10046H_AGC_CONF       0x43
 121 #define TDA10046H_AGC_GAINS      0x46
 122 #define TDA10046H_AGC_TUN_MIN    0x47
 123 #define TDA10046H_AGC_TUN_MAX    0x48
 124 #define TDA10046H_AGC_IF_MIN     0x49
 125 #define TDA10046H_AGC_IF_MAX     0x4A
 126
 127 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 128 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 129
 130 #define TDA10046H_CVBER_CTRL     0x4F
 131 #define TDA10046H_AGC_IF_LEVEL   0x52
 132 #define TDA10046H_CODE_CPT       0x57
 133 #define TDA10046H_CODE_IN        0x58
 134
 135
 136 #define FE_TYPE_TDA10045H     0
 137 #define FE_TYPE_TDA10046H     1
 138
 139 #define TUNER_TYPE_TD1344     0
 140 #define TUNER_TYPE_TD1316     1
 141
 142 #define dprintk if (tda1004x_debug) printk
 143
 144 static struct dvb_frontend_info tda10045h_info = {
 145         .name = "Philips TDA10045H",
 146         .type = FE_OFDM,
 147         .frequency_min = 51000000,
 148         .frequency_max = 858000000,
 149         .frequency_stepsize = 166667,
 150         .caps =
 151             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 152             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 153             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 154             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
 155 };
 156
 157 static struct dvb_frontend_info tda10046h_info = {
 158         .name = "Philips TDA10046H",
 159         .type = FE_OFDM,
 160         .frequency_min = 51000000,
 161         .frequency_max = 858000000,
 162         .frequency_stepsize = 166667,
 163         .caps =
 164             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 165             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 166             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 167             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
 168 };
 169
 170
 171 struct tda1004x_state {
 172         u8 tda1004x_address;
 173         u8 tuner_address;
 174         u8 initialised:1;
 175         u8 tuner_type:2;
 176         u8 fe_type:2;
 177 };
 178
 179
 180 struct fwinfo {
 181         int file_size;
 182         int fw_offset;
 183         int fw_size;
 184 };
 185 static struct fwinfo tda10045h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x34cc5,.fw_size = 30555} };
 186 static int tda10045h_fwinfo_count = sizeof(tda10045h_fwinfo) / sizeof(struct fwinfo);
 187
 188 static struct fwinfo tda10046h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x3c4f9,.fw_size = 24479} };
 189 static int tda10046h_fwinfo_count = sizeof(tda10046h_fwinfo) / sizeof(struct fwinfo);
 190
 191 static int errno;
 192
 193
 194 static int tda1004x_write_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int data)
 195 {
 196         int ret;
 197         u8 buf[] = { reg, data };
 198         struct i2c_msg msg = { .addr=0, .flags=0, .buf=buf, .len=2 };
 199
 200         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 201
 202         msg.addr = tda_state->tda1004x_address;
 203         ret = i2c->xfer(i2c, &msg, 1);
 204
 205         if (ret != 1)
 206                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 207                        __FUNCTION__, reg, data, ret);
 208
 209         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 210                 reg, data, ret);
 211         return (ret != 1) ? -1 : 0;
 212 }
 213
 214 static int tda1004x_read_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg)
 215 {
 216         int ret;
 217         u8 b0[] = { reg };
 218         u8 b1[] = { 0 };
 219         struct i2c_msg msg[] = {{ .addr=0, .flags=0, .buf=b0, .len=1},
 220                                 { .addr=0, .flags=I2C_M_RD, .buf=b1, .len = 1}};
 221
 222         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 223
 224         msg[0].addr = tda_state->tda1004x_address;
 225         msg[1].addr = tda_state->tda1004x_address;
 226         ret = i2c->xfer(i2c, msg, 2);
 227
 228         if (ret != 2) {
 229                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 230                        ret);
 231                 return -1;
 232         }
 233
 234         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 235                 reg, b1[0], ret);
 236         return b1[0];
 237 }
 238
 239 static int tda1004x_write_mask(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int mask, int data)
 240 {
 241         int val;
 242         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 243                 mask, data);
 244
 245         // read a byte and check
 246         val = tda1004x_read_byte(i2c, tda_state, reg);
 247         if (val < 0)
 248                 return val;
 249
 250         // mask if off
 251         val = val & ~mask;
 252         val |= data & 0xff;
 253
 254         // write it out again
 255         return tda1004x_write_byte(i2c, tda_state, reg, val);
 256 }
 257
 258 static int tda1004x_write_buf(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, unsigned char *buf, int len)
 259 {
 260         int i;
 261         int result;
 262
 263         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 264
 265         result = 0;
 266         for (i = 0; i < len; i++) {
 267                 result = tda1004x_write_byte(i2c, tda_state, reg + i, buf[i]);
 268                 if (result != 0)
 269                         break;
 270         }
 271
 272         return result;
 273 }
 274
 275 static int tda1004x_enable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 276 {
 277         int result;
 278         dprintk("%s\n", __FUNCTION__);
 279
 280         result = tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 2);
 281         dvb_delay(1);
 282         return result;
 283 }
 284
 285 static int tda1004x_disable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 286 {
 287
 288         dprintk("%s\n", __FUNCTION__);
 289
 290         return tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 0);
 291 }
 292
 293
 294 static int tda10045h_set_bandwidth(struct dvb_i2c_bus *i2c,
 295                                    struct tda1004x_state *tda_state,
 296                                    fe_bandwidth_t bandwidth)
 297 {
 298         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 299         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 300         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 301
 302         switch (bandwidth) {
 303         case BANDWIDTH_6_MHZ:
 304                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
 305                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 306                 break;
 307
 308         case BANDWIDTH_7_MHZ:
 309                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x80);
 310                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 311                 break;
 312
 313         case BANDWIDTH_8_MHZ:
 314                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
 315                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 316                 break;
 317
 318         default:
 319                 return -EINVAL;
 320         }
 321
 322         tda1004x_write_byte(i2c, tda_state, TDA10045H_IOFFSET, 0);
 323
 324         // done
 325         return 0;
 326 }
 327
 328
 329 static int tda10046h_set_bandwidth(struct dvb_i2c_bus *i2c,
 330                                    struct tda1004x_state *tda_state,
 331                                    fe_bandwidth_t bandwidth)
 332 {
 333         static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
 334         static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
 335         static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
 336
 337         switch (bandwidth) {
 338         case BANDWIDTH_6_MHZ:
 339                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 340                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
 341                 break;
 342
 343         case BANDWIDTH_7_MHZ:
 344                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 345                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
 346                 break;
 347
 348         case BANDWIDTH_8_MHZ:
 349                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 350                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0xFF);
 351                 break;
 352
 353         default:
 354                 return -EINVAL;
 355         }
 356
 357         // done
 358         return 0;
 359 }
 360
 361
 362 static int tda1004x_fwupload(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 363 {
 364         u8 fw_buf[65];
 365         struct i2c_msg fw_msg = {.addr = 0,.flags = 0,.buf = fw_buf,.len = 0 };
 366         unsigned char *firmware = NULL;
 367         int filesize;
 368         int fd;
 369         int fwinfo_idx;
 370         int fw_size = 0;
 371         int fw_pos, fw_offset;
 372         int tx_size;
 373         mm_segment_t fs = get_fs();
 374         int dspCodeCounterReg=0, dspCodeInReg=0, dspVersion=0;
 375         int fwInfoCount=0;
 376         struct fwinfo* fwInfo = NULL;
 377         unsigned long timeout;
 378
 379         // DSP parameters
 380         switch(tda_state->fe_type) {
 381         case FE_TYPE_TDA10045H:
 382                 dspCodeCounterReg = TDA10045H_FWPAGE;
 383                 dspCodeInReg = TDA10045H_CODE_IN;
 384                 dspVersion = 0x2c;
 385                 fwInfoCount = tda10045h_fwinfo_count;
 386                 fwInfo = tda10045h_fwinfo;
 387                 break;
 388
 389         case FE_TYPE_TDA10046H:
 390                 dspCodeCounterReg = TDA10046H_CODE_CPT;
 391                 dspCodeInReg = TDA10046H_CODE_IN;
 392                 dspVersion = 0x20;
 393                 fwInfoCount = tda10046h_fwinfo_count;
 394                 fwInfo = tda10046h_fwinfo;
 395                 break;
 396         }
 397
 398         // Load the firmware
 399         set_fs(get_ds());
 400         fd = sys_open(tda1004x_firmware, 0, 0);
 401         if (fd < 0) {
 402                 printk("%s: Unable to open firmware %s\n", __FUNCTION__,
 403                        tda1004x_firmware);
 404                 return -EIO;
 405         }
 406         filesize = sys_lseek(fd, 0L, 2);
 407         if (filesize <= 0) {
 408                 printk("%s: Firmware %s is empty\n", __FUNCTION__,
 409                        tda1004x_firmware);
 410                 sys_close(fd);
 411                 return -EIO;
 412         }
 413
 414         // find extraction parameters for firmware
 415         for (fwinfo_idx = 0; fwinfo_idx < fwInfoCount; fwinfo_idx++) {
 416                 if (fwInfo[fwinfo_idx].file_size == filesize)
 417                         break;
 418         }
 419         if (fwinfo_idx >= fwInfoCount) {
 420                 printk("%s: Unsupported firmware %s\n", __FUNCTION__, tda1004x_firmware);
 421                 sys_close(fd);
 422                 return -EIO;
 423         }
 424         fw_size = fwInfo[fwinfo_idx].fw_size;
 425         fw_offset = fwInfo[fwinfo_idx].fw_offset;
 426
 427         // allocate buffer for it
 428         firmware = vmalloc(fw_size);
 429         if (firmware == NULL) {
 430                 printk("%s: Out of memory loading firmware\n",
 431                        __FUNCTION__);
 432                 sys_close(fd);
 433                 return -EIO;
 434         }
 435
 436         // read it!
 437         sys_lseek(fd, fw_offset, 0);
 438         if (sys_read(fd, firmware, fw_size) != fw_size) {
 439                 printk("%s: Failed to read firmware\n", __FUNCTION__);
 440                 vfree(firmware);
 441                 sys_close(fd);
 442                 return -EIO;
 443         }
 444         sys_close(fd);
 445         set_fs(fs);
 446
 447         // set some valid bandwith parameters before uploading
 448         switch(tda_state->fe_type) {
 449         case FE_TYPE_TDA10045H:
 450                 // reset chip
 451                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0);
 452                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
 453                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
 454                 dvb_delay(10);
 455
 456                 // set parameters
 457                 tda10045h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ);
 458                 break;
 459
 460         case FE_TYPE_TDA10046H:
 461                 // reset chip
 462                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0);
 463                 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 1, 0);
 464                 dvb_delay(10);
 465
 466                 // set parameters
 467                 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10);
 468                 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0);
 469                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99);
 470                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 471                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
 472                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 473                 break;
 474         }
 475
 476         // do the firmware upload
 477         tda1004x_write_byte(i2c, tda_state, dspCodeCounterReg, 0); // clear code counter
 478         fw_msg.addr = tda_state->tda1004x_address;
 479         fw_pos = 0;
 480         while (fw_pos != fw_size) {
 481
 482                 // work out how much to send this time
 483                 tx_size = fw_size - fw_pos;
 484                 if (tx_size > 0x10) {
 485                         tx_size = 0x10;
 486                 }
 487
 488                 // send the chunk
 489                 fw_buf[0] = dspCodeInReg;
 490                 memcpy(fw_buf + 1, firmware + fw_pos, tx_size);
 491                 fw_msg.len = tx_size + 1;
 492                 if (i2c->xfer(i2c, &fw_msg, 1) != 1) {
 493                         printk("tda1004x: Error during firmware upload\n");
 494                         vfree(firmware);
 495                         return -EIO;
 496                 }
 497                 fw_pos += tx_size;
 498
 499                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, fw_pos);
 500         }
 501         vfree(firmware);
 502
 503         // wait for DSP to initialise
 504         switch(tda_state->fe_type) {
 505         case FE_TYPE_TDA10045H:
 506                 // DSPREADY doesn't seem to work on the TDA10045H
 507                 dvb_delay(100);
 508                 break;
 509
 510         case FE_TYPE_TDA10046H:
 511                 timeout = jiffies + HZ;
 512                 while(!(tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD) & 0x20)) {
 513                         if (time_after(jiffies, timeout)) {
 514                                 printk("tda1004x: DSP failed to initialised.\n");
 515                                 return -EIO;
 516                         }
 517
 518                         dvb_delay(1);
 519                 }
 520                 break;
 521         }
 522
 523         // check upload was OK
 524         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 525         tda1004x_write_byte(i2c, tda_state, TDA1004X_DSP_CMD, 0x67);
 526         if ((tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA1) != 0x67) ||
 527             (tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA2) != dspVersion)) {
 528                 printk("%s: firmware upload failed!\n", __FUNCTION__);
 529                 return -EIO;
 530         }
 531
 532         // success
 533         return 0;
 534 }
 535
 536
 537 static int tda10045h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 538 {
 539         struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = NULL,.len = 0 };
 540         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 541
 542         dprintk("%s\n", __FUNCTION__);
 543
 544         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 545
 546         // Disable the MC44BC374C
 547         tda1004x_enable_tuner_i2c(i2c, tda_state);
 548         tuner_msg.addr = MC44BC374_ADDRESS;
 549         tuner_msg.buf = disable_mc44BC374c;
 550         tuner_msg.len = sizeof(disable_mc44BC374c);
 551         if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 552                 i2c->xfer(i2c, &tuner_msg, 1);
 553         }
 554         tda1004x_disable_tuner_i2c(i2c, tda_state);
 555
 556         // tda setup
 557         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 558         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
 559         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0); // no frequency inversion
 560         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 561         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 562         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 563         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 564         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 565         tda1004x_write_mask(i2c, tda_state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 566         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 567         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONFADC1, 0x2e);
 568
 569         // done
 570         return 0;
 571 }
 572
 573
 574
 575 static int tda10046h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 576 {
 577         struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = NULL,.len = 0 };
 578         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 579
 580         dprintk("%s\n", __FUNCTION__);
 581
 582         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0); // wake up the chip
 583
 584         // Disable the MC44BC374C
 585         tda1004x_enable_tuner_i2c(i2c, tda_state);
 586         tuner_msg.addr = MC44BC374_ADDRESS;
 587         tuner_msg.buf = disable_mc44BC374c;
 588         tuner_msg.len = sizeof(disable_mc44BC374c);
 589         if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 590                 i2c->xfer(i2c, &tuner_msg, 1);
 591         }
 592         tda1004x_disable_tuner_i2c(i2c, tda_state);
 593
 594         // tda setup
 595         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 596         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0x40); // TT TDA10046H needs inversion ON
 597         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
 598         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
 599         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10); // PLL M = 10
 600         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 601         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
 602         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
 603         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
 604         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_CONF, 0); // AGC setup
 605         tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
 606         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MIN, 0);    // }
 607         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 608         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MIN, 0);     // }
 609         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 610         tda1004x_write_mask(i2c, tda_state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
 611         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
 612         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
 613         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 614         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
 615         tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
 616         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
 617         tda1004x_write_byte(i2c, tda_state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
 618         tda1004x_write_mask(i2c, tda_state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
 619         tda10046h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 620
 621         // done
 622         return 0;
 623 }
 624
 625
 626
 627 static int tda1004x_encode_fec(int fec)
 628 {
 629         // convert known FEC values
 630         switch (fec) {
 631         case FEC_1_2:
 632                 return 0;
 633         case FEC_2_3:
 634                 return 1;
 635         case FEC_3_4:
 636                 return 2;
 637         case FEC_5_6:
 638                 return 3;
 639         case FEC_7_8:
 640                 return 4;
 641         }
 642
 643         // unsupported
 644         return -EINVAL;
 645 }
 646
 647 static int tda1004x_decode_fec(int tdafec)
 648 {
 649         // convert known FEC values
 650         switch (tdafec) {
 651         case 0:
 652                 return FEC_1_2;
 653         case 1:
 654                 return FEC_2_3;
 655         case 2:
 656                 return FEC_3_4;
 657         case 3:
 658                 return FEC_5_6;
 659         case 4:
 660                 return FEC_7_8;
 661         }
 662
 663         // unsupported
 664         return -1;
 665 }
 666
 667 static int tda1004x_set_frequency(struct dvb_i2c_bus *i2c,
 668                            struct tda1004x_state *tda_state,
 669                            struct dvb_frontend_parameters *fe_params)
 670 {
 671         u8 tuner_buf[4];
 672         struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=tuner_buf, .len=sizeof(tuner_buf) };
 673         int tuner_frequency = 0;
 674         u8 band, cp, filter;
 675         int counter, counter2;
 676
 677         dprintk("%s\n", __FUNCTION__);
 678
 679         // setup the frequency buffer
 680         switch (tda_state->tuner_type) {
 681         case TUNER_TYPE_TD1344:
 682
 683                 // setup tuner buffer
 684                 // ((Fif+((1000000/6)/2)) + Finput)/(1000000/6)
 685                 tuner_frequency =
 686                         (((fe_params->frequency / 1000) * 6) + 217502) / 1000;
 687                 tuner_buf[0] = tuner_frequency >> 8;
 688                 tuner_buf[1] = tuner_frequency & 0xff;
 689                 tuner_buf[2] = 0x88;
 690                 if (fe_params->frequency < 550000000) {
 691                         tuner_buf[3] = 0xab;
 692                 } else {
 693                         tuner_buf[3] = 0xeb;
 694                 }
 695
 696                 // tune it
 697                 tda1004x_enable_tuner_i2c(i2c, tda_state);
 698                 tuner_msg.addr = tda_state->tuner_address;
 699                 tuner_msg.len = 4;
 700                 i2c->xfer(i2c, &tuner_msg, 1);
 701
 702                 // wait for it to finish
 703                 tuner_msg.len = 1;
 704                 tuner_msg.flags = I2C_M_RD;
 705                 counter = 0;
 706                 counter2 = 0;
 707                 while (counter++ < 100) {
 708                         if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
 709                                 if (tuner_buf[0] & 0x40) {
 710                                         counter2++;
 711                                 } else {
 712                                         counter2 = 0;
 713                                 }
 714                         }
 715
 716                         if (counter2 > 10) {
 717                                 break;
 718                         }
 719                 }
 720                 tda1004x_disable_tuner_i2c(i2c, tda_state);
 721                 break;
 722
 723         case TUNER_TYPE_TD1316:
 724                 // determine charge pump
 725                 tuner_frequency = fe_params->frequency + 36130000;
 726                 if (tuner_frequency < 87000000) {
 727                         return -EINVAL;
 728                 } else if (tuner_frequency < 130000000) {
 729                         cp = 3;
 730                 } else if (tuner_frequency < 160000000) {
 731                         cp = 5;
 732                 } else if (tuner_frequency < 200000000) {
 733                         cp = 6;
 734                 } else if (tuner_frequency < 290000000) {
 735                         cp = 3;
 736                 } else if (tuner_frequency < 420000000) {
 737                         cp = 5;
 738                 } else if (tuner_frequency < 480000000) {
 739                         cp = 6;
 740                 } else if (tuner_frequency < 620000000) {
 741                         cp = 3;
 742                 } else if (tuner_frequency < 830000000) {
 743                         cp = 5;
 744                 } else if (tuner_frequency < 895000000) {
 745                         cp = 7;
 746                 } else {
 747                         return -EINVAL;
 748                 }
 749
 750                 // determine band
 751                 if (fe_params->frequency < 49000000) {
 752                         return -EINVAL;
 753                 } else if (fe_params->frequency < 159000000) {
 754                         band = 1;
 755                 } else if (fe_params->frequency < 444000000) {
 756                         band = 2;
 757                 } else if (fe_params->frequency < 861000000) {
 758                         band = 4;
 759                 } else {
 760                         return -EINVAL;
 761                 }
 762
 763                 // work out filter
 764                 switch (fe_params->u.ofdm.bandwidth) {
 765                 case BANDWIDTH_6_MHZ:
 766                         filter = 0;
 767                         break;
 768
 769                 case BANDWIDTH_7_MHZ:
 770                         filter = 0;
 771                         break;
 772
 773                 case BANDWIDTH_8_MHZ:
 774                         filter = 1;
 775                         break;
 776
 777                 default:
 778                         return -EINVAL;
 779                 }
 780
 781                 // calculate divisor
 782                 // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
 783                 tuner_frequency =
 784                         (((fe_params->frequency / 1000) * 6) + 217280) / 1000;
 785
 786                 // setup tuner buffer
 787                 tuner_buf[0] = tuner_frequency >> 8;
 788                 tuner_buf[1] = tuner_frequency & 0xff;
 789                 tuner_buf[2] = 0xca;
 790                 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
 791
 792                 // tune it
 793                 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
 794                         // setup auto offset
 795                         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10);
 796                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x80, 0);
 797                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0);
 798
 799                         // disable agc_conf[2]
 800                         tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 0);
 801                 }
 802                 tda1004x_enable_tuner_i2c(i2c, tda_state);
 803                 tuner_msg.addr = tda_state->tuner_address;
 804                 tuner_msg.len = 4;
 805                 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 806                         return -EIO;
 807                 }
 808                 dvb_delay(1);
 809                 tda1004x_disable_tuner_i2c(i2c, tda_state);
 810                 if (tda_state->fe_type == FE_TYPE_TDA10046H)
 811                         tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 4);
 812                 break;
 813
 814         default:
 815                 return -EINVAL;
 816         }
 817
 818         dprintk("%s: success\n", __FUNCTION__);
 819
 820         // done
 821         return 0;
 822 }
 823
 824 static int tda1004x_set_fe(struct dvb_i2c_bus *i2c,
 825                            struct tda1004x_state *tda_state,
 826                            struct dvb_frontend_parameters *fe_params)
 827 {
 828         int tmp;
 829         int inversion;
 830
 831         dprintk("%s\n", __FUNCTION__);
 832
 833         // set frequency
 834         if ((tmp = tda1004x_set_frequency(i2c, tda_state, fe_params)) < 0)
 835                 return tmp;
 836
 837         // hardcoded to use auto as much as possible
 838         fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 839         fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 840         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 841
 842         // Set standard params.. or put them to auto
 843         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 844             (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 845             (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 846             (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 847                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 1);       // enable auto
 848                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x03, 0);        // turn off constellation bits
 849                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0);        // turn off hierarchy bits
 850                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x3f, 0);        // turn off FEC bits
 851         } else {
 852                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 0);       // disable auto
 853
 854                 // set HP FEC
 855                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 856                 if (tmp < 0) return tmp;
 857                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 7, tmp);
 858
 859                 // set LP FEC
 860                 if (fe_params->u.ofdm.code_rate_LP != FEC_NONE) {
 861                         tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 862                         if (tmp < 0) return tmp;
 863                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 864                 }
 865
 866                 // set constellation
 867                 switch (fe_params->u.ofdm.constellation) {
 868                 case QPSK:
 869                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 0);
 870                         break;
 871
 872                 case QAM_16:
 873                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 1);
 874                         break;
 875
 876                 case QAM_64:
 877                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 2);
 878                         break;
 879
 880                 default:
 881                         return -EINVAL;
 882                 }
 883
 884                 // set hierarchy
 885                 switch (fe_params->u.ofdm.hierarchy_information) {
 886                 case HIERARCHY_NONE:
 887                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 888                         break;
 889
 890                 case HIERARCHY_1:
 891                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 892                         break;
 893
 894                 case HIERARCHY_2:
 895                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 896                         break;
 897
 898                 case HIERARCHY_4:
 899                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 900                         break;
 901
 902                 default:
 903                         return -EINVAL;
 904                 }
 905         }
 906
 907         // set bandwidth
 908         switch(tda_state->fe_type) {
 909         case FE_TYPE_TDA10045H:
 910                 tda10045h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
 911                 break;
 912
 913         case FE_TYPE_TDA10046H:
 914                 tda10046h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
 915                 break;
 916         }
 917
 918         // need to invert the inversion for TT TDA10046H
 919         inversion = fe_params->inversion;
 920         if (tda_state->fe_type == FE_TYPE_TDA10046H) {
 921                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 922         }
 923
 924         // set inversion
 925         switch (inversion) {
 926         case INVERSION_OFF:
 927                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0);
 928                 break;
 929
 930         case INVERSION_ON:
 931                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0x20);
 932                 break;
 933
 934         default:
 935                 return -EINVAL;
 936         }
 937
 938         // set guard interval
 939         switch (fe_params->u.ofdm.guard_interval) {
 940         case GUARD_INTERVAL_1_32:
 941                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 942                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 943                 break;
 944
 945         case GUARD_INTERVAL_1_16:
 946                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 947                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 948                 break;
 949
 950         case GUARD_INTERVAL_1_8:
 951                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 952                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 953                 break;
 954
 955         case GUARD_INTERVAL_1_4:
 956                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 957                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 958                 break;
 959
 960         case GUARD_INTERVAL_AUTO:
 961                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 2);
 962                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 963                 break;
 964
 965         default:
 966                 return -EINVAL;
 967         }
 968
 969         // set transmission mode
 970         switch (fe_params->u.ofdm.transmission_mode) {
 971         case TRANSMISSION_MODE_2K:
 972                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
 973                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 974                 break;
 975
 976         case TRANSMISSION_MODE_8K:
 977                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
 978                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 979                 break;
 980
 981         case TRANSMISSION_MODE_AUTO:
 982                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 4);
 983                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0);
 984                 break;
 985
 986         default:
 987                 return -EINVAL;
 988         }
 989
 990         // start the lock
 991         switch(tda_state->fe_type) {
 992         case FE_TYPE_TDA10045H:
 993         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
 994         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
 995         dvb_delay(10);
 996                 break;
 997
 998         case FE_TYPE_TDA10046H:
 999                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x40, 0x40);
1000                 dvb_delay(10);
1001                 break;
1002         }
1003
1004         // done
1005         return 0;
1006 }
1007
1008
1009 static int tda1004x_get_fe(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, struct dvb_frontend_parameters *fe_params)
1010 {
1011
1012         dprintk("%s\n", __FUNCTION__);
1013
1014         // inversion status
1015         fe_params->inversion = INVERSION_OFF;
1016         if (tda1004x_read_byte(i2c, tda_state, TDA1004X_CONFC1) & 0x20) {
1017                 fe_params->inversion = INVERSION_ON;
1018         }
1019
1020         // need to invert the inversion for TT TDA10046H
1021         if (tda_state->fe_type == FE_TYPE_TDA10046H) {
1022                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
1023         }
1024
1025         // bandwidth
1026         switch(tda_state->fe_type) {
1027         case FE_TYPE_TDA10045H:
1028                 switch (tda1004x_read_byte(i2c, tda_state, TDA10045H_WREF_LSB)) {
1029         case 0x14:
1030                 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1031                 break;
1032         case 0xdb:
1033                 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1034                 break;
1035         case 0x4f:
1036                 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1037                 break;
1038         }
1039                 break;
1040
1041         case FE_TYPE_TDA10046H:
1042                 switch (tda1004x_read_byte(i2c, tda_state, TDA10046H_TIME_WREF1)) {
1043                 case 0x60:
1044                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1045                         break;
1046                 case 0x6e:
1047                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1048                         break;
1049                 case 0x80:
1050                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1051                         break;
1052                 }
1053                 break;
1054         }
1055
1056         // FEC
1057         fe_params->u.ofdm.code_rate_HP =
1058             tda1004x_decode_fec(tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) & 7);
1059         fe_params->u.ofdm.code_rate_LP =
1060             tda1004x_decode_fec((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) >> 3) & 7);
1061
1062         // constellation
1063         switch (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 3) {
1064         case 0:
1065                 fe_params->u.ofdm.constellation = QPSK;
1066                 break;
1067         case 1:
1068                 fe_params->u.ofdm.constellation = QAM_16;
1069                 break;
1070         case 2:
1071                 fe_params->u.ofdm.constellation = QAM_64;
1072                 break;
1073         }
1074
1075         // transmission mode
1076         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1077         if (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x10) {
1078                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1079         }
1080
1081         // guard interval
1082         switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
1083         case 0:
1084                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1085                 break;
1086         case 1:
1087                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1088                 break;
1089         case 2:
1090                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1091                 break;
1092         case 3:
1093                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1094                 break;
1095         }
1096
1097         // hierarchy
1098         switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
1099         case 0:
1100                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1101                 break;
1102         case 1:
1103                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
1104                 break;
1105         case 2:
1106                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
1107                 break;
1108         case 3:
1109                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
1110                 break;
1111         }
1112
1113         // done
1114         return 0;
1115 }
1116
1117
1118 static int tda1004x_read_status(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, fe_status_t * fe_status)
1119 {
1120         int status;
1121         int cber;
1122         int vber;
1123
1124         dprintk("%s\n", __FUNCTION__);
1125
1126         // read status
1127         status = tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD);
1128         if (status == -1) {
1129                 return -EIO;
1130         }
1131
1132         // decode
1133         *fe_status = 0;
1134         if (status & 4) *fe_status |= FE_HAS_SIGNAL;
1135         if (status & 2) *fe_status |= FE_HAS_CARRIER;
1136         if (status & 8) *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1137
1138         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1139         // is getting anything valid
1140         if (!(*fe_status & FE_HAS_VITERBI)) {
1141                 // read the CBER
1142                 cber = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1143                 if (cber == -1) return -EIO;
1144                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1145                 if (status == -1) return -EIO;
1146                 cber |= (status << 8);
1147                 tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1148
1149                 if (cber != 65535) {
1150                         *fe_status |= FE_HAS_VITERBI;
1151                 }
1152         }
1153
1154         // if we DO have some valid VITERBI output, but don't already have SYNC
1155         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1156         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1157                 // read the VBER
1158                 vber = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_LSB);
1159                 if (vber == -1) return -EIO;
1160                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MID);
1161                 if (status == -1) return -EIO;
1162                 vber |= (status << 8);
1163                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MSB);
1164                 if (status == -1) return -EIO;
1165                 vber |= ((status << 16) & 0x0f);
1166                 tda1004x_read_byte(i2c, tda_state, TDA1004X_CVBER_LUT);
1167
1168                 // if RS has passed some valid TS packets, then we must be
1169                 // getting some SYNC bytes
1170                 if (vber < 16632) {
1171                         *fe_status |= FE_HAS_SYNC;
1172                 }
1173         }
1174
1175         // success
1176         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1177         return 0;
1178 }
1179
1180 static int tda1004x_read_signal_strength(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * signal)
1181 {
1182         int tmp;
1183         int reg = 0;
1184
1185         dprintk("%s\n", __FUNCTION__);
1186
1187         // determine the register to use
1188         switch(tda_state->fe_type) {
1189         case FE_TYPE_TDA10045H:
1190                 reg = TDA10045H_S_AGC;
1191                 break;
1192
1193         case FE_TYPE_TDA10046H:
1194                 reg = TDA10046H_AGC_IF_LEVEL;
1195                 break;
1196         }
1197
1198         // read it
1199         tmp = tda1004x_read_byte(i2c, tda_state, reg);
1200         if (tmp < 0)
1201                 return -EIO;
1202
1203         // done
1204         *signal = (tmp << 8) | tmp;
1205         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1206         return 0;
1207 }
1208
1209
1210 static int tda1004x_read_snr(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * snr)
1211 {
1212         int tmp;
1213
1214         dprintk("%s\n", __FUNCTION__);
1215
1216         // read it
1217         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_SNR);
1218         if (tmp < 0)
1219                 return -EIO;
1220         if (tmp) {
1221                 tmp = 255 - tmp;
1222         }
1223
1224         // done
1225         *snr = ((tmp << 8) | tmp);
1226         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1227         return 0;
1228 }
1229
1230 static int tda1004x_read_ucblocks(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ucblocks)
1231 {
1232         int tmp;
1233         int tmp2;
1234         int counter;
1235
1236         dprintk("%s\n", __FUNCTION__);
1237
1238         // read the UCBLOCKS and reset
1239         counter = 0;
1240         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1241         if (tmp < 0)
1242                 return -EIO;
1243         tmp &= 0x7f;
1244         while (counter++ < 5) {
1245                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1246                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1247                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1248
1249                 tmp2 = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1250                 if (tmp2 < 0)
1251                         return -EIO;
1252                 tmp2 &= 0x7f;
1253                 if ((tmp2 < tmp) || (tmp2 == 0))
1254                         break;
1255         }
1256
1257         // done
1258         if (tmp != 0x7f) {
1259                 *ucblocks = tmp;
1260         } else {
1261                 *ucblocks = 0xffffffff;
1262         }
1263         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1264         return 0;
1265 }
1266
1267 static int tda1004x_read_ber(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ber)
1268 {
1269         int tmp;
1270
1271         dprintk("%s\n", __FUNCTION__);
1272
1273         // read it in
1274         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1275         if (tmp < 0) return -EIO;
1276         *ber = tmp << 1;
1277         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1278         if (tmp < 0) return -EIO;
1279         *ber |= (tmp << 9);
1280         tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1281
1282         // done
1283         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1284         return 0;
1285 }
1286
1287 static int tda1004x_sleep(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state)
1288 {
1289         switch(tda_state->fe_type) {
1290         case FE_TYPE_TDA10045H:
1291                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0x10);
1292                 break;
1293
1294         case FE_TYPE_TDA10046H:
1295                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 1);
1296                 break;
1297         }
1298
1299         return 0;
1300 }
1301
1302
1303 static int tda1004x_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
1304 {
1305         int status = 0;
1306         struct dvb_i2c_bus *i2c = fe->i2c;
1307         struct tda1004x_state *tda_state = (struct tda1004x_state *) fe->data;
1308
1309         dprintk("%s: cmd=0x%x\n", __FUNCTION__, cmd);
1310
1311         switch (cmd) {
1312         case FE_GET_INFO:
1313                 switch(tda_state->fe_type) {
1314                 case FE_TYPE_TDA10045H:
1315                         memcpy(arg, &tda10045h_info, sizeof(struct dvb_frontend_info));
1316                         break;
1317
1318                 case FE_TYPE_TDA10046H:
1319                         memcpy(arg, &tda10046h_info, sizeof(struct dvb_frontend_info));
1320                         break;
1321                 }
1322                 break;
1323
1324         case FE_READ_STATUS:
1325                 return tda1004x_read_status(i2c, tda_state, (fe_status_t *) arg);
1326
1327         case FE_READ_BER:
1328                 return tda1004x_read_ber(i2c, tda_state, (u32 *) arg);
1329
1330         case FE_READ_SIGNAL_STRENGTH:
1331                 return tda1004x_read_signal_strength(i2c, tda_state, (u16 *) arg);
1332
1333         case FE_READ_SNR:
1334                 return tda1004x_read_snr(i2c, tda_state, (u16 *) arg);
1335
1336         case FE_READ_UNCORRECTED_BLOCKS:
1337                 return tda1004x_read_ucblocks(i2c, tda_state, (u32 *) arg);
1338
1339         case FE_SET_FRONTEND:
1340                 return tda1004x_set_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1341
1342         case FE_GET_FRONTEND:
1343                 return tda1004x_get_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1344
1345         case FE_SLEEP:
1346                 tda_state->initialised = 0;
1347                 return tda1004x_sleep(i2c, tda_state);
1348
1349         case FE_INIT:
1350
1351                 // don't bother reinitialising
1352                 if (tda_state->initialised)
1353                         return 0;
1354
1355                 // OK, perform initialisation
1356                 switch(tda_state->fe_type) {
1357                 case FE_TYPE_TDA10045H:
1358                         status = tda10045h_init(i2c, tda_state);
1359                         break;
1360
1361                 case FE_TYPE_TDA10046H:
1362                         status = tda10046h_init(i2c, tda_state);
1363                         break;
1364                 }
1365                 if (status == 0)
1366                         tda_state->initialised = 1;
1367                 return status;
1368
1369         case FE_GET_TUNE_SETTINGS:
1370         {
1371                 struct dvb_frontend_tune_settings* fesettings = (struct dvb_frontend_tune_settings*) arg;
1372                 fesettings->min_delay_ms = 800;
1373                 fesettings->step_size = 166667;
1374                 fesettings->max_drift = 166667*2;
1375                 return 0;
1376         }
1377
1378         default:
1379                 return -EOPNOTSUPP;
1380         }
1381
1382         return 0;
1383 }
1384
1385
1386 static int tda1004x_attach(struct dvb_i2c_bus *i2c, void **data)
1387 {
1388         int tda1004x_address = -1;
1389         int tuner_address = -1;
1390         int fe_type = -1;
1391         int tuner_type = -1;
1392         struct tda1004x_state tda_state;
1393         struct tda1004x_state* ptda_state;
1394         struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=NULL, .len=0 };
1395         static u8 td1344_init[] = { 0x0b, 0xf5, 0x88, 0xab };
1396         static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
1397         static u8 td1316_init_tda10046h[] = { 0x0b, 0xf5, 0x80, 0xab };
1398         int status;
1399
1400         dprintk("%s\n", __FUNCTION__);
1401
1402         // probe for tda10045h
1403         if (tda1004x_address == -1) {
1404                 tda_state.tda1004x_address = 0x08;
1405         if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x25) {
1406                         tda1004x_address = 0x08;
1407                         fe_type = FE_TYPE_TDA10045H;
1408                 printk("tda1004x: Detected Philips TDA10045H.\n");
1409         }
1410         }
1411
1412         // probe for tda10046h
1413         if (tda1004x_address == -1) {
1414                 tda_state.tda1004x_address = 0x08;
1415                 if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x46) {
1416                         tda1004x_address = 0x08;
1417                         fe_type = FE_TYPE_TDA10046H;
1418                         printk("tda1004x: Detected Philips TDA10046H.\n");
1419                 }
1420         }
1421
1422         // did we find a frontend?
1423         if (tda1004x_address == -1) {
1424                 return -ENODEV;
1425         }
1426
1427         // enable access to the tuner
1428         tda1004x_enable_tuner_i2c(i2c, &tda_state);
1429
1430         // check for a TD1344 first
1431         if (tuner_address == -1) {
1432                 tuner_msg.addr = 0x61;
1433         tuner_msg.buf = td1344_init;
1434         tuner_msg.len = sizeof(td1344_init);
1435         if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1436                 dvb_delay(1);
1437                         tuner_address = 0x61;
1438                         tuner_type = TUNER_TYPE_TD1344;
1439                         printk("tda1004x: Detected Philips TD1344 tuner.\n");
1440                 }
1441         }
1442
1443         // OK, try a TD1316 on address 0x63
1444         if (tuner_address == -1) {
1445                 tuner_msg.addr = 0x63;
1446                 tuner_msg.buf = td1316_init;
1447                 tuner_msg.len = sizeof(td1316_init);
1448                 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1449                         dvb_delay(1);
1450                         tuner_address = 0x63;
1451                         tuner_type = TUNER_TYPE_TD1316;
1452                         printk("tda1004x: Detected Philips TD1316 tuner.\n");
1453                 }
1454         }
1455
1456         // OK, TD1316 again, on address 0x60 (TDA10046H)
1457         if (tuner_address == -1) {
1458                 tuner_msg.addr = 0x60;
1459                 tuner_msg.buf = td1316_init_tda10046h;
1460                 tuner_msg.len = sizeof(td1316_init_tda10046h);
1461                 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1462                         dvb_delay(1);
1463                         tuner_address = 0x60;
1464                         tuner_type = TUNER_TYPE_TD1316;
1465                         printk("tda1004x: Detected Philips TD1316 tuner.\n");
1466                 }
1467         }
1468         tda1004x_disable_tuner_i2c(i2c, &tda_state);
1469
1470         // did we find a tuner?
1471         if (tuner_address == -1) {
1472                 printk("tda1004x: Detected, but with unknown tuner.\n");
1473                 return -ENODEV;
1474         }
1475
1476         // create state
1477         tda_state.tda1004x_address = tda1004x_address;
1478         tda_state.fe_type = fe_type;
1479         tda_state.tuner_address = tuner_address;
1480         tda_state.tuner_type = tuner_type;
1481         tda_state.initialised = 0;
1482
1483         // upload firmware
1484         if ((status = tda1004x_fwupload(i2c, &tda_state)) != 0) return status;
1485
1486         // create the real state we'll be passing about
1487         if ((ptda_state = (struct tda1004x_state*) kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL)) == NULL) {
1488                 return -ENOMEM;
1489         }
1490         memcpy(ptda_state, &tda_state, sizeof(struct tda1004x_state));
1491         *data = ptda_state;
1492
1493         // register
1494         switch(tda_state.fe_type) {
1495         case FE_TYPE_TDA10045H:
1496                 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10045h_info);
1497
1498         case FE_TYPE_TDA10046H:
1499                 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10046h_info);
1500         }
1501
1502         // should not get here
1503         return -EINVAL;
1504 }
1505
1506
1507 static
1508 void tda1004x_detach(struct dvb_i2c_bus *i2c, void *data)
1509 {
1510         dprintk("%s\n", __FUNCTION__);
1511
1512         kfree(data);
1513         dvb_unregister_frontend(tda1004x_ioctl, i2c);
1514 }
1515
1516
1517 static
1518 int __init init_tda1004x(void)
1519 {
1520         return dvb_register_i2c_device(THIS_MODULE, tda1004x_attach, tda1004x_detach);
1521 }
1522
1523
1524 static
1525 void __exit exit_tda1004x(void)
1526 {
1527         dvb_unregister_i2c_device(tda1004x_attach);
1528 }
1529
1530 module_init(init_tda1004x);
1531 module_exit(exit_tda1004x);
1532
1533 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Frontend");
1534 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1535 MODULE_LICENSE("GPL");
1536
1537 MODULE_PARM(tda1004x_debug, "i");
1538 MODULE_PARM_DESC(tda1004x_debug, "enable verbose debug messages");
1539
1540 MODULE_PARM(tda1004x_firmware, "s");
1541 MODULE_PARM_DESC(tda1004x_firmware, "Where to find the firmware file");