drivers/media/dvb/frontends/tda1004x.c

   1   /*
   2      Driver for Philips tda1004xh OFDM Frontend
   3
   4      (c) 2003, 2004 Andrew de Quincey & Robert Schlabbach
   5
   6      This program is free software; you can redistribute it and/or modify
   7      it under the terms of the GNU General Public License as published by
   8      the Free Software Foundation; either version 2 of the License, or
   9      (at your option) any later version.
  10
  11      This program is distributed in the hope that it will be useful,
  12      but WITHOUT ANY WARRANTY; without even the implied warranty of
  13      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15      GNU General Public License for more details.
  16
  17      You should have received a copy of the GNU General Public License
  18      along with this program; if not, write to the Free Software
  19      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21    */
  22
  23 /*
  24     This driver needs a copy of the DLL "ttlcdacc.dll" from the Haupauge or Technotrend
  25     windows driver saved as '/usr/lib/hotplug/firmware/tda1004x.bin'.
  26     You can also pass the complete file name with the module parameter 'tda1004x_firmware'.
  27
  28     Currently the DLL from v2.15a of the technotrend driver is supported. Other versions can
  29     be added reasonably painlessly.
  30
  31     Windows driver URL: http://www.technotrend.de/
  32  */
  33
  34
  35 #include <linux/kernel.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/module.h>
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41 #include <linux/fs.h>
  42 #include <linux/fcntl.h>
  43 #include <linux/errno.h>
  44 #include <linux/syscalls.h>
  45
  46 #include "dvb_frontend.h"
  47 #include "dvb_functions.h"
  48
  49 #ifndef DVB_TDA1004X_FIRMWARE_FILE
  50 #define DVB_TDA1004X_FIRMWARE_FILE "/usr/lib/hotplug/firmware/tda1004x.bin"
  51 #endif
  52
  53 static int tda1004x_debug = 0;
  54 static char *tda1004x_firmware = DVB_TDA1004X_FIRMWARE_FILE;
  55
  56 #define MC44BC374_ADDRESS        0x65
  57
  58 #define TDA1004X_CHIPID          0x00
  59 #define TDA1004X_AUTO            0x01
  60 #define TDA1004X_IN_CONF1        0x02
  61 #define TDA1004X_IN_CONF2        0x03
  62 #define TDA1004X_OUT_CONF1       0x04
  63 #define TDA1004X_OUT_CONF2       0x05
  64 #define TDA1004X_STATUS_CD       0x06
  65 #define TDA1004X_CONFC4          0x07
  66 #define TDA1004X_DSSPARE2        0x0C
  67 #define TDA10045H_CODE_IN        0x0D
  68 #define TDA10045H_FWPAGE         0x0E
  69 #define TDA1004X_SCAN_CPT        0x10
  70 #define TDA1004X_DSP_CMD         0x11
  71 #define TDA1004X_DSP_ARG         0x12
  72 #define TDA1004X_DSP_DATA1       0x13
  73 #define TDA1004X_DSP_DATA2       0x14
  74 #define TDA1004X_CONFADC1        0x15
  75 #define TDA1004X_CONFC1          0x16
  76 #define TDA10045H_S_AGC          0x1a
  77 #define TDA10046H_AGC_TUN_LEVEL  0x1a
  78 #define TDA1004X_SNR             0x1c
  79 #define TDA1004X_CONF_TS1        0x1e
  80 #define TDA1004X_CONF_TS2        0x1f
  81 #define TDA1004X_CBER_RESET      0x20
  82 #define TDA1004X_CBER_MSB        0x21
  83 #define TDA1004X_CBER_LSB        0x22
  84 #define TDA1004X_CVBER_LUT       0x23
  85 #define TDA1004X_VBER_MSB        0x24
  86 #define TDA1004X_VBER_MID        0x25
  87 #define TDA1004X_VBER_LSB        0x26
  88 #define TDA1004X_UNCOR           0x27
  89
  90 #define TDA10045H_CONFPLL_P      0x2D
  91 #define TDA10045H_CONFPLL_M_MSB  0x2E
  92 #define TDA10045H_CONFPLL_M_LSB  0x2F
  93 #define TDA10045H_CONFPLL_N      0x30
  94
  95 #define TDA10046H_CONFPLL1       0x2D
  96 #define TDA10046H_CONFPLL2       0x2F
  97 #define TDA10046H_CONFPLL3       0x30
  98 #define TDA10046H_TIME_WREF1     0x31
  99 #define TDA10046H_TIME_WREF2     0x32
 100 #define TDA10046H_TIME_WREF3     0x33
 101 #define TDA10046H_TIME_WREF4     0x34
 102 #define TDA10046H_TIME_WREF5     0x35
 103
 104 #define TDA10045H_UNSURW_MSB     0x31
 105 #define TDA10045H_UNSURW_LSB     0x32
 106 #define TDA10045H_WREF_MSB       0x33
 107 #define TDA10045H_WREF_MID       0x34
 108 #define TDA10045H_WREF_LSB       0x35
 109 #define TDA10045H_MUXOUT         0x36
 110 #define TDA1004X_CONFADC2        0x37
 111
 112 #define TDA10045H_IOFFSET        0x38
 113
 114 #define TDA10046H_CONF_TRISTATE1 0x3B
 115 #define TDA10046H_CONF_TRISTATE2 0x3C
 116 #define TDA10046H_CONF_POLARITY  0x3D
 117 #define TDA10046H_FREQ_OFFSET    0x3E
 118 #define TDA10046H_GPIO_OUT_SEL   0x41
 119 #define TDA10046H_GPIO_SELECT    0x42
 120 #define TDA10046H_AGC_CONF       0x43
 121 #define TDA10046H_AGC_GAINS      0x46
 122 #define TDA10046H_AGC_TUN_MIN    0x47
 123 #define TDA10046H_AGC_TUN_MAX    0x48
 124 #define TDA10046H_AGC_IF_MIN     0x49
 125 #define TDA10046H_AGC_IF_MAX     0x4A
 126
 127 #define TDA10046H_FREQ_PHY2_MSB  0x4D
 128 #define TDA10046H_FREQ_PHY2_LSB  0x4E
 129
 130 #define TDA10046H_CVBER_CTRL     0x4F
 131 #define TDA10046H_AGC_IF_LEVEL   0x52
 132 #define TDA10046H_CODE_CPT       0x57
 133 #define TDA10046H_CODE_IN        0x58
 134
 135
 136 #define FE_TYPE_TDA10045H     0
 137 #define FE_TYPE_TDA10046H     1
 138
 139 #define TUNER_TYPE_TD1344     0
 140 #define TUNER_TYPE_TD1316     1
 141
 142 #define dprintk if (tda1004x_debug) printk
 143
 144 static struct dvb_frontend_info tda10045h_info = {
 145         .name = "Philips TDA10045H",
 146         .type = FE_OFDM,
 147         .frequency_min = 51000000,
 148         .frequency_max = 858000000,
 149         .frequency_stepsize = 166667,
 150         .caps =
 151             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 152             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 153             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 154             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
 155 };
 156
 157 static struct dvb_frontend_info tda10046h_info = {
 158         .name = "Philips TDA10046H",
 159         .type = FE_OFDM,
 160         .frequency_min = 51000000,
 161         .frequency_max = 858000000,
 162         .frequency_stepsize = 166667,
 163         .caps =
 164             FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 165             FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 166             FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
 167             FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO
 168 };
 169
 170
 171 struct tda1004x_state {
 172         u8 tda1004x_address;
 173         u8 tuner_address;
 174         u8 initialised:1;
 175         u8 tuner_type:2;
 176         u8 fe_type:2;
 177 };
 178
 179
 180 struct fwinfo {
 181         int file_size;
 182         int fw_offset;
 183         int fw_size;
 184 };
 185 static struct fwinfo tda10045h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x34cc5,.fw_size = 30555} };
 186 static int tda10045h_fwinfo_count = sizeof(tda10045h_fwinfo) / sizeof(struct fwinfo);
 187
 188 static struct fwinfo tda10046h_fwinfo[] = { {.file_size = 286720,.fw_offset = 0x3c4f9,.fw_size = 24479} };
 189 static int tda10046h_fwinfo_count = sizeof(tda10046h_fwinfo) / sizeof(struct fwinfo);
 190
 191
 192 static int tda1004x_write_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int data)
 193 {
 194         int ret;
 195         u8 buf[] = { reg, data };
 196         struct i2c_msg msg = { .addr=0, .flags=0, .buf=buf, .len=2 };
 197
 198         dprintk("%s: reg=0x%x, data=0x%x\n", __FUNCTION__, reg, data);
 199
 200         msg.addr = tda_state->tda1004x_address;
 201         ret = i2c->xfer(i2c, &msg, 1);
 202
 203         if (ret != 1)
 204                 dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
 205                        __FUNCTION__, reg, data, ret);
 206
 207         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 208                 reg, data, ret);
 209         return (ret != 1) ? -1 : 0;
 210 }
 211
 212 static int tda1004x_read_byte(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg)
 213 {
 214         int ret;
 215         u8 b0[] = { reg };
 216         u8 b1[] = { 0 };
 217         struct i2c_msg msg[] = {{ .addr=0, .flags=0, .buf=b0, .len=1},
 218                                 { .addr=0, .flags=I2C_M_RD, .buf=b1, .len = 1}};
 219
 220         dprintk("%s: reg=0x%x\n", __FUNCTION__, reg);
 221
 222         msg[0].addr = tda_state->tda1004x_address;
 223         msg[1].addr = tda_state->tda1004x_address;
 224         ret = i2c->xfer(i2c, msg, 2);
 225
 226         if (ret != 2) {
 227                 dprintk("%s: error reg=0x%x, ret=%i\n", __FUNCTION__, reg,
 228                        ret);
 229                 return -1;
 230         }
 231
 232         dprintk("%s: success reg=0x%x, data=0x%x, ret=%i\n", __FUNCTION__,
 233                 reg, b1[0], ret);
 234         return b1[0];
 235 }
 236
 237 static int tda1004x_write_mask(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, int mask, int data)
 238 {
 239         int val;
 240         dprintk("%s: reg=0x%x, mask=0x%x, data=0x%x\n", __FUNCTION__, reg,
 241                 mask, data);
 242
 243         // read a byte and check
 244         val = tda1004x_read_byte(i2c, tda_state, reg);
 245         if (val < 0)
 246                 return val;
 247
 248         // mask if off
 249         val = val & ~mask;
 250         val |= data & 0xff;
 251
 252         // write it out again
 253         return tda1004x_write_byte(i2c, tda_state, reg, val);
 254 }
 255
 256 static int tda1004x_write_buf(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state, int reg, unsigned char *buf, int len)
 257 {
 258         int i;
 259         int result;
 260
 261         dprintk("%s: reg=0x%x, len=0x%x\n", __FUNCTION__, reg, len);
 262
 263         result = 0;
 264         for (i = 0; i < len; i++) {
 265                 result = tda1004x_write_byte(i2c, tda_state, reg + i, buf[i]);
 266                 if (result != 0)
 267                         break;
 268         }
 269
 270         return result;
 271 }
 272
 273 static int tda1004x_enable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 274 {
 275         int result;
 276         dprintk("%s\n", __FUNCTION__);
 277
 278         result = tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 2);
 279         dvb_delay(1);
 280         return result;
 281 }
 282
 283 static int tda1004x_disable_tuner_i2c(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 284 {
 285
 286         dprintk("%s\n", __FUNCTION__);
 287
 288         return tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 2, 0);
 289 }
 290
 291
 292 static int tda10045h_set_bandwidth(struct dvb_i2c_bus *i2c,
 293                                    struct tda1004x_state *tda_state,
 294                                    fe_bandwidth_t bandwidth)
 295 {
 296         static u8 bandwidth_6mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x60, 0x1e, 0xa7, 0x45, 0x4f };
 297         static u8 bandwidth_7mhz[] = { 0x02, 0x00, 0x37, 0x00, 0x4a, 0x2f, 0x6d, 0x76, 0xdb };
 298         static u8 bandwidth_8mhz[] = { 0x02, 0x00, 0x3d, 0x00, 0x48, 0x17, 0x89, 0xc7, 0x14 };
 299
 300         switch (bandwidth) {
 301         case BANDWIDTH_6_MHZ:
 302                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
 303                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 304                 break;
 305
 306         case BANDWIDTH_7_MHZ:
 307                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x80);
 308                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 309                 break;
 310
 311         case BANDWIDTH_8_MHZ:
 312                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0x14);
 313                 tda1004x_write_buf(i2c, tda_state, TDA10045H_CONFPLL_P, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 314                 break;
 315
 316         default:
 317                 return -EINVAL;
 318         }
 319
 320         tda1004x_write_byte(i2c, tda_state, TDA10045H_IOFFSET, 0);
 321
 322         // done
 323         return 0;
 324 }
 325
 326
 327 static int tda10046h_set_bandwidth(struct dvb_i2c_bus *i2c,
 328                                    struct tda1004x_state *tda_state,
 329                                    fe_bandwidth_t bandwidth)
 330 {
 331         static u8 bandwidth_6mhz[] = { 0x80, 0x15, 0xfe, 0xab, 0x8e };
 332         static u8 bandwidth_7mhz[] = { 0x6e, 0x02, 0x53, 0xc8, 0x25 };
 333         static u8 bandwidth_8mhz[] = { 0x60, 0x12, 0xa8, 0xe4, 0xbd };
 334
 335         switch (bandwidth) {
 336         case BANDWIDTH_6_MHZ:
 337                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_6mhz, sizeof(bandwidth_6mhz));
 338                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
 339                 break;
 340
 341         case BANDWIDTH_7_MHZ:
 342                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_7mhz, sizeof(bandwidth_7mhz));
 343                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0);
 344                 break;
 345
 346         case BANDWIDTH_8_MHZ:
 347                 tda1004x_write_buf(i2c, tda_state, TDA10046H_TIME_WREF1, bandwidth_8mhz, sizeof(bandwidth_8mhz));
 348                 tda1004x_write_byte(i2c, tda_state, TDA1004X_DSSPARE2, 0xFF);
 349                 break;
 350
 351         default:
 352                 return -EINVAL;
 353         }
 354
 355         // done
 356         return 0;
 357 }
 358
 359
 360 static int tda1004x_fwupload(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 361 {
 362         u8 fw_buf[65];
 363         struct i2c_msg fw_msg = {.addr = 0,.flags = 0,.buf = fw_buf,.len = 0 };
 364         unsigned char *firmware = NULL;
 365         int filesize;
 366         int fd;
 367         int fwinfo_idx;
 368         int fw_size = 0;
 369         int fw_pos, fw_offset;
 370         int tx_size;
 371         mm_segment_t fs = get_fs();
 372         int dspCodeCounterReg=0, dspCodeInReg=0, dspVersion=0;
 373         int fwInfoCount=0;
 374         struct fwinfo* fwInfo = NULL;
 375         unsigned long timeout;
 376
 377         // DSP parameters
 378         switch(tda_state->fe_type) {
 379         case FE_TYPE_TDA10045H:
 380                 dspCodeCounterReg = TDA10045H_FWPAGE;
 381                 dspCodeInReg = TDA10045H_CODE_IN;
 382                 dspVersion = 0x2c;
 383                 fwInfoCount = tda10045h_fwinfo_count;
 384                 fwInfo = tda10045h_fwinfo;
 385                 break;
 386
 387         case FE_TYPE_TDA10046H:
 388                 dspCodeCounterReg = TDA10046H_CODE_CPT;
 389                 dspCodeInReg = TDA10046H_CODE_IN;
 390                 dspVersion = 0x20;
 391                 fwInfoCount = tda10046h_fwinfo_count;
 392                 fwInfo = tda10046h_fwinfo;
 393                 break;
 394         }
 395
 396         // Load the firmware
 397         set_fs(get_ds());
 398         fd = sys_open(tda1004x_firmware, 0, 0);
 399         if (fd < 0) {
 400                 printk("%s: Unable to open firmware %s\n", __FUNCTION__,
 401                        tda1004x_firmware);
 402                 return -EIO;
 403         }
 404         filesize = sys_lseek(fd, 0L, 2);
 405         if (filesize <= 0) {
 406                 printk("%s: Firmware %s is empty\n", __FUNCTION__,
 407                        tda1004x_firmware);
 408                 sys_close(fd);
 409                 return -EIO;
 410         }
 411
 412         // find extraction parameters for firmware
 413         for (fwinfo_idx = 0; fwinfo_idx < fwInfoCount; fwinfo_idx++) {
 414                 if (fwInfo[fwinfo_idx].file_size == filesize)
 415                         break;
 416         }
 417         if (fwinfo_idx >= fwInfoCount) {
 418                 printk("%s: Unsupported firmware %s\n", __FUNCTION__, tda1004x_firmware);
 419                 sys_close(fd);
 420                 return -EIO;
 421         }
 422         fw_size = fwInfo[fwinfo_idx].fw_size;
 423         fw_offset = fwInfo[fwinfo_idx].fw_offset;
 424
 425         // allocate buffer for it
 426         firmware = vmalloc(fw_size);
 427         if (firmware == NULL) {
 428                 printk("%s: Out of memory loading firmware\n",
 429                        __FUNCTION__);
 430                 sys_close(fd);
 431                 return -EIO;
 432         }
 433
 434         // read it!
 435         sys_lseek(fd, fw_offset, 0);
 436         if (sys_read(fd, firmware, fw_size) != fw_size) {
 437                 printk("%s: Failed to read firmware\n", __FUNCTION__);
 438                 vfree(firmware);
 439                 sys_close(fd);
 440                 return -EIO;
 441         }
 442         sys_close(fd);
 443         set_fs(fs);
 444
 445         // set some valid bandwith parameters before uploading
 446         switch(tda_state->fe_type) {
 447         case FE_TYPE_TDA10045H:
 448                 // reset chip
 449                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0);
 450                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
 451                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
 452                 dvb_delay(10);
 453
 454                 // set parameters
 455                 tda10045h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ);
 456                 break;
 457
 458         case FE_TYPE_TDA10046H:
 459                 // reset chip
 460                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0);
 461                 tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 1, 0);
 462                 dvb_delay(10);
 463
 464                 // set parameters
 465                 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10);
 466                 tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0);
 467                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99);
 468                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4);
 469                 tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c);
 470                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST
 471                 break;
 472         }
 473
 474         // do the firmware upload
 475         tda1004x_write_byte(i2c, tda_state, dspCodeCounterReg, 0); // clear code counter
 476         fw_msg.addr = tda_state->tda1004x_address;
 477         fw_pos = 0;
 478         while (fw_pos != fw_size) {
 479
 480                 // work out how much to send this time
 481                 tx_size = fw_size - fw_pos;
 482                 if (tx_size > 0x10) {
 483                         tx_size = 0x10;
 484                 }
 485
 486                 // send the chunk
 487                 fw_buf[0] = dspCodeInReg;
 488                 memcpy(fw_buf + 1, firmware + fw_pos, tx_size);
 489                 fw_msg.len = tx_size + 1;
 490                 if (i2c->xfer(i2c, &fw_msg, 1) != 1) {
 491                         printk("tda1004x: Error during firmware upload\n");
 492                         vfree(firmware);
 493                         return -EIO;
 494                 }
 495                 fw_pos += tx_size;
 496
 497                 dprintk("%s: fw_pos=0x%x\n", __FUNCTION__, fw_pos);
 498         }
 499         vfree(firmware);
 500
 501         // wait for DSP to initialise
 502         switch(tda_state->fe_type) {
 503         case FE_TYPE_TDA10045H:
 504                 // DSPREADY doesn't seem to work on the TDA10045H
 505                 dvb_delay(100);
 506                 break;
 507
 508         case FE_TYPE_TDA10046H:
 509                 timeout = jiffies + HZ;
 510                 while(!(tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD) & 0x20)) {
 511                         if (time_after(jiffies, timeout)) {
 512                                 printk("tda1004x: DSP failed to initialised.\n");
 513                                 return -EIO;
 514                         }
 515
 516                         dvb_delay(1);
 517                 }
 518                 break;
 519         }
 520
 521         // check upload was OK
 522         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP
 523         tda1004x_write_byte(i2c, tda_state, TDA1004X_DSP_CMD, 0x67);
 524         if ((tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA1) != 0x67) ||
 525             (tda1004x_read_byte(i2c, tda_state, TDA1004X_DSP_DATA2) != dspVersion)) {
 526                 printk("%s: firmware upload failed!\n", __FUNCTION__);
 527                 return -EIO;
 528         }
 529
 530         // success
 531         return 0;
 532 }
 533
 534
 535 static int tda10045h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 536 {
 537         struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = NULL,.len = 0 };
 538         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 539
 540         dprintk("%s\n", __FUNCTION__);
 541
 542         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC
 543
 544         // Disable the MC44BC374C
 545         tda1004x_enable_tuner_i2c(i2c, tda_state);
 546         tuner_msg.addr = MC44BC374_ADDRESS;
 547         tuner_msg.buf = disable_mc44BC374c;
 548         tuner_msg.len = sizeof(disable_mc44BC374c);
 549         if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 550                 i2c->xfer(i2c, &tuner_msg, 1);
 551         }
 552         tda1004x_disable_tuner_i2c(i2c, tda_state);
 553
 554         // tda setup
 555         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 556         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
 557         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0); // no frequency inversion
 558         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer
 559         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset
 560         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset
 561         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 0); // setup MPEG2 TS interface
 562         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS2, 0); // setup MPEG2 TS interface
 563         tda1004x_write_mask(i2c, tda_state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits
 564         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity
 565         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONFADC1, 0x2e);
 566
 567         // done
 568         return 0;
 569 }
 570
 571
 572
 573 static int tda10046h_init(struct dvb_i2c_bus *i2c, struct tda1004x_state *tda_state)
 574 {
 575         struct i2c_msg tuner_msg = {.addr = 0,.flags = 0,.buf = NULL,.len = 0 };
 576         static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
 577
 578         dprintk("%s\n", __FUNCTION__);
 579
 580         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 0); // wake up the chip
 581
 582         // Disable the MC44BC374C
 583         tda1004x_enable_tuner_i2c(i2c, tda_state);
 584         tuner_msg.addr = MC44BC374_ADDRESS;
 585         tuner_msg.buf = disable_mc44BC374c;
 586         tuner_msg.len = sizeof(disable_mc44BC374c);
 587         if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 588                 i2c->xfer(i2c, &tuner_msg, 1);
 589         }
 590         tda1004x_disable_tuner_i2c(i2c, tda_state);
 591
 592         // tda setup
 593         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer
 594         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x40, 0x40); // TT TDA10046H needs inversion ON
 595         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 8, 0); // select HP stream
 596         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x80, 0); // disable pulse killer
 597         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL2, 10); // PLL M = 10
 598         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONFPLL3, 0); // PLL P = N = 0
 599         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_OFFSET, 99); // FREQOFFS = 99
 600         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_MSB, 0xd4); // } PHY2 = -11221
 601         tda1004x_write_byte(i2c, tda_state, TDA10046H_FREQ_PHY2_LSB, 0x2c); // }
 602         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_CONF, 0); // AGC setup
 603         tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_POLARITY, 0x60, 0x60); // set AGC polarities
 604         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MIN, 0);    // }
 605         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_TUN_MAX, 0xff); // } AGC min/max values
 606         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MIN, 0);     // }
 607         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_IF_MAX, 0xff);  // }
 608         tda1004x_write_mask(i2c, tda_state, TDA10046H_CVBER_CTRL, 0x30, 0x10); // 10^6 VBER measurement bits
 609         tda1004x_write_byte(i2c, tda_state, TDA10046H_AGC_GAINS, 1); // IF gain 2, TUN gain 1
 610         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x80, 0); // crystal is 50ppm
 611         tda1004x_write_byte(i2c, tda_state, TDA1004X_CONF_TS1, 7); // MPEG2 interface config
 612         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONF_TS2, 0x31, 0); // MPEG2 interface config
 613         tda1004x_write_mask(i2c, tda_state, TDA10046H_CONF_TRISTATE1, 0x9e, 0); // disable AGC_TUN
 614         tda1004x_write_byte(i2c, tda_state, TDA10046H_CONF_TRISTATE2, 0xe1); // tristate setup
 615         tda1004x_write_byte(i2c, tda_state, TDA10046H_GPIO_OUT_SEL, 0xcc); // GPIO output config
 616         tda1004x_write_mask(i2c, tda_state, TDA10046H_GPIO_SELECT, 8, 8); // GPIO select
 617         tda10046h_set_bandwidth(i2c, tda_state, BANDWIDTH_8_MHZ); // default bandwidth 8 MHz
 618
 619         // done
 620         return 0;
 621 }
 622
 623
 624
 625 static int tda1004x_encode_fec(int fec)
 626 {
 627         // convert known FEC values
 628         switch (fec) {
 629         case FEC_1_2:
 630                 return 0;
 631         case FEC_2_3:
 632                 return 1;
 633         case FEC_3_4:
 634                 return 2;
 635         case FEC_5_6:
 636                 return 3;
 637         case FEC_7_8:
 638                 return 4;
 639         }
 640
 641         // unsupported
 642         return -EINVAL;
 643 }
 644
 645 static int tda1004x_decode_fec(int tdafec)
 646 {
 647         // convert known FEC values
 648         switch (tdafec) {
 649         case 0:
 650                 return FEC_1_2;
 651         case 1:
 652                 return FEC_2_3;
 653         case 2:
 654                 return FEC_3_4;
 655         case 3:
 656                 return FEC_5_6;
 657         case 4:
 658                 return FEC_7_8;
 659         }
 660
 661         // unsupported
 662         return -1;
 663 }
 664
 665 static int tda1004x_set_frequency(struct dvb_i2c_bus *i2c,
 666                            struct tda1004x_state *tda_state,
 667                            struct dvb_frontend_parameters *fe_params)
 668 {
 669         u8 tuner_buf[4];
 670         struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=tuner_buf, .len=sizeof(tuner_buf) };
 671         int tuner_frequency = 0;
 672         u8 band, cp, filter;
 673         int counter, counter2;
 674
 675         dprintk("%s\n", __FUNCTION__);
 676
 677         // setup the frequency buffer
 678         switch (tda_state->tuner_type) {
 679         case TUNER_TYPE_TD1344:
 680
 681                 // setup tuner buffer
 682                 // ((Fif+((1000000/6)/2)) + Finput)/(1000000/6)
 683                 tuner_frequency =
 684                         (((fe_params->frequency / 1000) * 6) + 217502) / 1000;
 685                 tuner_buf[0] = tuner_frequency >> 8;
 686                 tuner_buf[1] = tuner_frequency & 0xff;
 687                 tuner_buf[2] = 0x88;
 688                 if (fe_params->frequency < 550000000) {
 689                         tuner_buf[3] = 0xab;
 690                 } else {
 691                         tuner_buf[3] = 0xeb;
 692                 }
 693
 694                 // tune it
 695                 tda1004x_enable_tuner_i2c(i2c, tda_state);
 696                 tuner_msg.addr = tda_state->tuner_address;
 697                 tuner_msg.len = 4;
 698                 i2c->xfer(i2c, &tuner_msg, 1);
 699
 700                 // wait for it to finish
 701                 tuner_msg.len = 1;
 702                 tuner_msg.flags = I2C_M_RD;
 703                 counter = 0;
 704                 counter2 = 0;
 705                 while (counter++ < 100) {
 706                         if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
 707                                 if (tuner_buf[0] & 0x40) {
 708                                         counter2++;
 709                                 } else {
 710                                         counter2 = 0;
 711                                 }
 712                         }
 713
 714                         if (counter2 > 10) {
 715                                 break;
 716                         }
 717                 }
 718                 tda1004x_disable_tuner_i2c(i2c, tda_state);
 719                 break;
 720
 721         case TUNER_TYPE_TD1316:
 722                 // determine charge pump
 723                 tuner_frequency = fe_params->frequency + 36130000;
 724                 if (tuner_frequency < 87000000) {
 725                         return -EINVAL;
 726                 } else if (tuner_frequency < 130000000) {
 727                         cp = 3;
 728                 } else if (tuner_frequency < 160000000) {
 729                         cp = 5;
 730                 } else if (tuner_frequency < 200000000) {
 731                         cp = 6;
 732                 } else if (tuner_frequency < 290000000) {
 733                         cp = 3;
 734                 } else if (tuner_frequency < 420000000) {
 735                         cp = 5;
 736                 } else if (tuner_frequency < 480000000) {
 737                         cp = 6;
 738                 } else if (tuner_frequency < 620000000) {
 739                         cp = 3;
 740                 } else if (tuner_frequency < 830000000) {
 741                         cp = 5;
 742                 } else if (tuner_frequency < 895000000) {
 743                         cp = 7;
 744                 } else {
 745                         return -EINVAL;
 746                 }
 747
 748                 // determine band
 749                 if (fe_params->frequency < 49000000) {
 750                         return -EINVAL;
 751                 } else if (fe_params->frequency < 159000000) {
 752                         band = 1;
 753                 } else if (fe_params->frequency < 444000000) {
 754                         band = 2;
 755                 } else if (fe_params->frequency < 861000000) {
 756                         band = 4;
 757                 } else {
 758                         return -EINVAL;
 759                 }
 760
 761                 // work out filter
 762                 switch (fe_params->u.ofdm.bandwidth) {
 763                 case BANDWIDTH_6_MHZ:
 764                         filter = 0;
 765                         break;
 766
 767                 case BANDWIDTH_7_MHZ:
 768                         filter = 0;
 769                         break;
 770
 771                 case BANDWIDTH_8_MHZ:
 772                         filter = 1;
 773                         break;
 774
 775                 default:
 776                         return -EINVAL;
 777                 }
 778
 779                 // calculate divisor
 780                 // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
 781                 tuner_frequency =
 782                         (((fe_params->frequency / 1000) * 6) + 217280) / 1000;
 783
 784                 // setup tuner buffer
 785                 tuner_buf[0] = tuner_frequency >> 8;
 786                 tuner_buf[1] = tuner_frequency & 0xff;
 787                 tuner_buf[2] = 0xca;
 788                 tuner_buf[3] = (cp << 5) | (filter << 3) | band;
 789
 790                 // tune it
 791                 if (tda_state->fe_type == FE_TYPE_TDA10046H) {
 792                         // setup auto offset
 793                         tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x10, 0x10);
 794                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x80, 0);
 795                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0xC0, 0);
 796
 797                         // disable agc_conf[2]
 798                         tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 0);
 799                 }
 800                 tda1004x_enable_tuner_i2c(i2c, tda_state);
 801                 tuner_msg.addr = tda_state->tuner_address;
 802                 tuner_msg.len = 4;
 803                 if (i2c->xfer(i2c, &tuner_msg, 1) != 1) {
 804                         return -EIO;
 805                 }
 806                 dvb_delay(1);
 807                 tda1004x_disable_tuner_i2c(i2c, tda_state);
 808                 if (tda_state->fe_type == FE_TYPE_TDA10046H)
 809                         tda1004x_write_mask(i2c, tda_state, TDA10046H_AGC_CONF, 4, 4);
 810                 break;
 811
 812         default:
 813                 return -EINVAL;
 814         }
 815
 816         dprintk("%s: success\n", __FUNCTION__);
 817
 818         // done
 819         return 0;
 820 }
 821
 822 static int tda1004x_set_fe(struct dvb_i2c_bus *i2c,
 823                            struct tda1004x_state *tda_state,
 824                            struct dvb_frontend_parameters *fe_params)
 825 {
 826         int tmp;
 827         int inversion;
 828
 829         dprintk("%s\n", __FUNCTION__);
 830
 831         // set frequency
 832         if ((tmp = tda1004x_set_frequency(i2c, tda_state, fe_params)) < 0)
 833                 return tmp;
 834
 835         // hardcoded to use auto as much as possible
 836         fe_params->u.ofdm.code_rate_HP = FEC_AUTO;
 837         fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_AUTO;
 838         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_AUTO;
 839
 840         // Set standard params.. or put them to auto
 841         if ((fe_params->u.ofdm.code_rate_HP == FEC_AUTO) ||
 842             (fe_params->u.ofdm.code_rate_LP == FEC_AUTO) ||
 843             (fe_params->u.ofdm.constellation == QAM_AUTO) ||
 844             (fe_params->u.ofdm.hierarchy_information == HIERARCHY_AUTO)) {
 845                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 1);       // enable auto
 846                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x03, 0);        // turn off constellation bits
 847                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0);        // turn off hierarchy bits
 848                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x3f, 0);        // turn off FEC bits
 849         } else {
 850                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 1, 0);       // disable auto
 851
 852                 // set HP FEC
 853                 tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_HP);
 854                 if (tmp < 0) return tmp;
 855                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 7, tmp);
 856
 857                 // set LP FEC
 858                 if (fe_params->u.ofdm.code_rate_LP != FEC_NONE) {
 859                         tmp = tda1004x_encode_fec(fe_params->u.ofdm.code_rate_LP);
 860                         if (tmp < 0) return tmp;
 861                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF2, 0x38, tmp << 3);
 862                 }
 863
 864                 // set constellation
 865                 switch (fe_params->u.ofdm.constellation) {
 866                 case QPSK:
 867                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 0);
 868                         break;
 869
 870                 case QAM_16:
 871                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 1);
 872                         break;
 873
 874                 case QAM_64:
 875                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 3, 2);
 876                         break;
 877
 878                 default:
 879                         return -EINVAL;
 880                 }
 881
 882                 // set hierarchy
 883                 switch (fe_params->u.ofdm.hierarchy_information) {
 884                 case HIERARCHY_NONE:
 885                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 0 << 5);
 886                         break;
 887
 888                 case HIERARCHY_1:
 889                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 1 << 5);
 890                         break;
 891
 892                 case HIERARCHY_2:
 893                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 2 << 5);
 894                         break;
 895
 896                 case HIERARCHY_4:
 897                         tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x60, 3 << 5);
 898                         break;
 899
 900                 default:
 901                         return -EINVAL;
 902                 }
 903         }
 904
 905         // set bandwidth
 906         switch(tda_state->fe_type) {
 907         case FE_TYPE_TDA10045H:
 908                 tda10045h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
 909                 break;
 910
 911         case FE_TYPE_TDA10046H:
 912                 tda10046h_set_bandwidth(i2c, tda_state, fe_params->u.ofdm.bandwidth);
 913                 break;
 914         }
 915
 916         // need to invert the inversion for TT TDA10046H
 917         inversion = fe_params->inversion;
 918         if (tda_state->fe_type == FE_TYPE_TDA10046H) {
 919                 inversion = inversion ? INVERSION_OFF : INVERSION_ON;
 920         }
 921
 922         // set inversion
 923         switch (inversion) {
 924         case INVERSION_OFF:
 925                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0);
 926                 break;
 927
 928         case INVERSION_ON:
 929                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC1, 0x20, 0x20);
 930                 break;
 931
 932         default:
 933                 return -EINVAL;
 934         }
 935
 936         // set guard interval
 937         switch (fe_params->u.ofdm.guard_interval) {
 938         case GUARD_INTERVAL_1_32:
 939                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 940                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 941                 break;
 942
 943         case GUARD_INTERVAL_1_16:
 944                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 945                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 1 << 2);
 946                 break;
 947
 948         case GUARD_INTERVAL_1_8:
 949                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 950                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 2 << 2);
 951                 break;
 952
 953         case GUARD_INTERVAL_1_4:
 954                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 0);
 955                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 3 << 2);
 956                 break;
 957
 958         case GUARD_INTERVAL_AUTO:
 959                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 2, 2);
 960                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x0c, 0 << 2);
 961                 break;
 962
 963         default:
 964                 return -EINVAL;
 965         }
 966
 967         // set transmission mode
 968         switch (fe_params->u.ofdm.transmission_mode) {
 969         case TRANSMISSION_MODE_2K:
 970                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
 971                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0 << 4);
 972                 break;
 973
 974         case TRANSMISSION_MODE_8K:
 975                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 0);
 976                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 1 << 4);
 977                 break;
 978
 979         case TRANSMISSION_MODE_AUTO:
 980                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 4, 4);
 981                 tda1004x_write_mask(i2c, tda_state, TDA1004X_IN_CONF1, 0x10, 0);
 982                 break;
 983
 984         default:
 985                 return -EINVAL;
 986         }
 987
 988         // start the lock
 989         switch(tda_state->fe_type) {
 990         case FE_TYPE_TDA10045H:
 991         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 8);
 992         tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 8, 0);
 993         dvb_delay(10);
 994                 break;
 995
 996         case FE_TYPE_TDA10046H:
 997                 tda1004x_write_mask(i2c, tda_state, TDA1004X_AUTO, 0x40, 0x40);
 998                 dvb_delay(10);
 999                 break;
1000         }
1001
1002         // done
1003         return 0;
1004 }
1005
1006
1007 static int tda1004x_get_fe(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, struct dvb_frontend_parameters *fe_params)
1008 {
1009
1010         dprintk("%s\n", __FUNCTION__);
1011
1012         // inversion status
1013         fe_params->inversion = INVERSION_OFF;
1014         if (tda1004x_read_byte(i2c, tda_state, TDA1004X_CONFC1) & 0x20) {
1015                 fe_params->inversion = INVERSION_ON;
1016         }
1017
1018         // need to invert the inversion for TT TDA10046H
1019         if (tda_state->fe_type == FE_TYPE_TDA10046H) {
1020                 fe_params->inversion = fe_params->inversion ? INVERSION_OFF : INVERSION_ON;
1021         }
1022
1023         // bandwidth
1024         switch(tda_state->fe_type) {
1025         case FE_TYPE_TDA10045H:
1026                 switch (tda1004x_read_byte(i2c, tda_state, TDA10045H_WREF_LSB)) {
1027         case 0x14:
1028                 fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1029                 break;
1030         case 0xdb:
1031                 fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1032                 break;
1033         case 0x4f:
1034                 fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1035                 break;
1036         }
1037                 break;
1038
1039         case FE_TYPE_TDA10046H:
1040                 switch (tda1004x_read_byte(i2c, tda_state, TDA10046H_TIME_WREF1)) {
1041                 case 0x60:
1042                         fe_params->u.ofdm.bandwidth = BANDWIDTH_8_MHZ;
1043                         break;
1044                 case 0x6e:
1045                         fe_params->u.ofdm.bandwidth = BANDWIDTH_7_MHZ;
1046                         break;
1047                 case 0x80:
1048                         fe_params->u.ofdm.bandwidth = BANDWIDTH_6_MHZ;
1049                         break;
1050                 }
1051                 break;
1052         }
1053
1054         // FEC
1055         fe_params->u.ofdm.code_rate_HP =
1056             tda1004x_decode_fec(tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) & 7);
1057         fe_params->u.ofdm.code_rate_LP =
1058             tda1004x_decode_fec((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF2) >> 3) & 7);
1059
1060         // constellation
1061         switch (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 3) {
1062         case 0:
1063                 fe_params->u.ofdm.constellation = QPSK;
1064                 break;
1065         case 1:
1066                 fe_params->u.ofdm.constellation = QAM_16;
1067                 break;
1068         case 2:
1069                 fe_params->u.ofdm.constellation = QAM_64;
1070                 break;
1071         }
1072
1073         // transmission mode
1074         fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_2K;
1075         if (tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x10) {
1076                 fe_params->u.ofdm.transmission_mode = TRANSMISSION_MODE_8K;
1077         }
1078
1079         // guard interval
1080         switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x0c) >> 2) {
1081         case 0:
1082                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_32;
1083                 break;
1084         case 1:
1085                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_16;
1086                 break;
1087         case 2:
1088                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_8;
1089                 break;
1090         case 3:
1091                 fe_params->u.ofdm.guard_interval = GUARD_INTERVAL_1_4;
1092                 break;
1093         }
1094
1095         // hierarchy
1096         switch ((tda1004x_read_byte(i2c, tda_state, TDA1004X_OUT_CONF1) & 0x60) >> 5) {
1097         case 0:
1098                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_NONE;
1099                 break;
1100         case 1:
1101                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_1;
1102                 break;
1103         case 2:
1104                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_2;
1105                 break;
1106         case 3:
1107                 fe_params->u.ofdm.hierarchy_information = HIERARCHY_4;
1108                 break;
1109         }
1110
1111         // done
1112         return 0;
1113 }
1114
1115
1116 static int tda1004x_read_status(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, fe_status_t * fe_status)
1117 {
1118         int status;
1119         int cber;
1120         int vber;
1121
1122         dprintk("%s\n", __FUNCTION__);
1123
1124         // read status
1125         status = tda1004x_read_byte(i2c, tda_state, TDA1004X_STATUS_CD);
1126         if (status == -1) {
1127                 return -EIO;
1128         }
1129
1130         // decode
1131         *fe_status = 0;
1132         if (status & 4) *fe_status |= FE_HAS_SIGNAL;
1133         if (status & 2) *fe_status |= FE_HAS_CARRIER;
1134         if (status & 8) *fe_status |= FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
1135
1136         // if we don't already have VITERBI (i.e. not LOCKED), see if the viterbi
1137         // is getting anything valid
1138         if (!(*fe_status & FE_HAS_VITERBI)) {
1139                 // read the CBER
1140                 cber = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1141                 if (cber == -1) return -EIO;
1142                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1143                 if (status == -1) return -EIO;
1144                 cber |= (status << 8);
1145                 tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1146
1147                 if (cber != 65535) {
1148                         *fe_status |= FE_HAS_VITERBI;
1149                 }
1150         }
1151
1152         // if we DO have some valid VITERBI output, but don't already have SYNC
1153         // bytes (i.e. not LOCKED), see if the RS decoder is getting anything valid.
1154         if ((*fe_status & FE_HAS_VITERBI) && (!(*fe_status & FE_HAS_SYNC))) {
1155                 // read the VBER
1156                 vber = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_LSB);
1157                 if (vber == -1) return -EIO;
1158                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MID);
1159                 if (status == -1) return -EIO;
1160                 vber |= (status << 8);
1161                 status = tda1004x_read_byte(i2c, tda_state, TDA1004X_VBER_MSB);
1162                 if (status == -1) return -EIO;
1163                 vber |= ((status << 16) & 0x0f);
1164                 tda1004x_read_byte(i2c, tda_state, TDA1004X_CVBER_LUT);
1165
1166                 // if RS has passed some valid TS packets, then we must be
1167                 // getting some SYNC bytes
1168                 if (vber < 16632) {
1169                         *fe_status |= FE_HAS_SYNC;
1170                 }
1171         }
1172
1173         // success
1174         dprintk("%s: fe_status=0x%x\n", __FUNCTION__, *fe_status);
1175         return 0;
1176 }
1177
1178 static int tda1004x_read_signal_strength(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * signal)
1179 {
1180         int tmp;
1181         int reg = 0;
1182
1183         dprintk("%s\n", __FUNCTION__);
1184
1185         // determine the register to use
1186         switch(tda_state->fe_type) {
1187         case FE_TYPE_TDA10045H:
1188                 reg = TDA10045H_S_AGC;
1189                 break;
1190
1191         case FE_TYPE_TDA10046H:
1192                 reg = TDA10046H_AGC_IF_LEVEL;
1193                 break;
1194         }
1195
1196         // read it
1197         tmp = tda1004x_read_byte(i2c, tda_state, reg);
1198         if (tmp < 0)
1199                 return -EIO;
1200
1201         // done
1202         *signal = (tmp << 8) | tmp;
1203         dprintk("%s: signal=0x%x\n", __FUNCTION__, *signal);
1204         return 0;
1205 }
1206
1207
1208 static int tda1004x_read_snr(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u16 * snr)
1209 {
1210         int tmp;
1211
1212         dprintk("%s\n", __FUNCTION__);
1213
1214         // read it
1215         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_SNR);
1216         if (tmp < 0)
1217                 return -EIO;
1218         if (tmp) {
1219                 tmp = 255 - tmp;
1220         }
1221
1222         // done
1223         *snr = ((tmp << 8) | tmp);
1224         dprintk("%s: snr=0x%x\n", __FUNCTION__, *snr);
1225         return 0;
1226 }
1227
1228 static int tda1004x_read_ucblocks(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ucblocks)
1229 {
1230         int tmp;
1231         int tmp2;
1232         int counter;
1233
1234         dprintk("%s\n", __FUNCTION__);
1235
1236         // read the UCBLOCKS and reset
1237         counter = 0;
1238         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1239         if (tmp < 0)
1240                 return -EIO;
1241         tmp &= 0x7f;
1242         while (counter++ < 5) {
1243                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1244                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1245                 tda1004x_write_mask(i2c, tda_state, TDA1004X_UNCOR, 0x80, 0);
1246
1247                 tmp2 = tda1004x_read_byte(i2c, tda_state, TDA1004X_UNCOR);
1248                 if (tmp2 < 0)
1249                         return -EIO;
1250                 tmp2 &= 0x7f;
1251                 if ((tmp2 < tmp) || (tmp2 == 0))
1252                         break;
1253         }
1254
1255         // done
1256         if (tmp != 0x7f) {
1257                 *ucblocks = tmp;
1258         } else {
1259                 *ucblocks = 0xffffffff;
1260         }
1261         dprintk("%s: ucblocks=0x%x\n", __FUNCTION__, *ucblocks);
1262         return 0;
1263 }
1264
1265 static int tda1004x_read_ber(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state, u32* ber)
1266 {
1267         int tmp;
1268
1269         dprintk("%s\n", __FUNCTION__);
1270
1271         // read it in
1272         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_LSB);
1273         if (tmp < 0) return -EIO;
1274         *ber = tmp << 1;
1275         tmp = tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_MSB);
1276         if (tmp < 0) return -EIO;
1277         *ber |= (tmp << 9);
1278         tda1004x_read_byte(i2c, tda_state, TDA1004X_CBER_RESET);
1279
1280         // done
1281         dprintk("%s: ber=0x%x\n", __FUNCTION__, *ber);
1282         return 0;
1283 }
1284
1285 static int tda1004x_sleep(struct dvb_i2c_bus *i2c, struct tda1004x_state* tda_state)
1286 {
1287         switch(tda_state->fe_type) {
1288         case FE_TYPE_TDA10045H:
1289                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFADC1, 0x10, 0x10);
1290                 break;
1291
1292         case FE_TYPE_TDA10046H:
1293                 tda1004x_write_mask(i2c, tda_state, TDA1004X_CONFC4, 1, 1);
1294                 break;
1295         }
1296
1297         return 0;
1298 }
1299
1300
1301 static int tda1004x_ioctl(struct dvb_frontend *fe, unsigned int cmd, void *arg)
1302 {
1303         int status = 0;
1304         struct dvb_i2c_bus *i2c = fe->i2c;
1305         struct tda1004x_state *tda_state = (struct tda1004x_state *) fe->data;
1306
1307         dprintk("%s: cmd=0x%x\n", __FUNCTION__, cmd);
1308
1309         switch (cmd) {
1310         case FE_GET_INFO:
1311                 switch(tda_state->fe_type) {
1312                 case FE_TYPE_TDA10045H:
1313                         memcpy(arg, &tda10045h_info, sizeof(struct dvb_frontend_info));
1314                         break;
1315
1316                 case FE_TYPE_TDA10046H:
1317                         memcpy(arg, &tda10046h_info, sizeof(struct dvb_frontend_info));
1318                         break;
1319                 }
1320                 break;
1321
1322         case FE_READ_STATUS:
1323                 return tda1004x_read_status(i2c, tda_state, (fe_status_t *) arg);
1324
1325         case FE_READ_BER:
1326                 return tda1004x_read_ber(i2c, tda_state, (u32 *) arg);
1327
1328         case FE_READ_SIGNAL_STRENGTH:
1329                 return tda1004x_read_signal_strength(i2c, tda_state, (u16 *) arg);
1330
1331         case FE_READ_SNR:
1332                 return tda1004x_read_snr(i2c, tda_state, (u16 *) arg);
1333
1334         case FE_READ_UNCORRECTED_BLOCKS:
1335                 return tda1004x_read_ucblocks(i2c, tda_state, (u32 *) arg);
1336
1337         case FE_SET_FRONTEND:
1338                 return tda1004x_set_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1339
1340         case FE_GET_FRONTEND:
1341                 return tda1004x_get_fe(i2c, tda_state, (struct dvb_frontend_parameters*) arg);
1342
1343         case FE_SLEEP:
1344                 tda_state->initialised = 0;
1345                 return tda1004x_sleep(i2c, tda_state);
1346
1347         case FE_INIT:
1348
1349                 // don't bother reinitialising
1350                 if (tda_state->initialised)
1351                         return 0;
1352
1353                 // OK, perform initialisation
1354                 switch(tda_state->fe_type) {
1355                 case FE_TYPE_TDA10045H:
1356                         status = tda10045h_init(i2c, tda_state);
1357                         break;
1358
1359                 case FE_TYPE_TDA10046H:
1360                         status = tda10046h_init(i2c, tda_state);
1361                         break;
1362                 }
1363                 if (status == 0)
1364                         tda_state->initialised = 1;
1365                 return status;
1366
1367         case FE_GET_TUNE_SETTINGS:
1368         {
1369                 struct dvb_frontend_tune_settings* fesettings = (struct dvb_frontend_tune_settings*) arg;
1370                 fesettings->min_delay_ms = 800;
1371                 fesettings->step_size = 166667;
1372                 fesettings->max_drift = 166667*2;
1373                 return 0;
1374         }
1375
1376         default:
1377                 return -EOPNOTSUPP;
1378         }
1379
1380         return 0;
1381 }
1382
1383
1384 static int tda1004x_attach(struct dvb_i2c_bus *i2c, void **data)
1385 {
1386         int tda1004x_address = -1;
1387         int tuner_address = -1;
1388         int fe_type = -1;
1389         int tuner_type = -1;
1390         struct tda1004x_state tda_state;
1391         struct tda1004x_state* ptda_state;
1392         struct i2c_msg tuner_msg = {.addr=0, .flags=0, .buf=NULL, .len=0 };
1393         static u8 td1344_init[] = { 0x0b, 0xf5, 0x88, 0xab };
1394         static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
1395         static u8 td1316_init_tda10046h[] = { 0x0b, 0xf5, 0x80, 0xab };
1396         int status;
1397
1398         dprintk("%s\n", __FUNCTION__);
1399
1400         // probe for tda10045h
1401         if (tda1004x_address == -1) {
1402                 tda_state.tda1004x_address = 0x08;
1403         if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x25) {
1404                         tda1004x_address = 0x08;
1405                         fe_type = FE_TYPE_TDA10045H;
1406                 printk("tda1004x: Detected Philips TDA10045H.\n");
1407         }
1408         }
1409
1410         // probe for tda10046h
1411         if (tda1004x_address == -1) {
1412                 tda_state.tda1004x_address = 0x08;
1413                 if (tda1004x_read_byte(i2c, &tda_state, TDA1004X_CHIPID) == 0x46) {
1414                         tda1004x_address = 0x08;
1415                         fe_type = FE_TYPE_TDA10046H;
1416                         printk("tda1004x: Detected Philips TDA10046H.\n");
1417                 }
1418         }
1419
1420         // did we find a frontend?
1421         if (tda1004x_address == -1) {
1422                 return -ENODEV;
1423         }
1424
1425         // enable access to the tuner
1426         tda1004x_enable_tuner_i2c(i2c, &tda_state);
1427
1428         // check for a TD1344 first
1429         if (tuner_address == -1) {
1430                 tuner_msg.addr = 0x61;
1431         tuner_msg.buf = td1344_init;
1432         tuner_msg.len = sizeof(td1344_init);
1433         if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1434                 dvb_delay(1);
1435                         tuner_address = 0x61;
1436                         tuner_type = TUNER_TYPE_TD1344;
1437                         printk("tda1004x: Detected Philips TD1344 tuner.\n");
1438                 }
1439         }
1440
1441         // OK, try a TD1316 on address 0x63
1442         if (tuner_address == -1) {
1443                 tuner_msg.addr = 0x63;
1444                 tuner_msg.buf = td1316_init;
1445                 tuner_msg.len = sizeof(td1316_init);
1446                 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1447                         dvb_delay(1);
1448                         tuner_address = 0x63;
1449                         tuner_type = TUNER_TYPE_TD1316;
1450                         printk("tda1004x: Detected Philips TD1316 tuner.\n");
1451                 }
1452         }
1453
1454         // OK, TD1316 again, on address 0x60 (TDA10046H)
1455         if (tuner_address == -1) {
1456                 tuner_msg.addr = 0x60;
1457                 tuner_msg.buf = td1316_init_tda10046h;
1458                 tuner_msg.len = sizeof(td1316_init_tda10046h);
1459                 if (i2c->xfer(i2c, &tuner_msg, 1) == 1) {
1460                         dvb_delay(1);
1461                         tuner_address = 0x60;
1462                         tuner_type = TUNER_TYPE_TD1316;
1463                         printk("tda1004x: Detected Philips TD1316 tuner.\n");
1464                 }
1465         }
1466         tda1004x_disable_tuner_i2c(i2c, &tda_state);
1467
1468         // did we find a tuner?
1469         if (tuner_address == -1) {
1470                 printk("tda1004x: Detected, but with unknown tuner.\n");
1471                 return -ENODEV;
1472         }
1473
1474         // create state
1475         tda_state.tda1004x_address = tda1004x_address;
1476         tda_state.fe_type = fe_type;
1477         tda_state.tuner_address = tuner_address;
1478         tda_state.tuner_type = tuner_type;
1479         tda_state.initialised = 0;
1480
1481         // upload firmware
1482         if ((status = tda1004x_fwupload(i2c, &tda_state)) != 0) return status;
1483
1484         // create the real state we'll be passing about
1485         if ((ptda_state = (struct tda1004x_state*) kmalloc(sizeof(struct tda1004x_state), GFP_KERNEL)) == NULL) {
1486                 return -ENOMEM;
1487         }
1488         memcpy(ptda_state, &tda_state, sizeof(struct tda1004x_state));
1489         *data = ptda_state;
1490
1491         // register
1492         switch(tda_state.fe_type) {
1493         case FE_TYPE_TDA10045H:
1494                 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10045h_info);
1495
1496         case FE_TYPE_TDA10046H:
1497                 return dvb_register_frontend(tda1004x_ioctl, i2c, ptda_state, &tda10046h_info);
1498         }
1499
1500         // should not get here
1501         return -EINVAL;
1502 }
1503
1504
1505 static
1506 void tda1004x_detach(struct dvb_i2c_bus *i2c, void *data)
1507 {
1508         dprintk("%s\n", __FUNCTION__);
1509
1510         kfree(data);
1511         dvb_unregister_frontend(tda1004x_ioctl, i2c);
1512 }
1513
1514
1515 static
1516 int __init init_tda1004x(void)
1517 {
1518         return dvb_register_i2c_device(THIS_MODULE, tda1004x_attach, tda1004x_detach);
1519 }
1520
1521
1522 static
1523 void __exit exit_tda1004x(void)
1524 {
1525         dvb_unregister_i2c_device(tda1004x_attach);
1526 }
1527
1528 module_init(init_tda1004x);
1529 module_exit(exit_tda1004x);
1530
1531 MODULE_DESCRIPTION("Philips TDA10045H & TDA10046H DVB-T Frontend");
1532 MODULE_AUTHOR("Andrew de Quincey & Robert Schlabbach");
1533 MODULE_LICENSE("GPL");
1534
1535 MODULE_PARM(tda1004x_debug, "i");
1536 MODULE_PARM_DESC(tda1004x_debug, "enable verbose debug messages");
1537
1538 MODULE_PARM(tda1004x_firmware, "s");
1539 MODULE_PARM_DESC(tda1004x_firmware, "Where to find the firmware file");