drivers/media/dvb/frontends/ves1820.c

   1 /*
   2     VES1820  - Single Chip Cable Channel Receiver driver module
   3
   4     Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14     GNU General Public License for more details.
  15
  16     You should have received a copy of the GNU General Public License
  17     along with this program; if not, write to the Free Software
  18     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19 */
  20
  21 #include <linux/config.h>
  22 #include <linux/delay.h>
  23 #include <linux/errno.h>
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/string.h>
  28 #include <linux/slab.h>
  29 #include <asm/div64.h>
  30
  31 #include "dvb_frontend.h"
  32 #include "ves1820.h"
  33
  34
  35
  36 struct ves1820_state {
  37
  38         struct i2c_adapter *i2c;
  39
  40         struct dvb_frontend_ops ops;
  41
  42         /* configuration settings */
  43         const struct ves1820_config* config;
  44
  45         struct dvb_frontend frontend;
  46
  47         /* private demodulator data */
  48         u8 reg0;
  49         u8 pwm;
  50 };
  51
  52
  53 static int verbose;
  54
  55 static u8 ves1820_inittab[] = {
  56         0x69, 0x6A, 0x93, 0x12, 0x12, 0x46, 0x26, 0x1A,
  57         0x43, 0x6A, 0xAA, 0xAA, 0x1E, 0x85, 0x43, 0x20,
  58         0xE0, 0x00, 0xA1, 0x00, 0x00, 0x00, 0x00, 0x00,
  59         0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
  60         0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  61         0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  62         0x00, 0x00, 0x00, 0x00, 0x40
  63 };
  64
  65 static int ves1820_writereg(struct ves1820_state *state, u8 reg, u8 data)
  66 {
  67         u8 buf[] = { 0x00, reg, data };
  68         struct i2c_msg msg = {.addr = state->config->demod_address,.flags = 0,.buf = buf,.len = 3 };
  69         int ret;
  70
  71         ret = i2c_transfer(state->i2c, &msg, 1);
  72
  73         if (ret != 1)
  74                 printk("ves1820: %s(): writereg error (reg == 0x%02x,"
  75                         "val == 0x%02x, ret == %i)\n", __FUNCTION__, reg, data, ret);
  76
  77         msleep(10);
  78         return (ret != 1) ? -EREMOTEIO : 0;
  79 }
  80
  81 static u8 ves1820_readreg(struct ves1820_state *state, u8 reg)
  82 {
  83         u8 b0 [] = { 0x00, reg };
  84         u8 b1 [] = { 0 };
  85         struct i2c_msg msg[] = {
  86                 {.addr = state->config->demod_address,.flags = 0,.buf = b0,.len = 2},
  87                 {.addr = state->config->demod_address,.flags = I2C_M_RD,.buf = b1,.len = 1}
  88         };
  89         int ret;
  90
  91         ret = i2c_transfer(state->i2c, msg, 2);
  92
  93         if (ret != 2)
  94                 printk("ves1820: %s(): readreg error (reg == 0x%02x,"
  95                 "ret == %i)\n", __FUNCTION__, reg, ret);
  96
  97         return b1[0];
  98 }
  99
 100
 101 static int ves1820_setup_reg0(struct ves1820_state *state, u8 reg0, fe_spectral_inversion_t inversion)
 102 {
 103         reg0 |= state->reg0 & 0x62;
 104
 105         if (INVERSION_ON == inversion) {
 106                 if (!state->config->invert) reg0 |= 0x20;
 107                 else reg0 &= ~0x20;
 108
 109         } else if (INVERSION_OFF == inversion) {
 110
 111                 if (!state->config->invert) reg0 &= ~0x20;
 112                 else reg0 |= 0x20;
 113         }
 114
 115                         ves1820_writereg(state, 0x00, reg0 & 0xfe);
 116                         ves1820_writereg(state, 0x00, reg0 | 0x01);
 117
 118         state->reg0 = reg0;
 119
 120         return 0;
 121 }
 122
 123 static int ves1820_set_symbolrate(struct ves1820_state *state, u32 symbolrate)
 124 {
 125         s32 BDR;
 126         s32 BDRI;
 127         s16 SFIL=0;
 128         u16 NDEC = 0;
 129         u32 ratio;
 130         u32 fin;
 131         u32 tmp;
 132         u64 fptmp;
 133         u64 fpxin;
 134
 135         if (symbolrate > state->config->xin / 2)
 136                 symbolrate = state->config->xin / 2;
 137
 138         if (symbolrate < 500000)
 139                 symbolrate = 500000;
 140
 141         if (symbolrate < state->config->xin / 16)
 142                 NDEC = 1;
 143         if (symbolrate < state->config->xin / 32)
 144                 NDEC = 2;
 145         if (symbolrate < state->config->xin / 64)
 146                 NDEC = 3;
 147
 148         /* yeuch! */
 149         fpxin = state->config->xin * 10;
 150         fptmp = fpxin; do_div(fptmp, 123);
 151         if (symbolrate < fptmp);
 152                 SFIL = 1;
 153         fptmp = fpxin; do_div(fptmp, 160);
 154         if (symbolrate < fptmp);
 155                 SFIL = 0;
 156         fptmp = fpxin; do_div(fptmp, 246);
 157         if (symbolrate < fptmp);
 158                 SFIL = 1;
 159         fptmp = fpxin; do_div(fptmp, 320);
 160         if (symbolrate < fptmp);
 161                 SFIL = 0;
 162         fptmp = fpxin; do_div(fptmp, 492);
 163         if (symbolrate < fptmp);
 164                 SFIL = 1;
 165         fptmp = fpxin; do_div(fptmp, 640);
 166         if (symbolrate < fptmp);
 167                 SFIL = 0;
 168         fptmp = fpxin; do_div(fptmp, 984);
 169         if (symbolrate < fptmp);
 170                 SFIL = 1;
 171
 172         fin = state->config->xin >> 4;
 173         symbolrate <<= NDEC;
 174         ratio = (symbolrate << 4) / fin;
 175         tmp = ((symbolrate << 4) % fin) << 8;
 176         ratio = (ratio << 8) + tmp / fin;
 177         tmp = (tmp % fin) << 8;
 178         ratio = (ratio << 8) + (tmp + fin / 2) / fin;
 179
 180         BDR = ratio;
 181         BDRI = (((state->config->xin << 5) / symbolrate) + 1) / 2;
 182
 183         if (BDRI > 0xFF)
 184                 BDRI = 0xFF;
 185
 186         SFIL = (SFIL << 4) | ves1820_inittab[0x0E];
 187
 188         NDEC = (NDEC << 6) | ves1820_inittab[0x03];
 189
 190         ves1820_writereg(state, 0x03, NDEC);
 191         ves1820_writereg(state, 0x0a, BDR & 0xff);
 192         ves1820_writereg(state, 0x0b, (BDR >> 8) & 0xff);
 193         ves1820_writereg(state, 0x0c, (BDR >> 16) & 0x3f);
 194
 195         ves1820_writereg(state, 0x0d, BDRI);
 196         ves1820_writereg(state, 0x0e, SFIL);
 197
 198         return 0;
 199 }
 200
 201
 202
 203
 204
 205
 206
 207
 208
 209
 210
 211
 212
 213 static int ves1820_init(struct dvb_frontend* fe)
 214 {
 215         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 216         int i;
 217         int val;
 218
 219         ves1820_writereg(state, 0, 0);
 220
 221         for (i = 0; i < 53; i++) {
 222                 val = ves1820_inittab[i];
 223                 if ((i == 2) && (state->config->selagc)) val |= 0x08;
 224                 ves1820_writereg(state, i, val);
 225         }
 226
 227         ves1820_writereg(state, 0x34, state->pwm);
 228
 229         if (state->config->pll_init) state->config->pll_init(fe);
 230
 231         return 0;
 232 }
 233
 234 static int ves1820_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 235 {
 236         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 237         static const u8 reg0x00 [] = { 0x00, 0x04, 0x08, 0x0c, 0x10 };
 238         static const u8 reg0x01 [] = {  140,  140,  106,  100,   92 };
 239         static const u8 reg0x05 [] = {  135,  100,   70,   54,   38 };
 240         static const u8 reg0x08 [] = {  162,  116,   67,   52,   35 };
 241         static const u8 reg0x09 [] = {  145,  150,  106,  126,  107 };
 242         int real_qam = p->u.qam.modulation - QAM_16;
 243
 244         if (real_qam < 0 || real_qam > 4)
 245                 return -EINVAL;
 246
 247         state->config->pll_set(fe, p);
 248         ves1820_set_symbolrate(state, p->u.qam.symbol_rate);
 249         ves1820_writereg(state, 0x34, state->pwm);
 250
 251         ves1820_writereg(state, 0x01, reg0x01[real_qam]);
 252         ves1820_writereg(state, 0x05, reg0x05[real_qam]);
 253         ves1820_writereg(state, 0x08, reg0x08[real_qam]);
 254         ves1820_writereg(state, 0x09, reg0x09[real_qam]);
 255
 256         ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
 257
 258         return 0;
 259 }
 260
 261 static int ves1820_read_status(struct dvb_frontend* fe, fe_status_t* status)
 262 {
 263         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 264                 int sync;
 265
 266                 *status = 0;
 267
 268                         sync = ves1820_readreg(state, 0x11);
 269
 270                 if (sync & 1)
 271                         *status |= FE_HAS_SIGNAL;
 272
 273                 if (sync & 2)
 274                         *status |= FE_HAS_CARRIER;
 275
 276                 if (sync & 2)           /* XXX FIXME! */
 277                         *status |= FE_HAS_VITERBI;
 278
 279                 if (sync & 4)
 280                         *status |= FE_HAS_SYNC;
 281
 282                 if (sync & 8)
 283                         *status |= FE_HAS_LOCK;
 284
 285         return 0;
 286         }
 287
 288 static int ves1820_read_ber(struct dvb_frontend* fe, u32* ber)
 289         {
 290         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 291
 292         u32 _ber = ves1820_readreg(state, 0x14) |
 293                                         (ves1820_readreg(state, 0x15) << 8) |
 294                                         ((ves1820_readreg(state, 0x16) & 0x0f) << 16);
 295         *ber = 10 * _ber;
 296
 297         return 0;
 298         }
 299
 300 static int ves1820_read_signal_strength(struct dvb_frontend* fe, u16* strength)
 301         {
 302         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 303
 304                         u8 gain = ves1820_readreg(state, 0x17);
 305         *strength = (gain << 8) | gain;
 306
 307         return 0;
 308         }
 309
 310 static int ves1820_read_snr(struct dvb_frontend* fe, u16* snr)
 311         {
 312         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 313
 314                         u8 quality = ~ves1820_readreg(state, 0x18);
 315         *snr = (quality << 8) | quality;
 316
 317         return 0;
 318         }
 319
 320 static int ves1820_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 321 {
 322         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 323
 324         *ucblocks = ves1820_readreg(state, 0x13) & 0x7f;
 325         if (*ucblocks == 0x7f)
 326                 *ucblocks = 0xffffffff;
 327
 328                 /* reset uncorrected block counter */
 329                 ves1820_writereg(state, 0x10, ves1820_inittab[0x10] & 0xdf);
 330                 ves1820_writereg(state, 0x10, ves1820_inittab[0x10]);
 331
 332         return 0;
 333 }
 334
 335 static int ves1820_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 336         {
 337         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 338                 int sync;
 339                 s8 afc = 0;
 340
 341                         sync = ves1820_readreg(state, 0x11);
 342                         afc = ves1820_readreg(state, 0x19);
 343                 if (verbose) {
 344                         /* AFC only valid when carrier has been recovered */
 345                                 printk(sync & 2 ? "ves1820: AFC (%d) %dHz\n" :
 346                                         "ves1820: [AFC (%d) %dHz]\n", afc, -((s32) p->u.qam.symbol_rate * afc) >> 10);
 347                 }
 348
 349         if (!state->config->invert) {
 350                 p->inversion = (state->reg0 & 0x20) ? INVERSION_ON : INVERSION_OFF;
 351         } else {
 352                 p->inversion = (!(state->reg0 & 0x20)) ? INVERSION_ON : INVERSION_OFF;
 353         }
 354
 355                         p->u.qam.modulation = ((state->reg0 >> 2) & 7) + QAM_16;
 356
 357                 p->u.qam.fec_inner = FEC_NONE;
 358
 359                 p->frequency = ((p->frequency + 31250) / 62500) * 62500;
 360                 if (sync & 2)
 361                         p->frequency -= ((s32)p->u.qam.symbol_rate * afc) >> 10;
 362
 363         return 0;
 364 }
 365
 366 static int ves1820_sleep(struct dvb_frontend* fe)
 367 {
 368         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 369
 370         ves1820_writereg(state, 0x1b, 0x02);    /* pdown ADC */
 371         ves1820_writereg(state, 0x00, 0x80);    /* standby */
 372
 373         return 0;
 374 }
 375
 376 static int ves1820_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
 377 {
 378
 379         fesettings->min_delay_ms = 200;
 380         fesettings->step_size = 0;
 381         fesettings->max_drift = 0;
 382         return 0;
 383 }
 384
 385 static void ves1820_release(struct dvb_frontend* fe)
 386 {
 387         struct ves1820_state* state = (struct ves1820_state*) fe->demodulator_priv;
 388         kfree(state);
 389 }
 390
 391 static struct dvb_frontend_ops ves1820_ops;
 392
 393 struct dvb_frontend* ves1820_attach(const struct ves1820_config* config,
 394                                     struct i2c_adapter* i2c,
 395                                     u8 pwm)
 396 {
 397         struct ves1820_state* state = NULL;
 398
 399         /* allocate memory for the internal state */
 400         state = (struct ves1820_state*) kmalloc(sizeof(struct ves1820_state), GFP_KERNEL);
 401         if (state == NULL)
 402                 goto error;
 403
 404         /* setup the state */
 405         memcpy(&state->ops, &ves1820_ops, sizeof(struct dvb_frontend_ops));
 406         state->reg0 = ves1820_inittab[0];
 407         state->config = config;
 408         state->i2c = i2c;
 409         state->pwm = pwm;
 410
 411         /* check if the demod is there */
 412         if ((ves1820_readreg(state, 0x1a) & 0xf0) != 0x70)
 413                 goto error;
 414
 415         if (verbose)
 416                 printk("ves1820: pwm=0x%02x\n", state->pwm);
 417
 418         state->ops.info.symbol_rate_min = (state->config->xin / 2) / 64;      /* SACLK/64 == (XIN/2)/64 */
 419         state->ops.info.symbol_rate_max = (state->config->xin / 2) / 4;       /* SACLK/4 */
 420
 421         /* create dvb_frontend */
 422         state->frontend.ops = &state->ops;
 423         state->frontend.demodulator_priv = state;
 424         return &state->frontend;
 425
 426 error:
 427         if (state) kfree(state);
 428         return NULL;
 429         }
 430
 431 static struct dvb_frontend_ops ves1820_ops = {
 432
 433         .info = {
 434                 .name = "VLSI VES1820 DVB-C",
 435                 .type = FE_QAM,
 436                 .frequency_stepsize = 62500,
 437                 .frequency_min = 51000000,
 438                 .frequency_max = 858000000,
 439                 .caps = FE_CAN_QAM_16 |
 440                         FE_CAN_QAM_32 |
 441                         FE_CAN_QAM_64 |
 442                         FE_CAN_QAM_128 |
 443                         FE_CAN_QAM_256 |
 444                         FE_CAN_FEC_AUTO
 445         },
 446
 447         .release = ves1820_release,
 448
 449         .init = ves1820_init,
 450         .sleep = ves1820_sleep,
 451
 452         .set_frontend = ves1820_set_parameters,
 453         .get_frontend = ves1820_get_frontend,
 454         .get_tune_settings = ves1820_get_tune_settings,
 455
 456         .read_status = ves1820_read_status,
 457         .read_ber = ves1820_read_ber,
 458         .read_signal_strength = ves1820_read_signal_strength,
 459         .read_snr = ves1820_read_snr,
 460         .read_ucblocks = ves1820_read_ucblocks,
 461 };
 462
 463 module_param(verbose, int, 0644);
 464 MODULE_PARM_DESC(verbose, "print AFC offset after tuning for debugging the PWM setting");
 465
 466 MODULE_DESCRIPTION("VLSI VES1820 DVB-C Demodulator driver");
 467 MODULE_AUTHOR("Ralph Metzler, Holger Waechtler");
 468 MODULE_LICENSE("GPL");
 469
 470 EXPORT_SYMBOL(ves1820_attach);