drivers/media/video/cx88/cx88-mpeg.c

   1 /*
   2  * $Id: cx88-mpeg.c,v 1.14 2004/10/25 11:26:36 kraxel Exp $
   3  *
   4  *  Support for the mpeg transport stream transfers
   5  *  PCI function #2 of the cx2388x.
   6  *
   7  *    (c) 2004 Jelle Foks <jelle@foks.8m.com>
   8  *    (c) 2004 Chris Pascoe <c.pascoe@itee.uq.edu.au>
   9  *    (c) 2004 Gerd Knorr <kraxel@bytesex.org>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify
  12  *  it under the terms of the GNU General Public License as published by
  13  *  the Free Software Foundation; either version 2 of the License, or
  14  *  (at your option) any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful,
  17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *  GNU General Public License for more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License
  22  *  along with this program; if not, write to the Free Software
  23  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/device.h>
  29 #include <linux/interrupt.h>
  30 #include <asm/delay.h>
  31
  32 #include "cx88.h"
  33
  34 /* ------------------------------------------------------------------ */
  35
  36 MODULE_DESCRIPTION("mpeg driver for cx2388x based TV cards");
  37 MODULE_AUTHOR("Jelle Foks <jelle@foks.8m.com>");
  38 MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  39 MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  40 MODULE_LICENSE("GPL");
  41
  42 static unsigned int debug = 0;
  43 module_param(debug,int,0644);
  44 MODULE_PARM_DESC(debug,"enable debug messages [mpeg]");
  45
  46 #define dprintk(level,fmt, arg...)      if (debug >= level) \
  47         printk(KERN_DEBUG "%s/2: " fmt, dev->core->name , ## arg)
  48
  49 /* ------------------------------------------------------------------ */
  50
  51 static int cx8802_start_dma(struct cx8802_dev    *dev,
  52                             struct cx88_dmaqueue *q,
  53                             struct cx88_buffer   *buf)
  54 {
  55         struct cx88_core *core = dev->core;
  56
  57         dprintk(1, "cx8802_start_mpegport_dma %d\n", buf->vb.width);
  58
  59         /* setup fifo + format */
  60         cx88_sram_channel_setup(core, &cx88_sram_channels[SRAM_CH28],
  61                                 dev->ts_packet_size, buf->risc.dma);
  62
  63         /* write TS length to chip */
  64         cx_write(MO_TS_LNGTH, buf->vb.width);
  65
  66 #if 1
  67         /* FIXME: this needs a review.
  68          * also: move to cx88-blackbird + cx88-dvb source files? */
  69
  70         if (cx88_boards[core->board].dvb) {
  71                 /* Setup TS portion of chip */
  72                 cx_write(TS_GEN_CNTRL, 0x0c);
  73         }
  74
  75         if (cx88_boards[core->board].blackbird) {
  76                 cx_write(MO_PINMUX_IO, 0x88); /* enable MPEG parallel IO */
  77
  78                 // cx_write(TS_F2_CMD_STAT_MM, 0x2900106); /* F2_CMD_STAT_MM defaults + master + memory space */
  79                 cx_write(TS_GEN_CNTRL, 0x46); /* punctured clock TS & posedge driven & software reset */
  80                 udelay(100);
  81
  82                 cx_write(TS_HW_SOP_CNTRL, 0x408); /* mpeg start byte */
  83                 //cx_write(TS_HW_SOP_CNTRL, 0x2F0BC0); /* mpeg start byte ts: 0x2F0BC0 ? */
  84                 cx_write(TS_VALERR_CNTRL, 0x2000);
  85
  86                 cx_write(TS_GEN_CNTRL, 0x06); /* punctured clock TS & posedge driven */
  87                 udelay(100);
  88         }
  89 #endif
  90
  91         /* reset counter */
  92         cx_write(MO_TS_GPCNTRL, GP_COUNT_CONTROL_RESET);
  93         q->count = 1;
  94
  95         /* enable irqs */
  96         cx_set(MO_PCI_INTMSK, 0x00fc04);
  97         cx_write(MO_TS_INTMSK,  0x1f0011);
  98
  99         /* start dma */
 100         cx_write(MO_DEV_CNTRL2, (1<<5)); /* FIXME: s/write/set/ ??? */
 101         cx_write(MO_TS_DMACNTRL, 0x11);
 102         return 0;
 103 }
 104
 105 static int cx8802_stop_dma(struct cx8802_dev *dev)
 106 {
 107         struct cx88_core *core = dev->core;
 108
 109         /* stop dma */
 110         cx_clear(MO_TS_DMACNTRL, 0x11);
 111
 112         /* disable irqs */
 113         cx_clear(MO_PCI_INTMSK, 0x000004);
 114         cx_clear(MO_TS_INTMSK, 0x1f0011);
 115
 116         /* Reset the controller */
 117         cx_write(TS_GEN_CNTRL, 0xcd);
 118         return 0;
 119 }
 120
 121 static int cx8802_restart_queue(struct cx8802_dev    *dev,
 122                                 struct cx88_dmaqueue *q)
 123 {
 124         struct cx88_buffer *buf;
 125         struct list_head *item;
 126
 127         if (list_empty(&q->active))
 128                 return 0;
 129
 130         buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
 131         dprintk(2,"restart_queue [%p/%d]: restart dma\n",
 132                 buf, buf->vb.i);
 133         cx8802_start_dma(dev, q, buf);
 134         list_for_each(item,&q->active) {
 135                 buf = list_entry(item, struct cx88_buffer, vb.queue);
 136                 buf->count = q->count++;
 137         }
 138         mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 139         return 0;
 140 }
 141
 142 /* ------------------------------------------------------------------ */
 143
 144 int cx8802_buf_prepare(struct cx8802_dev *dev, struct cx88_buffer *buf)
 145 {
 146         int size = dev->ts_packet_size * dev->ts_packet_count;
 147         int rc;
 148
 149         dprintk(1, "%s: %p\n", __FUNCTION__, buf);
 150         if (0 != buf->vb.baddr  &&  buf->vb.bsize < size)
 151                 return -EINVAL;
 152
 153         if (STATE_NEEDS_INIT == buf->vb.state) {
 154                 buf->vb.width  = dev->ts_packet_size;
 155                 buf->vb.height = dev->ts_packet_count;
 156                 buf->vb.size   = size;
 157                 buf->vb.field  = V4L2_FIELD_TOP;
 158
 159                 if (0 != (rc = videobuf_iolock(dev->pci,&buf->vb,NULL)))
 160                         goto fail;
 161                 cx88_risc_databuffer(dev->pci, &buf->risc,
 162                                      buf->vb.dma.sglist,
 163                                      buf->vb.width, buf->vb.height);
 164         }
 165         buf->vb.state = STATE_PREPARED;
 166         return 0;
 167
 168  fail:
 169         cx88_free_buffer(dev->pci,buf);
 170         return rc;
 171 }
 172
 173 void cx8802_buf_queue(struct cx8802_dev *dev, struct cx88_buffer *buf)
 174 {
 175         struct cx88_buffer    *prev;
 176         struct cx88_dmaqueue  *q    = &dev->mpegq;
 177
 178         /* add jump to stopper */
 179         buf->risc.jmp[0] = cpu_to_le32(RISC_JUMP | RISC_IRQ1 | RISC_CNT_INC);
 180         buf->risc.jmp[1] = cpu_to_le32(q->stopper.dma);
 181
 182         if (list_empty(&q->active)) {
 183                 list_add_tail(&buf->vb.queue,&q->active);
 184                 cx8802_start_dma(dev, q, buf);
 185                 buf->vb.state = STATE_ACTIVE;
 186                 buf->count    = q->count++;
 187                 mod_timer(&q->timeout, jiffies+BUFFER_TIMEOUT);
 188                 dprintk(2,"[%p/%d] %s - first active\n",
 189                         buf, buf->vb.i, __FUNCTION__);
 190
 191         } else {
 192                 prev = list_entry(q->active.prev, struct cx88_buffer, vb.queue);
 193                 list_add_tail(&buf->vb.queue,&q->active);
 194                 buf->vb.state = STATE_ACTIVE;
 195                 buf->count    = q->count++;
 196                 prev->risc.jmp[1] = cpu_to_le32(buf->risc.dma);
 197                 dprintk(2,"[%p/%d] %s - append to active\n",
 198                         buf, buf->vb.i, __FUNCTION__);
 199         }
 200 }
 201
 202 /* ----------------------------------------------------------- */
 203
 204 static void do_cancel_buffers(struct cx8802_dev *dev, char *reason, int restart)
 205 {
 206         struct cx88_dmaqueue *q = &dev->mpegq;
 207         struct cx88_buffer *buf;
 208         unsigned long flags;
 209
 210         spin_lock_irqsave(&dev->slock,flags);
 211         while (!list_empty(&q->active)) {
 212                 buf = list_entry(q->active.next, struct cx88_buffer, vb.queue);
 213                 list_del(&buf->vb.queue);
 214                 buf->vb.state = STATE_ERROR;
 215                 wake_up(&buf->vb.done);
 216                 dprintk(1,"[%p/%d] %s - dma=0x%08lx\n",
 217                         buf, buf->vb.i, reason, (unsigned long)buf->risc.dma);
 218         }
 219         if (restart)
 220                 cx8802_restart_queue(dev,q);
 221         spin_unlock_irqrestore(&dev->slock,flags);
 222 }
 223
 224 void cx8802_cancel_buffers(struct cx8802_dev *dev)
 225 {
 226         struct cx88_dmaqueue *q = &dev->mpegq;
 227
 228         del_timer_sync(&q->timeout);
 229         cx8802_stop_dma(dev);
 230         do_cancel_buffers(dev,"cancel",0);
 231 }
 232
 233 static void cx8802_timeout(unsigned long data)
 234 {
 235         struct cx8802_dev *dev = (struct cx8802_dev*)data;
 236
 237         dprintk(1, "%s\n",__FUNCTION__);
 238
 239         if (debug)
 240                 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
 241         cx8802_stop_dma(dev);
 242         do_cancel_buffers(dev,"timeout",1);
 243 }
 244
 245 static void cx8802_mpeg_irq(struct cx8802_dev *dev)
 246 {
 247         struct cx88_core *core = dev->core;
 248         u32 status, mask, count;
 249
 250         status = cx_read(MO_TS_INTSTAT);
 251         mask   = cx_read(MO_TS_INTMSK);
 252         if (0 == (status & mask))
 253                 return;
 254
 255         cx_write(MO_TS_INTSTAT, status);
 256         if (debug || (status & mask & ~0xff))
 257                 cx88_print_irqbits(core->name, "irq mpeg ",
 258                                    cx88_mpeg_irqs, status, mask);
 259
 260         /* risc op code error */
 261         if (status & (1 << 16)) {
 262                 printk(KERN_WARNING "%s: mpeg risc op code error\n",core->name);
 263                 cx_clear(MO_TS_DMACNTRL, 0x11);
 264                 cx88_sram_channel_dump(dev->core, &cx88_sram_channels[SRAM_CH28]);
 265         }
 266
 267         /* risc1 y */
 268         if (status & 0x01) {
 269                 spin_lock(&dev->slock);
 270                 count = cx_read(MO_TS_GPCNT);
 271                 cx88_wakeup(dev->core, &dev->mpegq, count);
 272                 spin_unlock(&dev->slock);
 273         }
 274
 275         /* risc2 y */
 276         if (status & 0x10) {
 277                 spin_lock(&dev->slock);
 278                 cx8802_restart_queue(dev,&dev->mpegq);
 279                 spin_unlock(&dev->slock);
 280         }
 281
 282         /* other general errors */
 283         if (status & 0x1f0100) {
 284                 spin_lock(&dev->slock);
 285                 cx8802_stop_dma(dev);
 286                 cx8802_restart_queue(dev,&dev->mpegq);
 287                 spin_unlock(&dev->slock);
 288         }
 289 }
 290
 291 static irqreturn_t cx8802_irq(int irq, void *dev_id, struct pt_regs *regs)
 292 {
 293         struct cx8802_dev *dev = dev_id;
 294         struct cx88_core *core = dev->core;
 295         u32 status, mask;
 296         int loop, handled = 0;
 297
 298         for (loop = 0; loop < 10; loop++) {
 299                 status = cx_read(MO_PCI_INTSTAT) & (~0x1f | 0x04);
 300                 mask   = cx_read(MO_PCI_INTMSK);
 301                 if (0 == (status & mask))
 302                         goto out;
 303                 handled = 1;
 304                 cx_write(MO_PCI_INTSTAT, status);
 305
 306                 if (status & mask & ~0x1f)
 307                         cx88_irq(core,status,mask);
 308                 if (status & 0x04)
 309                         cx8802_mpeg_irq(dev);
 310         };
 311         if (10 == loop) {
 312                 printk(KERN_WARNING "%s/0: irq loop -- clearing mask\n",
 313                        core->name);
 314                 cx_write(MO_PCI_INTMSK,0);
 315         }
 316
 317  out:
 318         return IRQ_RETVAL(handled);
 319 }
 320
 321 /* ----------------------------------------------------------- */
 322 /* exported stuff                                              */
 323
 324 int cx8802_init_common(struct cx8802_dev *dev)
 325 {
 326         int err;
 327
 328         /* pci init */
 329         if (pci_enable_device(dev->pci))
 330                 return -EIO;
 331         pci_set_master(dev->pci);
 332         if (!pci_dma_supported(dev->pci,0xffffffff)) {
 333                 printk("%s/2: Oops: no 32bit PCI DMA ???\n",dev->core->name);
 334                 return -EIO;
 335         }
 336
 337         pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev);
 338         pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER,  &dev->pci_lat);
 339         printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, "
 340                "latency: %d, mmio: 0x%lx\n", dev->core->name,
 341                pci_name(dev->pci), dev->pci_rev, dev->pci->irq,
 342                dev->pci_lat,pci_resource_start(dev->pci,0));
 343
 344         /* initialize driver struct */
 345         init_MUTEX(&dev->lock);
 346         dev->slock = SPIN_LOCK_UNLOCKED;
 347
 348         /* init dma queue */
 349         INIT_LIST_HEAD(&dev->mpegq.active);
 350         INIT_LIST_HEAD(&dev->mpegq.queued);
 351         dev->mpegq.timeout.function = cx8802_timeout;
 352         dev->mpegq.timeout.data     = (unsigned long)dev;
 353         init_timer(&dev->mpegq.timeout);
 354         cx88_risc_stopper(dev->pci,&dev->mpegq.stopper,
 355                           MO_TS_DMACNTRL,0x11,0x00);
 356
 357 #if 0 /* FIXME */
 358         /* initialize hardware */
 359         cx8802_reset(dev);
 360 #endif
 361
 362         /* get irq */
 363         err = request_irq(dev->pci->irq, cx8802_irq,
 364                           SA_SHIRQ | SA_INTERRUPT, dev->core->name, dev);
 365         if (err < 0) {
 366                 printk(KERN_ERR "%s: can't get IRQ %d\n",
 367                        dev->core->name, dev->pci->irq);
 368                 return err;
 369         }
 370
 371 #if 0 /* FIXME */
 372         /* register i2c bus + load i2c helpers */
 373         cx88_card_setup(dev);
 374 #endif
 375
 376         /* everything worked */
 377         pci_set_drvdata(dev->pci,dev);
 378         return 0;
 379 }
 380
 381 void cx8802_fini_common(struct cx8802_dev *dev)
 382 {
 383         cx8802_stop_dma(dev);
 384         pci_disable_device(dev->pci);
 385
 386         /* unregister stuff */
 387         free_irq(dev->pci->irq, dev);
 388         pci_set_drvdata(dev->pci, NULL);
 389
 390         /* free memory */
 391         btcx_riscmem_free(dev->pci,&dev->mpegq.stopper);
 392 }
 393
 394 /* ----------------------------------------------------------- */
 395
 396 int cx8802_suspend_common(struct pci_dev *pci_dev, u32 state)
 397 {
 398         struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
 399         struct cx88_core *core = dev->core;
 400
 401         /* stop mpeg dma */
 402         spin_lock(&dev->slock);
 403         if (!list_empty(&dev->mpegq.active)) {
 404                 printk("%s: suspend mpeg\n", core->name);
 405                 cx8802_stop_dma(dev);
 406                 del_timer(&dev->mpegq.timeout);
 407         }
 408         spin_unlock(&dev->slock);
 409
 410 #if 1
 411         /* FIXME -- shutdown device */
 412         cx88_shutdown(dev->core);
 413 #endif
 414
 415         pci_save_state(pci_dev);
 416         if (0 != pci_set_power_state(pci_dev, state)) {
 417                 pci_disable_device(pci_dev);
 418                 dev->state.disabled = 1;
 419         }
 420         return 0;
 421 }
 422
 423 int cx8802_resume_common(struct pci_dev *pci_dev)
 424 {
 425         struct cx8802_dev *dev = pci_get_drvdata(pci_dev);
 426         struct cx88_core *core = dev->core;
 427
 428         if (dev->state.disabled) {
 429                 pci_enable_device(pci_dev);
 430                 dev->state.disabled = 0;
 431         }
 432         pci_set_power_state(pci_dev, 0);
 433         pci_restore_state(pci_dev);
 434
 435 #if 1
 436         /* FIXME: re-initialize hardware */
 437         cx88_reset(dev->core);
 438 #endif
 439
 440         /* restart video+vbi capture */
 441         spin_lock(&dev->slock);
 442         if (!list_empty(&dev->mpegq.active)) {
 443                 printk("%s: resume mpeg\n", core->name);
 444                 cx8802_restart_queue(dev,&dev->mpegq);
 445         }
 446         spin_unlock(&dev->slock);
 447
 448         return 0;
 449 }
 450
 451 /* ----------------------------------------------------------- */
 452
 453 EXPORT_SYMBOL(cx8802_buf_prepare);
 454 EXPORT_SYMBOL(cx8802_buf_queue);
 455 EXPORT_SYMBOL(cx8802_cancel_buffers);
 456
 457 EXPORT_SYMBOL(cx8802_init_common);
 458 EXPORT_SYMBOL(cx8802_fini_common);
 459
 460 EXPORT_SYMBOL(cx8802_suspend_common);
 461 EXPORT_SYMBOL(cx8802_resume_common);
 462
 463 /* ----------------------------------------------------------- */
 464 /*
 465  * Local variables:
 466  * c-basic-offset: 8
 467  * End:
 468  */