drivers/mmc/wbsd.h

   1 /*
   2  *  linux/drivers/mmc/wbsd.h - Winbond W83L51xD SD/MMC driver
   3  *
   4  *  Copyright (C) 2004-2005 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 const int config_ports[] = { 0x2E, 0x4E };
  12 const int unlock_codes[] = { 0x83, 0x87 };
  13
  14 const int valid_ids[] = {
  15         0x7112,
  16         };
  17
  18 #define LOCK_CODE               0xAA
  19
  20 #define WBSD_CONF_SWRST         0x02
  21 #define WBSD_CONF_DEVICE        0x07
  22 #define WBSD_CONF_ID_HI         0x20
  23 #define WBSD_CONF_ID_LO         0x21
  24 #define WBSD_CONF_POWER         0x22
  25 #define WBSD_CONF_PME           0x23
  26 #define WBSD_CONF_PMES          0x24
  27
  28 #define WBSD_CONF_ENABLE        0x30
  29 #define WBSD_CONF_PORT_HI       0x60
  30 #define WBSD_CONF_PORT_LO       0x61
  31 #define WBSD_CONF_IRQ           0x70
  32 #define WBSD_CONF_DRQ           0x74
  33
  34 #define WBSD_CONF_PINS          0xF0
  35
  36 #define DEVICE_SD               0x03
  37
  38 #define WBSD_CMDR               0x00
  39 #define WBSD_DFR                0x01
  40 #define WBSD_EIR                0x02
  41 #define WBSD_ISR                0x03
  42 #define WBSD_FSR                0x04
  43 #define WBSD_IDXR               0x05
  44 #define WBSD_DATAR              0x06
  45 #define WBSD_CSR                0x07
  46
  47 #define WBSD_EINT_CARD          0x40
  48 #define WBSD_EINT_FIFO_THRE     0x20
  49 #define WBSD_EINT_CCRC          0x10
  50 #define WBSD_EINT_TIMEOUT       0x08
  51 #define WBSD_EINT_PROGEND       0x04
  52 #define WBSD_EINT_CRC           0x02
  53 #define WBSD_EINT_TC            0x01
  54
  55 #define WBSD_INT_PENDING        0x80
  56 #define WBSD_INT_CARD           0x40
  57 #define WBSD_INT_FIFO_THRE      0x20
  58 #define WBSD_INT_CRC            0x10
  59 #define WBSD_INT_TIMEOUT        0x08
  60 #define WBSD_INT_PROGEND        0x04
  61 #define WBSD_INT_BUSYEND        0x02
  62 #define WBSD_INT_TC             0x01
  63
  64 #define WBSD_FIFO_EMPTY         0x80
  65 #define WBSD_FIFO_FULL          0x40
  66 #define WBSD_FIFO_EMTHRE        0x20
  67 #define WBSD_FIFO_FUTHRE        0x10
  68 #define WBSD_FIFO_SZMASK        0x0F
  69
  70 #define WBSD_MSLED              0x20
  71 #define WBSD_POWER_N            0x10
  72 #define WBSD_WRPT               0x04
  73 #define WBSD_CARDPRESENT        0x01
  74
  75 #define WBSD_IDX_CLK            0x01
  76 #define WBSD_IDX_PBSMSB         0x02
  77 #define WBSD_IDX_TAAC           0x03
  78 #define WBSD_IDX_NSAC           0x04
  79 #define WBSD_IDX_PBSLSB         0x05
  80 #define WBSD_IDX_SETUP          0x06
  81 #define WBSD_IDX_DMA            0x07
  82 #define WBSD_IDX_FIFOEN         0x08
  83 #define WBSD_IDX_STATUS         0x10
  84 #define WBSD_IDX_RSPLEN         0x1E
  85 #define WBSD_IDX_RESP0          0x1F
  86 #define WBSD_IDX_RESP1          0x20
  87 #define WBSD_IDX_RESP2          0x21
  88 #define WBSD_IDX_RESP3          0x22
  89 #define WBSD_IDX_RESP4          0x23
  90 #define WBSD_IDX_RESP5          0x24
  91 #define WBSD_IDX_RESP6          0x25
  92 #define WBSD_IDX_RESP7          0x26
  93 #define WBSD_IDX_RESP8          0x27
  94 #define WBSD_IDX_RESP9          0x28
  95 #define WBSD_IDX_RESP10         0x29
  96 #define WBSD_IDX_RESP11         0x2A
  97 #define WBSD_IDX_RESP12         0x2B
  98 #define WBSD_IDX_RESP13         0x2C
  99 #define WBSD_IDX_RESP14         0x2D
 100 #define WBSD_IDX_RESP15         0x2E
 101 #define WBSD_IDX_RESP16         0x2F
 102 #define WBSD_IDX_CRCSTATUS      0x30
 103 #define WBSD_IDX_ISR            0x3F
 104
 105 #define WBSD_CLK_375K           0x00
 106 #define WBSD_CLK_12M            0x01
 107 #define WBSD_CLK_16M            0x02
 108 #define WBSD_CLK_24M            0x03
 109
 110 #define WBSD_DAT3_H             0x08
 111 #define WBSD_FIFO_RESET         0x04
 112 #define WBSD_SOFT_RESET         0x02
 113 #define WBSD_INC_INDEX          0x01
 114
 115 #define WBSD_DMA_SINGLE         0x02
 116 #define WBSD_DMA_ENABLE         0x01
 117
 118 #define WBSD_FIFOEN_EMPTY       0x20
 119 #define WBSD_FIFOEN_FULL        0x10
 120 #define WBSD_FIFO_THREMASK      0x0F
 121
 122 #define WBSD_BLOCK_READ         0x80
 123 #define WBSD_BLOCK_WRITE        0x40
 124 #define WBSD_BUSY               0x20
 125 #define WBSD_CARDTRAFFIC        0x04
 126 #define WBSD_SENDCMD            0x02
 127 #define WBSD_RECVRES            0x01
 128
 129 #define WBSD_RSP_SHORT          0x00
 130 #define WBSD_RSP_LONG           0x01
 131
 132 #define WBSD_CRC_MASK           0x1F
 133 #define WBSD_CRC_OK             0x05 /* S010E (00101) */
 134 #define WBSD_CRC_FAIL           0x0B /* S101E (01011) */
 135
 136
 137 struct wbsd_host
 138 {
 139         struct mmc_host*        mmc;            /* MMC structure */
 140
 141         spinlock_t              lock;           /* Mutex */
 142
 143         struct mmc_request*     mrq;            /* Current request */
 144
 145         u8                      isr;            /* Accumulated ISR */
 146
 147         struct scatterlist*     cur_sg;         /* Current SG entry */
 148         unsigned int            num_sg;         /* Number of entries left */
 149         void*                   mapped_sg;      /* vaddr of mapped sg */
 150
 151         unsigned int            offset;         /* Offset into current entry */
 152         unsigned int            remain;         /* Data left in curren entry */
 153
 154         int                     size;           /* Total size of transfer */
 155
 156         char*                   dma_buffer;     /* ISA DMA buffer */
 157         dma_addr_t              dma_addr;       /* Physical address for same */
 158
 159         int                     firsterr;       /* See fifo functions */
 160
 161         u8                      clk;            /* Current clock speed */
 162
 163         int                     config;         /* Config port */
 164         u8                      unlock_code;    /* Code to unlock config */
 165
 166         int                     chip_id;        /* ID of controller */
 167
 168         int                     base;           /* I/O port base */
 169         int                     irq;            /* Interrupt */
 170         int                     dma;            /* DMA channel */
 171
 172         struct tasklet_struct   card_tasklet;   /* Tasklet structures */
 173         struct tasklet_struct   fifo_tasklet;
 174         struct tasklet_struct   crc_tasklet;
 175         struct tasklet_struct   timeout_tasklet;
 176         struct tasklet_struct   finish_tasklet;
 177         struct tasklet_struct   block_tasklet;
 178 };