drivers/mtd/nand/s3c2410.c

   1 /* linux/drivers/mtd/nand/s3c2410.c
   2  *
   3  * Copyright (c) 2004,2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Samsung S3C2410/S3C240 NAND driver
   8  *
   9  * Changelog:
  10  *      21-Sep-2004  BJD  Initial version
  11  *      23-Sep-2004  BJD  Mulitple device support
  12  *      28-Sep-2004  BJD  Fixed ECC placement for Hardware mode
  13  *      12-Oct-2004  BJD  Fixed errors in use of platform data
  14  *      18-Feb-2005  BJD  Fix sparse errors
  15  *      14-Mar-2005  BJD  Applied tglx's code reduction patch
  16  *      02-May-2005  BJD  Fixed s3c2440 support
  17  *      02-May-2005  BJD  Reduced hwcontrol decode
  18  *      20-Jun-2005  BJD  Updated s3c2440 support, fixed timing bug
  19  *      08-Jul-2005  BJD  Fix OOPS when no platform data supplied
  20  *      20-Oct-2005  BJD  Fix timing calculation bug
  21  *
  22  * $Id: s3c2410.c,v 1.20 2005/11/07 11:14:31 gleixner Exp $
  23  *
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License as published by
  26  * the Free Software Foundation; either version 2 of the License, or
  27  * (at your option) any later version.
  28  *
  29  * This program is distributed in the hope that it will be useful,
  30  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  32  * GNU General Public License for more details.
  33  *
  34  * You should have received a copy of the GNU General Public License
  35  * along with this program; if not, write to the Free Software
  36  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  37 */
  38
  39 #include <config/mtd/nand/s3c2410/hwecc.h>
  40 #include <config/mtd/nand/s3c2410/debug.h>
  41
  42 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  43 #define DEBUG
  44 #endif
  45
  46 #include <linux/module.h>
  47 #include <linux/types.h>
  48 #include <linux/init.h>
  49 #include <linux/kernel.h>
  50 #include <linux/string.h>
  51 #include <linux/ioport.h>
  52 #include <linux/platform_device.h>
  53 #include <linux/delay.h>
  54 #include <linux/err.h>
  55 #include <linux/slab.h>
  56 #include <linux/clk.h>
  57
  58 #include <linux/mtd/mtd.h>
  59 #include <linux/mtd/nand.h>
  60 #include <linux/mtd/nand_ecc.h>
  61 #include <linux/mtd/partitions.h>
  62
  63 #include <asm/io.h>
  64
  65 #include <asm/arch/regs-nand.h>
  66 #include <asm/arch/nand.h>
  67
  68 #define PFX "s3c2410-nand: "
  69
  70 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
  71 static int hardware_ecc = 1;
  72 #else
  73 static int hardware_ecc = 0;
  74 #endif
  75
  76 /* new oob placement block for use with hardware ecc generation
  77  */
  78
  79 static struct nand_oobinfo nand_hw_eccoob = {
  80         .useecc         = MTD_NANDECC_AUTOPLACE,
  81         .eccbytes       = 3,
  82         .eccpos         = {0, 1, 2 },
  83         .oobfree        = { {8, 8} }
  84 };
  85
  86 /* controller and mtd information */
  87
  88 struct s3c2410_nand_info;
  89
  90 struct s3c2410_nand_mtd {
  91         struct mtd_info                 mtd;
  92         struct nand_chip                chip;
  93         struct s3c2410_nand_set         *set;
  94         struct s3c2410_nand_info        *info;
  95         int                             scan_res;
  96 };
  97
  98 /* overview of the s3c2410 nand state */
  99
 100 struct s3c2410_nand_info {
 101         /* mtd info */
 102         struct nand_hw_control          controller;
 103         struct s3c2410_nand_mtd         *mtds;
 104         struct s3c2410_platform_nand    *platform;
 105
 106         /* device info */
 107         struct device                   *device;
 108         struct resource                 *area;
 109         struct clk                      *clk;
 110         void __iomem                    *regs;
 111         int                             mtd_count;
 112
 113         unsigned char                   is_s3c2440;
 114 };
 115
 116 /* conversion functions */
 117
 118 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 119 {
 120         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
 121 }
 122
 123 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 124 {
 125         return s3c2410_nand_mtd_toours(mtd)->info;
 126 }
 127
 128 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 129 {
 130         return platform_get_drvdata(dev);
 131 }
 132
 133 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 134 {
 135         return dev->dev.platform_data;
 136 }
 137
 138 /* timing calculations */
 139
 140 #define NS_IN_KHZ 1000000
 141
 142 static int s3c2410_nand_calc_rate(int wanted, unsigned long clk, int max)
 143 {
 144         int result;
 145
 146         result = (wanted * clk) / NS_IN_KHZ;
 147         result++;
 148
 149         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 150
 151         if (result > max) {
 152                 printk("%d ns is too big for current clock rate %ld\n",
 153                        wanted, clk);
 154                 return -1;
 155         }
 156
 157         if (result < 1)
 158                 result = 1;
 159
 160         return result;
 161 }
 162
 163 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 164
 165 /* controller setup */
 166
 167 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
 168                                struct platform_device *pdev)
 169 {
 170         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 171         unsigned long clkrate = clk_get_rate(info->clk);
 172         int tacls, twrph0, twrph1;
 173         unsigned long cfg;
 174
 175         /* calculate the timing information for the controller */
 176
 177         clkrate /= 1000;        /* turn clock into kHz for ease of use */
 178
 179         if (plat != NULL) {
 180                 tacls  = s3c2410_nand_calc_rate(plat->tacls, clkrate, 4);
 181                 twrph0 = s3c2410_nand_calc_rate(plat->twrph0, clkrate, 8);
 182                 twrph1 = s3c2410_nand_calc_rate(plat->twrph1, clkrate, 8);
 183         } else {
 184                 /* default timings */
 185                 tacls = 4;
 186                 twrph0 = 8;
 187                 twrph1 = 8;
 188         }
 189
 190         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 191                 printk(KERN_ERR PFX "cannot get timings suitable for board\n");
 192                 return -EINVAL;
 193         }
 194
 195         printk(KERN_INFO PFX "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 196                tacls, to_ns(tacls, clkrate),
 197                twrph0, to_ns(twrph0, clkrate),
 198                twrph1, to_ns(twrph1, clkrate));
 199
 200         if (!info->is_s3c2440) {
 201                 cfg  = S3C2410_NFCONF_EN;
 202                 cfg |= S3C2410_NFCONF_TACLS(tacls-1);
 203                 cfg |= S3C2410_NFCONF_TWRPH0(twrph0-1);
 204                 cfg |= S3C2410_NFCONF_TWRPH1(twrph1-1);
 205         } else {
 206                 cfg   = S3C2440_NFCONF_TACLS(tacls-1);
 207                 cfg  |= S3C2440_NFCONF_TWRPH0(twrph0-1);
 208                 cfg  |= S3C2440_NFCONF_TWRPH1(twrph1-1);
 209         }
 210
 211         pr_debug(PFX "NF_CONF is 0x%lx\n", cfg);
 212
 213         writel(cfg, info->regs + S3C2410_NFCONF);
 214         return 0;
 215 }
 216
 217 /* select chip */
 218
 219 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
 220 {
 221         struct s3c2410_nand_info *info;
 222         struct s3c2410_nand_mtd *nmtd;
 223         struct nand_chip *this = mtd->priv;
 224         void __iomem *reg;
 225         unsigned long cur;
 226         unsigned long bit;
 227
 228         nmtd = this->priv;
 229         info = nmtd->info;
 230
 231         bit = (info->is_s3c2440) ? S3C2440_NFCONT_nFCE : S3C2410_NFCONF_nFCE;
 232         reg = info->regs+((info->is_s3c2440) ? S3C2440_NFCONT:S3C2410_NFCONF);
 233
 234         cur = readl(reg);
 235
 236         if (chip == -1) {
 237                 cur |= bit;
 238         } else {
 239                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 240                         printk(KERN_ERR PFX "chip %d out of range\n", chip);
 241                         return;
 242                 }
 243
 244                 if (info->platform != NULL) {
 245                         if (info->platform->select_chip != NULL)
 246                                 (info->platform->select_chip)(nmtd->set, chip);
 247                 }
 248
 249                 cur &= ~bit;
 250         }
 251
 252         writel(cur, reg);
 253 }
 254
 255 /* command and control functions
 256  *
 257  * Note, these all use tglx's method of changing the IO_ADDR_W field
 258  * to make the code simpler, and use the nand layer's code to issue the
 259  * command and address sequences via the proper IO ports.
 260  *
 261 */
 262
 263 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 264 {
 265         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 266         struct nand_chip *chip = mtd->priv;
 267
 268         switch (cmd) {
 269         case NAND_CTL_SETNCE:
 270         case NAND_CTL_CLRNCE:
 271                 printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__);
 272                 break;
 273
 274         case NAND_CTL_SETCLE:
 275                 chip->IO_ADDR_W = info->regs + S3C2410_NFCMD;
 276                 break;
 277
 278         case NAND_CTL_SETALE:
 279                 chip->IO_ADDR_W = info->regs + S3C2410_NFADDR;
 280                 break;
 281
 282                 /* NAND_CTL_CLRCLE: */
 283                 /* NAND_CTL_CLRALE: */
 284         default:
 285                 chip->IO_ADDR_W = info->regs + S3C2410_NFDATA;
 286                 break;
 287         }
 288 }
 289
 290 /* command and control functions */
 291
 292 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd)
 293 {
 294         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 295         struct nand_chip *chip = mtd->priv;
 296
 297         switch (cmd) {
 298         case NAND_CTL_SETNCE:
 299         case NAND_CTL_CLRNCE:
 300                 printk(KERN_ERR "%s: called for NCE\n", __FUNCTION__);
 301                 break;
 302
 303         case NAND_CTL_SETCLE:
 304                 chip->IO_ADDR_W = info->regs + S3C2440_NFCMD;
 305                 break;
 306
 307         case NAND_CTL_SETALE:
 308                 chip->IO_ADDR_W = info->regs + S3C2440_NFADDR;
 309                 break;
 310
 311                 /* NAND_CTL_CLRCLE: */
 312                 /* NAND_CTL_CLRALE: */
 313         default:
 314                 chip->IO_ADDR_W = info->regs + S3C2440_NFDATA;
 315                 break;
 316         }
 317 }
 318
 319 /* s3c2410_nand_devready()
 320  *
 321  * returns 0 if the nand is busy, 1 if it is ready
 322 */
 323
 324 static int s3c2410_nand_devready(struct mtd_info *mtd)
 325 {
 326         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 327
 328         if (info->is_s3c2440)
 329                 return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 330         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 331 }
 332
 333
 334 /* ECC handling functions */
 335
 336 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 337                                      u_char *read_ecc, u_char *calc_ecc)
 338 {
 339         pr_debug("s3c2410_nand_correct_data(%p,%p,%p,%p)\n",
 340                  mtd, dat, read_ecc, calc_ecc);
 341
 342         pr_debug("eccs: read %02x,%02x,%02x vs calc %02x,%02x,%02x\n",
 343                  read_ecc[0], read_ecc[1], read_ecc[2],
 344                  calc_ecc[0], calc_ecc[1], calc_ecc[2]);
 345
 346         if (read_ecc[0] == calc_ecc[0] &&
 347             read_ecc[1] == calc_ecc[1] &&
 348             read_ecc[2] == calc_ecc[2])
 349                 return 0;
 350
 351         /* we curently have no method for correcting the error */
 352
 353         return -1;
 354 }
 355
 356 /* ECC functions
 357  *
 358  * These allow the s3c2410 and s3c2440 to use the controller's ECC
 359  * generator block to ECC the data as it passes through]
 360 */
 361
 362 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 363 {
 364         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 365         unsigned long ctrl;
 366
 367         ctrl = readl(info->regs + S3C2410_NFCONF);
 368         ctrl |= S3C2410_NFCONF_INITECC;
 369         writel(ctrl, info->regs + S3C2410_NFCONF);
 370 }
 371
 372 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 373 {
 374         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 375         unsigned long ctrl;
 376
 377         ctrl = readl(info->regs + S3C2440_NFCONT);
 378         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 379 }
 380
 381 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd,
 382                                       const u_char *dat, u_char *ecc_code)
 383 {
 384         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 385
 386         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 387         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 388         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 389
 390         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n",
 391                  ecc_code[0], ecc_code[1], ecc_code[2]);
 392
 393         return 0;
 394 }
 395
 396
 397 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd,
 398                                       const u_char *dat, u_char *ecc_code)
 399 {
 400         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 401         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 402
 403         ecc_code[0] = ecc;
 404         ecc_code[1] = ecc >> 8;
 405         ecc_code[2] = ecc >> 16;
 406
 407         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n",
 408                  ecc_code[0], ecc_code[1], ecc_code[2]);
 409
 410         return 0;
 411 }
 412
 413
 414 /* over-ride the standard functions for a little more speed. We can
 415  * use read/write block to move the data buffers to/from the controller
 416 */
 417
 418 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 419 {
 420         struct nand_chip *this = mtd->priv;
 421         readsb(this->IO_ADDR_R, buf, len);
 422 }
 423
 424 static void s3c2410_nand_write_buf(struct mtd_info *mtd,
 425                                    const u_char *buf, int len)
 426 {
 427         struct nand_chip *this = mtd->priv;
 428         writesb(this->IO_ADDR_W, buf, len);
 429 }
 430
 431 /* device management functions */
 432
 433 static int s3c2410_nand_remove(struct platform_device *pdev)
 434 {
 435         struct s3c2410_nand_info *info = to_nand_info(pdev);
 436
 437         platform_set_drvdata(pdev, NULL);
 438
 439         if (info == NULL)
 440                 return 0;
 441
 442         /* first thing we need to do is release all our mtds
 443          * and their partitions, then go through freeing the
 444          * resources used
 445          */
 446
 447         if (info->mtds != NULL) {
 448                 struct s3c2410_nand_mtd *ptr = info->mtds;
 449                 int mtdno;
 450
 451                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 452                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 453                         nand_release(&ptr->mtd);
 454                 }
 455
 456                 kfree(info->mtds);
 457         }
 458
 459         /* free the common resources */
 460
 461         if (info->clk != NULL && !IS_ERR(info->clk)) {
 462                 clk_disable(info->clk);
 463                 clk_put(info->clk);
 464         }
 465
 466         if (info->regs != NULL) {
 467                 iounmap(info->regs);
 468                 info->regs = NULL;
 469         }
 470
 471         if (info->area != NULL) {
 472                 release_resource(info->area);
 473                 kfree(info->area);
 474                 info->area = NULL;
 475         }
 476
 477         kfree(info);
 478
 479         return 0;
 480 }
 481
 482 #ifdef CONFIG_MTD_PARTITIONS
 483 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 484                                       struct s3c2410_nand_mtd *mtd,
 485                                       struct s3c2410_nand_set *set)
 486 {
 487         if (set == NULL)
 488                 return add_mtd_device(&mtd->mtd);
 489
 490         if (set->nr_partitions > 0 && set->partitions != NULL) {
 491                 return add_mtd_partitions(&mtd->mtd,
 492                                           set->partitions,
 493                                           set->nr_partitions);
 494         }
 495
 496         return add_mtd_device(&mtd->mtd);
 497 }
 498 #else
 499 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 500                                       struct s3c2410_nand_mtd *mtd,
 501                                       struct s3c2410_nand_set *set)
 502 {
 503         return add_mtd_device(&mtd->mtd);
 504 }
 505 #endif
 506
 507 /* s3c2410_nand_init_chip
 508  *
 509  * init a single instance of an chip
 510 */
 511
 512 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 513                                    struct s3c2410_nand_mtd *nmtd,
 514                                    struct s3c2410_nand_set *set)
 515 {
 516         struct nand_chip *chip = &nmtd->chip;
 517
 518         chip->IO_ADDR_R    = info->regs + S3C2410_NFDATA;
 519         chip->IO_ADDR_W    = info->regs + S3C2410_NFDATA;
 520         chip->hwcontrol    = s3c2410_nand_hwcontrol;
 521         chip->dev_ready    = s3c2410_nand_devready;
 522         chip->write_buf    = s3c2410_nand_write_buf;
 523         chip->read_buf     = s3c2410_nand_read_buf;
 524         chip->select_chip  = s3c2410_nand_select_chip;
 525         chip->chip_delay   = 50;
 526         chip->priv         = nmtd;
 527         chip->options      = 0;
 528         chip->controller   = &info->controller;
 529
 530         if (info->is_s3c2440) {
 531                 chip->IO_ADDR_R  = info->regs + S3C2440_NFDATA;
 532                 chip->IO_ADDR_W  = info->regs + S3C2440_NFDATA;
 533                 chip->hwcontrol  = s3c2440_nand_hwcontrol;
 534         }
 535
 536         nmtd->info         = info;
 537         nmtd->mtd.priv     = chip;
 538         nmtd->set          = set;
 539
 540         if (hardware_ecc) {
 541                 chip->correct_data  = s3c2410_nand_correct_data;
 542                 chip->enable_hwecc  = s3c2410_nand_enable_hwecc;
 543                 chip->calculate_ecc = s3c2410_nand_calculate_ecc;
 544                 chip->eccmode       = NAND_ECC_HW3_512;
 545                 chip->autooob       = &nand_hw_eccoob;
 546
 547                 if (info->is_s3c2440) {
 548                         chip->enable_hwecc  = s3c2440_nand_enable_hwecc;
 549                         chip->calculate_ecc = s3c2440_nand_calculate_ecc;
 550                 }
 551         } else {
 552                 chip->eccmode       = NAND_ECC_SOFT;
 553         }
 554 }
 555
 556 /* s3c2410_nand_probe
 557  *
 558  * called by device layer when it finds a device matching
 559  * one our driver can handled. This code checks to see if
 560  * it can allocate all necessary resources then calls the
 561  * nand layer to look for devices
 562 */
 563
 564 static int s3c24xx_nand_probe(struct platform_device *pdev, int is_s3c2440)
 565 {
 566         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 567         struct s3c2410_nand_info *info;
 568         struct s3c2410_nand_mtd *nmtd;
 569         struct s3c2410_nand_set *sets;
 570         struct resource *res;
 571         int err = 0;
 572         int size;
 573         int nr_sets;
 574         int setno;
 575
 576         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
 577
 578         info = kmalloc(sizeof(*info), GFP_KERNEL);
 579         if (info == NULL) {
 580                 dev_err(&pdev->dev, "no memory for flash info\n");
 581                 err = -ENOMEM;
 582                 goto exit_error;
 583         }
 584
 585         memzero(info, sizeof(*info));
 586         platform_set_drvdata(pdev, info);
 587
 588         spin_lock_init(&info->controller.lock);
 589         init_waitqueue_head(&info->controller.wq);
 590
 591         /* get the clock source and enable it */
 592
 593         info->clk = clk_get(&pdev->dev, "nand");
 594         if (IS_ERR(info->clk)) {
 595                 dev_err(&pdev->dev, "failed to get clock");
 596                 err = -ENOENT;
 597                 goto exit_error;
 598         }
 599
 600         clk_enable(info->clk);
 601
 602         /* allocate and map the resource */
 603
 604         /* currently we assume we have the one resource */
 605         res  = pdev->resource;
 606         size = res->end - res->start + 1;
 607
 608         info->area = request_mem_region(res->start, size, pdev->name);
 609
 610         if (info->area == NULL) {
 611                 dev_err(&pdev->dev, "cannot reserve register region\n");
 612                 err = -ENOENT;
 613                 goto exit_error;
 614         }
 615
 616         info->device     = &pdev->dev;
 617         info->platform   = plat;
 618         info->regs       = ioremap(res->start, size);
 619         info->is_s3c2440 = is_s3c2440;
 620
 621         if (info->regs == NULL) {
 622                 dev_err(&pdev->dev, "cannot reserve register region\n");
 623                 err = -EIO;
 624                 goto exit_error;
 625         }
 626
 627         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
 628
 629         /* initialise the hardware */
 630
 631         err = s3c2410_nand_inithw(info, pdev);
 632         if (err != 0)
 633                 goto exit_error;
 634
 635         sets = (plat != NULL) ? plat->sets : NULL;
 636         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
 637
 638         info->mtd_count = nr_sets;
 639
 640         /* allocate our information */
 641
 642         size = nr_sets * sizeof(*info->mtds);
 643         info->mtds = kmalloc(size, GFP_KERNEL);
 644         if (info->mtds == NULL) {
 645                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
 646                 err = -ENOMEM;
 647                 goto exit_error;
 648         }
 649
 650         memzero(info->mtds, size);
 651
 652         /* initialise all possible chips */
 653
 654         nmtd = info->mtds;
 655
 656         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
 657                 pr_debug("initialising set %d (%p, info %p)\n",
 658                          setno, nmtd, info);
 659
 660                 s3c2410_nand_init_chip(info, nmtd, sets);
 661
 662                 nmtd->scan_res = nand_scan(&nmtd->mtd,
 663                                            (sets) ? sets->nr_chips : 1);
 664
 665                 if (nmtd->scan_res == 0) {
 666                         s3c2410_nand_add_partition(info, nmtd, sets);
 667                 }
 668
 669                 if (sets != NULL)
 670                         sets++;
 671         }
 672
 673         pr_debug("initialised ok\n");
 674         return 0;
 675
 676  exit_error:
 677         s3c2410_nand_remove(pdev);
 678
 679         if (err == 0)
 680                 err = -EINVAL;
 681         return err;
 682 }
 683
 684 /* driver device registration */
 685
 686 static int s3c2410_nand_probe(struct platform_device *dev)
 687 {
 688         return s3c24xx_nand_probe(dev, 0);
 689 }
 690
 691 static int s3c2440_nand_probe(struct platform_device *dev)
 692 {
 693         return s3c24xx_nand_probe(dev, 1);
 694 }
 695
 696 static struct platform_driver s3c2410_nand_driver = {
 697         .probe          = s3c2410_nand_probe,
 698         .remove         = s3c2410_nand_remove,
 699         .driver         = {
 700                 .name   = "s3c2410-nand",
 701                 .owner  = THIS_MODULE,
 702         },
 703 };
 704
 705 static struct platform_driver s3c2440_nand_driver = {
 706         .probe          = s3c2440_nand_probe,
 707         .remove         = s3c2410_nand_remove,
 708         .driver         = {
 709                 .name   = "s3c2440-nand",
 710                 .owner  = THIS_MODULE,
 711         },
 712 };
 713
 714 static int __init s3c2410_nand_init(void)
 715 {
 716         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
 717
 718         platform_driver_register(&s3c2440_nand_driver);
 719         return platform_driver_register(&s3c2410_nand_driver);
 720 }
 721
 722 static void __exit s3c2410_nand_exit(void)
 723 {
 724         platform_driver_unregister(&s3c2440_nand_driver);
 725         platform_driver_unregister(&s3c2410_nand_driver);
 726 }
 727
 728 module_init(s3c2410_nand_init);
 729 module_exit(s3c2410_nand_exit);
 730
 731 MODULE_LICENSE("GPL");
 732 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
 733 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");