3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
23 This driver is for boards based on the RTL8129 and RTL8139
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
46 Tigran Aivazian - bug fixes, skbuff free cleanup
48 Martin Mares - suggestions for PCI cleanup
50 David S. Miller - PCI DMA and softnet updates
52 Ernst Gill - fixes ported from BSD driver
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
57 Gerard Sharp - bug fix, testing and feedback
59 David Ford - Rx ring wrap fix
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
67 Santiago Garcia Mantinan - testing and feedback
69 Jens David - 2.2.x kernel backports
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
74 Jean-Jacques Michel - bug fix
76 Tobias Ringström - Rx interrupt status checking suggestion
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
83 Robert Kuebel - Save kernel thread from dying on any signal.
85 Submitting bug reports:
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/kernel.h>
99 #include <linux/compiler.h>
100 #include <linux/pci.h>
101 #include <linux/init.h>
102 #include <linux/ioport.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <linux/suspend.h>
113 #include <asm/uaccess.h>
116 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
117 #define PFX DRV_NAME ": "
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
125 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
126 #ifdef CONFIG_8139TOO_PIO
130 /* define to 1 to enable copious debugging info */
133 /* define to 1 to disable lightweight runtime debugging checks */
134 #undef RTL8139_NDEBUG
138 /* note: prints function name for you */
139 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
141 # define DPRINTK(fmt, args...)
144 #ifdef RTL8139_NDEBUG
145 # define assert(expr) do {} while (0)
147 # define assert(expr) \
148 if(unlikely(!(expr))) { \
149 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
150 #expr,__FILE__,__FUNCTION__,__LINE__); \
155 /* A few user-configurable values. */
158 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
159 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
161 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
162 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
163 static int multicast_filter_limit = 32;
165 /* bitmapped message enable number */
166 static int debug = -1;
170 * Warning: 64K ring has hardware issues and may lock up.
172 #if defined(CONFIG_SH_DREAMCAST)
173 #define RX_BUF_IDX 1 /* 16K ring */
175 #define RX_BUF_IDX 2 /* 32K ring */
177 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
178 #define RX_BUF_PAD 16
179 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
181 #if RX_BUF_LEN == 65536
182 #define RX_BUF_TOT_LEN RX_BUF_LEN
184 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
187 /* Number of Tx descriptor registers. */
188 #define NUM_TX_DESC 4
190 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
191 #define MAX_ETH_FRAME_SIZE 1536
193 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
194 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
195 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
197 /* PCI Tuning Parameters
198 Threshold is bytes transferred to chip before transmission starts. */
199 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
201 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
202 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
203 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
205 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
207 /* Operational parameters that usually are not changed. */
208 /* Time in jiffies before concluding the transmitter is hung. */
209 #define TX_TIMEOUT (6*HZ)
213 HAS_MII_XCVR = 0x010000,
214 HAS_CHIP_XCVR = 0x020000,
215 HAS_LNK_CHNG = 0x040000,
218 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
219 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
220 #define RTL_MIN_IO_SIZE 0x80
221 #define RTL8139B_IO_SIZE 256
223 #define RTL8129_CAPS HAS_MII_XCVR
224 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
232 /* indexed by board_t, above */
236 } board_info[] __devinitdata = {
237 { "RealTek RTL8139", RTL8139_CAPS },
238 { "RealTek RTL8129", RTL8129_CAPS },
242 static struct pci_device_id rtl8139_pci_tbl[] = {
243 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
263 #ifdef CONFIG_SH_SECUREEDGE5410
264 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
265 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
267 #ifdef CONFIG_8139TOO_8129
268 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
271 /* some crazy cards report invalid vendor ids like
272 * 0x0001 here. The other ids are valid and constant,
273 * so we simply don't match on the main vendor id.
275 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
277 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
281 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
284 const char str[ETH_GSTRING_LEN];
285 } ethtool_stats_keys[] = {
289 { "rx_lost_in_ring" },
292 /* The rest of these values should never change. */
294 /* Symbolic offsets to registers. */
295 enum RTL8139_registers {
296 MAC0 = 0, /* Ethernet hardware address. */
297 MAR0 = 8, /* Multicast filter. */
298 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
299 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
308 Timer = 0x48, /* A general-purpose counter. */
309 RxMissed = 0x4C, /* 24 bits valid, write clears. */
316 Config4 = 0x5A, /* absent on RTL-8139A */
320 BasicModeCtrl = 0x62,
321 BasicModeStatus = 0x64,
324 NWayExpansion = 0x6A,
325 /* Undocumented registers, but required for proper operation. */
326 FIFOTMS = 0x70, /* FIFO Control and test. */
327 CSCR = 0x74, /* Chip Status and Configuration Register. */
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
334 MultiIntrClear = 0xF000,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
370 RxMulticast = 0x8000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
381 /* Bits in RxConfig. */
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
388 AcceptAllPhys = 0x01,
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 TxIFG1 = (1 << 25), /* Interframe Gap Time */
394 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
395 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
396 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
397 TxClearAbt = (1 << 0), /* Clear abort (WO) */
398 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
399 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
401 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
404 /* Bits in Config1 */
406 Cfg1_PM_Enable = 0x01,
407 Cfg1_VPD_Enable = 0x02,
410 LWAKE = 0x10, /* not on 8139, 8139A */
411 Cfg1_Driver_Load = 0x20,
414 SLEEP = (1 << 1), /* only on 8139, 8139A */
415 PWRDN = (1 << 0), /* only on 8139, 8139A */
418 /* Bits in Config3 */
420 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
421 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
422 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
423 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
424 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
425 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
426 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
427 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
430 /* Bits in Config4 */
432 LWPTN = (1 << 2), /* not on 8139, 8139A */
435 /* Bits in Config5 */
437 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
438 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
439 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
440 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
441 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
442 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
443 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
447 /* rx fifo threshold */
449 RxCfgFIFONone = (7 << RxCfgFIFOShift),
453 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
455 /* rx ring buffer length */
457 RxCfgRcv16K = (1 << 11),
458 RxCfgRcv32K = (1 << 12),
459 RxCfgRcv64K = (1 << 11) | (1 << 12),
461 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
465 /* Twister tuning parameters from RealTek.
466 Completely undocumented, but required to tune bad links on some boards. */
468 CSCR_LinkOKBit = 0x0400,
469 CSCR_LinkChangeBit = 0x0800,
470 CSCR_LinkStatusBits = 0x0f000,
471 CSCR_LinkDownOffCmd = 0x003c0,
472 CSCR_LinkDownCmd = 0x0f3c0,
477 Cfg9346_Unlock = 0xC0,
494 HasHltClk = (1 << 0),
498 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
499 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
500 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
502 /* directly indexed by chip_t, above */
503 const static struct {
505 u32 version; /* from RTL8139C/RTL8139D docs */
507 } rtl_chip_info[] = {
509 HW_REVID(1, 0, 0, 0, 0, 0, 0),
514 HW_REVID(1, 1, 0, 0, 0, 0, 0),
519 HW_REVID(1, 1, 1, 0, 0, 0, 0),
520 HasHltClk, /* XXX undocumented? */
524 HW_REVID(1, 1, 1, 0, 0, 1, 0),
525 HasHltClk, /* XXX undocumented? */
529 HW_REVID(1, 1, 1, 1, 0, 0, 0),
534 HW_REVID(1, 1, 1, 1, 1, 0, 0),
539 HW_REVID(1, 1, 1, 0, 1, 0, 0),
544 HW_REVID(1, 1, 1, 1, 0, 1, 0),
549 HW_REVID(1, 1, 1, 0, 1, 0, 1),
554 HW_REVID(1, 1, 1, 0, 1, 1, 1),
559 struct rtl_extra_stats {
560 unsigned long early_rx;
561 unsigned long tx_buf_mapped;
562 unsigned long tx_timeouts;
563 unsigned long rx_lost_in_ring;
566 struct rtl8139_private {
569 struct pci_dev *pci_dev;
572 struct net_device_stats stats;
573 unsigned char *rx_ring;
574 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
575 unsigned int tx_flag;
576 unsigned long cur_tx;
577 unsigned long dirty_tx;
578 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
579 unsigned char *tx_bufs; /* Tx bounce buffer region. */
580 dma_addr_t rx_ring_dma;
581 dma_addr_t tx_bufs_dma;
582 signed char phys[4]; /* MII device addresses. */
583 char twistie, twist_row, twist_col; /* Twister tune state. */
584 unsigned int default_port:4; /* Last dev->if_port value. */
589 wait_queue_head_t thr_wait;
590 struct completion thr_exited;
592 struct rtl_extra_stats xstats;
594 struct mii_if_info mii;
595 unsigned int regs_len;
596 unsigned long fifo_copy_timeout;
599 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
600 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
601 MODULE_LICENSE("GPL");
602 MODULE_VERSION(DRV_VERSION);
604 MODULE_PARM (multicast_filter_limit, "i");
605 MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
606 MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
607 MODULE_PARM (debug, "i");
608 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
609 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
610 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
611 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
613 static int read_eeprom (void *ioaddr, int location, int addr_len);
614 static int rtl8139_open (struct net_device *dev);
615 static int mdio_read (struct net_device *dev, int phy_id, int location);
616 static void mdio_write (struct net_device *dev, int phy_id, int location,
618 static void rtl8139_start_thread(struct net_device *dev);
619 static void rtl8139_tx_timeout (struct net_device *dev);
620 static void rtl8139_init_ring (struct net_device *dev);
621 static int rtl8139_start_xmit (struct sk_buff *skb,
622 struct net_device *dev);
623 static int rtl8139_poll(struct net_device *dev, int *budget);
624 #ifdef CONFIG_NET_POLL_CONTROLLER
625 static void rtl8139_poll_controller(struct net_device *dev);
627 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
628 struct pt_regs *regs);
629 static int rtl8139_close (struct net_device *dev);
630 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
631 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
632 static void rtl8139_set_rx_mode (struct net_device *dev);
633 static void __set_rx_mode (struct net_device *dev);
634 static void rtl8139_hw_start (struct net_device *dev);
635 static struct ethtool_ops rtl8139_ethtool_ops;
639 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
640 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
641 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
642 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
643 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
644 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
645 #define RTL_W8_F RTL_W8
646 #define RTL_W16_F RTL_W16
647 #define RTL_W32_F RTL_W32
654 #define readb(addr) inb((unsigned long)(addr))
655 #define readw(addr) inw((unsigned long)(addr))
656 #define readl(addr) inl((unsigned long)(addr))
657 #define writeb(val,addr) outb((val),(unsigned long)(addr))
658 #define writew(val,addr) outw((val),(unsigned long)(addr))
659 #define writel(val,addr) outl((val),(unsigned long)(addr))
663 /* write MMIO register, with flush */
664 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
665 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
666 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
667 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
670 #define MMIO_FLUSH_AUDIT_COMPLETE 1
671 #if MMIO_FLUSH_AUDIT_COMPLETE
673 /* write MMIO register */
674 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
675 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
676 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
680 /* write MMIO register, then flush */
681 #define RTL_W8 RTL_W8_F
682 #define RTL_W16 RTL_W16_F
683 #define RTL_W32 RTL_W32_F
685 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
687 /* read MMIO register */
688 #define RTL_R8(reg) readb (ioaddr + (reg))
689 #define RTL_R16(reg) readw (ioaddr + (reg))
690 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
692 #endif /* USE_IO_OPS */
695 static const u16 rtl8139_intr_mask =
696 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
697 TxErr | TxOK | RxErr | RxOK;
699 static const u16 rtl8139_norx_intr_mask =
700 PCIErr | PCSTimeout | RxUnderrun |
701 TxErr | TxOK | RxErr ;
704 static const unsigned int rtl8139_rx_config =
705 RxCfgRcv8K | RxNoWrap |
706 (RX_FIFO_THRESH << RxCfgFIFOShift) |
707 (RX_DMA_BURST << RxCfgDMAShift);
708 #elif RX_BUF_IDX == 1
709 static const unsigned int rtl8139_rx_config =
710 RxCfgRcv16K | RxNoWrap |
711 (RX_FIFO_THRESH << RxCfgFIFOShift) |
712 (RX_DMA_BURST << RxCfgDMAShift);
713 #elif RX_BUF_IDX == 2
714 static const unsigned int rtl8139_rx_config =
715 RxCfgRcv32K | RxNoWrap |
716 (RX_FIFO_THRESH << RxCfgFIFOShift) |
717 (RX_DMA_BURST << RxCfgDMAShift);
718 #elif RX_BUF_IDX == 3
719 static const unsigned int rtl8139_rx_config =
721 (RX_FIFO_THRESH << RxCfgFIFOShift) |
722 (RX_DMA_BURST << RxCfgDMAShift);
724 #error "Invalid configuration for 8139_RXBUF_IDX"
727 static const unsigned int rtl8139_tx_config =
728 (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
730 static void __rtl8139_cleanup_dev (struct net_device *dev)
732 struct rtl8139_private *tp;
733 struct pci_dev *pdev;
735 assert (dev != NULL);
736 assert (dev->priv != NULL);
739 assert (tp->pci_dev != NULL);
744 iounmap (tp->mmio_addr);
745 #endif /* !USE_IO_OPS */
747 /* it's ok to call this even if we have no regions to free */
748 pci_release_regions (pdev);
752 pci_set_drvdata (pdev, NULL);
756 static void rtl8139_chip_reset (void *ioaddr)
760 /* Soft reset the chip. */
761 RTL_W8 (ChipCmd, CmdReset);
763 /* Check that the chip has finished the reset. */
764 for (i = 1000; i > 0; i--) {
766 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
773 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
774 struct net_device **dev_out)
777 struct net_device *dev;
778 struct rtl8139_private *tp;
782 unsigned long pio_start, pio_end, pio_flags, pio_len;
783 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
786 assert (pdev != NULL);
790 /* dev and dev->priv zeroed in alloc_etherdev */
791 dev = alloc_etherdev (sizeof (*tp));
793 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
796 SET_MODULE_OWNER(dev);
797 SET_NETDEV_DEV(dev, &pdev->dev);
802 /* enable device (incl. PCI PM wakeup and hotplug setup) */
803 rc = pci_enable_device (pdev);
807 pio_start = pci_resource_start (pdev, 0);
808 pio_end = pci_resource_end (pdev, 0);
809 pio_flags = pci_resource_flags (pdev, 0);
810 pio_len = pci_resource_len (pdev, 0);
812 mmio_start = pci_resource_start (pdev, 1);
813 mmio_end = pci_resource_end (pdev, 1);
814 mmio_flags = pci_resource_flags (pdev, 1);
815 mmio_len = pci_resource_len (pdev, 1);
817 /* set this immediately, we need to know before
818 * we talk to the chip directly */
819 DPRINTK("PIO region size == 0x%02X\n", pio_len);
820 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
823 /* make sure PCI base addr 0 is PIO */
824 if (!(pio_flags & IORESOURCE_IO)) {
825 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
829 /* check for weird/broken PCI region reporting */
830 if (pio_len < RTL_MIN_IO_SIZE) {
831 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
836 /* make sure PCI base addr 1 is MMIO */
837 if (!(mmio_flags & IORESOURCE_MEM)) {
838 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
842 if (mmio_len < RTL_MIN_IO_SIZE) {
843 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
849 rc = pci_request_regions (pdev, "8139too");
853 /* enable PCI bus-mastering */
854 pci_set_master (pdev);
857 ioaddr = (void *) pio_start;
858 dev->base_addr = pio_start;
859 tp->mmio_addr = ioaddr;
860 tp->regs_len = pio_len;
862 /* ioremap MMIO region */
863 ioaddr = ioremap (mmio_start, mmio_len);
864 if (ioaddr == NULL) {
865 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
869 dev->base_addr = (long) ioaddr;
870 tp->mmio_addr = ioaddr;
871 tp->regs_len = mmio_len;
872 #endif /* USE_IO_OPS */
874 /* Bring old chips out of low-power mode. */
875 RTL_W8 (HltClk, 'R');
877 /* check for missing/broken hardware */
878 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
879 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
885 /* identify chip attached to board */
886 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
887 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
888 if (version == rtl_chip_info[i].version) {
893 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
894 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
896 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
900 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
901 version, i, rtl_chip_info[i].name);
903 if (tp->chipset >= CH_8139B) {
904 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
905 DPRINTK("PCI PM wakeup\n");
906 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
909 new_tmp8 |= Cfg1_PM_Enable;
910 if (new_tmp8 != tmp8) {
911 RTL_W8 (Cfg9346, Cfg9346_Unlock);
912 RTL_W8 (Config1, tmp8);
913 RTL_W8 (Cfg9346, Cfg9346_Lock);
915 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
916 tmp8 = RTL_R8 (Config4);
918 RTL_W8 (Cfg9346, Cfg9346_Unlock);
919 RTL_W8 (Config4, tmp8 & ~LWPTN);
920 RTL_W8 (Cfg9346, Cfg9346_Lock);
924 DPRINTK("Old chip wakeup\n");
925 tmp8 = RTL_R8 (Config1);
926 tmp8 &= ~(SLEEP | PWRDN);
927 RTL_W8 (Config1, tmp8);
930 rtl8139_chip_reset (ioaddr);
936 __rtl8139_cleanup_dev (dev);
941 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
942 const struct pci_device_id *ent)
944 struct net_device *dev = NULL;
945 struct rtl8139_private *tp;
946 int i, addr_len, option;
948 static int board_idx = -1;
951 assert (pdev != NULL);
952 assert (ent != NULL);
956 /* when we're built into the kernel, the driver version message
957 * is only printed if at least one 8139 board has been found
961 static int printed_version;
962 if (!printed_version++)
963 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
967 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
969 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
970 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
971 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
972 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
973 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
976 i = rtl8139_init_board (pdev, &dev);
980 assert (dev != NULL);
983 ioaddr = tp->mmio_addr;
984 assert (ioaddr != NULL);
986 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
987 for (i = 0; i < 3; i++)
988 ((u16 *) (dev->dev_addr))[i] =
989 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
991 /* The Rtl8139-specific entries in the device structure. */
992 dev->open = rtl8139_open;
993 dev->hard_start_xmit = rtl8139_start_xmit;
994 dev->poll = rtl8139_poll;
996 dev->stop = rtl8139_close;
997 dev->get_stats = rtl8139_get_stats;
998 dev->set_multicast_list = rtl8139_set_rx_mode;
999 dev->do_ioctl = netdev_ioctl;
1000 dev->ethtool_ops = &rtl8139_ethtool_ops;
1001 dev->tx_timeout = rtl8139_tx_timeout;
1002 dev->watchdog_timeo = TX_TIMEOUT;
1003 #ifdef CONFIG_NET_POLL_CONTROLLER
1004 dev->poll_controller = rtl8139_poll_controller;
1007 /* note: the hardware is not capable of sg/csum/highdma, however
1008 * through the use of skb_copy_and_csum_dev we enable these
1011 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1013 dev->irq = pdev->irq;
1015 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
1018 /* note: tp->chipset set in rtl8139_init_board */
1019 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1020 tp->mmio_addr = ioaddr;
1022 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1023 spin_lock_init (&tp->lock);
1024 spin_lock_init (&tp->rx_lock);
1025 init_waitqueue_head (&tp->thr_wait);
1026 init_completion (&tp->thr_exited);
1028 tp->mii.mdio_read = mdio_read;
1029 tp->mii.mdio_write = mdio_write;
1030 tp->mii.phy_id_mask = 0x3f;
1031 tp->mii.reg_num_mask = 0x1f;
1033 /* dev is fully set up and ready to use now */
1034 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1035 i = register_netdev (dev);
1036 if (i) goto err_out;
1038 pci_set_drvdata (pdev, dev);
1040 printk (KERN_INFO "%s: %s at 0x%lx, "
1041 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1044 board_info[ent->driver_data].name,
1046 dev->dev_addr[0], dev->dev_addr[1],
1047 dev->dev_addr[2], dev->dev_addr[3],
1048 dev->dev_addr[4], dev->dev_addr[5],
1051 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1052 dev->name, rtl_chip_info[tp->chipset].name);
1054 /* Find the connected MII xcvrs.
1055 Doing this in open() would allow detecting external xcvrs later, but
1056 takes too much time. */
1057 #ifdef CONFIG_8139TOO_8129
1058 if (tp->drv_flags & HAS_MII_XCVR) {
1059 int phy, phy_idx = 0;
1060 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1061 int mii_status = mdio_read(dev, phy, 1);
1062 if (mii_status != 0xffff && mii_status != 0x0000) {
1063 u16 advertising = mdio_read(dev, phy, 4);
1064 tp->phys[phy_idx++] = phy;
1065 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1066 "advertising %4.4x.\n",
1067 dev->name, phy, mii_status, advertising);
1071 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1079 tp->mii.phy_id = tp->phys[0];
1081 /* The lower four bits are the media type. */
1082 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1084 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1085 tp->default_port = option & 0xFF;
1086 if (tp->default_port)
1087 tp->mii.force_media = 1;
1089 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1090 tp->mii.full_duplex = full_duplex[board_idx];
1091 if (tp->mii.full_duplex) {
1092 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1093 /* Changing the MII-advertised media because might prevent
1095 tp->mii.force_media = 1;
1097 if (tp->default_port) {
1098 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1099 (option & 0x20 ? 100 : 10),
1100 (option & 0x10 ? "full" : "half"));
1101 mdio_write(dev, tp->phys[0], 0,
1102 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1103 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1106 /* Put the chip into low-power mode. */
1107 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1108 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1113 __rtl8139_cleanup_dev (dev);
1118 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1120 struct net_device *dev = pci_get_drvdata (pdev);
1121 struct rtl8139_private *np;
1123 assert (dev != NULL);
1125 assert (np != NULL);
1127 unregister_netdev (dev);
1129 __rtl8139_cleanup_dev (dev);
1133 /* Serial EEPROM section. */
1135 /* EEPROM_Ctrl bits. */
1136 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1137 #define EE_CS 0x08 /* EEPROM chip select. */
1138 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1139 #define EE_WRITE_0 0x00
1140 #define EE_WRITE_1 0x02
1141 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1142 #define EE_ENB (0x80 | EE_CS)
1144 /* Delay between EEPROM clock transitions.
1145 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1148 #define eeprom_delay() readl(ee_addr)
1150 /* The EEPROM commands include the alway-set leading bit. */
1151 #define EE_WRITE_CMD (5)
1152 #define EE_READ_CMD (6)
1153 #define EE_ERASE_CMD (7)
1155 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1158 unsigned retval = 0;
1159 void *ee_addr = ioaddr + Cfg9346;
1160 int read_cmd = location | (EE_READ_CMD << addr_len);
1162 writeb (EE_ENB & ~EE_CS, ee_addr);
1163 writeb (EE_ENB, ee_addr);
1166 /* Shift the read command bits out. */
1167 for (i = 4 + addr_len; i >= 0; i--) {
1168 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1169 writeb (EE_ENB | dataval, ee_addr);
1171 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1174 writeb (EE_ENB, ee_addr);
1177 for (i = 16; i > 0; i--) {
1178 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1181 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1183 writeb (EE_ENB, ee_addr);
1187 /* Terminate the EEPROM access. */
1188 writeb (~EE_CS, ee_addr);
1194 /* MII serial management: mostly bogus for now. */
1195 /* Read and write the MII management registers using software-generated
1196 serial MDIO protocol.
1197 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1198 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1199 "overclocking" issues. */
1200 #define MDIO_DIR 0x80
1201 #define MDIO_DATA_OUT 0x04
1202 #define MDIO_DATA_IN 0x02
1203 #define MDIO_CLK 0x01
1204 #define MDIO_WRITE0 (MDIO_DIR)
1205 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1207 #define mdio_delay(mdio_addr) readb(mdio_addr)
1210 static char mii_2_8139_map[8] = {
1222 #ifdef CONFIG_8139TOO_8129
1223 /* Syncronize the MII management interface by shifting 32 one bits out. */
1224 static void mdio_sync (void *mdio_addr)
1228 for (i = 32; i >= 0; i--) {
1229 writeb (MDIO_WRITE1, mdio_addr);
1230 mdio_delay (mdio_addr);
1231 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1232 mdio_delay (mdio_addr);
1237 static int mdio_read (struct net_device *dev, int phy_id, int location)
1239 struct rtl8139_private *tp = dev->priv;
1241 #ifdef CONFIG_8139TOO_8129
1242 void *mdio_addr = tp->mmio_addr + Config4;
1243 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1247 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1248 return location < 8 && mii_2_8139_map[location] ?
1249 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1252 #ifdef CONFIG_8139TOO_8129
1253 mdio_sync (mdio_addr);
1254 /* Shift the read command bits out. */
1255 for (i = 15; i >= 0; i--) {
1256 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1258 writeb (MDIO_DIR | dataval, mdio_addr);
1259 mdio_delay (mdio_addr);
1260 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1261 mdio_delay (mdio_addr);
1264 /* Read the two transition, 16 data, and wire-idle bits. */
1265 for (i = 19; i > 0; i--) {
1266 writeb (0, mdio_addr);
1267 mdio_delay (mdio_addr);
1268 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1269 writeb (MDIO_CLK, mdio_addr);
1270 mdio_delay (mdio_addr);
1274 return (retval >> 1) & 0xffff;
1278 static void mdio_write (struct net_device *dev, int phy_id, int location,
1281 struct rtl8139_private *tp = dev->priv;
1282 #ifdef CONFIG_8139TOO_8129
1283 void *mdio_addr = tp->mmio_addr + Config4;
1284 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1288 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1289 void *ioaddr = tp->mmio_addr;
1290 if (location == 0) {
1291 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1292 RTL_W16 (BasicModeCtrl, value);
1293 RTL_W8 (Cfg9346, Cfg9346_Lock);
1294 } else if (location < 8 && mii_2_8139_map[location])
1295 RTL_W16 (mii_2_8139_map[location], value);
1299 #ifdef CONFIG_8139TOO_8129
1300 mdio_sync (mdio_addr);
1302 /* Shift the command bits out. */
1303 for (i = 31; i >= 0; i--) {
1305 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1306 writeb (dataval, mdio_addr);
1307 mdio_delay (mdio_addr);
1308 writeb (dataval | MDIO_CLK, mdio_addr);
1309 mdio_delay (mdio_addr);
1311 /* Clear out extra bits. */
1312 for (i = 2; i > 0; i--) {
1313 writeb (0, mdio_addr);
1314 mdio_delay (mdio_addr);
1315 writeb (MDIO_CLK, mdio_addr);
1316 mdio_delay (mdio_addr);
1322 static int rtl8139_open (struct net_device *dev)
1324 struct rtl8139_private *tp = dev->priv;
1326 void *ioaddr = tp->mmio_addr;
1328 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1332 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1334 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1336 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1337 free_irq(dev->irq, dev);
1340 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1341 tp->tx_bufs, tp->tx_bufs_dma);
1343 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1344 tp->rx_ring, tp->rx_ring_dma);
1350 tp->mii.full_duplex = tp->mii.force_media;
1351 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1353 rtl8139_init_ring (dev);
1354 rtl8139_hw_start (dev);
1355 netif_start_queue (dev);
1357 if (netif_msg_ifup(tp))
1358 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1359 " GP Pins %2.2x %s-duplex.\n",
1360 dev->name, pci_resource_start (tp->pci_dev, 1),
1361 dev->irq, RTL_R8 (MediaStatus),
1362 tp->mii.full_duplex ? "full" : "half");
1364 rtl8139_start_thread(dev);
1370 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1372 struct rtl8139_private *tp = dev->priv;
1374 if (tp->phys[0] >= 0) {
1375 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1379 /* Start the hardware at open or resume. */
1380 static void rtl8139_hw_start (struct net_device *dev)
1382 struct rtl8139_private *tp = dev->priv;
1383 void *ioaddr = tp->mmio_addr;
1387 /* Bring old chips out of low-power mode. */
1388 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1389 RTL_W8 (HltClk, 'R');
1391 rtl8139_chip_reset (ioaddr);
1393 /* unlock Config[01234] and BMCR register writes */
1394 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1395 /* Restore our idea of the MAC address. */
1396 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1397 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1399 /* Must enable Tx/Rx before setting transfer thresholds! */
1400 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1402 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1403 RTL_W32 (RxConfig, tp->rx_config);
1405 /* Check this value: the documentation for IFG contradicts ifself. */
1406 RTL_W32 (TxConfig, rtl8139_tx_config);
1410 rtl_check_media (dev, 1);
1412 if (tp->chipset >= CH_8139B) {
1413 /* Disable magic packet scanning, which is enabled
1414 * when PM is enabled in Config1. It can be reenabled
1415 * via ETHTOOL_SWOL if desired. */
1416 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1419 DPRINTK("init buffer addresses\n");
1421 /* Lock Config[01234] and BMCR register writes */
1422 RTL_W8 (Cfg9346, Cfg9346_Lock);
1424 /* init Rx ring buffer DMA address */
1425 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1427 /* init Tx buffer DMA addresses */
1428 for (i = 0; i < NUM_TX_DESC; i++)
1429 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1431 RTL_W32 (RxMissed, 0);
1433 rtl8139_set_rx_mode (dev);
1435 /* no early-rx interrupts */
1436 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1438 /* make sure RxTx has started */
1439 tmp = RTL_R8 (ChipCmd);
1440 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1441 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1443 /* Enable all known interrupts by setting the interrupt mask. */
1444 RTL_W16 (IntrMask, rtl8139_intr_mask);
1448 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1449 static void rtl8139_init_ring (struct net_device *dev)
1451 struct rtl8139_private *tp = dev->priv;
1458 for (i = 0; i < NUM_TX_DESC; i++)
1459 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1463 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1464 static int next_tick = 3 * HZ;
1466 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1467 static inline void rtl8139_tune_twister (struct net_device *dev,
1468 struct rtl8139_private *tp) {}
1470 enum TwisterParamVals {
1471 PARA78_default = 0x78fa8388,
1472 PARA7c_default = 0xcb38de43, /* param[0][3] */
1473 PARA7c_xxx = 0xcb38de43,
1476 static const unsigned long param[4][4] = {
1477 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1478 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1479 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1480 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1483 static void rtl8139_tune_twister (struct net_device *dev,
1484 struct rtl8139_private *tp)
1487 void *ioaddr = tp->mmio_addr;
1489 /* This is a complicated state machine to configure the "twister" for
1490 impedance/echos based on the cable length.
1491 All of this is magic and undocumented.
1493 switch (tp->twistie) {
1495 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1496 /* We have link beat, let us tune the twister. */
1497 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1498 tp->twistie = 2; /* Change to state 2. */
1499 next_tick = HZ / 10;
1501 /* Just put in some reasonable defaults for when beat returns. */
1502 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1503 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1504 RTL_W32 (PARA78, PARA78_default);
1505 RTL_W32 (PARA7c, PARA7c_default);
1506 tp->twistie = 0; /* Bail from future actions. */
1510 /* Read how long it took to hear the echo. */
1511 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1512 if (linkcase == 0x7000)
1514 else if (linkcase == 0x3000)
1516 else if (linkcase == 0x1000)
1521 tp->twistie = 3; /* Change to state 2. */
1522 next_tick = HZ / 10;
1525 /* Put out four tuning parameters, one per 100msec. */
1526 if (tp->twist_col == 0)
1527 RTL_W16 (FIFOTMS, 0);
1528 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1529 [(int) tp->twist_col]);
1530 next_tick = HZ / 10;
1531 if (++tp->twist_col >= 4) {
1532 /* For short cables we are done.
1533 For long cables (row == 3) check for mistune. */
1535 (tp->twist_row == 3) ? 4 : 0;
1539 /* Special case for long cables: check for mistune. */
1540 if ((RTL_R16 (CSCR) &
1541 CSCR_LinkStatusBits) == 0x7000) {
1545 RTL_W32 (PARA7c, 0xfb38de03);
1547 next_tick = HZ / 10;
1551 /* Retune for shorter cable (column 2). */
1552 RTL_W32 (FIFOTMS, 0x20);
1553 RTL_W32 (PARA78, PARA78_default);
1554 RTL_W32 (PARA7c, PARA7c_default);
1555 RTL_W32 (FIFOTMS, 0x00);
1559 next_tick = HZ / 10;
1567 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1569 static inline void rtl8139_thread_iter (struct net_device *dev,
1570 struct rtl8139_private *tp,
1575 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1577 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1578 int duplex = (mii_lpa & LPA_100FULL)
1579 || (mii_lpa & 0x01C0) == 0x0040;
1580 if (tp->mii.full_duplex != duplex) {
1581 tp->mii.full_duplex = duplex;
1585 "%s: Setting %s-duplex based on MII #%d link"
1586 " partner ability of %4.4x.\n",
1588 tp->mii.full_duplex ? "full" : "half",
1589 tp->phys[0], mii_lpa);
1591 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1595 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1596 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1597 RTL_W8 (Cfg9346, Cfg9346_Lock);
1602 next_tick = HZ * 60;
1604 rtl8139_tune_twister (dev, tp);
1606 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1607 dev->name, RTL_R16 (NWayLPAR));
1608 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1609 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1610 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1611 dev->name, RTL_R8 (Config0),
1615 static int rtl8139_thread (void *data)
1617 struct net_device *dev = data;
1618 struct rtl8139_private *tp = dev->priv;
1619 unsigned long timeout;
1621 daemonize("%s", dev->name);
1622 allow_signal(SIGTERM);
1625 timeout = next_tick;
1627 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1628 /* make swsusp happy with our thread */
1629 if (current->flags & PF_FREEZE)
1630 refrigerator(PF_FREEZE);
1631 } while (!signal_pending (current) && (timeout > 0));
1633 if (signal_pending (current)) {
1634 flush_signals(current);
1637 if (tp->time_to_die)
1641 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1645 complete_and_exit (&tp->thr_exited, 0);
1648 static void rtl8139_start_thread(struct net_device *dev)
1650 struct rtl8139_private *tp = dev->priv;
1654 tp->time_to_die = 0;
1655 if (tp->chipset == CH_8139_K)
1657 else if (tp->drv_flags & HAS_LNK_CHNG)
1660 tp->thr_pid = kernel_thread(rtl8139_thread, dev, CLONE_FS|CLONE_FILES);
1661 if (tp->thr_pid < 0) {
1662 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1667 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1672 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1676 static void rtl8139_tx_timeout (struct net_device *dev)
1678 struct rtl8139_private *tp = dev->priv;
1679 void *ioaddr = tp->mmio_addr;
1682 unsigned long flags;
1684 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1685 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1686 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1687 /* Emit info to figure out what went wrong. */
1688 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1689 dev->name, tp->cur_tx, tp->dirty_tx);
1690 for (i = 0; i < NUM_TX_DESC; i++)
1691 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1692 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1693 i == tp->dirty_tx % NUM_TX_DESC ?
1694 " (queue head)" : "");
1696 tp->xstats.tx_timeouts++;
1698 /* disable Tx ASAP, if not already */
1699 tmp8 = RTL_R8 (ChipCmd);
1700 if (tmp8 & CmdTxEnb)
1701 RTL_W8 (ChipCmd, CmdRxEnb);
1703 spin_lock(&tp->rx_lock);
1704 /* Disable interrupts by clearing the interrupt mask. */
1705 RTL_W16 (IntrMask, 0x0000);
1707 /* Stop a shared interrupt from scavenging while we are. */
1708 spin_lock_irqsave (&tp->lock, flags);
1709 rtl8139_tx_clear (tp);
1710 spin_unlock_irqrestore (&tp->lock, flags);
1712 /* ...and finally, reset everything */
1713 if (netif_running(dev)) {
1714 rtl8139_hw_start (dev);
1715 netif_wake_queue (dev);
1717 spin_unlock(&tp->rx_lock);
1721 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1723 struct rtl8139_private *tp = dev->priv;
1724 void *ioaddr = tp->mmio_addr;
1726 unsigned int len = skb->len;
1728 /* Calculate the next Tx descriptor entry. */
1729 entry = tp->cur_tx % NUM_TX_DESC;
1731 /* Note: the chip doesn't have auto-pad! */
1732 if (likely(len < TX_BUF_SIZE)) {
1734 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1735 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1739 tp->stats.tx_dropped++;
1743 spin_lock_irq(&tp->lock);
1744 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1745 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1747 dev->trans_start = jiffies;
1752 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1753 netif_stop_queue (dev);
1754 spin_unlock_irq(&tp->lock);
1756 if (netif_msg_tx_queued(tp))
1757 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1758 dev->name, len, entry);
1764 static void rtl8139_tx_interrupt (struct net_device *dev,
1765 struct rtl8139_private *tp,
1768 unsigned long dirty_tx, tx_left;
1770 assert (dev != NULL);
1771 assert (tp != NULL);
1772 assert (ioaddr != NULL);
1774 dirty_tx = tp->dirty_tx;
1775 tx_left = tp->cur_tx - dirty_tx;
1776 while (tx_left > 0) {
1777 int entry = dirty_tx % NUM_TX_DESC;
1780 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1782 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1783 break; /* It still hasn't been Txed */
1785 /* Note: TxCarrierLost is always asserted at 100mbps. */
1786 if (txstatus & (TxOutOfWindow | TxAborted)) {
1787 /* There was an major error, log it. */
1788 if (netif_msg_tx_err(tp))
1789 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1790 dev->name, txstatus);
1791 tp->stats.tx_errors++;
1792 if (txstatus & TxAborted) {
1793 tp->stats.tx_aborted_errors++;
1794 RTL_W32 (TxConfig, TxClearAbt);
1795 RTL_W16 (IntrStatus, TxErr);
1798 if (txstatus & TxCarrierLost)
1799 tp->stats.tx_carrier_errors++;
1800 if (txstatus & TxOutOfWindow)
1801 tp->stats.tx_window_errors++;
1803 if (txstatus & TxUnderrun) {
1804 /* Add 64 to the Tx FIFO threshold. */
1805 if (tp->tx_flag < 0x00300000)
1806 tp->tx_flag += 0x00020000;
1807 tp->stats.tx_fifo_errors++;
1809 tp->stats.collisions += (txstatus >> 24) & 15;
1810 tp->stats.tx_bytes += txstatus & 0x7ff;
1811 tp->stats.tx_packets++;
1818 #ifndef RTL8139_NDEBUG
1819 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1820 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1821 dev->name, dirty_tx, tp->cur_tx);
1822 dirty_tx += NUM_TX_DESC;
1824 #endif /* RTL8139_NDEBUG */
1826 /* only wake the queue if we did work, and the queue is stopped */
1827 if (tp->dirty_tx != dirty_tx) {
1828 tp->dirty_tx = dirty_tx;
1830 netif_wake_queue (dev);
1835 /* TODO: clean this up! Rx reset need not be this intensive */
1836 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1837 struct rtl8139_private *tp, void *ioaddr)
1840 #ifdef CONFIG_8139_OLD_RX_RESET
1844 if (netif_msg_rx_err (tp))
1845 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1846 dev->name, rx_status);
1847 tp->stats.rx_errors++;
1848 if (!(rx_status & RxStatusOK)) {
1849 if (rx_status & RxTooLong) {
1850 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1851 dev->name, rx_status);
1852 /* A.C.: The chip hangs here. */
1854 if (rx_status & (RxBadSymbol | RxBadAlign))
1855 tp->stats.rx_frame_errors++;
1856 if (rx_status & (RxRunt | RxTooLong))
1857 tp->stats.rx_length_errors++;
1858 if (rx_status & RxCRCErr)
1859 tp->stats.rx_crc_errors++;
1861 tp->xstats.rx_lost_in_ring++;
1864 #ifndef CONFIG_8139_OLD_RX_RESET
1865 tmp8 = RTL_R8 (ChipCmd);
1866 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1867 RTL_W8 (ChipCmd, tmp8);
1868 RTL_W32 (RxConfig, tp->rx_config);
1871 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1873 /* disable receive */
1874 RTL_W8_F (ChipCmd, CmdTxEnb);
1876 while (--tmp_work > 0) {
1878 tmp8 = RTL_R8 (ChipCmd);
1879 if (!(tmp8 & CmdRxEnb))
1883 printk (KERN_WARNING PFX "rx stop wait too long\n");
1884 /* restart receive */
1886 while (--tmp_work > 0) {
1887 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1889 tmp8 = RTL_R8 (ChipCmd);
1890 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1894 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1896 /* and reinitialize all rx related registers */
1897 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1898 /* Must enable Tx/Rx before setting transfer thresholds! */
1899 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1901 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1902 RTL_W32 (RxConfig, tp->rx_config);
1905 DPRINTK("init buffer addresses\n");
1907 /* Lock Config[01234] and BMCR register writes */
1908 RTL_W8 (Cfg9346, Cfg9346_Lock);
1910 /* init Rx ring buffer DMA address */
1911 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1913 /* A.C.: Reset the multicast list. */
1914 __set_rx_mode (dev);
1919 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1920 u32 offset, unsigned int size)
1922 u32 left = RX_BUF_LEN - offset;
1925 memcpy(skb->data, ring + offset, left);
1926 memcpy(skb->data+left, ring, size - left);
1928 memcpy(skb->data, ring + offset, size);
1932 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1934 void *ioaddr = tp->mmio_addr;
1937 status = RTL_R16 (IntrStatus) & RxAckBits;
1939 /* Clear out errors and receive interrupts */
1940 if (likely(status != 0)) {
1941 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1942 tp->stats.rx_errors++;
1943 if (status & RxFIFOOver)
1944 tp->stats.rx_fifo_errors++;
1946 RTL_W16_F (IntrStatus, RxAckBits);
1950 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1953 void *ioaddr = tp->mmio_addr;
1955 unsigned char *rx_ring = tp->rx_ring;
1956 unsigned int cur_rx = tp->cur_rx;
1957 unsigned int rx_size = 0;
1959 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1960 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1961 RTL_R16 (RxBufAddr),
1962 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1964 while (netif_running(dev) && received < budget
1965 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1966 u32 ring_offset = cur_rx % RX_BUF_LEN;
1968 unsigned int pkt_size;
1969 struct sk_buff *skb;
1973 /* read size+status of next frame from DMA ring buffer */
1974 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1975 rx_size = rx_status >> 16;
1976 pkt_size = rx_size - 4;
1978 if (netif_msg_rx_status(tp))
1979 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1980 " cur %4.4x.\n", dev->name, rx_status,
1982 #if RTL8139_DEBUG > 2
1985 DPRINTK ("%s: Frame contents ", dev->name);
1986 for (i = 0; i < 70; i++)
1988 rx_ring[ring_offset + i]);
1993 /* Packet copy from FIFO still in progress.
1994 * Theoretically, this should never happen
1995 * since EarlyRx is disabled.
1997 if (unlikely(rx_size == 0xfff0)) {
1998 if (!tp->fifo_copy_timeout)
1999 tp->fifo_copy_timeout = jiffies + 2;
2000 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
2001 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
2005 if (netif_msg_intr(tp)) {
2006 printk(KERN_DEBUG "%s: fifo copy in progress.",
2009 tp->xstats.early_rx++;
2014 tp->fifo_copy_timeout = 0;
2016 /* If Rx err or invalid rx_size/rx_status received
2017 * (which happens if we get lost in the ring),
2018 * Rx process gets reset, so we abort any further
2021 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2023 (!(rx_status & RxStatusOK)))) {
2024 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2029 /* Malloc up new buffer, compatible with net-2e. */
2030 /* Omit the four octet CRC from the length. */
2032 skb = dev_alloc_skb (pkt_size + 2);
2035 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2037 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2039 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2041 skb_put (skb, pkt_size);
2043 skb->protocol = eth_type_trans (skb, dev);
2045 dev->last_rx = jiffies;
2046 tp->stats.rx_bytes += pkt_size;
2047 tp->stats.rx_packets++;
2049 netif_receive_skb (skb);
2051 if (net_ratelimit())
2052 printk (KERN_WARNING
2053 "%s: Memory squeeze, dropping packet.\n",
2055 tp->stats.rx_dropped++;
2059 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2060 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2062 rtl8139_isr_ack(tp);
2065 if (unlikely(!received || rx_size == 0xfff0))
2066 rtl8139_isr_ack(tp);
2068 #if RTL8139_DEBUG > 1
2069 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2070 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2071 RTL_R16 (RxBufAddr),
2072 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2075 tp->cur_rx = cur_rx;
2078 * The receive buffer should be mostly empty.
2079 * Tell NAPI to reenable the Rx irq.
2081 if (tp->fifo_copy_timeout)
2089 static void rtl8139_weird_interrupt (struct net_device *dev,
2090 struct rtl8139_private *tp,
2092 int status, int link_changed)
2094 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2097 assert (dev != NULL);
2098 assert (tp != NULL);
2099 assert (ioaddr != NULL);
2101 /* Update the error count. */
2102 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2103 RTL_W32 (RxMissed, 0);
2105 if ((status & RxUnderrun) && link_changed &&
2106 (tp->drv_flags & HAS_LNK_CHNG)) {
2107 rtl_check_media(dev, 0);
2108 status &= ~RxUnderrun;
2111 if (status & (RxUnderrun | RxErr))
2112 tp->stats.rx_errors++;
2114 if (status & PCSTimeout)
2115 tp->stats.rx_length_errors++;
2116 if (status & RxUnderrun)
2117 tp->stats.rx_fifo_errors++;
2118 if (status & PCIErr) {
2120 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2121 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2123 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2124 dev->name, pci_cmd_status);
2128 static int rtl8139_poll(struct net_device *dev, int *budget)
2130 struct rtl8139_private *tp = dev->priv;
2131 void *ioaddr = tp->mmio_addr;
2132 int orig_budget = min(*budget, dev->quota);
2135 spin_lock(&tp->rx_lock);
2136 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2139 work_done = rtl8139_rx(dev, tp, orig_budget);
2140 if (likely(work_done > 0)) {
2141 *budget -= work_done;
2142 dev->quota -= work_done;
2143 done = (work_done < orig_budget);
2149 * Order is important since data can get interrupted
2150 * again when we think we are done.
2152 local_irq_disable();
2153 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2154 __netif_rx_complete(dev);
2157 spin_unlock(&tp->rx_lock);
2162 /* The interrupt handler does all of the Rx thread work and cleans up
2163 after the Tx thread. */
2164 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2165 struct pt_regs *regs)
2167 struct net_device *dev = (struct net_device *) dev_instance;
2168 struct rtl8139_private *tp = dev->priv;
2169 void *ioaddr = tp->mmio_addr;
2170 u16 status, ackstat;
2171 int link_changed = 0; /* avoid bogus "uninit" warning */
2174 spin_lock (&tp->lock);
2175 status = RTL_R16 (IntrStatus);
2178 if (unlikely((status & rtl8139_intr_mask) == 0))
2183 /* h/w no longer present (hotplug?) or major error, bail */
2184 if (unlikely(status == 0xFFFF))
2187 /* close possible race's with dev_close */
2188 if (unlikely(!netif_running(dev))) {
2189 RTL_W16 (IntrMask, 0);
2193 /* Acknowledge all of the current interrupt sources ASAP, but
2194 an first get an additional status bit from CSCR. */
2195 if (unlikely(status & RxUnderrun))
2196 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2198 ackstat = status & ~(RxAckBits | TxErr);
2200 RTL_W16 (IntrStatus, ackstat);
2202 /* Receive packets are processed by poll routine.
2203 If not running start it now. */
2204 if (status & RxAckBits){
2205 if (netif_rx_schedule_prep(dev)) {
2206 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2207 __netif_rx_schedule (dev);
2211 /* Check uncommon events with one test. */
2212 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2213 rtl8139_weird_interrupt (dev, tp, ioaddr,
2214 status, link_changed);
2216 if (status & (TxOK | TxErr)) {
2217 rtl8139_tx_interrupt (dev, tp, ioaddr);
2219 RTL_W16 (IntrStatus, TxErr);
2222 spin_unlock (&tp->lock);
2224 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2225 dev->name, RTL_R16 (IntrStatus));
2226 return IRQ_RETVAL(handled);
2229 #ifdef CONFIG_NET_POLL_CONTROLLER
2231 * Polling receive - used by netconsole and other diagnostic tools
2232 * to allow network i/o with interrupts disabled.
2234 static void rtl8139_poll_controller(struct net_device *dev)
2236 disable_irq(dev->irq);
2237 rtl8139_interrupt(dev->irq, dev, NULL);
2238 enable_irq(dev->irq);
2242 static int rtl8139_close (struct net_device *dev)
2244 struct rtl8139_private *tp = dev->priv;
2245 void *ioaddr = tp->mmio_addr;
2247 unsigned long flags;
2249 netif_stop_queue (dev);
2251 if (tp->thr_pid >= 0) {
2252 tp->time_to_die = 1;
2254 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2256 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2259 wait_for_completion (&tp->thr_exited);
2262 if (netif_msg_ifdown(tp))
2263 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2264 dev->name, RTL_R16 (IntrStatus));
2266 spin_lock_irqsave (&tp->lock, flags);
2268 /* Stop the chip's Tx and Rx DMA processes. */
2269 RTL_W8 (ChipCmd, 0);
2271 /* Disable interrupts by clearing the interrupt mask. */
2272 RTL_W16 (IntrMask, 0);
2274 /* Update the error counts. */
2275 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2276 RTL_W32 (RxMissed, 0);
2278 spin_unlock_irqrestore (&tp->lock, flags);
2280 synchronize_irq (dev->irq); /* racy, but that's ok here */
2281 free_irq (dev->irq, dev);
2283 rtl8139_tx_clear (tp);
2285 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2286 tp->rx_ring, tp->rx_ring_dma);
2287 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2288 tp->tx_bufs, tp->tx_bufs_dma);
2292 /* Green! Put the chip in low-power mode. */
2293 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2295 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2296 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2302 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2303 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2304 other threads or interrupts aren't messing with the 8139. */
2305 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2307 struct rtl8139_private *np = dev->priv;
2308 void *ioaddr = np->mmio_addr;
2310 spin_lock_irq(&np->lock);
2311 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2312 u8 cfg3 = RTL_R8 (Config3);
2313 u8 cfg5 = RTL_R8 (Config5);
2315 wol->supported = WAKE_PHY | WAKE_MAGIC
2316 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2319 if (cfg3 & Cfg3_LinkUp)
2320 wol->wolopts |= WAKE_PHY;
2321 if (cfg3 & Cfg3_Magic)
2322 wol->wolopts |= WAKE_MAGIC;
2323 /* (KON)FIXME: See how netdev_set_wol() handles the
2324 following constants. */
2325 if (cfg5 & Cfg5_UWF)
2326 wol->wolopts |= WAKE_UCAST;
2327 if (cfg5 & Cfg5_MWF)
2328 wol->wolopts |= WAKE_MCAST;
2329 if (cfg5 & Cfg5_BWF)
2330 wol->wolopts |= WAKE_BCAST;
2332 spin_unlock_irq(&np->lock);
2336 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2337 that wol points to kernel memory and other threads or interrupts
2338 aren't messing with the 8139. */
2339 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2341 struct rtl8139_private *np = dev->priv;
2342 void *ioaddr = np->mmio_addr;
2346 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2347 ? (WAKE_PHY | WAKE_MAGIC
2348 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2350 if (wol->wolopts & ~support)
2353 spin_lock_irq(&np->lock);
2354 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2355 if (wol->wolopts & WAKE_PHY)
2356 cfg3 |= Cfg3_LinkUp;
2357 if (wol->wolopts & WAKE_MAGIC)
2359 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2360 RTL_W8 (Config3, cfg3);
2361 RTL_W8 (Cfg9346, Cfg9346_Lock);
2363 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2364 /* (KON)FIXME: These are untested. We may have to set the
2365 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2367 if (wol->wolopts & WAKE_UCAST)
2369 if (wol->wolopts & WAKE_MCAST)
2371 if (wol->wolopts & WAKE_BCAST)
2373 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2374 spin_unlock_irq(&np->lock);
2379 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2381 struct rtl8139_private *np = dev->priv;
2382 strcpy(info->driver, DRV_NAME);
2383 strcpy(info->version, DRV_VERSION);
2384 strcpy(info->bus_info, pci_name(np->pci_dev));
2385 info->regdump_len = np->regs_len;
2388 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2390 struct rtl8139_private *np = dev->priv;
2391 spin_lock_irq(&np->lock);
2392 mii_ethtool_gset(&np->mii, cmd);
2393 spin_unlock_irq(&np->lock);
2397 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2399 struct rtl8139_private *np = dev->priv;
2401 spin_lock_irq(&np->lock);
2402 rc = mii_ethtool_sset(&np->mii, cmd);
2403 spin_unlock_irq(&np->lock);
2407 static int rtl8139_nway_reset(struct net_device *dev)
2409 struct rtl8139_private *np = dev->priv;
2410 return mii_nway_restart(&np->mii);
2413 static u32 rtl8139_get_link(struct net_device *dev)
2415 struct rtl8139_private *np = dev->priv;
2416 return mii_link_ok(&np->mii);
2419 static u32 rtl8139_get_msglevel(struct net_device *dev)
2421 struct rtl8139_private *np = dev->priv;
2422 return np->msg_enable;
2425 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2427 struct rtl8139_private *np = dev->priv;
2428 np->msg_enable = datum;
2431 /* TODO: we are too slack to do reg dumping for pio, for now */
2432 #ifdef CONFIG_8139TOO_PIO
2433 #define rtl8139_get_regs_len NULL
2434 #define rtl8139_get_regs NULL
2436 static int rtl8139_get_regs_len(struct net_device *dev)
2438 struct rtl8139_private *np = dev->priv;
2439 return np->regs_len;
2442 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2444 struct rtl8139_private *np = dev->priv;
2446 regs->version = RTL_REGS_VER;
2448 spin_lock_irq(&np->lock);
2449 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2450 spin_unlock_irq(&np->lock);
2452 #endif /* CONFIG_8139TOO_MMIO */
2454 static int rtl8139_get_stats_count(struct net_device *dev)
2456 return RTL_NUM_STATS;
2459 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2461 struct rtl8139_private *np = dev->priv;
2463 data[0] = np->xstats.early_rx;
2464 data[1] = np->xstats.tx_buf_mapped;
2465 data[2] = np->xstats.tx_timeouts;
2466 data[3] = np->xstats.rx_lost_in_ring;
2469 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2471 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2474 static struct ethtool_ops rtl8139_ethtool_ops = {
2475 .get_drvinfo = rtl8139_get_drvinfo,
2476 .get_settings = rtl8139_get_settings,
2477 .set_settings = rtl8139_set_settings,
2478 .get_regs_len = rtl8139_get_regs_len,
2479 .get_regs = rtl8139_get_regs,
2480 .nway_reset = rtl8139_nway_reset,
2481 .get_link = rtl8139_get_link,
2482 .get_msglevel = rtl8139_get_msglevel,
2483 .set_msglevel = rtl8139_set_msglevel,
2484 .get_wol = rtl8139_get_wol,
2485 .set_wol = rtl8139_set_wol,
2486 .get_strings = rtl8139_get_strings,
2487 .get_stats_count = rtl8139_get_stats_count,
2488 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2491 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2493 struct rtl8139_private *np = dev->priv;
2496 if (!netif_running(dev))
2499 spin_lock_irq(&np->lock);
2500 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2501 spin_unlock_irq(&np->lock);
2507 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2509 struct rtl8139_private *tp = dev->priv;
2510 void *ioaddr = tp->mmio_addr;
2511 unsigned long flags;
2513 if (netif_running(dev)) {
2514 spin_lock_irqsave (&tp->lock, flags);
2515 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2516 RTL_W32 (RxMissed, 0);
2517 spin_unlock_irqrestore (&tp->lock, flags);
2523 /* Set or clear the multicast filter for this adaptor.
2524 This routine is not state sensitive and need not be SMP locked. */
2526 static void __set_rx_mode (struct net_device *dev)
2528 struct rtl8139_private *tp = dev->priv;
2529 void *ioaddr = tp->mmio_addr;
2530 u32 mc_filter[2]; /* Multicast hash filter */
2534 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2535 dev->name, dev->flags, RTL_R32 (RxConfig));
2537 /* Note: do not reorder, GCC is clever about common statements. */
2538 if (dev->flags & IFF_PROMISC) {
2539 /* Unconditionally log net taps. */
2540 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2543 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2545 mc_filter[1] = mc_filter[0] = 0xffffffff;
2546 } else if ((dev->mc_count > multicast_filter_limit)
2547 || (dev->flags & IFF_ALLMULTI)) {
2548 /* Too many to filter perfectly -- accept all multicasts. */
2549 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2550 mc_filter[1] = mc_filter[0] = 0xffffffff;
2552 struct dev_mc_list *mclist;
2553 rx_mode = AcceptBroadcast | AcceptMyPhys;
2554 mc_filter[1] = mc_filter[0] = 0;
2555 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2556 i++, mclist = mclist->next) {
2557 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2559 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2560 rx_mode |= AcceptMulticast;
2564 /* We can safely update without stopping the chip. */
2565 tmp = rtl8139_rx_config | rx_mode;
2566 if (tp->rx_config != tmp) {
2567 RTL_W32_F (RxConfig, tmp);
2568 tp->rx_config = tmp;
2570 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2571 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2574 static void rtl8139_set_rx_mode (struct net_device *dev)
2576 unsigned long flags;
2577 struct rtl8139_private *tp = dev->priv;
2579 spin_lock_irqsave (&tp->lock, flags);
2581 spin_unlock_irqrestore (&tp->lock, flags);
2586 static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
2588 struct net_device *dev = pci_get_drvdata (pdev);
2589 struct rtl8139_private *tp = dev->priv;
2590 void *ioaddr = tp->mmio_addr;
2591 unsigned long flags;
2593 pci_save_state (pdev, tp->pci_state);
2595 if (!netif_running (dev))
2598 netif_device_detach (dev);
2600 spin_lock_irqsave (&tp->lock, flags);
2602 /* Disable interrupts, stop Tx and Rx. */
2603 RTL_W16 (IntrMask, 0);
2604 RTL_W8 (ChipCmd, 0);
2606 /* Update the error counts. */
2607 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2608 RTL_W32 (RxMissed, 0);
2610 spin_unlock_irqrestore (&tp->lock, flags);
2612 pci_set_power_state (pdev, 3);
2618 static int rtl8139_resume (struct pci_dev *pdev)
2620 struct net_device *dev = pci_get_drvdata (pdev);
2621 struct rtl8139_private *tp = dev->priv;
2623 pci_restore_state (pdev, tp->pci_state);
2624 if (!netif_running (dev))
2626 pci_set_power_state (pdev, 0);
2627 rtl8139_init_ring (dev);
2628 rtl8139_hw_start (dev);
2629 netif_device_attach (dev);
2633 #endif /* CONFIG_PM */
2636 static struct pci_driver rtl8139_pci_driver = {
2638 .id_table = rtl8139_pci_tbl,
2639 .probe = rtl8139_init_one,
2640 .remove = __devexit_p(rtl8139_remove_one),
2642 .suspend = rtl8139_suspend,
2643 .resume = rtl8139_resume,
2644 #endif /* CONFIG_PM */
2648 static int __init rtl8139_init_module (void)
2650 /* when we're a module, we always print a version message,
2651 * even if no 8139 board is found.
2654 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2657 return pci_module_init (&rtl8139_pci_driver);
2661 static void __exit rtl8139_cleanup_module (void)
2663 pci_unregister_driver (&rtl8139_pci_driver);
2667 module_init(rtl8139_init_module);
2668 module_exit(rtl8139_cleanup_module);