drivers/net/amd8111e.c

   1
   2 /* Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
   3  * Copyright (C) 2004 Advanced Micro Devices
   4  *
   5  *
   6  * Copyright 2001,2002 Jeff Garzik <jgarzik@mandrakesoft.com> [ 8139cp.c,tg3.c ]
   7  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)[ tg3.c]
   8  * Copyright 1996-1999 Thomas Bogendoerfer [ pcnet32.c ]
   9  * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
  10  * Copyright 1993 United States Government as represented by the
  11  *      Director, National Security Agency.[ pcnet32.c ]
  12  * Carsten Langgaard, carstenl@mips.com [ pcnet32.c ]
  13  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  14  *
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; if not, write to the Free Software
  28  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307
  29  * USA
  30
  31 Module Name:
  32
  33         amd8111e.c
  34
  35 Abstract:
  36
  37          AMD8111 based 10/100 Ethernet Controller Driver.
  38
  39 Environment:
  40
  41         Kernel Mode
  42
  43 Revision History:
  44         3.0.0
  45            Initial Revision.
  46         3.0.1
  47          1. Dynamic interrupt coalescing.
  48          2. Removed prev_stats.
  49          3. MII support.
  50          4. Dynamic IPG support
  51         3.0.2  05/29/2003
  52          1. Bug fix: Fixed failure to send jumbo packets larger than 4k.
  53          2. Bug fix: Fixed VLAN support failure.
  54          3. Bug fix: Fixed receive interrupt coalescing bug.
  55          4. Dynamic IPG support is disabled by default.
  56         3.0.3 06/05/2003
  57          1. Bug fix: Fixed failure to close the interface if SMP is enabled.
  58         3.0.4 12/09/2003
  59          1. Added set_mac_address routine for bonding driver support.
  60          2. Tested the driver for bonding support
  61          3. Bug fix: Fixed mismach in actual receive buffer lenth and lenth
  62             indicated to the h/w.
  63          4. Modified amd8111e_rx() routine to receive all the received packets
  64             in the first interrupt.
  65          5. Bug fix: Corrected  rx_errors  reported in get_stats() function.
  66         3.0.5 03/22/2004
  67          1. Added NAPI support
  68
  69 */
  70
  71
  72 #include <linux/config.h>
  73 #include <linux/module.h>
  74 #include <linux/kernel.h>
  75 #include <linux/types.h>
  76 #include <linux/compiler.h>
  77 #include <linux/slab.h>
  78 #include <linux/delay.h>
  79 #include <linux/init.h>
  80 #include <linux/ioport.h>
  81 #include <linux/pci.h>
  82 #include <linux/netdevice.h>
  83 #include <linux/etherdevice.h>
  84 #include <linux/skbuff.h>
  85 #include <linux/ethtool.h>
  86 #include <linux/mii.h>
  87 #include <linux/if_vlan.h>
  88 #include <linux/ctype.h>
  89 #include <linux/crc32.h>
  90
  91 #include <asm/system.h>
  92 #include <asm/io.h>
  93 #include <asm/byteorder.h>
  94 #include <asm/uaccess.h>
  95
  96 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  97 #define AMD8111E_VLAN_TAG_USED 1
  98 #else
  99 #define AMD8111E_VLAN_TAG_USED 0
 100 #endif
 101
 102 #include "amd8111e.h"
 103 #define MODULE_NAME     "amd8111e"
 104 #define MODULE_VERS     "3.0.5"
 105 MODULE_AUTHOR("Advanced Micro Devices, Inc.");
 106 MODULE_DESCRIPTION ("AMD8111 based 10/100 Ethernet Controller. Driver Version 3.0.3");
 107 MODULE_LICENSE("GPL");
 108 module_param_array(speed_duplex, int, NULL, 0);
 109 MODULE_PARM_DESC(speed_duplex, "Set device speed and duplex modes, 0: Auto Negotitate, 1: 10Mbps Half Duplex, 2: 10Mbps Full Duplex, 3: 100Mbps Half Duplex, 4: 100Mbps Full Duplex");
 110 module_param_array(coalesce, bool, NULL, 0);
 111 MODULE_PARM_DESC(coalesce, "Enable or Disable interrupt coalescing, 1: Enable, 0: Disable");
 112 module_param_array(dynamic_ipg, bool, NULL, 0);
 113 MODULE_PARM_DESC(dynamic_ipg, "Enable or Disable dynamic IPG, 1: Enable, 0: Disable");
 114
 115 static struct pci_device_id amd8111e_pci_tbl[] = {
 116
 117         { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD8111E_7462,
 118          PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 119         { 0, }
 120
 121 };
 122 /*
 123 This function will read the PHY registers.
 124 */
 125 static int amd8111e_read_phy(struct amd8111e_priv* lp, int phy_id, int reg, u32* val)
 126 {
 127         void __iomem *mmio = lp->mmio;
 128         unsigned int reg_val;
 129         unsigned int repeat= REPEAT_CNT;
 130
 131         reg_val = readl(mmio + PHY_ACCESS);
 132         while (reg_val & PHY_CMD_ACTIVE)
 133                 reg_val = readl( mmio + PHY_ACCESS );
 134
 135         writel( PHY_RD_CMD | ((phy_id & 0x1f) << 21) |
 136                            ((reg & 0x1f) << 16),  mmio +PHY_ACCESS);
 137         do{
 138                 reg_val = readl(mmio + PHY_ACCESS);
 139                 udelay(30);  /* It takes 30 us to read/write data */
 140         } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
 141         if(reg_val & PHY_RD_ERR)
 142                 goto err_phy_read;
 143
 144         *val = reg_val & 0xffff;
 145         return 0;
 146 err_phy_read:
 147         *val = 0;
 148         return -EINVAL;
 149
 150 }
 151
 152 /*
 153 This function will write into PHY registers.
 154 */
 155 static int amd8111e_write_phy(struct amd8111e_priv* lp,int phy_id, int reg, u32 val)
 156 {
 157         unsigned int repeat = REPEAT_CNT
 158         void __iomem *mmio = lp->mmio;
 159         unsigned int reg_val;
 160
 161         reg_val = readl(mmio + PHY_ACCESS);
 162         while (reg_val & PHY_CMD_ACTIVE)
 163                 reg_val = readl( mmio + PHY_ACCESS );
 164
 165         writel( PHY_WR_CMD | ((phy_id & 0x1f) << 21) |
 166                            ((reg & 0x1f) << 16)|val, mmio + PHY_ACCESS);
 167
 168         do{
 169                 reg_val = readl(mmio + PHY_ACCESS);
 170                 udelay(30);  /* It takes 30 us to read/write the data */
 171         } while (--repeat && (reg_val & PHY_CMD_ACTIVE));
 172
 173         if(reg_val & PHY_RD_ERR)
 174                 goto err_phy_write;
 175
 176         return 0;
 177
 178 err_phy_write:
 179         return -EINVAL;
 180
 181 }
 182 /*
 183 This is the mii register read function provided to the mii interface.
 184 */
 185 static int amd8111e_mdio_read(struct net_device * dev, int phy_id, int reg_num)
 186 {
 187         struct amd8111e_priv* lp = netdev_priv(dev);
 188         unsigned int reg_val;
 189
 190         amd8111e_read_phy(lp,phy_id,reg_num,&reg_val);
 191         return reg_val;
 192
 193 }
 194
 195 /*
 196 This is the mii register write function provided to the mii interface.
 197 */
 198 static void amd8111e_mdio_write(struct net_device * dev, int phy_id, int reg_num, int val)
 199 {
 200         struct amd8111e_priv* lp = netdev_priv(dev);
 201
 202         amd8111e_write_phy(lp, phy_id, reg_num, val);
 203 }
 204
 205 /*
 206 This function will set PHY speed. During initialization sets the original speed to 100 full.
 207 */
 208 static void amd8111e_set_ext_phy(struct net_device *dev)
 209 {
 210         struct amd8111e_priv *lp = netdev_priv(dev);
 211         u32 bmcr,advert,tmp;
 212
 213         /* Determine mii register values to set the speed */
 214         advert = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_ADVERTISE);
 215         tmp = advert & ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
 216         switch (lp->ext_phy_option){
 217
 218                 default:
 219                 case SPEED_AUTONEG: /* advertise all values */
 220                         tmp |= ( ADVERTISE_10HALF|ADVERTISE_10FULL|
 221                                 ADVERTISE_100HALF|ADVERTISE_100FULL) ;
 222                         break;
 223                 case SPEED10_HALF:
 224                         tmp |= ADVERTISE_10HALF;
 225                         break;
 226                 case SPEED10_FULL:
 227                         tmp |= ADVERTISE_10FULL;
 228                         break;
 229                 case SPEED100_HALF:
 230                         tmp |= ADVERTISE_100HALF;
 231                         break;
 232                 case SPEED100_FULL:
 233                         tmp |= ADVERTISE_100FULL;
 234                         break;
 235         }
 236
 237         if(advert != tmp)
 238                 amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_ADVERTISE, tmp);
 239         /* Restart auto negotiation */
 240         bmcr = amd8111e_mdio_read(dev, lp->ext_phy_addr, MII_BMCR);
 241         bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
 242         amd8111e_mdio_write(dev, lp->ext_phy_addr, MII_BMCR, bmcr);
 243
 244 }
 245
 246 /*
 247 This function will unmap skb->data space and will free
 248 all transmit and receive skbuffs.
 249 */
 250 static int amd8111e_free_skbs(struct net_device *dev)
 251 {
 252         struct amd8111e_priv *lp = netdev_priv(dev);
 253         struct sk_buff* rx_skbuff;
 254         int i;
 255
 256         /* Freeing transmit skbs */
 257         for(i = 0; i < NUM_TX_BUFFERS; i++){
 258                 if(lp->tx_skbuff[i]){
 259                         pci_unmap_single(lp->pci_dev,lp->tx_dma_addr[i],                                        lp->tx_skbuff[i]->len,PCI_DMA_TODEVICE);
 260                         dev_kfree_skb (lp->tx_skbuff[i]);
 261                         lp->tx_skbuff[i] = NULL;
 262                         lp->tx_dma_addr[i] = 0;
 263                 }
 264         }
 265         /* Freeing previously allocated receive buffers */
 266         for (i = 0; i < NUM_RX_BUFFERS; i++){
 267                 rx_skbuff = lp->rx_skbuff[i];
 268                 if(rx_skbuff != NULL){
 269                         pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[i],
 270                                   lp->rx_buff_len - 2,PCI_DMA_FROMDEVICE);
 271                         dev_kfree_skb(lp->rx_skbuff[i]);
 272                         lp->rx_skbuff[i] = NULL;
 273                         lp->rx_dma_addr[i] = 0;
 274                 }
 275         }
 276
 277         return 0;
 278 }
 279
 280 /*
 281 This will set the receive buffer length corresponding to the mtu size of networkinterface.
 282 */
 283 static inline void amd8111e_set_rx_buff_len(struct net_device* dev)
 284 {
 285         struct amd8111e_priv* lp = netdev_priv(dev);
 286         unsigned int mtu = dev->mtu;
 287
 288         if (mtu > ETH_DATA_LEN){
 289                 /* MTU + ethernet header + FCS
 290                 + optional VLAN tag + skb reserve space 2 */
 291
 292                 lp->rx_buff_len = mtu + ETH_HLEN + 10;
 293                 lp->options |= OPTION_JUMBO_ENABLE;
 294         } else{
 295                 lp->rx_buff_len = PKT_BUFF_SZ;
 296                 lp->options &= ~OPTION_JUMBO_ENABLE;
 297         }
 298 }
 299
 300 /*
 301 This function will free all the previously allocated buffers, determine new receive buffer length  and will allocate new receive buffers. This function also allocates and initializes both the transmitter and receive hardware descriptors.
 302  */
 303 static int amd8111e_init_ring(struct net_device *dev)
 304 {
 305         struct amd8111e_priv *lp = netdev_priv(dev);
 306         int i;
 307
 308         lp->rx_idx = lp->tx_idx = 0;
 309         lp->tx_complete_idx = 0;
 310         lp->tx_ring_idx = 0;
 311
 312
 313         if(lp->opened)
 314                 /* Free previously allocated transmit and receive skbs */
 315                 amd8111e_free_skbs(dev);
 316
 317         else{
 318                  /* allocate the tx and rx descriptors */
 319                 if((lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
 320                         sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
 321                         &lp->tx_ring_dma_addr)) == NULL)
 322
 323                         goto err_no_mem;
 324
 325                 if((lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
 326                         sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
 327                         &lp->rx_ring_dma_addr)) == NULL)
 328
 329                         goto err_free_tx_ring;
 330
 331         }
 332         /* Set new receive buff size */
 333         amd8111e_set_rx_buff_len(dev);
 334
 335         /* Allocating receive  skbs */
 336         for (i = 0; i < NUM_RX_BUFFERS; i++) {
 337
 338                 if (!(lp->rx_skbuff[i] = dev_alloc_skb(lp->rx_buff_len))) {
 339                                 /* Release previos allocated skbs */
 340                                 for(--i; i >= 0 ;i--)
 341                                         dev_kfree_skb(lp->rx_skbuff[i]);
 342                                 goto err_free_rx_ring;
 343                 }
 344                 skb_reserve(lp->rx_skbuff[i],2);
 345         }
 346         /* Initilaizing receive descriptors */
 347         for (i = 0; i < NUM_RX_BUFFERS; i++) {
 348                 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev,
 349                         lp->rx_skbuff[i]->data,lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 350
 351                 lp->rx_ring[i].buff_phy_addr = cpu_to_le32(lp->rx_dma_addr[i]);
 352                 lp->rx_ring[i].buff_count = cpu_to_le16(lp->rx_buff_len-2);
 353                 wmb();
 354                 lp->rx_ring[i].rx_flags = cpu_to_le16(OWN_BIT);
 355         }
 356
 357         /* Initializing transmit descriptors */
 358         for (i = 0; i < NUM_TX_RING_DR; i++) {
 359                 lp->tx_ring[i].buff_phy_addr = 0;
 360                 lp->tx_ring[i].tx_flags = 0;
 361                 lp->tx_ring[i].buff_count = 0;
 362         }
 363
 364         return 0;
 365
 366 err_free_rx_ring:
 367
 368         pci_free_consistent(lp->pci_dev,
 369                 sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,lp->rx_ring,
 370                 lp->rx_ring_dma_addr);
 371
 372 err_free_tx_ring:
 373
 374         pci_free_consistent(lp->pci_dev,
 375                  sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,lp->tx_ring,
 376                  lp->tx_ring_dma_addr);
 377
 378 err_no_mem:
 379         return -ENOMEM;
 380 }
 381 /* This function will set the interrupt coalescing according to the input arguments */
 382 static int amd8111e_set_coalesce(struct net_device * dev, enum coal_mode cmod)
 383 {
 384         unsigned int timeout;
 385         unsigned int event_count;
 386
 387         struct amd8111e_priv *lp = netdev_priv(dev);
 388         void __iomem *mmio = lp->mmio;
 389         struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
 390
 391
 392         switch(cmod)
 393         {
 394                 case RX_INTR_COAL :
 395                         timeout = coal_conf->rx_timeout;
 396                         event_count = coal_conf->rx_event_count;
 397                         if( timeout > MAX_TIMEOUT ||
 398                                         event_count > MAX_EVENT_COUNT )
 399                         return -EINVAL;
 400
 401                         timeout = timeout * DELAY_TIMER_CONV;
 402                         writel(VAL0|STINTEN, mmio+INTEN0);
 403                         writel((u32)DLY_INT_A_R0|( event_count<< 16 )|timeout,
 404                                                         mmio+DLY_INT_A);
 405                         break;
 406
 407                 case TX_INTR_COAL :
 408                         timeout = coal_conf->tx_timeout;
 409                         event_count = coal_conf->tx_event_count;
 410                         if( timeout > MAX_TIMEOUT ||
 411                                         event_count > MAX_EVENT_COUNT )
 412                         return -EINVAL;
 413
 414
 415                         timeout = timeout * DELAY_TIMER_CONV;
 416                         writel(VAL0|STINTEN,mmio+INTEN0);
 417                         writel((u32)DLY_INT_B_T0|( event_count<< 16 )|timeout,
 418                                                          mmio+DLY_INT_B);
 419                         break;
 420
 421                 case DISABLE_COAL:
 422                         writel(0,mmio+STVAL);
 423                         writel(STINTEN, mmio+INTEN0);
 424                         writel(0, mmio +DLY_INT_B);
 425                         writel(0, mmio+DLY_INT_A);
 426                         break;
 427                  case ENABLE_COAL:
 428                        /* Start the timer */
 429                         writel((u32)SOFT_TIMER_FREQ, mmio+STVAL); /*  0.5 sec */
 430                         writel(VAL0|STINTEN, mmio+INTEN0);
 431                         break;
 432                 default:
 433                         break;
 434
 435    }
 436         return 0;
 437
 438 }
 439
 440 /*
 441 This function initializes the device registers  and starts the device.
 442 */
 443 static int amd8111e_restart(struct net_device *dev)
 444 {
 445         struct amd8111e_priv *lp = netdev_priv(dev);
 446         void __iomem *mmio = lp->mmio;
 447         int i,reg_val;
 448
 449         /* stop the chip */
 450          writel(RUN, mmio + CMD0);
 451
 452         if(amd8111e_init_ring(dev))
 453                 return -ENOMEM;
 454
 455         /* enable the port manager and set auto negotiation always */
 456         writel((u32) VAL1|EN_PMGR, mmio + CMD3 );
 457         writel((u32)XPHYANE|XPHYRST , mmio + CTRL2);
 458
 459         amd8111e_set_ext_phy(dev);
 460
 461         /* set control registers */
 462         reg_val = readl(mmio + CTRL1);
 463         reg_val &= ~XMTSP_MASK;
 464         writel( reg_val| XMTSP_128 | CACHE_ALIGN, mmio + CTRL1 );
 465
 466         /* enable interrupt */
 467         writel( APINT5EN | APINT4EN | APINT3EN | APINT2EN | APINT1EN |
 468                 APINT0EN | MIIPDTINTEN | MCCIINTEN | MCCINTEN | MREINTEN |
 469                 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0);
 470
 471         writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0);
 472
 473         /* initialize tx and rx ring base addresses */
 474         writel((u32)lp->tx_ring_dma_addr,mmio + XMT_RING_BASE_ADDR0);
 475         writel((u32)lp->rx_ring_dma_addr,mmio+ RCV_RING_BASE_ADDR0);
 476
 477         writew((u32)NUM_TX_RING_DR, mmio + XMT_RING_LEN0);
 478         writew((u16)NUM_RX_RING_DR, mmio + RCV_RING_LEN0);
 479
 480         /* set default IPG to 96 */
 481         writew((u32)DEFAULT_IPG,mmio+IPG);
 482         writew((u32)(DEFAULT_IPG-IFS1_DELTA), mmio + IFS1);
 483
 484         if(lp->options & OPTION_JUMBO_ENABLE){
 485                 writel((u32)VAL2|JUMBO, mmio + CMD3);
 486                 /* Reset REX_UFLO */
 487                 writel( REX_UFLO, mmio + CMD2);
 488                 /* Should not set REX_UFLO for jumbo frames */
 489                 writel( VAL0 | APAD_XMT|REX_RTRY , mmio + CMD2);
 490         }else{
 491                 writel( VAL0 | APAD_XMT | REX_RTRY|REX_UFLO, mmio + CMD2);
 492                 writel((u32)JUMBO, mmio + CMD3);
 493         }
 494
 495 #if AMD8111E_VLAN_TAG_USED
 496         writel((u32) VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3);
 497 #endif
 498         writel( VAL0 | APAD_XMT | REX_RTRY, mmio + CMD2 );
 499
 500         /* Setting the MAC address to the device */
 501         for(i = 0; i < ETH_ADDR_LEN; i++)
 502                 writeb( dev->dev_addr[i], mmio + PADR + i );
 503
 504         /* Enable interrupt coalesce */
 505         if(lp->options & OPTION_INTR_COAL_ENABLE){
 506                 printk(KERN_INFO "%s: Interrupt Coalescing Enabled.\n",
 507                                                                 dev->name);
 508                 amd8111e_set_coalesce(dev,ENABLE_COAL);
 509         }
 510
 511         /* set RUN bit to start the chip */
 512         writel(VAL2 | RDMD0, mmio + CMD0);
 513         writel(VAL0 | INTREN | RUN, mmio + CMD0);
 514
 515         /* To avoid PCI posting bug */
 516         readl(mmio+CMD0);
 517         return 0;
 518 }
 519 /*
 520 This function clears necessary the device registers.
 521 */
 522 static void amd8111e_init_hw_default( struct amd8111e_priv* lp)
 523 {
 524         unsigned int reg_val;
 525         unsigned int logic_filter[2] ={0,};
 526         void __iomem *mmio = lp->mmio;
 527
 528
 529         /* stop the chip */
 530         writel(RUN, mmio + CMD0);
 531
 532         /* AUTOPOLL0 Register *//*TBD default value is 8100 in FPS */
 533         writew( 0x8100 | lp->ext_phy_addr, mmio + AUTOPOLL0);
 534
 535         /* Clear RCV_RING_BASE_ADDR */
 536         writel(0, mmio + RCV_RING_BASE_ADDR0);
 537
 538         /* Clear XMT_RING_BASE_ADDR */
 539         writel(0, mmio + XMT_RING_BASE_ADDR0);
 540         writel(0, mmio + XMT_RING_BASE_ADDR1);
 541         writel(0, mmio + XMT_RING_BASE_ADDR2);
 542         writel(0, mmio + XMT_RING_BASE_ADDR3);
 543
 544         /* Clear CMD0  */
 545         writel(CMD0_CLEAR,mmio + CMD0);
 546
 547         /* Clear CMD2 */
 548         writel(CMD2_CLEAR, mmio +CMD2);
 549
 550         /* Clear CMD7 */
 551         writel(CMD7_CLEAR , mmio + CMD7);
 552
 553         /* Clear DLY_INT_A and DLY_INT_B */
 554         writel(0x0, mmio + DLY_INT_A);
 555         writel(0x0, mmio + DLY_INT_B);
 556
 557         /* Clear FLOW_CONTROL */
 558         writel(0x0, mmio + FLOW_CONTROL);
 559
 560         /* Clear INT0  write 1 to clear register */
 561         reg_val = readl(mmio + INT0);
 562         writel(reg_val, mmio + INT0);
 563
 564         /* Clear STVAL */
 565         writel(0x0, mmio + STVAL);
 566
 567         /* Clear INTEN0 */
 568         writel( INTEN0_CLEAR, mmio + INTEN0);
 569
 570         /* Clear LADRF */
 571         writel(0x0 , mmio + LADRF);
 572
 573         /* Set SRAM_SIZE & SRAM_BOUNDARY registers  */
 574         writel( 0x80010,mmio + SRAM_SIZE);
 575
 576         /* Clear RCV_RING0_LEN */
 577         writel(0x0, mmio +  RCV_RING_LEN0);
 578
 579         /* Clear XMT_RING0/1/2/3_LEN */
 580         writel(0x0, mmio +  XMT_RING_LEN0);
 581         writel(0x0, mmio +  XMT_RING_LEN1);
 582         writel(0x0, mmio +  XMT_RING_LEN2);
 583         writel(0x0, mmio +  XMT_RING_LEN3);
 584
 585         /* Clear XMT_RING_LIMIT */
 586         writel(0x0, mmio + XMT_RING_LIMIT);
 587
 588         /* Clear MIB */
 589         writew(MIB_CLEAR, mmio + MIB_ADDR);
 590
 591         /* Clear LARF */
 592         amd8111e_writeq(*(u64*)logic_filter,mmio+LADRF);
 593
 594         /* SRAM_SIZE register */
 595         reg_val = readl(mmio + SRAM_SIZE);
 596
 597         if(lp->options & OPTION_JUMBO_ENABLE)
 598                 writel( VAL2|JUMBO, mmio + CMD3);
 599 #if AMD8111E_VLAN_TAG_USED
 600         writel(VAL2|VSIZE|VL_TAG_DEL, mmio + CMD3 );
 601 #endif
 602         /* Set default value to CTRL1 Register */
 603         writel(CTRL1_DEFAULT, mmio + CTRL1);
 604
 605         /* To avoid PCI posting bug */
 606         readl(mmio + CMD2);
 607
 608 }
 609
 610 /*
 611 This function disables the interrupt and clears all the pending
 612 interrupts in INT0
 613  */
 614 static void amd8111e_disable_interrupt(struct amd8111e_priv* lp)
 615 {
 616         u32 intr0;
 617
 618         /* Disable interrupt */
 619         writel(INTREN, lp->mmio + CMD0);
 620
 621         /* Clear INT0 */
 622         intr0 = readl(lp->mmio + INT0);
 623         writel(intr0, lp->mmio + INT0);
 624
 625         /* To avoid PCI posting bug */
 626         readl(lp->mmio + INT0);
 627
 628 }
 629
 630 /*
 631 This function stops the chip.
 632 */
 633 static void amd8111e_stop_chip(struct amd8111e_priv* lp)
 634 {
 635         writel(RUN, lp->mmio + CMD0);
 636
 637         /* To avoid PCI posting bug */
 638         readl(lp->mmio + CMD0);
 639 }
 640
 641 /*
 642 This function frees the  transmiter and receiver descriptor rings.
 643 */
 644 static void amd8111e_free_ring(struct amd8111e_priv* lp)
 645 {
 646
 647         /* Free transmit and receive skbs */
 648         amd8111e_free_skbs(lp->amd8111e_net_dev);
 649
 650         /* Free transmit and receive descriptor rings */
 651         if(lp->rx_ring){
 652                 pci_free_consistent(lp->pci_dev,
 653                         sizeof(struct amd8111e_rx_dr)*NUM_RX_RING_DR,
 654                         lp->rx_ring, lp->rx_ring_dma_addr);
 655                 lp->rx_ring = NULL;
 656         }
 657
 658         if(lp->tx_ring){
 659                 pci_free_consistent(lp->pci_dev,
 660                         sizeof(struct amd8111e_tx_dr)*NUM_TX_RING_DR,
 661                         lp->tx_ring, lp->tx_ring_dma_addr);
 662
 663                 lp->tx_ring = NULL;
 664         }
 665
 666 }
 667 #if AMD8111E_VLAN_TAG_USED
 668 /*
 669 This is the receive indication function for packets with vlan tag.
 670 */
 671 static int amd8111e_vlan_rx(struct amd8111e_priv *lp, struct sk_buff *skb, u16 vlan_tag)
 672 {
 673 #ifdef CONFIG_AMD8111E_NAPI
 674         return vlan_hwaccel_receive_skb(skb, lp->vlgrp,vlan_tag);
 675 #else
 676         return vlan_hwaccel_rx(skb, lp->vlgrp, vlan_tag);
 677 #endif /* CONFIG_AMD8111E_NAPI */
 678 }
 679 #endif
 680
 681 /*
 682 This function will free all the transmit skbs that are actually transmitted by the device. It will check the ownership of the skb before freeing the skb.
 683 */
 684 static int amd8111e_tx(struct net_device *dev)
 685 {
 686         struct amd8111e_priv* lp = netdev_priv(dev);
 687         int tx_index = lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
 688         int status;
 689         /* Complete all the transmit packet */
 690         while (lp->tx_complete_idx != lp->tx_idx){
 691                 tx_index =  lp->tx_complete_idx & TX_RING_DR_MOD_MASK;
 692                 status = le16_to_cpu(lp->tx_ring[tx_index].tx_flags);
 693
 694                 if(status & OWN_BIT)
 695                         break;  /* It still hasn't been Txed */
 696
 697                 lp->tx_ring[tx_index].buff_phy_addr = 0;
 698
 699                 /* We must free the original skb */
 700                 if (lp->tx_skbuff[tx_index]) {
 701                         pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[tx_index],
 702                                         lp->tx_skbuff[tx_index]->len,
 703                                         PCI_DMA_TODEVICE);
 704                         dev_kfree_skb_irq (lp->tx_skbuff[tx_index]);
 705                         lp->tx_skbuff[tx_index] = NULL;
 706                         lp->tx_dma_addr[tx_index] = 0;
 707                 }
 708                 lp->tx_complete_idx++;
 709                 /*COAL update tx coalescing parameters */
 710                 lp->coal_conf.tx_packets++;
 711                 lp->coal_conf.tx_bytes += lp->tx_ring[tx_index].buff_count;
 712
 713                 if (netif_queue_stopped(dev) &&
 714                         lp->tx_complete_idx > lp->tx_idx - NUM_TX_BUFFERS +2){
 715                         /* The ring is no longer full, clear tbusy. */
 716                         /* lp->tx_full = 0; */
 717                         netif_wake_queue (dev);
 718                 }
 719         }
 720         return 0;
 721 }
 722
 723 #ifdef CONFIG_AMD8111E_NAPI
 724 /* This function handles the driver receive operation in polling mode */
 725 static int amd8111e_rx_poll(struct net_device *dev, int * budget)
 726 {
 727         struct amd8111e_priv *lp = netdev_priv(dev);
 728         int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
 729         void __iomem *mmio = lp->mmio;
 730         struct sk_buff *skb,*new_skb;
 731         int min_pkt_len, status;
 732         unsigned int intr0;
 733         int num_rx_pkt = 0;
 734         /*int max_rx_pkt = NUM_RX_BUFFERS;*/
 735         short pkt_len;
 736 #if AMD8111E_VLAN_TAG_USED
 737         short vtag;
 738 #endif
 739         int rx_pkt_limit = dev->quota;
 740
 741         do{
 742                 /* process receive packets until we use the quota*/
 743                 /* If we own the next entry, it's a new packet. Send it up. */
 744                 while(1) {
 745                         status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
 746                         if (status & OWN_BIT)
 747                                 break;
 748
 749                         /*
 750                          * There is a tricky error noted by John Murphy,
 751                          * <murf@perftech.com> to Russ Nelson: Even with
 752                          * full-sized * buffers it's possible for a
 753                          * jabber packet to use two buffers, with only
 754                          * the last correctly noting the error.
 755                          */
 756
 757                         if(status & ERR_BIT) {
 758                                 /* reseting flags */
 759                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 760                                 goto err_next_pkt;
 761                         }
 762                         /* check for STP and ENP */
 763                         if(!((status & STP_BIT) && (status & ENP_BIT))){
 764                                 /* reseting flags */
 765                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 766                                 goto err_next_pkt;
 767                         }
 768                         pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
 769
 770 #if AMD8111E_VLAN_TAG_USED
 771                         vtag = status & TT_MASK;
 772                         /*MAC will strip vlan tag*/
 773                         if(lp->vlgrp != NULL && vtag !=0)
 774                                 min_pkt_len =MIN_PKT_LEN - 4;
 775                         else
 776 #endif
 777                                 min_pkt_len =MIN_PKT_LEN;
 778
 779                         if (pkt_len < min_pkt_len) {
 780                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 781                                 lp->drv_rx_errors++;
 782                                 goto err_next_pkt;
 783                         }
 784                         if(--rx_pkt_limit < 0)
 785                                 goto rx_not_empty;
 786                         if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
 787                                 /* if allocation fail,
 788                                    ignore that pkt and go to next one */
 789                                 lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 790                                 lp->drv_rx_errors++;
 791                                 goto err_next_pkt;
 792                         }
 793
 794                         skb_reserve(new_skb, 2);
 795                         skb = lp->rx_skbuff[rx_index];
 796                         pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
 797                                          lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 798                         skb_put(skb, pkt_len);
 799                         skb->dev = dev;
 800                         lp->rx_skbuff[rx_index] = new_skb;
 801                         new_skb->dev = dev;
 802                         lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
 803                                                                    new_skb->data,
 804                                                                    lp->rx_buff_len-2,
 805                                                                    PCI_DMA_FROMDEVICE);
 806
 807                         skb->protocol = eth_type_trans(skb, dev);
 808
 809 #if AMD8111E_VLAN_TAG_USED
 810                         if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
 811                                 amd8111e_vlan_rx(lp, skb,
 812                                          le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
 813                         } else
 814 #endif
 815                                 netif_receive_skb(skb);
 816                         /*COAL update rx coalescing parameters*/
 817                         lp->coal_conf.rx_packets++;
 818                         lp->coal_conf.rx_bytes += pkt_len;
 819                         num_rx_pkt++;
 820                         dev->last_rx = jiffies;
 821
 822                 err_next_pkt:
 823                         lp->rx_ring[rx_index].buff_phy_addr
 824                                 = cpu_to_le32(lp->rx_dma_addr[rx_index]);
 825                         lp->rx_ring[rx_index].buff_count =
 826                                 cpu_to_le16(lp->rx_buff_len-2);
 827                         wmb();
 828                         lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
 829                         rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
 830                 }
 831                 /* Check the interrupt status register for more packets in the
 832                    mean time. Process them since we have not used up our quota.*/
 833
 834                 intr0 = readl(mmio + INT0);
 835                 /*Ack receive packets */
 836                 writel(intr0 & RINT0,mmio + INT0);
 837
 838         } while(intr0 & RINT0);
 839
 840         /* Receive descriptor is empty now */
 841         dev->quota -= num_rx_pkt;
 842         *budget -= num_rx_pkt;
 843         netif_rx_complete(dev);
 844         /* enable receive interrupt */
 845         writel(VAL0|RINTEN0, mmio + INTEN0);
 846         writel(VAL2 | RDMD0, mmio + CMD0);
 847         return 0;
 848 rx_not_empty:
 849         /* Do not call a netif_rx_complete */
 850         dev->quota -= num_rx_pkt;
 851         *budget -= num_rx_pkt;
 852         return 1;
 853
 854
 855 }
 856
 857 #else
 858 /*
 859 This function will check the ownership of receive buffers and descriptors. It will indicate to kernel up to half the number of maximum receive buffers in the descriptor ring, in a single receive interrupt. It will also replenish the descriptors with new skbs.
 860 */
 861 static int amd8111e_rx(struct net_device *dev)
 862 {
 863         struct amd8111e_priv *lp = netdev_priv(dev);
 864         struct sk_buff *skb,*new_skb;
 865         int rx_index = lp->rx_idx & RX_RING_DR_MOD_MASK;
 866         int min_pkt_len, status;
 867         int num_rx_pkt = 0;
 868         int max_rx_pkt = NUM_RX_BUFFERS;
 869         short pkt_len;
 870 #if AMD8111E_VLAN_TAG_USED
 871         short vtag;
 872 #endif
 873
 874         /* If we own the next entry, it's a new packet. Send it up. */
 875         while(++num_rx_pkt <= max_rx_pkt){
 876                 status = le16_to_cpu(lp->rx_ring[rx_index].rx_flags);
 877                 if(status & OWN_BIT)
 878                         return 0;
 879
 880                 /* check if err summary bit is set */
 881                 if(status & ERR_BIT){
 882                         /*
 883                          * There is a tricky error noted by John Murphy,
 884                          * <murf@perftech.com> to Russ Nelson: Even with full-sized
 885                          * buffers it's possible for a jabber packet to use two
 886                          * buffers, with only the last correctly noting the error.                       */
 887                         /* reseting flags */
 888                         lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 889                         goto err_next_pkt;
 890                 }
 891                 /* check for STP and ENP */
 892                 if(!((status & STP_BIT) && (status & ENP_BIT))){
 893                         /* reseting flags */
 894                         lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 895                         goto err_next_pkt;
 896                 }
 897                 pkt_len = le16_to_cpu(lp->rx_ring[rx_index].msg_count) - 4;
 898
 899 #if AMD8111E_VLAN_TAG_USED
 900                 vtag = status & TT_MASK;
 901                 /*MAC will strip vlan tag*/
 902                 if(lp->vlgrp != NULL && vtag !=0)
 903                         min_pkt_len =MIN_PKT_LEN - 4;
 904                 else
 905 #endif
 906                         min_pkt_len =MIN_PKT_LEN;
 907
 908                 if (pkt_len < min_pkt_len) {
 909                         lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 910                         lp->drv_rx_errors++;
 911                         goto err_next_pkt;
 912                 }
 913                 if(!(new_skb = dev_alloc_skb(lp->rx_buff_len))){
 914                         /* if allocation fail,
 915                                 ignore that pkt and go to next one */
 916                         lp->rx_ring[rx_index].rx_flags &= RESET_RX_FLAGS;
 917                         lp->drv_rx_errors++;
 918                         goto err_next_pkt;
 919                 }
 920
 921                 skb_reserve(new_skb, 2);
 922                 skb = lp->rx_skbuff[rx_index];
 923                 pci_unmap_single(lp->pci_dev,lp->rx_dma_addr[rx_index],
 924                         lp->rx_buff_len-2, PCI_DMA_FROMDEVICE);
 925                 skb_put(skb, pkt_len);
 926                 skb->dev = dev;
 927                 lp->rx_skbuff[rx_index] = new_skb;
 928                 new_skb->dev = dev;
 929                 lp->rx_dma_addr[rx_index] = pci_map_single(lp->pci_dev,
 930                         new_skb->data, lp->rx_buff_len-2,PCI_DMA_FROMDEVICE);
 931
 932                 skb->protocol = eth_type_trans(skb, dev);
 933
 934 #if AMD8111E_VLAN_TAG_USED
 935                 if(lp->vlgrp != NULL && (vtag == TT_VLAN_TAGGED)){
 936                         amd8111e_vlan_rx(lp, skb,
 937                                  le16_to_cpu(lp->rx_ring[rx_index].tag_ctrl_info));
 938                 } else
 939 #endif
 940
 941                         netif_rx (skb);
 942                         /*COAL update rx coalescing parameters*/
 943                         lp->coal_conf.rx_packets++;
 944                         lp->coal_conf.rx_bytes += pkt_len;
 945
 946                         dev->last_rx = jiffies;
 947
 948 err_next_pkt:
 949                 lp->rx_ring[rx_index].buff_phy_addr
 950                          = cpu_to_le32(lp->rx_dma_addr[rx_index]);
 951                 lp->rx_ring[rx_index].buff_count =
 952                                 cpu_to_le16(lp->rx_buff_len-2);
 953                 wmb();
 954                 lp->rx_ring[rx_index].rx_flags |= cpu_to_le16(OWN_BIT);
 955                 rx_index = (++lp->rx_idx) & RX_RING_DR_MOD_MASK;
 956         }
 957
 958         return 0;
 959 }
 960 #endif /* CONFIG_AMD8111E_NAPI */
 961 /*
 962 This function will indicate the link status to the kernel.
 963 */
 964 static int amd8111e_link_change(struct net_device* dev)
 965 {
 966         struct amd8111e_priv *lp = netdev_priv(dev);
 967         int status0,speed;
 968
 969         /* read the link change */
 970         status0 = readl(lp->mmio + STAT0);
 971
 972         if(status0 & LINK_STATS){
 973                 if(status0 & AUTONEG_COMPLETE)
 974                         lp->link_config.autoneg = AUTONEG_ENABLE;
 975                 else
 976                         lp->link_config.autoneg = AUTONEG_DISABLE;
 977
 978                 if(status0 & FULL_DPLX)
 979                         lp->link_config.duplex = DUPLEX_FULL;
 980                 else
 981                         lp->link_config.duplex = DUPLEX_HALF;
 982                 speed = (status0 & SPEED_MASK) >> 7;
 983                 if(speed == PHY_SPEED_10)
 984                         lp->link_config.speed = SPEED_10;
 985                 else if(speed == PHY_SPEED_100)
 986                         lp->link_config.speed = SPEED_100;
 987
 988                 printk(KERN_INFO "%s: Link is Up. Speed is %s Mbps %s Duplex\n",                        dev->name,
 989                        (lp->link_config.speed == SPEED_100) ? "100": "10",
 990                        (lp->link_config.duplex == DUPLEX_FULL)? "Full": "Half");
 991                 netif_carrier_on(dev);
 992         }
 993         else{
 994                 lp->link_config.speed = SPEED_INVALID;
 995                 lp->link_config.duplex = DUPLEX_INVALID;
 996                 lp->link_config.autoneg = AUTONEG_INVALID;
 997                 printk(KERN_INFO "%s: Link is Down.\n",dev->name);
 998                 netif_carrier_off(dev);
 999         }
1000
1001         return 0;
1002 }
1003 /*
1004 This function reads the mib counters.
1005 */
1006 static int amd8111e_read_mib(void __iomem *mmio, u8 MIB_COUNTER)
1007 {
1008         unsigned int  status;
1009         unsigned  int data;
1010         unsigned int repeat = REPEAT_CNT;
1011
1012         writew( MIB_RD_CMD | MIB_COUNTER, mmio + MIB_ADDR);
1013         do {
1014                 status = readw(mmio + MIB_ADDR);
1015                 udelay(2);      /* controller takes MAX 2 us to get mib data */
1016         }
1017         while (--repeat && (status & MIB_CMD_ACTIVE));
1018
1019         data = readl(mmio + MIB_DATA);
1020         return data;
1021 }
1022
1023 /*
1024 This function reads the mib registers and returns the hardware statistics. It  updates previous internal driver statistics with new values.
1025 */
1026 static struct net_device_stats *amd8111e_get_stats(struct net_device * dev)
1027 {
1028         struct amd8111e_priv *lp = netdev_priv(dev);
1029         void __iomem *mmio = lp->mmio;
1030         unsigned long flags;
1031         /* struct net_device_stats *prev_stats = &lp->prev_stats; */
1032         struct net_device_stats* new_stats = &lp->stats;
1033
1034         if(!lp->opened)
1035                 return &lp->stats;
1036         spin_lock_irqsave (&lp->lock, flags);
1037
1038         /* stats.rx_packets */
1039         new_stats->rx_packets = amd8111e_read_mib(mmio, rcv_broadcast_pkts)+
1040                                 amd8111e_read_mib(mmio, rcv_multicast_pkts)+
1041                                 amd8111e_read_mib(mmio, rcv_unicast_pkts);
1042
1043         /* stats.tx_packets */
1044         new_stats->tx_packets = amd8111e_read_mib(mmio, xmt_packets);
1045
1046         /*stats.rx_bytes */
1047         new_stats->rx_bytes = amd8111e_read_mib(mmio, rcv_octets);
1048
1049         /* stats.tx_bytes */
1050         new_stats->tx_bytes = amd8111e_read_mib(mmio, xmt_octets);
1051
1052         /* stats.rx_errors */
1053         /* hw errors + errors driver reported */
1054         new_stats->rx_errors = amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1055                                 amd8111e_read_mib(mmio, rcv_fragments)+
1056                                 amd8111e_read_mib(mmio, rcv_jabbers)+
1057                                 amd8111e_read_mib(mmio, rcv_alignment_errors)+
1058                                 amd8111e_read_mib(mmio, rcv_fcs_errors)+
1059                                 amd8111e_read_mib(mmio, rcv_miss_pkts)+
1060                                 lp->drv_rx_errors;
1061
1062         /* stats.tx_errors */
1063         new_stats->tx_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1064
1065         /* stats.rx_dropped*/
1066         new_stats->rx_dropped = amd8111e_read_mib(mmio, rcv_miss_pkts);
1067
1068         /* stats.tx_dropped*/
1069         new_stats->tx_dropped = amd8111e_read_mib(mmio,  xmt_underrun_pkts);
1070
1071         /* stats.multicast*/
1072         new_stats->multicast = amd8111e_read_mib(mmio, rcv_multicast_pkts);
1073
1074         /* stats.collisions*/
1075         new_stats->collisions = amd8111e_read_mib(mmio, xmt_collisions);
1076
1077         /* stats.rx_length_errors*/
1078         new_stats->rx_length_errors =
1079                 amd8111e_read_mib(mmio, rcv_undersize_pkts)+
1080                 amd8111e_read_mib(mmio, rcv_oversize_pkts);
1081
1082         /* stats.rx_over_errors*/
1083         new_stats->rx_over_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1084
1085         /* stats.rx_crc_errors*/
1086         new_stats->rx_crc_errors = amd8111e_read_mib(mmio, rcv_fcs_errors);
1087
1088         /* stats.rx_frame_errors*/
1089         new_stats->rx_frame_errors =
1090                 amd8111e_read_mib(mmio, rcv_alignment_errors);
1091
1092         /* stats.rx_fifo_errors */
1093         new_stats->rx_fifo_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1094
1095         /* stats.rx_missed_errors */
1096         new_stats->rx_missed_errors = amd8111e_read_mib(mmio, rcv_miss_pkts);
1097
1098         /* stats.tx_aborted_errors*/
1099         new_stats->tx_aborted_errors =
1100                 amd8111e_read_mib(mmio, xmt_excessive_collision);
1101
1102         /* stats.tx_carrier_errors*/
1103         new_stats->tx_carrier_errors =
1104                 amd8111e_read_mib(mmio, xmt_loss_carrier);
1105
1106         /* stats.tx_fifo_errors*/
1107         new_stats->tx_fifo_errors = amd8111e_read_mib(mmio, xmt_underrun_pkts);
1108
1109         /* stats.tx_window_errors*/
1110         new_stats->tx_window_errors =
1111                 amd8111e_read_mib(mmio, xmt_late_collision);
1112
1113         /* Reset the mibs for collecting new statistics */
1114         /* writew(MIB_CLEAR, mmio + MIB_ADDR);*/
1115
1116         spin_unlock_irqrestore (&lp->lock, flags);
1117
1118         return new_stats;
1119 }
1120 /* This function recalculate the interupt coalescing  mode on every interrupt
1121 according to the datarate and the packet rate.
1122 */
1123 static int amd8111e_calc_coalesce(struct net_device *dev)
1124 {
1125         struct amd8111e_priv *lp = netdev_priv(dev);
1126         struct amd8111e_coalesce_conf * coal_conf = &lp->coal_conf;
1127         int tx_pkt_rate;
1128         int rx_pkt_rate;
1129         int tx_data_rate;
1130         int rx_data_rate;
1131         int rx_pkt_size;
1132         int tx_pkt_size;
1133
1134         tx_pkt_rate = coal_conf->tx_packets - coal_conf->tx_prev_packets;
1135         coal_conf->tx_prev_packets =  coal_conf->tx_packets;
1136
1137         tx_data_rate = coal_conf->tx_bytes - coal_conf->tx_prev_bytes;
1138         coal_conf->tx_prev_bytes =  coal_conf->tx_bytes;
1139
1140         rx_pkt_rate = coal_conf->rx_packets - coal_conf->rx_prev_packets;
1141         coal_conf->rx_prev_packets =  coal_conf->rx_packets;
1142
1143         rx_data_rate = coal_conf->rx_bytes - coal_conf->rx_prev_bytes;
1144         coal_conf->rx_prev_bytes =  coal_conf->rx_bytes;
1145
1146         if(rx_pkt_rate < 800){
1147                 if(coal_conf->rx_coal_type != NO_COALESCE){
1148
1149                         coal_conf->rx_timeout = 0x0;
1150                         coal_conf->rx_event_count = 0;
1151                         amd8111e_set_coalesce(dev,RX_INTR_COAL);
1152                         coal_conf->rx_coal_type = NO_COALESCE;
1153                 }
1154         }
1155         else{
1156
1157                 rx_pkt_size = rx_data_rate/rx_pkt_rate;
1158                 if (rx_pkt_size < 128){
1159                         if(coal_conf->rx_coal_type != NO_COALESCE){
1160
1161                                 coal_conf->rx_timeout = 0;
1162                                 coal_conf->rx_event_count = 0;
1163                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1164                                 coal_conf->rx_coal_type = NO_COALESCE;
1165                         }
1166
1167                 }
1168                 else if ( (rx_pkt_size >= 128) && (rx_pkt_size < 512) ){
1169
1170                         if(coal_conf->rx_coal_type !=  LOW_COALESCE){
1171                                 coal_conf->rx_timeout = 1;
1172                                 coal_conf->rx_event_count = 4;
1173                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1174                                 coal_conf->rx_coal_type = LOW_COALESCE;
1175                         }
1176                 }
1177                 else if ((rx_pkt_size >= 512) && (rx_pkt_size < 1024)){
1178
1179                         if(coal_conf->rx_coal_type !=  MEDIUM_COALESCE){
1180                                 coal_conf->rx_timeout = 1;
1181                                 coal_conf->rx_event_count = 4;
1182                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1183                                 coal_conf->rx_coal_type = MEDIUM_COALESCE;
1184                         }
1185
1186                 }
1187                 else if(rx_pkt_size >= 1024){
1188                         if(coal_conf->rx_coal_type !=  HIGH_COALESCE){
1189                                 coal_conf->rx_timeout = 2;
1190                                 coal_conf->rx_event_count = 3;
1191                                 amd8111e_set_coalesce(dev,RX_INTR_COAL);
1192                                 coal_conf->rx_coal_type = HIGH_COALESCE;
1193                         }
1194                 }
1195         }
1196         /* NOW FOR TX INTR COALESC */
1197         if(tx_pkt_rate < 800){
1198                 if(coal_conf->tx_coal_type != NO_COALESCE){
1199
1200                         coal_conf->tx_timeout = 0x0;
1201                         coal_conf->tx_event_count = 0;
1202                         amd8111e_set_coalesce(dev,TX_INTR_COAL);
1203                         coal_conf->tx_coal_type = NO_COALESCE;
1204                 }
1205         }
1206         else{
1207
1208                 tx_pkt_size = tx_data_rate/tx_pkt_rate;
1209                 if (tx_pkt_size < 128){
1210
1211                         if(coal_conf->tx_coal_type != NO_COALESCE){
1212
1213                                 coal_conf->tx_timeout = 0;
1214                                 coal_conf->tx_event_count = 0;
1215                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1216                                 coal_conf->tx_coal_type = NO_COALESCE;
1217                         }
1218
1219                 }
1220                 else if ( (tx_pkt_size >= 128) && (tx_pkt_size < 512) ){
1221
1222                         if(coal_conf->tx_coal_type !=  LOW_COALESCE){
1223                                 coal_conf->tx_timeout = 1;
1224                                 coal_conf->tx_event_count = 2;
1225                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1226                                 coal_conf->tx_coal_type = LOW_COALESCE;
1227
1228                         }
1229                 }
1230                 else if ((tx_pkt_size >= 512) && (tx_pkt_size < 1024)){
1231
1232                         if(coal_conf->tx_coal_type !=  MEDIUM_COALESCE){
1233                                 coal_conf->tx_timeout = 2;
1234                                 coal_conf->tx_event_count = 5;
1235                                 amd8111e_set_coalesce(dev,TX_INTR_COAL);
1236                                 coal_conf->tx_coal_type = MEDIUM_COALESCE;
1237                         }
1238
1239                 }
1240                 else if(tx_pkt_size >= 1024){
1241                         if (tx_pkt_size >= 1024){
1242                                 if(coal_conf->tx_coal_type !=  HIGH_COALESCE){
1243                                         coal_conf->tx_timeout = 4;
1244                                         coal_conf->tx_event_count = 8;
1245                                         amd8111e_set_coalesce(dev,TX_INTR_COAL);
1246                                         coal_conf->tx_coal_type = HIGH_COALESCE;
1247                                 }
1248                         }
1249                 }
1250         }
1251         return 0;
1252
1253 }
1254 /*
1255 This is device interrupt function. It handles transmit, receive,link change and hardware timer interrupts.
1256 */
1257 static irqreturn_t amd8111e_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1258 {
1259
1260         struct net_device * dev = (struct net_device *) dev_id;
1261         struct amd8111e_priv *lp = netdev_priv(dev);
1262         void __iomem *mmio = lp->mmio;
1263         unsigned int intr0;
1264         unsigned int handled = 1;
1265
1266         if(dev == NULL)
1267                 return IRQ_NONE;
1268
1269         if (regs) spin_lock (&lp->lock);
1270         /* disabling interrupt */
1271         writel(INTREN, mmio + CMD0);
1272
1273         /* Read interrupt status */
1274         intr0 = readl(mmio + INT0);
1275
1276         /* Process all the INT event until INTR bit is clear. */
1277
1278         if (!(intr0 & INTR)){
1279                 handled = 0;
1280                 goto err_no_interrupt;
1281         }
1282
1283         /* Current driver processes 4 interrupts : RINT,TINT,LCINT,STINT */
1284         writel(intr0, mmio + INT0);
1285
1286         /* Check if Receive Interrupt has occurred. */
1287 #if CONFIG_AMD8111E_NAPI
1288         if(intr0 & RINT0){
1289                 if(netif_rx_schedule_prep(dev)){
1290                         /* Disable receive interupts */
1291                         writel(RINTEN0, mmio + INTEN0);
1292                         /* Schedule a polling routine */
1293                         __netif_rx_schedule(dev);
1294                 }
1295                 else {
1296                         printk("************Driver bug! \
1297                                 interrupt while in poll\n");
1298                         /* Fix by disabling interrupts */
1299                         writel(RINT0, mmio + INT0);
1300                 }
1301         }
1302 #else
1303         if(intr0 & RINT0){
1304                 amd8111e_rx(dev);
1305                 writel(VAL2 | RDMD0, mmio + CMD0);
1306         }
1307 #endif /* CONFIG_AMD8111E_NAPI */
1308         /* Check if  Transmit Interrupt has occurred. */
1309         if(intr0 & TINT0)
1310                 amd8111e_tx(dev);
1311
1312         /* Check if  Link Change Interrupt has occurred. */
1313         if (intr0 & LCINT)
1314                 amd8111e_link_change(dev);
1315
1316         /* Check if Hardware Timer Interrupt has occurred. */
1317         if (intr0 & STINT)
1318                 amd8111e_calc_coalesce(dev);
1319
1320 err_no_interrupt:
1321         writel( VAL0 | INTREN,mmio + CMD0);
1322
1323         if (regs) spin_unlock(&lp->lock);
1324
1325         return IRQ_RETVAL(handled);
1326 }
1327
1328 #ifdef CONFIG_NET_POLL_CONTROLLER
1329 static void amd8111e_poll(struct net_device *dev)
1330 {
1331         unsigned long flags;
1332         local_save_flags(flags);
1333         local_irq_disable();
1334         amd8111e_interrupt(0, dev, NULL);
1335         local_irq_restore(flags);
1336 }
1337 #endif
1338
1339
1340 /*
1341 This function closes the network interface and updates the statistics so that most recent statistics will be available after the interface is down.
1342 */
1343 static int amd8111e_close(struct net_device * dev)
1344 {
1345         struct amd8111e_priv *lp = netdev_priv(dev);
1346         netif_stop_queue(dev);
1347
1348         spin_lock_irq(&lp->lock);
1349
1350         amd8111e_disable_interrupt(lp);
1351         amd8111e_stop_chip(lp);
1352         amd8111e_free_ring(lp);
1353
1354         netif_carrier_off(lp->amd8111e_net_dev);
1355
1356         /* Delete ipg timer */
1357         if(lp->options & OPTION_DYN_IPG_ENABLE)
1358                 del_timer_sync(&lp->ipg_data.ipg_timer);
1359
1360         spin_unlock_irq(&lp->lock);
1361         free_irq(dev->irq, dev);
1362
1363         /* Update the statistics before closing */
1364         amd8111e_get_stats(dev);
1365         lp->opened = 0;
1366         return 0;
1367 }
1368 /* This function opens new interface.It requests irq for the device, initializes the device,buffers and descriptors, and starts the device.
1369 */
1370 static int amd8111e_open(struct net_device * dev )
1371 {
1372         struct amd8111e_priv *lp = netdev_priv(dev);
1373
1374         if(dev->irq ==0 || request_irq(dev->irq, amd8111e_interrupt, SA_SHIRQ,
1375                                          dev->name, dev))
1376                 return -EAGAIN;
1377
1378         spin_lock_irq(&lp->lock);
1379
1380         amd8111e_init_hw_default(lp);
1381
1382         if(amd8111e_restart(dev)){
1383                 spin_unlock_irq(&lp->lock);
1384                 if (dev->irq)
1385                         free_irq(dev->irq, dev);
1386                 return -ENOMEM;
1387         }
1388         /* Start ipg timer */
1389         if(lp->options & OPTION_DYN_IPG_ENABLE){
1390                 add_timer(&lp->ipg_data.ipg_timer);
1391                 printk(KERN_INFO "%s: Dynamic IPG Enabled.\n",dev->name);
1392         }
1393
1394         lp->opened = 1;
1395
1396         spin_unlock_irq(&lp->lock);
1397
1398         netif_start_queue(dev);
1399
1400         return 0;
1401 }
1402 /*
1403 This function checks if there is any transmit  descriptors available to queue more packet.
1404 */
1405 static int amd8111e_tx_queue_avail(struct amd8111e_priv* lp )
1406 {
1407         int tx_index = lp->tx_idx & TX_BUFF_MOD_MASK;
1408         if(lp->tx_skbuff[tx_index] != 0)
1409                 return -1;
1410         else
1411                 return 0;
1412
1413 }
1414 /*
1415 This function will queue the transmit packets to the descriptors and will trigger the send operation. It also initializes the transmit descriptors with buffer physical address, byte count, ownership to hardware etc.
1416 */
1417
1418 static int amd8111e_start_xmit(struct sk_buff *skb, struct net_device * dev)
1419 {
1420         struct amd8111e_priv *lp = netdev_priv(dev);
1421         int tx_index;
1422         unsigned long flags;
1423
1424         spin_lock_irqsave(&lp->lock, flags);
1425
1426         tx_index = lp->tx_idx & TX_RING_DR_MOD_MASK;
1427
1428         lp->tx_ring[tx_index].buff_count = cpu_to_le16(skb->len);
1429
1430         lp->tx_skbuff[tx_index] = skb;
1431         lp->tx_ring[tx_index].tx_flags = 0;
1432
1433 #if AMD8111E_VLAN_TAG_USED
1434         if((lp->vlgrp != NULL) && vlan_tx_tag_present(skb)){
1435                 lp->tx_ring[tx_index].tag_ctrl_cmd |=
1436                                 cpu_to_le16(TCC_VLAN_INSERT);
1437                 lp->tx_ring[tx_index].tag_ctrl_info =
1438                                 cpu_to_le16(vlan_tx_tag_get(skb));
1439
1440         }
1441 #endif
1442         lp->tx_dma_addr[tx_index] =
1443             pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1444         lp->tx_ring[tx_index].buff_phy_addr =
1445             (u32) cpu_to_le32(lp->tx_dma_addr[tx_index]);
1446
1447         /*  Set FCS and LTINT bits */
1448         wmb();
1449         lp->tx_ring[tx_index].tx_flags |=
1450             cpu_to_le16(OWN_BIT | STP_BIT | ENP_BIT|ADD_FCS_BIT|LTINT_BIT);
1451
1452         lp->tx_idx++;
1453
1454         /* Trigger an immediate send poll. */
1455         writel( VAL1 | TDMD0, lp->mmio + CMD0);
1456         writel( VAL2 | RDMD0,lp->mmio + CMD0);
1457
1458         dev->trans_start = jiffies;
1459
1460         if(amd8111e_tx_queue_avail(lp) < 0){
1461                 netif_stop_queue(dev);
1462         }
1463         spin_unlock_irqrestore(&lp->lock, flags);
1464         return 0;
1465 }
1466 /*
1467 This function returns all the memory mapped registers of the device.
1468 */
1469 static void amd8111e_read_regs(struct amd8111e_priv *lp, u32 *buf)
1470 {
1471         void __iomem *mmio = lp->mmio;
1472         /* Read only necessary registers */
1473         buf[0] = readl(mmio + XMT_RING_BASE_ADDR0);
1474         buf[1] = readl(mmio + XMT_RING_LEN0);
1475         buf[2] = readl(mmio + RCV_RING_BASE_ADDR0);
1476         buf[3] = readl(mmio + RCV_RING_LEN0);
1477         buf[4] = readl(mmio + CMD0);
1478         buf[5] = readl(mmio + CMD2);
1479         buf[6] = readl(mmio + CMD3);
1480         buf[7] = readl(mmio + CMD7);
1481         buf[8] = readl(mmio + INT0);
1482         buf[9] = readl(mmio + INTEN0);
1483         buf[10] = readl(mmio + LADRF);
1484         buf[11] = readl(mmio + LADRF+4);
1485         buf[12] = readl(mmio + STAT0);
1486 }
1487
1488 /*
1489 amd8111e crc generator implementation is different from the kernel
1490 ether_crc() function.
1491 */
1492 int amd8111e_ether_crc(int len, char* mac_addr)
1493 {
1494         int i,byte;
1495         unsigned char octet;
1496         u32 crc= INITCRC;
1497
1498         for(byte=0; byte < len; byte++){
1499                 octet = mac_addr[byte];
1500                 for( i=0;i < 8; i++){
1501                         /*If the next bit form the input stream is 1,subtract                            the divisor (CRC32) from the dividend(crc).*/
1502                         if( (octet & 0x1) ^ (crc & 0x1) ){
1503                                 crc >>= 1;
1504                                 crc ^= CRC32;
1505                         }
1506                         else
1507                                 crc >>= 1;
1508
1509                         octet >>= 1;
1510                 }
1511         }
1512         return crc;
1513 }
1514 /*
1515 This function sets promiscuos mode, all-multi mode or the multicast address
1516 list to the device.
1517 */
1518 static void amd8111e_set_multicast_list(struct net_device *dev)
1519 {
1520         struct dev_mc_list* mc_ptr;
1521         struct amd8111e_priv *lp = netdev_priv(dev);
1522         u32 mc_filter[2] ;
1523         int i,bit_num;
1524         if(dev->flags & IFF_PROMISC){
1525                 printk(KERN_INFO "%s: Setting  promiscuous mode.\n",dev->name);
1526                 writel( VAL2 | PROM, lp->mmio + CMD2);
1527                 return;
1528         }
1529         else
1530                 writel( PROM, lp->mmio + CMD2);
1531         if(dev->flags & IFF_ALLMULTI || dev->mc_count > MAX_FILTER_SIZE){
1532                 /* get all multicast packet */
1533                 mc_filter[1] = mc_filter[0] = 0xffffffff;
1534                 lp->mc_list = dev->mc_list;
1535                 lp->options |= OPTION_MULTICAST_ENABLE;
1536                 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1537                 return;
1538         }
1539         if( dev->mc_count == 0 ){
1540                 /* get only own packets */
1541                 mc_filter[1] = mc_filter[0] = 0;
1542                 lp->mc_list = NULL;
1543                 lp->options &= ~OPTION_MULTICAST_ENABLE;
1544                 amd8111e_writeq(*(u64*)mc_filter,lp->mmio + LADRF);
1545                 /* disable promiscous mode */
1546                 writel(PROM, lp->mmio + CMD2);
1547                 return;
1548         }
1549         /* load all the multicast addresses in the logic filter */
1550         lp->options |= OPTION_MULTICAST_ENABLE;
1551         lp->mc_list = dev->mc_list;
1552         mc_filter[1] = mc_filter[0] = 0;
1553         for (i = 0, mc_ptr = dev->mc_list; mc_ptr && i < dev->mc_count;
1554                      i++, mc_ptr = mc_ptr->next) {
1555                 bit_num = ( amd8111e_ether_crc(ETH_ALEN,mc_ptr->dmi_addr)                                                        >> 26 ) & 0x3f;
1556                 mc_filter[bit_num >> 5] |= 1 << (bit_num & 31);
1557         }
1558         amd8111e_writeq(*(u64*)mc_filter,lp->mmio+ LADRF);
1559
1560         /* To eliminate PCI posting bug */
1561         readl(lp->mmio + CMD2);
1562
1563 }
1564
1565 static void amd8111e_get_drvinfo(struct net_device* dev, struct ethtool_drvinfo *info)
1566 {
1567         struct amd8111e_priv *lp = netdev_priv(dev);
1568         struct pci_dev *pci_dev = lp->pci_dev;
1569         strcpy (info->driver, MODULE_NAME);
1570         strcpy (info->version, MODULE_VERS);
1571         sprintf(info->fw_version,"%u",chip_version);
1572         strcpy (info->bus_info, pci_name(pci_dev));
1573 }
1574
1575 static int amd8111e_get_regs_len(struct net_device *dev)
1576 {
1577         return AMD8111E_REG_DUMP_LEN;
1578 }
1579
1580 static void amd8111e_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
1581 {
1582         struct amd8111e_priv *lp = netdev_priv(dev);
1583         regs->version = 0;
1584         amd8111e_read_regs(lp, buf);
1585 }
1586
1587 static int amd8111e_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1588 {
1589         struct amd8111e_priv *lp = netdev_priv(dev);
1590         spin_lock_irq(&lp->lock);
1591         mii_ethtool_gset(&lp->mii_if, ecmd);
1592         spin_unlock_irq(&lp->lock);
1593         return 0;
1594 }
1595
1596 static int amd8111e_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1597 {
1598         struct amd8111e_priv *lp = netdev_priv(dev);
1599         int res;
1600         spin_lock_irq(&lp->lock);
1601         res = mii_ethtool_sset(&lp->mii_if, ecmd);
1602         spin_unlock_irq(&lp->lock);
1603         return res;
1604 }
1605
1606 static int amd8111e_nway_reset(struct net_device *dev)
1607 {
1608         struct amd8111e_priv *lp = netdev_priv(dev);
1609         return mii_nway_restart(&lp->mii_if);
1610 }
1611
1612 static u32 amd8111e_get_link(struct net_device *dev)
1613 {
1614         struct amd8111e_priv *lp = netdev_priv(dev);
1615         return mii_link_ok(&lp->mii_if);
1616 }
1617
1618 static void amd8111e_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1619 {
1620         struct amd8111e_priv *lp = netdev_priv(dev);
1621         wol_info->supported = WAKE_MAGIC|WAKE_PHY;
1622         if (lp->options & OPTION_WOL_ENABLE)
1623                 wol_info->wolopts = WAKE_MAGIC;
1624 }
1625
1626 static int amd8111e_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol_info)
1627 {
1628         struct amd8111e_priv *lp = netdev_priv(dev);
1629         if (wol_info->wolopts & ~(WAKE_MAGIC|WAKE_PHY))
1630                 return -EINVAL;
1631         spin_lock_irq(&lp->lock);
1632         if (wol_info->wolopts & WAKE_MAGIC)
1633                 lp->options |=
1634                         (OPTION_WOL_ENABLE | OPTION_WAKE_MAGIC_ENABLE);
1635         else if(wol_info->wolopts & WAKE_PHY)
1636                 lp->options |=
1637                         (OPTION_WOL_ENABLE | OPTION_WAKE_PHY_ENABLE);
1638         else
1639                 lp->options &= ~OPTION_WOL_ENABLE;
1640         spin_unlock_irq(&lp->lock);
1641         return 0;
1642 }
1643
1644 static struct ethtool_ops ops = {
1645         .get_drvinfo = amd8111e_get_drvinfo,
1646         .get_regs_len = amd8111e_get_regs_len,
1647         .get_regs = amd8111e_get_regs,
1648         .get_settings = amd8111e_get_settings,
1649         .set_settings = amd8111e_set_settings,
1650         .nway_reset = amd8111e_nway_reset,
1651         .get_link = amd8111e_get_link,
1652         .get_wol = amd8111e_get_wol,
1653         .set_wol = amd8111e_set_wol,
1654 };
1655
1656 /*
1657 This function handles all the  ethtool ioctls. It gives driver info, gets/sets driver speed, gets memory mapped register values, forces auto negotiation, sets/gets WOL options for ethtool application.
1658 */
1659
1660 static int amd8111e_ioctl(struct net_device * dev , struct ifreq *ifr, int cmd)
1661 {
1662         struct mii_ioctl_data *data = if_mii(ifr);
1663         struct amd8111e_priv *lp = netdev_priv(dev);
1664         int err;
1665         u32 mii_regval;
1666
1667         if (!capable(CAP_NET_ADMIN))
1668                 return -EPERM;
1669
1670         switch(cmd) {
1671         case SIOCGMIIPHY:
1672                 data->phy_id = lp->ext_phy_addr;
1673
1674         /* fallthru */
1675         case SIOCGMIIREG:
1676
1677                 spin_lock_irq(&lp->lock);
1678                 err = amd8111e_read_phy(lp, data->phy_id,
1679                         data->reg_num & PHY_REG_ADDR_MASK, &mii_regval);
1680                 spin_unlock_irq(&lp->lock);
1681
1682                 data->val_out = mii_regval;
1683                 return err;
1684
1685         case SIOCSMIIREG:
1686
1687                 spin_lock_irq(&lp->lock);
1688                 err = amd8111e_write_phy(lp, data->phy_id,
1689                         data->reg_num & PHY_REG_ADDR_MASK, data->val_in);
1690                 spin_unlock_irq(&lp->lock);
1691
1692                 return err;
1693
1694         default:
1695                 /* do nothing */
1696                 break;
1697         }
1698         return -EOPNOTSUPP;
1699 }
1700 static int amd8111e_set_mac_address(struct net_device *dev, void *p)
1701 {
1702         struct amd8111e_priv *lp = netdev_priv(dev);
1703         int i;
1704         struct sockaddr *addr = p;
1705
1706         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1707         spin_lock_irq(&lp->lock);
1708         /* Setting the MAC address to the device */
1709         for(i = 0; i < ETH_ADDR_LEN; i++)
1710                 writeb( dev->dev_addr[i], lp->mmio + PADR + i );
1711
1712         spin_unlock_irq(&lp->lock);
1713
1714         return 0;
1715 }
1716
1717 /*
1718 This function changes the mtu of the device. It restarts the device  to initialize the descriptor with new receive buffers.
1719 */
1720 int amd8111e_change_mtu(struct net_device *dev, int new_mtu)
1721 {
1722         struct amd8111e_priv *lp = netdev_priv(dev);
1723         int err;
1724
1725         if ((new_mtu < AMD8111E_MIN_MTU) || (new_mtu > AMD8111E_MAX_MTU))
1726                 return -EINVAL;
1727
1728         if (!netif_running(dev)) {
1729                 /* new_mtu will be used
1730                    when device starts netxt time */
1731                 dev->mtu = new_mtu;
1732                 return 0;
1733         }
1734
1735         spin_lock_irq(&lp->lock);
1736
1737         /* stop the chip */
1738         writel(RUN, lp->mmio + CMD0);
1739
1740         dev->mtu = new_mtu;
1741
1742         err = amd8111e_restart(dev);
1743         spin_unlock_irq(&lp->lock);
1744         if(!err)
1745                 netif_start_queue(dev);
1746         return err;
1747 }
1748
1749 #if AMD8111E_VLAN_TAG_USED
1750 static void amd8111e_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1751 {
1752         struct  amd8111e_priv *lp = netdev_priv(dev);
1753         spin_lock_irq(&lp->lock);
1754         lp->vlgrp = grp;
1755         spin_unlock_irq(&lp->lock);
1756 }
1757
1758 static void amd8111e_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1759 {
1760         struct amd8111e_priv *lp = netdev_priv(dev);
1761         spin_lock_irq(&lp->lock);
1762         if (lp->vlgrp)
1763                 lp->vlgrp->vlan_devices[vid] = NULL;
1764         spin_unlock_irq(&lp->lock);
1765 }
1766 #endif
1767 static int amd8111e_enable_magicpkt(struct amd8111e_priv* lp)
1768 {
1769         writel( VAL1|MPPLBA, lp->mmio + CMD3);
1770         writel( VAL0|MPEN_SW, lp->mmio + CMD7);
1771
1772         /* To eliminate PCI posting bug */
1773         readl(lp->mmio + CMD7);
1774         return 0;
1775 }
1776
1777 static int amd8111e_enable_link_change(struct amd8111e_priv* lp)
1778 {
1779
1780         /* Adapter is already stoped/suspended/interrupt-disabled */
1781         writel(VAL0|LCMODE_SW,lp->mmio + CMD7);
1782
1783         /* To eliminate PCI posting bug */
1784         readl(lp->mmio + CMD7);
1785         return 0;
1786 }
1787 /* This function is called when a packet transmission fails to complete within a  resonable period, on the assumption that an interrupts have been failed or the  interface is locked up. This function will reinitialize the hardware */
1788
1789 static void amd8111e_tx_timeout(struct net_device *dev)
1790 {
1791         struct amd8111e_priv* lp = netdev_priv(dev);
1792         int err;
1793
1794         printk(KERN_ERR "%s: transmit timed out, resetting\n",
1795                                                       dev->name);
1796         spin_lock_irq(&lp->lock);
1797         err = amd8111e_restart(dev);
1798         spin_unlock_irq(&lp->lock);
1799         if(!err)
1800                 netif_wake_queue(dev);
1801 }
1802 static int amd8111e_suspend(struct pci_dev *pci_dev, u32 state)
1803 {
1804         struct net_device *dev = pci_get_drvdata(pci_dev);
1805         struct amd8111e_priv *lp = netdev_priv(dev);
1806
1807         if (!netif_running(dev))
1808                 return 0;
1809
1810         /* disable the interrupt */
1811         spin_lock_irq(&lp->lock);
1812         amd8111e_disable_interrupt(lp);
1813         spin_unlock_irq(&lp->lock);
1814
1815         netif_device_detach(dev);
1816
1817         /* stop chip */
1818         spin_lock_irq(&lp->lock);
1819         if(lp->options & OPTION_DYN_IPG_ENABLE)
1820                 del_timer_sync(&lp->ipg_data.ipg_timer);
1821         amd8111e_stop_chip(lp);
1822         spin_unlock_irq(&lp->lock);
1823
1824         if(lp->options & OPTION_WOL_ENABLE){
1825                  /* enable wol */
1826                 if(lp->options & OPTION_WAKE_MAGIC_ENABLE)
1827                         amd8111e_enable_magicpkt(lp);
1828                 if(lp->options & OPTION_WAKE_PHY_ENABLE)
1829                         amd8111e_enable_link_change(lp);
1830
1831                 pci_enable_wake(pci_dev, PCI_D3hot, 1);
1832                 pci_enable_wake(pci_dev, PCI_D3cold, 1);
1833
1834         }
1835         else{
1836                 pci_enable_wake(pci_dev, PCI_D3hot, 0);
1837                 pci_enable_wake(pci_dev, PCI_D3cold, 0);
1838         }
1839
1840         pci_save_state(pci_dev);
1841         pci_set_power_state(pci_dev, PCI_D3hot);
1842
1843         return 0;
1844 }
1845 static int amd8111e_resume(struct pci_dev *pci_dev)
1846 {
1847         struct net_device *dev = pci_get_drvdata(pci_dev);
1848         struct amd8111e_priv *lp = netdev_priv(dev);
1849
1850         if (!netif_running(dev))
1851                 return 0;
1852
1853         pci_set_power_state(pci_dev, PCI_D0);
1854         pci_restore_state(pci_dev);
1855
1856         pci_enable_wake(pci_dev, PCI_D3hot, 0);
1857         pci_enable_wake(pci_dev, PCI_D3cold, 0); /* D3 cold */
1858
1859         netif_device_attach(dev);
1860
1861         spin_lock_irq(&lp->lock);
1862         amd8111e_restart(dev);
1863         /* Restart ipg timer */
1864         if(lp->options & OPTION_DYN_IPG_ENABLE)
1865                 mod_timer(&lp->ipg_data.ipg_timer,
1866                                 jiffies + IPG_CONVERGE_JIFFIES);
1867         spin_unlock_irq(&lp->lock);
1868
1869         return 0;
1870 }
1871
1872
1873 static void __devexit amd8111e_remove_one(struct pci_dev *pdev)
1874 {
1875         struct net_device *dev = pci_get_drvdata(pdev);
1876         if (dev) {
1877                 unregister_netdev(dev);
1878                 iounmap(((struct amd8111e_priv *)netdev_priv(dev))->mmio);
1879                 free_netdev(dev);
1880                 pci_release_regions(pdev);
1881                 pci_disable_device(pdev);
1882                 pci_set_drvdata(pdev, NULL);
1883         }
1884 }
1885 static void amd8111e_config_ipg(struct net_device* dev)
1886 {
1887         struct amd8111e_priv *lp = netdev_priv(dev);
1888         struct ipg_info* ipg_data = &lp->ipg_data;
1889         void __iomem *mmio = lp->mmio;
1890         unsigned int prev_col_cnt = ipg_data->col_cnt;
1891         unsigned int total_col_cnt;
1892         unsigned int tmp_ipg;
1893
1894         if(lp->link_config.duplex == DUPLEX_FULL){
1895                 ipg_data->ipg = DEFAULT_IPG;
1896                 return;
1897         }
1898
1899         if(ipg_data->ipg_state == SSTATE){
1900
1901                 if(ipg_data->timer_tick == IPG_STABLE_TIME){
1902
1903                         ipg_data->timer_tick = 0;
1904                         ipg_data->ipg = MIN_IPG - IPG_STEP;
1905                         ipg_data->current_ipg = MIN_IPG;
1906                         ipg_data->diff_col_cnt = 0xFFFFFFFF;
1907                         ipg_data->ipg_state = CSTATE;
1908                 }
1909                 else
1910                         ipg_data->timer_tick++;
1911         }
1912
1913         if(ipg_data->ipg_state == CSTATE){
1914
1915                 /* Get the current collision count */
1916
1917                 total_col_cnt = ipg_data->col_cnt =
1918                                 amd8111e_read_mib(mmio, xmt_collisions);
1919
1920                 if ((total_col_cnt - prev_col_cnt) <
1921                                 (ipg_data->diff_col_cnt)){
1922
1923                         ipg_data->diff_col_cnt =
1924                                 total_col_cnt - prev_col_cnt ;
1925
1926                         ipg_data->ipg = ipg_data->current_ipg;
1927                 }
1928
1929                 ipg_data->current_ipg += IPG_STEP;
1930
1931                 if (ipg_data->current_ipg <= MAX_IPG)
1932                         tmp_ipg = ipg_data->current_ipg;
1933                 else{
1934                         tmp_ipg = ipg_data->ipg;
1935                         ipg_data->ipg_state = SSTATE;
1936                 }
1937                 writew((u32)tmp_ipg, mmio + IPG);
1938                 writew((u32)(tmp_ipg - IFS1_DELTA), mmio + IFS1);
1939         }
1940          mod_timer(&lp->ipg_data.ipg_timer, jiffies + IPG_CONVERGE_JIFFIES);
1941         return;
1942
1943 }
1944
1945 static void __devinit amd8111e_probe_ext_phy(struct net_device* dev)
1946 {
1947         struct amd8111e_priv *lp = netdev_priv(dev);
1948         int i;
1949
1950         for (i = 0x1e; i >= 0; i--) {
1951                 u32 id1, id2;
1952
1953                 if (amd8111e_read_phy(lp, i, MII_PHYSID1, &id1))
1954                         continue;
1955                 if (amd8111e_read_phy(lp, i, MII_PHYSID2, &id2))
1956                         continue;
1957                 lp->ext_phy_id = (id1 << 16) | id2;
1958                 lp->ext_phy_addr = i;
1959                 return;
1960         }
1961         lp->ext_phy_id = 0;
1962         lp->ext_phy_addr = 1;
1963 }
1964
1965 static int __devinit amd8111e_probe_one(struct pci_dev *pdev,
1966                                   const struct pci_device_id *ent)
1967 {
1968         int err,i,pm_cap;
1969         unsigned long reg_addr,reg_len;
1970         struct amd8111e_priv* lp;
1971         struct net_device* dev;
1972
1973         err = pci_enable_device(pdev);
1974         if(err){
1975                 printk(KERN_ERR "amd8111e: Cannot enable new PCI device,"
1976                         "exiting.\n");
1977                 return err;
1978         }
1979
1980         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)){
1981                 printk(KERN_ERR "amd8111e: Cannot find PCI base address"
1982                        "exiting.\n");
1983                 err = -ENODEV;
1984                 goto err_disable_pdev;
1985         }
1986
1987         err = pci_request_regions(pdev, MODULE_NAME);
1988         if(err){
1989                 printk(KERN_ERR "amd8111e: Cannot obtain PCI resources, "
1990                        "exiting.\n");
1991                 goto err_disable_pdev;
1992         }
1993
1994         pci_set_master(pdev);
1995
1996         /* Find power-management capability. */
1997         if((pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM))==0){
1998                 printk(KERN_ERR "amd8111e: No Power Management capability, "
1999                        "exiting.\n");
2000                 goto err_free_reg;
2001         }
2002
2003         /* Initialize DMA */
2004         if(!pci_dma_supported(pdev, 0xffffffff)){
2005                 printk(KERN_ERR "amd8111e: DMA not supported,"
2006                         "exiting.\n");
2007                 goto  err_free_reg;
2008         } else
2009                 pdev->dma_mask = 0xffffffff;
2010
2011         reg_addr = pci_resource_start(pdev, 0);
2012         reg_len = pci_resource_len(pdev, 0);
2013
2014         dev = alloc_etherdev(sizeof(struct amd8111e_priv));
2015         if (!dev) {
2016                 printk(KERN_ERR "amd8111e: Etherdev alloc failed, exiting.\n");
2017                 err = -ENOMEM;
2018                 goto err_free_reg;
2019         }
2020
2021         SET_MODULE_OWNER(dev);
2022         SET_NETDEV_DEV(dev, &pdev->dev);
2023
2024 #if AMD8111E_VLAN_TAG_USED
2025         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX ;
2026         dev->vlan_rx_register =amd8111e_vlan_rx_register;
2027         dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
2028 #endif
2029
2030         lp = netdev_priv(dev);
2031         lp->pci_dev = pdev;
2032         lp->amd8111e_net_dev = dev;
2033         lp->pm_cap = pm_cap;
2034
2035         spin_lock_init(&lp->lock);
2036
2037         lp->mmio = ioremap(reg_addr, reg_len);
2038         if (lp->mmio == 0) {
2039                 printk(KERN_ERR "amd8111e: Cannot map device registers, "
2040                        "exiting\n");
2041                 err = -ENOMEM;
2042                 goto err_free_dev;
2043         }
2044
2045         /* Initializing MAC address */
2046         for(i = 0; i < ETH_ADDR_LEN; i++)
2047                         dev->dev_addr[i] =readb(lp->mmio + PADR + i);
2048
2049         /* Setting user defined parametrs */
2050         lp->ext_phy_option = speed_duplex[card_idx];
2051         if(coalesce[card_idx])
2052                 lp->options |= OPTION_INTR_COAL_ENABLE;
2053         if(dynamic_ipg[card_idx++])
2054                 lp->options |= OPTION_DYN_IPG_ENABLE;
2055
2056         /* Initialize driver entry points */
2057         dev->open = amd8111e_open;
2058         dev->hard_start_xmit = amd8111e_start_xmit;
2059         dev->stop = amd8111e_close;
2060         dev->get_stats = amd8111e_get_stats;
2061         dev->set_multicast_list = amd8111e_set_multicast_list;
2062         dev->set_mac_address = amd8111e_set_mac_address;
2063         dev->do_ioctl = amd8111e_ioctl;
2064         dev->change_mtu = amd8111e_change_mtu;
2065         SET_ETHTOOL_OPS(dev, &ops);
2066         dev->irq =pdev->irq;
2067         dev->tx_timeout = amd8111e_tx_timeout;
2068         dev->watchdog_timeo = AMD8111E_TX_TIMEOUT;
2069 #ifdef CONFIG_AMD8111E_NAPI
2070         dev->poll = amd8111e_rx_poll;
2071         dev->weight = 32;
2072 #endif
2073 #ifdef CONFIG_NET_POLL_CONTROLLER
2074         dev->poll_controller = amd8111e_poll;
2075 #endif
2076
2077 #if AMD8111E_VLAN_TAG_USED
2078         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2079         dev->vlan_rx_register =amd8111e_vlan_rx_register;
2080         dev->vlan_rx_kill_vid = amd8111e_vlan_rx_kill_vid;
2081 #endif
2082         /* Probe the external PHY */
2083         amd8111e_probe_ext_phy(dev);
2084
2085         /* setting mii default values */
2086         lp->mii_if.dev = dev;
2087         lp->mii_if.mdio_read = amd8111e_mdio_read;
2088         lp->mii_if.mdio_write = amd8111e_mdio_write;
2089         lp->mii_if.phy_id = lp->ext_phy_addr;
2090
2091         /* Set receive buffer length and set jumbo option*/
2092         amd8111e_set_rx_buff_len(dev);
2093
2094
2095         err = register_netdev(dev);
2096         if (err) {
2097                 printk(KERN_ERR "amd8111e: Cannot register net device, "
2098                        "exiting.\n");
2099                 goto err_iounmap;
2100         }
2101
2102         pci_set_drvdata(pdev, dev);
2103
2104         /* Initialize software ipg timer */
2105         if(lp->options & OPTION_DYN_IPG_ENABLE){
2106                 init_timer(&lp->ipg_data.ipg_timer);
2107                 lp->ipg_data.ipg_timer.data = (unsigned long) dev;
2108                 lp->ipg_data.ipg_timer.function = (void *)&amd8111e_config_ipg;
2109                 lp->ipg_data.ipg_timer.expires = jiffies +
2110                                                  IPG_CONVERGE_JIFFIES;
2111                 lp->ipg_data.ipg = DEFAULT_IPG;
2112                 lp->ipg_data.ipg_state = CSTATE;
2113         };
2114
2115         /*  display driver and device information */
2116
2117         chip_version = (readl(lp->mmio + CHIPID) & 0xf0000000)>>28;
2118         printk(KERN_INFO "%s: AMD-8111e Driver Version: %s\n",                                                           dev->name,MODULE_VERS);
2119         printk(KERN_INFO "%s: [ Rev %x ] PCI 10/100BaseT Ethernet ",                                                    dev->name, chip_version);
2120         for (i = 0; i < 6; i++)
2121                 printk("%2.2x%c",dev->dev_addr[i],i == 5 ? ' ' : ':');
2122         printk( "\n");
2123         if (lp->ext_phy_id)
2124                 printk(KERN_INFO "%s: Found MII PHY ID 0x%08x at address 0x%02x\n",
2125                        dev->name, lp->ext_phy_id, lp->ext_phy_addr);
2126         else
2127                 printk(KERN_INFO "%s: Couldn't detect MII PHY, assuming address 0x01\n",
2128                        dev->name);
2129         return 0;
2130 err_iounmap:
2131         iounmap(lp->mmio);
2132
2133 err_free_dev:
2134         free_netdev(dev);
2135
2136 err_free_reg:
2137         pci_release_regions(pdev);
2138
2139 err_disable_pdev:
2140         pci_disable_device(pdev);
2141         pci_set_drvdata(pdev, NULL);
2142         return err;
2143
2144 }
2145
2146 static struct pci_driver amd8111e_driver = {
2147         .name           = MODULE_NAME,
2148         .id_table       = amd8111e_pci_tbl,
2149         .probe          = amd8111e_probe_one,
2150         .remove         = __devexit_p(amd8111e_remove_one),
2151         .suspend        = amd8111e_suspend,
2152         .resume         = amd8111e_resume
2153 };
2154
2155 static int __init amd8111e_init(void)
2156 {
2157         return pci_module_init(&amd8111e_driver);
2158 }
2159
2160 static void __exit amd8111e_cleanup(void)
2161 {
2162         pci_unregister_driver(&amd8111e_driver);
2163 }
2164
2165 module_init(amd8111e_init);
2166 module_exit(amd8111e_cleanup);