drivers/net/arm/ether00.c

   1 /*
   2  *  drivers/net/ether00.c
   3  *
   4  *  Copyright (C) 2001 Altera Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* includes */
  22 #include <linux/config.h>
  23 #include <linux/pci.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/sched.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/module.h>
  30 #include <linux/tqueue.h>
  31 #include <linux/mtd/mtd.h>
  32 #include <linux/pld/pld_hotswap.h>
  33 #include <asm/arch/excalibur.h>
  34 #include <asm/arch/hardware.h>
  35 #include <asm/irq.h>
  36 #include <asm/io.h>
  37 #include <asm/sizes.h>
  38
  39 #include <asm/arch/ether00.h>
  40 #include <asm/arch/tdkphy.h>
  41
  42
  43 MODULE_AUTHOR("Clive Davies");
  44 MODULE_DESCRIPTION("Altera Ether00 IP core driver");
  45 MODULE_LICENSE("GPL");
  46
  47 #define PKT_BUF_SZ 1540 /* Size of each rx buffer */
  48 #define ETH_NR 4 /* Number of MACs this driver supports */
  49
  50 #define DEBUG(x)
  51
  52 #define __dma_va(x) (unsigned int)((unsigned int)priv->dma_data+(((unsigned int)(x))&(EXC_SPSRAM_BLOCK0_SIZE-1)))
  53 #define __dma_pa(x) (unsigned int)(EXC_SPSRAM_BLOCK0_BASE+(((unsigned int)(x))-(unsigned int)priv->dma_data))
  54
  55 #define ETHER00_BASE    0
  56 #define ETHER00_TYPE
  57 #define ETHER00_NAME "ether00"
  58 #define MAC_REG_SIZE 0x400 /* size of MAC register area */
  59
  60
  61
  62 /* typedefs */
  63
  64 /* The definition of the driver control structure */
  65
  66 #define RX_NUM_BUFF     10
  67 #define RX_NUM_FDESC    10
  68 #define TX_NUM_FDESC    10
  69
  70 struct tx_fda_ent{
  71         FDA_DESC  fd;
  72         BUF_DESC  bd;
  73         BUF_DESC  pad;
  74 };
  75 struct rx_fda_ent{
  76         FDA_DESC  fd;
  77         BUF_DESC  bd;
  78         BUF_DESC  pad;
  79 };
  80 struct rx_blist_ent{
  81         FDA_DESC  fd;
  82         BUF_DESC  bd;
  83         BUF_DESC  pad;
  84 };
  85 struct net_priv
  86 {
  87         struct net_device_stats stats;
  88         struct sk_buff* skb;
  89         void* dma_data;
  90         struct rx_blist_ent*  rx_blist_vp;
  91         struct rx_fda_ent* rx_fda_ptr;
  92         struct tx_fda_ent* tx_fdalist_vp;
  93         struct tq_struct  tq_memupdate;
  94         unsigned char   memupdate_scheduled;
  95         unsigned char   rx_disabled;
  96         unsigned char   queue_stopped;
  97         spinlock_t rx_lock;
  98 };
  99
 100 static const char vendor_id[2]={0x07,0xed};
 101
 102 #ifdef ETHER00_DEBUG
 103
 104 /* Dump (most) registers for debugging puposes */
 105
 106 static void dump_regs(struct net_device *dev){
 107         struct net_priv* priv=dev->priv;
 108         unsigned int* i;
 109
 110         printk("\n RX free descriptor area:\n");
 111
 112         for(i=(unsigned int*)priv->rx_fda_ptr;
 113             i<((unsigned int*)(priv->rx_fda_ptr+RX_NUM_FDESC));){
 114                 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
 115                 i+=4;
 116         }
 117
 118         printk("\n RX buffer list:\n");
 119
 120         for(i=(unsigned int*)priv->rx_blist_vp;
 121             i<((unsigned int*)(priv->rx_blist_vp+RX_NUM_BUFF));){
 122                 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
 123                 i+=4;
 124         }
 125
 126         printk("\n TX frame descriptor list:\n");
 127
 128         for(i=(unsigned int*)priv->tx_fdalist_vp;
 129             i<((unsigned int*)(priv->tx_fdalist_vp+TX_NUM_FDESC));){
 130                 printk("%#8x %#8x %#8x %#8x\n",*i,*(i+1),*(i+2),*(i+3));
 131                 i+=4;
 132         }
 133
 134         printk("\ndma ctl=%#x\n",readw(ETHER_DMA_CTL(dev->base_addr)));
 135         printk("txfrmptr=%#x\n",readw(ETHER_TXFRMPTR(dev->base_addr)));
 136         printk("txthrsh=%#x\n",readw(ETHER_TXTHRSH(dev->base_addr)));
 137         printk("txpollctr=%#x\n",readw(ETHER_TXPOLLCTR(dev->base_addr)));
 138         printk("blfrmptr=%#x\n",readw(ETHER_BLFRMPTR(dev->base_addr)));
 139         printk("rxfragsize=%#x\n",readw(ETHER_RXFRAGSIZE(dev->base_addr)));
 140         printk("tx_int_en=%#x\n",readw(ETHER_INT_EN(dev->base_addr)));
 141         printk("fda_bas=%#x\n",readw(ETHER_FDA_BAS(dev->base_addr)));
 142         printk("fda_lim=%#x\n",readw(ETHER_FDA_LIM(dev->base_addr)));
 143         printk("int_src=%#x\n",readw(ETHER_INT_SRC(dev->base_addr)));
 144         printk("pausecnt=%#x\n",readw(ETHER_PAUSECNT(dev->base_addr)));
 145         printk("rempaucnt=%#x\n",readw(ETHER_REMPAUCNT(dev->base_addr)));
 146         printk("txconfrmstat=%#x\n",readw(ETHER_TXCONFRMSTAT(dev->base_addr)));
 147         printk("mac_ctl=%#x\n",readw(ETHER_MAC_CTL(dev->base_addr)));
 148         printk("arc_ctl=%#x\n",readw(ETHER_ARC_CTL(dev->base_addr)));
 149         printk("tx_ctl=%#x\n",readw(ETHER_TX_CTL(dev->base_addr)));
 150 }
 151 #endif /* ETHER00_DEBUG */
 152
 153
 154 static int ether00_write_phy(struct net_device *dev, short address, short value)
 155 {
 156         volatile int count = 1024;
 157         writew(value,ETHER_MD_DATA(dev->base_addr));
 158         writew( ETHER_MD_CA_BUSY_MSK |
 159                 ETHER_MD_CA_WR_MSK |
 160                 (address & ETHER_MD_CA_ADDR_MSK),
 161                 ETHER_MD_CA(dev->base_addr));
 162
 163         /* Wait for the command to complete */
 164         while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
 165                 count--;
 166         }
 167         if (!count){
 168                 printk("Write to phy failed, addr=%#x, data=%#x\n",address, value);
 169                 return -EIO;
 170         }
 171         return 0;
 172 }
 173
 174 static int ether00_read_phy(struct net_device *dev, short address)
 175 {
 176         volatile int count = 1024;
 177         writew( ETHER_MD_CA_BUSY_MSK |
 178                 (address & ETHER_MD_CA_ADDR_MSK),
 179                 ETHER_MD_CA(dev->base_addr));
 180
 181         /* Wait for the command to complete */
 182         while((readw(ETHER_MD_CA(dev->base_addr)) & ETHER_MD_CA_BUSY_MSK)&&count){
 183                 count--;
 184         }
 185         if (!count){
 186                 printk(KERN_WARNING "Read from phy timed out\n");
 187                 return -EIO;
 188         }
 189         return readw(ETHER_MD_DATA(dev->base_addr));
 190 }
 191
 192 static void ether00_phy_int(int irq_num, void* dev_id, struct pt_regs* regs)
 193 {
 194         struct net_device* dev=dev_id;
 195         int irq_status;
 196
 197         irq_status=ether00_read_phy(dev, PHY_IRQ_CONTROL);
 198
 199         if(irq_status & PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK){
 200                 /*
 201                  * Autonegotiation complete on epxa10db. The mac doesn't
 202                  * twig if we're in full duplex so we need to check the
 203                  * phy status register and configure the mac accordingly
 204                  */
 205                 if(ether00_read_phy(dev, PHY_STATUS)&(PHY_STATUS_10T_F_MSK|PHY_STATUS_100_X_F_MSK)){
 206                         int tmp;
 207                         tmp=readl(ETHER_MAC_CTL(dev->base_addr));
 208                         writel(tmp|ETHER_MAC_CTL_FULLDUP_MSK,ETHER_MAC_CTL(dev->base_addr));
 209                 }
 210         }
 211
 212         if(irq_status&PHY_IRQ_CONTROL_LS_CHG_INT_MSK){
 213
 214                 if(ether00_read_phy(dev, PHY_STATUS)& PHY_STATUS_LINK_MSK){
 215                         /* Link is up */
 216                         netif_carrier_on(dev);
 217                         //printk("Carrier on\n");
 218                 }else{
 219                         netif_carrier_off(dev);
 220                         //printk("Carrier off\n");
 221
 222                 }
 223         }
 224
 225 }
 226
 227 static void setup_blist_entry(struct sk_buff* skb,struct rx_blist_ent* blist_ent_ptr){
 228         /* Make the buffer consistent with the cache as the mac is going to write
 229          * directly into it*/
 230         blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
 231         blist_ent_ptr->bd.BuffData=(char*)__pa(skb->data);
 232         consistent_sync(skb->data,PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 233         /* align IP on 16 Byte (DMA_CTL set to skip 2 bytes) */
 234         skb_reserve(skb,2);
 235         blist_ent_ptr->bd.BuffLength=PKT_BUF_SZ-2;
 236         blist_ent_ptr->fd.FDLength=1;
 237         blist_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
 238         blist_ent_ptr->bd.BDCtl=BDCTL_COWNSBD_MSK;
 239 }
 240
 241
 242 static int ether00_mem_init(struct net_device* dev)
 243 {
 244         struct net_priv* priv=dev->priv;
 245         struct tx_fda_ent *tx_fd_ptr,*tx_end_ptr;
 246         struct rx_blist_ent* blist_ent_ptr;
 247         int i;
 248
 249         /*
 250          * Grab a block of on chip SRAM to contain the control stuctures for
 251          * the ethernet MAC. This uncached becuase it needs to be accesses by both
 252          * bus masters (cpu + mac). However, it shouldn't matter too much in terms
 253          * of speed as its on chip memory
 254          */
 255         priv->dma_data=ioremap_nocache(EXC_SPSRAM_BLOCK0_BASE,EXC_SPSRAM_BLOCK0_SIZE );
 256         if (!priv->dma_data)
 257                 return -ENOMEM;
 258
 259         priv->rx_fda_ptr=(struct rx_fda_ent*)priv->dma_data;
 260         /*
 261          * Now share it out amongst the Frame descriptors and the buffer list
 262          */
 263         priv->rx_blist_vp=(struct rx_blist_ent*)((unsigned int)priv->dma_data+RX_NUM_FDESC*sizeof(struct rx_fda_ent));
 264
 265         /*
 266          *Initalise the FDA list
 267          */
 268         /* set ownership to the controller */
 269         memset(priv->rx_fda_ptr,0x80,RX_NUM_FDESC*sizeof(struct rx_fda_ent));
 270
 271         /*
 272          *Initialise the buffer list
 273          */
 274         blist_ent_ptr=priv->rx_blist_vp;
 275         i=0;
 276         while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
 277                 struct sk_buff *skb;
 278                 blist_ent_ptr->fd.FDLength=1;
 279                 skb=dev_alloc_skb(PKT_BUF_SZ);
 280                 if(skb){
 281                         setup_blist_entry(skb,blist_ent_ptr);
 282                         blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(blist_ent_ptr+1);
 283                         blist_ent_ptr->bd.BDStat=i++;
 284                         blist_ent_ptr++;
 285                 }
 286                 else
 287                 {
 288                         printk("Failed to initalise buffer list\n");
 289                 }
 290
 291         }
 292         blist_ent_ptr--;
 293         blist_ent_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->rx_blist_vp);
 294
 295         priv->tx_fdalist_vp=(struct tx_fda_ent*)(priv->rx_blist_vp+RX_NUM_BUFF);
 296
 297         /* Initialise the buffers to be a circular list. The mac will then go poll
 298          * the list until it finds a frame ready to transmit */
 299         tx_end_ptr=priv->tx_fdalist_vp+TX_NUM_FDESC;
 300         for(tx_fd_ptr=priv->tx_fdalist_vp;tx_fd_ptr<tx_end_ptr;tx_fd_ptr++){
 301                 tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa((tx_fd_ptr+1));
 302                 tx_fd_ptr->fd.FDCtl=1;
 303                 tx_fd_ptr->fd.FDStat=0;
 304                 tx_fd_ptr->fd.FDLength=1;
 305
 306         }
 307         /* Change the last FDNext pointer to make a circular list */
 308         tx_fd_ptr--;
 309         tx_fd_ptr->fd.FDNext=(FDA_DESC*)__dma_pa(priv->tx_fdalist_vp);
 310
 311         /* Point the device at the chain of Rx and Tx Buffers */
 312         writel((unsigned int)__dma_pa(priv->rx_fda_ptr),ETHER_FDA_BAS(dev->base_addr));
 313         writel((RX_NUM_FDESC-1)*sizeof(struct rx_fda_ent),ETHER_FDA_LIM(dev->base_addr));
 314         writel((unsigned int)__dma_pa(priv->rx_blist_vp),ETHER_BLFRMPTR(dev->base_addr));
 315
 316         writel((unsigned int)__dma_pa(priv->tx_fdalist_vp),ETHER_TXFRMPTR(dev->base_addr));
 317
 318         return 0;
 319 }
 320
 321
 322 void ether00_mem_update(void* dev_id)
 323 {
 324         struct net_device* dev=dev_id;
 325         struct net_priv* priv=dev->priv;
 326         struct sk_buff* skb;
 327         struct tx_fda_ent *fda_ptr=priv->tx_fdalist_vp;
 328         struct rx_blist_ent* blist_ent_ptr;
 329         unsigned long flags;
 330
 331         priv->tq_memupdate.sync=0;
 332         //priv->tq_memupdate.list=
 333         priv->memupdate_scheduled=0;
 334
 335         /* Transmit interrupt */
 336         while(fda_ptr<(priv->tx_fdalist_vp+TX_NUM_FDESC)){
 337                 if(!(FDCTL_COWNSFD_MSK&fda_ptr->fd.FDCtl) && (ETHER_TX_STAT_COMP_MSK&fda_ptr->fd.FDStat)){
 338                         priv->stats.tx_packets++;
 339                         priv->stats.tx_bytes+=fda_ptr->bd.BuffLength;
 340                         skb=(struct sk_buff*)fda_ptr->fd.FDSystem;
 341                         //printk("%d:txcln:fda=%#x skb=%#x\n",jiffies,fda_ptr,skb);
 342                         dev_kfree_skb(skb);
 343                         fda_ptr->fd.FDSystem=0;
 344                         fda_ptr->fd.FDStat=0;
 345                         fda_ptr->fd.FDCtl=0;
 346                 }
 347                 fda_ptr++;
 348         }
 349         /* Fill in any missing buffers from the received queue */
 350         spin_lock_irqsave(&priv->rx_lock,flags);
 351         blist_ent_ptr=priv->rx_blist_vp;
 352         while(blist_ent_ptr<(priv->rx_blist_vp+RX_NUM_BUFF)){
 353                 /* fd.FDSystem of 0 indicates we failed to allocate the buffer in the ISR */
 354                 if(!blist_ent_ptr->fd.FDSystem){
 355                         struct sk_buff *skb;
 356                         skb=dev_alloc_skb(PKT_BUF_SZ);
 357                         blist_ent_ptr->fd.FDSystem=(unsigned int)skb;
 358                         if(skb){
 359                                 setup_blist_entry(skb,blist_ent_ptr);
 360                         }
 361                         else
 362                         {
 363                                 break;
 364                         }
 365                 }
 366                 blist_ent_ptr++;
 367         }
 368         spin_unlock_irqrestore(&priv->rx_lock,flags);
 369         if(priv->queue_stopped){
 370                 //printk("%d:cln:start q\n",jiffies);
 371                 netif_start_queue(dev);
 372         }
 373         if(priv->rx_disabled){
 374                 //printk("%d:enable_irq\n",jiffies);
 375                 priv->rx_disabled=0;
 376                 writel(ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
 377
 378         }
 379 }
 380
 381
 382 static void ether00_int( int irq_num, void* dev_id, struct pt_regs* regs)
 383 {
 384         struct net_device* dev=dev_id;
 385         struct net_priv* priv=dev->priv;
 386
 387         unsigned int   interruptValue;
 388
 389         interruptValue=readl(ETHER_INT_SRC(dev->base_addr));
 390
 391         //printk("INT_SRC=%x\n",interruptValue);
 392
 393         if(!(readl(ETHER_INT_SRC(dev->base_addr)) & ETHER_INT_SRC_IRQ_MSK))
 394         {
 395                 return;         /* Interrupt wasn't caused by us!! */
 396         }
 397
 398         if(readl(ETHER_INT_SRC(dev->base_addr))&
 399            (ETHER_INT_SRC_INTMACRX_MSK |
 400             ETHER_INT_SRC_FDAEX_MSK |
 401             ETHER_INT_SRC_BLEX_MSK)) {
 402                 struct rx_blist_ent* blist_ent_ptr;
 403                 struct rx_fda_ent* fda_ent_ptr;
 404                 struct sk_buff* skb;
 405
 406                 fda_ent_ptr=priv->rx_fda_ptr;
 407                 spin_lock(&priv->rx_lock);
 408                 while(fda_ent_ptr<(priv->rx_fda_ptr+RX_NUM_FDESC)){
 409                         int result;
 410
 411                         if(!(fda_ent_ptr->fd.FDCtl&FDCTL_COWNSFD_MSK))
 412                         {
 413                                 /* This frame is ready for processing */
 414                                 /*find the corresponding buffer in the bufferlist */
 415                                 blist_ent_ptr=priv->rx_blist_vp+fda_ent_ptr->bd.BDStat;
 416                                 skb=(struct sk_buff*)blist_ent_ptr->fd.FDSystem;
 417
 418                                 /* Pass this skb up the stack */
 419                                 skb->dev=dev;
 420                                 skb_put(skb,fda_ent_ptr->fd.FDLength);
 421                                 skb->protocol=eth_type_trans(skb,dev);
 422                                 skb->ip_summed=CHECKSUM_UNNECESSARY;
 423                                 result=netif_rx(skb);
 424                                 /* Update statistics */
 425                                 priv->stats.rx_packets++;
 426                                 priv->stats.rx_bytes+=fda_ent_ptr->fd.FDLength;
 427
 428                                 /* Free the FDA entry */
 429                                 fda_ent_ptr->bd.BDStat=0xff;
 430                                 fda_ent_ptr->fd.FDCtl=FDCTL_COWNSFD_MSK;
 431
 432                                 /* Allocate a new skb and point the bd entry to it */
 433                                 blist_ent_ptr->fd.FDSystem=0;
 434                                 skb=dev_alloc_skb(PKT_BUF_SZ);
 435                                 //printk("allocskb=%#x\n",skb);
 436                                 if(skb){
 437                                         setup_blist_entry(skb,blist_ent_ptr);
 438
 439                                 }
 440                                 else if(!priv->memupdate_scheduled){
 441                                         int tmp;
 442                                         /* There are no buffers at the moment, so schedule */
 443                                         /* the background task to sort this out */
 444                                         schedule_task(&priv->tq_memupdate);
 445                                         priv->memupdate_scheduled=1;
 446                                         printk(KERN_DEBUG "%s:No buffers",dev->name);
 447                                         /* If this interrupt was due to a lack of buffers then
 448                                          * we'd better stop the receiver too */
 449                                         if(interruptValue&ETHER_INT_SRC_BLEX_MSK){
 450                                                 priv->rx_disabled=1;
 451                                                 tmp=readl(ETHER_INT_SRC(dev->base_addr));
 452                                                 writel(tmp&~ETHER_RX_CTL_RXEN_MSK,ETHER_RX_CTL(dev->base_addr));
 453                                                 printk(KERN_DEBUG "%s:Halting rx",dev->name);
 454                                         }
 455
 456                                 }
 457
 458                         }
 459                         fda_ent_ptr++;
 460                 }
 461                 spin_unlock(&priv->rx_lock);
 462
 463                 /* Clear the  interrupts */
 464                 writel(ETHER_INT_SRC_INTMACRX_MSK | ETHER_INT_SRC_FDAEX_MSK
 465                        | ETHER_INT_SRC_BLEX_MSK,ETHER_INT_SRC(dev->base_addr));
 466
 467         }
 468
 469         if(readl(ETHER_INT_SRC(dev->base_addr))&ETHER_INT_SRC_INTMACTX_MSK){
 470
 471                 if(!priv->memupdate_scheduled){
 472                         schedule_task(&priv->tq_memupdate);
 473                         priv->memupdate_scheduled=1;
 474                 }
 475                 /* Clear the interrupt */
 476                 writel(ETHER_INT_SRC_INTMACTX_MSK,ETHER_INT_SRC(dev->base_addr));
 477         }
 478
 479         if (readl(ETHER_INT_SRC(dev->base_addr)) & (ETHER_INT_SRC_SWINT_MSK|
 480                                                     ETHER_INT_SRC_INTEARNOT_MSK|
 481                                                     ETHER_INT_SRC_INTLINK_MSK|
 482                                                     ETHER_INT_SRC_INTEXBD_MSK|
 483                                                     ETHER_INT_SRC_INTTXCTLCMP_MSK))
 484         {
 485                 /*
 486                  *      Not using any of these so they shouldn't happen
 487                  *
 488                  *      In the cased of INTEXBD - if you allocate more
 489                  *      than 28 decsriptors you may need to think about this
 490                  */
 491                 printk("Not using this interrupt\n");
 492         }
 493
 494         if (readl(ETHER_INT_SRC(dev->base_addr)) &
 495             (ETHER_INT_SRC_INTSBUS_MSK |
 496              ETHER_INT_SRC_INTNRABT_MSK
 497              |ETHER_INT_SRC_DMPARERR_MSK))
 498         {
 499                 /*
 500                  * Hardware errors, we can either ignore them and hope they go away
 501                  *or reset the device, I'll try the first for now to see if they happen
 502                  */
 503                 printk("Hardware error\n");
 504         }
 505 }
 506
 507 static void ether00_setup_ethernet_address(struct net_device* dev)
 508 {
 509         int tmp;
 510
 511         dev->addr_len=6;
 512         writew(0,ETHER_ARC_ADR(dev->base_addr));
 513         writel((dev->dev_addr[0]<<24) |
 514                 (dev->dev_addr[1]<<16) |
 515                 (dev->dev_addr[2]<<8) |
 516                 dev->dev_addr[3],
 517                 ETHER_ARC_DATA(dev->base_addr));
 518
 519         writew(4,ETHER_ARC_ADR(dev->base_addr));
 520         tmp=readl(ETHER_ARC_DATA(dev->base_addr));
 521         tmp&=0xffff;
 522         tmp|=(dev->dev_addr[4]<<24) | (dev->dev_addr[5]<<16);
 523         writel(tmp, ETHER_ARC_DATA(dev->base_addr));
 524         /* Enable this entry in the ARC */
 525
 526         writel(1,ETHER_ARC_ENA(dev->base_addr));
 527
 528         return;
 529 }
 530
 531
 532 static void ether00_reset(struct net_device *dev)
 533 {
 534         /* reset the controller */
 535         writew(ETHER_MAC_CTL_RESET_MSK,ETHER_MAC_CTL(dev->base_addr));
 536
 537         /*
 538          * Make sure we're not going to send anything
 539          */
 540
 541         writew(ETHER_TX_CTL_TXHALT_MSK,ETHER_TX_CTL(dev->base_addr));
 542
 543         /*
 544          * Make sure we're not going to receive anything
 545          */
 546         writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
 547
 548         /*
 549          * Disable Interrupts for now, and set the burst size to 8 bytes
 550          */
 551
 552         writel(ETHER_DMA_CTL_INTMASK_MSK |
 553                ((8 << ETHER_DMA_CTL_DMBURST_OFST) & ETHER_DMA_CTL_DMBURST_MSK)
 554                |(2<<ETHER_DMA_CTL_RXALIGN_OFST),
 555                ETHER_DMA_CTL(dev->base_addr));
 556
 557
 558         /*
 559          * Set TxThrsh - start transmitting a packet after 1514
 560          * bytes or when a packet is complete, whichever comes first
 561          */
 562          writew(1514,ETHER_TXTHRSH(dev->base_addr));
 563
 564         /*
 565          * Set TxPollCtr.  Each cycle is
 566          * 61.44 microseconds with a 33 MHz bus
 567          */
 568          writew(1,ETHER_TXPOLLCTR(dev->base_addr));
 569
 570         /*
 571          * Set Rx_Ctl - Turn off reception and let RxData turn it
 572          * on later
 573          */
 574          writew(ETHER_RX_CTL_RXHALT_MSK,ETHER_RX_CTL(dev->base_addr));
 575
 576 }
 577
 578
 579 static void ether00_set_multicast(struct net_device* dev)
 580 {
 581         int count=dev->mc_count;
 582
 583         /* Set promiscuous mode if it's asked for. */
 584
 585         if (dev->flags&IFF_PROMISC){
 586
 587                 writew( ETHER_ARC_CTL_COMPEN_MSK |
 588                         ETHER_ARC_CTL_BROADACC_MSK |
 589                         ETHER_ARC_CTL_GROUPACC_MSK |
 590                         ETHER_ARC_CTL_STATIONACC_MSK,
 591                         ETHER_ARC_CTL(dev->base_addr));
 592                 return;
 593         }
 594
 595         /*
 596          * Get all multicast packets if required, or if there are too
 597          * many addresses to fit in hardware
 598          */
 599         if (dev->flags & IFF_ALLMULTI){
 600                 writew( ETHER_ARC_CTL_COMPEN_MSK |
 601                         ETHER_ARC_CTL_GROUPACC_MSK |
 602                         ETHER_ARC_CTL_BROADACC_MSK,
 603                         ETHER_ARC_CTL(dev->base_addr));
 604                 return;
 605         }
 606         if (dev->mc_count > (ETHER_ARC_SIZE - 1)){
 607
 608                 printk(KERN_WARNING "Too many multicast addresses for hardware to filter - receiving all multicast packets\n");
 609                 writew( ETHER_ARC_CTL_COMPEN_MSK |
 610                         ETHER_ARC_CTL_GROUPACC_MSK |
 611                         ETHER_ARC_CTL_BROADACC_MSK,
 612                         ETHER_ARC_CTL(dev->base_addr));
 613                 return;
 614         }
 615
 616         if(dev->mc_count){
 617                 struct dev_mc_list *mc_list_ent=dev->mc_list;
 618                 unsigned int temp,i;
 619                 DEBUG(printk("mc_count=%d mc_list=%#x\n",dev-> mc_count, dev->mc_list));
 620                 DEBUG(printk("mc addr=%02#x%02x%02x%02x%02x%02x\n",
 621                              mc_list_ent->dmi_addr[5],
 622                              mc_list_ent->dmi_addr[4],
 623                              mc_list_ent->dmi_addr[3],
 624                              mc_list_ent->dmi_addr[2],
 625                              mc_list_ent->dmi_addr[1],
 626                              mc_list_ent->dmi_addr[0]);)
 627
 628                 /*
 629                  * The first 6 bytes are the MAC address, so
 630                  * don't change them!
 631                  */
 632                 writew(4,ETHER_ARC_ADR(dev->base_addr));
 633                 temp=readl(ETHER_ARC_DATA(dev->base_addr));
 634                 temp&=0xffff0000;
 635
 636                 /* Disable the current multicast stuff */
 637                 writel(1,ETHER_ARC_ENA(dev->base_addr));
 638
 639                 for(;;){
 640                         temp|=mc_list_ent->dmi_addr[1] |
 641                                 mc_list_ent->dmi_addr[0]<<8;
 642                         writel(temp,ETHER_ARC_DATA(dev->base_addr));
 643
 644                         i=readl(ETHER_ARC_ADR(dev->base_addr));
 645                         writew(i+4,ETHER_ARC_ADR(dev->base_addr));
 646
 647                         temp=mc_list_ent->dmi_addr[5]|
 648                                 mc_list_ent->dmi_addr[4]<<8 |
 649                                 mc_list_ent->dmi_addr[3]<<16 |
 650                                 mc_list_ent->dmi_addr[2]<<24;
 651                         writel(temp,ETHER_ARC_DATA(dev->base_addr));
 652
 653                         count--;
 654                         if(!mc_list_ent->next || !count){
 655                                 break;
 656                         }
 657                         DEBUG(printk("mc_list_next=%#x\n",mc_list_ent->next);)
 658                         mc_list_ent=mc_list_ent->next;
 659
 660
 661                         i=readl(ETHER_ARC_ADR(dev->base_addr));
 662                         writel(i+4,ETHER_ARC_ADR(dev->base_addr));
 663
 664                         temp=mc_list_ent->dmi_addr[3]|
 665                                 mc_list_ent->dmi_addr[2]<<8 |
 666                                 mc_list_ent->dmi_addr[1]<<16 |
 667                                 mc_list_ent->dmi_addr[0]<<24;
 668                         writel(temp,ETHER_ARC_DATA(dev->base_addr));
 669
 670                         i=readl(ETHER_ARC_ADR(dev->base_addr));
 671                         writel(i+4,ETHER_ARC_ADR(dev->base_addr));
 672
 673                         temp=mc_list_ent->dmi_addr[4]<<16 |
 674                                 mc_list_ent->dmi_addr[5]<<24;
 675
 676                         writel(temp,ETHER_ARC_DATA(dev->base_addr));
 677
 678                         count--;
 679                         if(!mc_list_ent->next || !count){
 680                                 break;
 681                         }
 682                         mc_list_ent=mc_list_ent->next;
 683                 }
 684
 685
 686                 if(count)
 687                         printk(KERN_WARNING "Multicast list size error\n");
 688
 689
 690                 writew( ETHER_ARC_CTL_BROADACC_MSK|
 691                         ETHER_ARC_CTL_COMPEN_MSK,
 692                         ETHER_ARC_CTL(dev->base_addr));
 693
 694         }
 695
 696         /* enable the active ARC enties */
 697         writew((1<<(count+2))-1,ETHER_ARC_ENA(dev->base_addr));
 698 }
 699
 700
 701 static int ether00_open(struct net_device* dev)
 702 {
 703         int result,tmp;
 704         struct net_priv* priv;
 705
 706         if (!is_valid_ether_addr(dev->dev_addr))
 707                 return -EINVAL;
 708
 709         /* Install interrupt handlers */
 710         result=request_irq(dev->irq,ether00_int,0,"ether00",dev);
 711         if(result)
 712                 goto open_err1;
 713
 714         result=request_irq(2,ether00_phy_int,0,"ether00_phy",dev);
 715         if(result)
 716                 goto open_err2;
 717
 718         ether00_reset(dev);
 719         result=ether00_mem_init(dev);
 720         if(result)
 721                 goto open_err3;
 722
 723
 724         ether00_setup_ethernet_address(dev);
 725
 726         ether00_set_multicast(dev);
 727
 728         result=ether00_write_phy(dev,PHY_CONTROL, PHY_CONTROL_ANEGEN_MSK | PHY_CONTROL_RANEG_MSK);
 729         if(result)
 730                 goto open_err4;
 731         result=ether00_write_phy(dev,PHY_IRQ_CONTROL, PHY_IRQ_CONTROL_LS_CHG_IE_MSK |
 732                                  PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK);
 733         if(result)
 734                 goto open_err4;
 735
 736         /* Start the device enable interrupts */
 737         writew(ETHER_RX_CTL_RXEN_MSK
 738 //             | ETHER_RX_CTL_STRIPCRC_MSK
 739                | ETHER_RX_CTL_ENGOOD_MSK
 740                | ETHER_RX_CTL_ENRXPAR_MSK| ETHER_RX_CTL_ENLONGERR_MSK
 741                | ETHER_RX_CTL_ENOVER_MSK| ETHER_RX_CTL_ENCRCERR_MSK,
 742                ETHER_RX_CTL(dev->base_addr));
 743
 744         writew(ETHER_TX_CTL_TXEN_MSK|
 745                ETHER_TX_CTL_ENEXDEFER_MSK|
 746                ETHER_TX_CTL_ENLCARR_MSK|
 747                ETHER_TX_CTL_ENEXCOLL_MSK|
 748                ETHER_TX_CTL_ENLATECOLL_MSK|
 749                ETHER_TX_CTL_ENTXPAR_MSK|
 750                ETHER_TX_CTL_ENCOMP_MSK,
 751                ETHER_TX_CTL(dev->base_addr));
 752
 753         tmp=readl(ETHER_DMA_CTL(dev->base_addr));
 754         writel(tmp&~ETHER_DMA_CTL_INTMASK_MSK,ETHER_DMA_CTL(dev->base_addr));
 755
 756         return 0;
 757
 758  open_err4:
 759         ether00_reset(dev);
 760  open_err3:
 761         free_irq(2,dev);
 762  open_err2:
 763         free_irq(dev->irq,dev);
 764  open_err1:
 765         return result;
 766
 767 }
 768
 769
 770 static int ether00_tx(struct sk_buff* skb, struct net_device* dev)
 771 {
 772         struct net_priv *priv=dev->priv;
 773         struct tx_fda_ent *fda_ptr;
 774         int i;
 775
 776
 777         /*
 778          *      Find an empty slot in which to stick the frame
 779          */
 780         fda_ptr=(struct tx_fda_ent*)__dma_va(readl(ETHER_TXFRMPTR(dev->base_addr)));
 781         i=0;
 782         while(i<TX_NUM_FDESC){
 783                 if (fda_ptr->fd.FDStat||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
 784                         fda_ptr =(struct tx_fda_ent*) __dma_va((struct tx_fda_ent*)fda_ptr->fd.FDNext);
 785                 }
 786                 else {
 787                         break;
 788                 }
 789                 i++;
 790         }
 791
 792         /* Write the skb data from the cache*/
 793         consistent_sync(skb->data,skb->len,PCI_DMA_TODEVICE);
 794         fda_ptr->bd.BuffData=(char*)__pa(skb->data);
 795         fda_ptr->bd.BuffLength=(unsigned short)skb->len;
 796         /* Save the pointer to the skb for freeing later */
 797         fda_ptr->fd.FDSystem=(unsigned int)skb;
 798         fda_ptr->fd.FDStat=0;
 799         /* Pass ownership of the buffers to the controller */
 800         fda_ptr->fd.FDCtl=1;
 801         fda_ptr->fd.FDCtl|=FDCTL_COWNSFD_MSK;
 802
 803         /* If the next buffer in the list is full, stop the queue */
 804         fda_ptr=(struct tx_fda_ent*)__dma_va(fda_ptr->fd.FDNext);
 805         if ((fda_ptr->fd.FDStat)||(fda_ptr->fd.FDCtl & FDCTL_COWNSFD_MSK)){
 806                 netif_stop_queue(dev);
 807                 priv->queue_stopped=1;
 808         }
 809
 810         return 0;
 811 }
 812
 813 static struct net_device_stats *ether00_stats(struct net_device* dev)
 814 {
 815         struct net_priv *priv=dev->priv;
 816         return &priv->stats;
 817 }
 818
 819
 820 static int ether00_stop(struct net_device* dev)
 821 {
 822         struct net_priv *priv=dev->priv;
 823         int tmp;
 824
 825         /* Stop/disable the device. */
 826         tmp=readw(ETHER_RX_CTL(dev->base_addr));
 827         tmp&=~(ETHER_RX_CTL_RXEN_MSK | ETHER_RX_CTL_ENGOOD_MSK);
 828         tmp|=ETHER_RX_CTL_RXHALT_MSK;
 829         writew(tmp,ETHER_RX_CTL(dev->base_addr));
 830
 831         tmp=readl(ETHER_TX_CTL(dev->base_addr));
 832         tmp&=~ETHER_TX_CTL_TXEN_MSK;
 833         tmp|=ETHER_TX_CTL_TXHALT_MSK;
 834         writel(tmp,ETHER_TX_CTL(dev->base_addr));
 835
 836         /* Free up system resources */
 837         free_irq(dev->irq,dev);
 838         free_irq(2,dev);
 839         iounmap(priv->dma_data);
 840
 841         return 0;
 842 }
 843
 844
 845 static void ether00_get_ethernet_address(struct net_device* dev)
 846 {
 847         struct mtd_info *mymtd=NULL;
 848         int i;
 849         size_t retlen;
 850
 851         /*
 852          * For the Epxa10 dev board (camelot), the ethernet MAC
 853          * address is of the form  00:aa:aa:00:xx:xx where
 854          * 00:aa:aa is the Altera vendor ID and xx:xx is the
 855          * last 2 bytes of the board serial number, as programmed
 856          * into the OTP area of the flash device on EBI1. If this
 857          * isn't an expa10 dev board, or there's no mtd support to
 858          * read the serial number from flash then we'll force the
 859          * use to set their own mac address using ifconfig.
 860          */
 861
 862 #ifdef CONFIG_ARCH_CAMELOT
 863 #ifdef CONFIG_MTD
 864         /* get the mtd_info structure for the first mtd device*/
 865         for(i=0;i<MAX_MTD_DEVICES;i++){
 866                 mymtd=get_mtd_device(NULL,i);
 867                 if(!mymtd||!strcmp(mymtd->name,"EPXA10DB flash"))
 868                         break;
 869         }
 870
 871         if(!mymtd || !mymtd->read_user_prot_reg){
 872                 printk(KERN_WARNING "%s: Failed to read MAC address from flash\n",dev->name);
 873         }else{
 874                 mymtd->read_user_prot_reg(mymtd,2,1,&retlen,&dev->dev_addr[5]);
 875                 mymtd->read_user_prot_reg(mymtd,3,1,&retlen,&dev->dev_addr[4]);
 876                 dev->dev_addr[3]=0;
 877                 dev->dev_addr[2]=vendor_id[1];
 878                 dev->dev_addr[1]=vendor_id[0];
 879                 dev->dev_addr[0]=0;
 880         }
 881 #else
 882         printk(KERN_WARNING "%s: MTD support required to read MAC address from EPXA10 dev board\n", dev->name);
 883 #endif
 884 #endif
 885
 886         if (!is_valid_ether_addr(dev->dev_addr))
 887                 printk("%s: Invalid ethernet MAC address.  Please set using "
 888                         "ifconfig\n", dev->name);
 889
 890 }
 891
 892 /*
 893  * Keep a mapping of dev_info addresses -> port lines to use when
 894  * removing ports dev==NULL indicates unused entry
 895  */
 896
 897
 898 static struct net_device* dev_list[ETH_NR];
 899
 900 static int ether00_add_device(struct pldhs_dev_info* dev_info,void* dev_ps_data)
 901 {
 902         struct net_device *dev;
 903         struct net_priv *priv;
 904         void *map_addr;
 905         int result;
 906         int i;
 907
 908         i=0;
 909         while(dev_list[i] && i < ETH_NR)
 910                 i++;
 911
 912         if(i==ETH_NR){
 913                 printk(KERN_WARNING "ether00: Maximum number of ports reached\n");
 914                 return 0;
 915         }
 916
 917
 918         if (!request_mem_region(dev_info->base_addr, MAC_REG_SIZE, "ether00"))
 919                 return -EBUSY;
 920
 921         dev = alloc_etherdev(sizeof(struct net_priv));
 922         if(!dev) {
 923                 result = -ENOMEM;
 924                 goto out_release;
 925         }
 926         priv = dev->priv;
 927
 928         priv->tq_memupdate.routine=ether00_mem_update;
 929         priv->tq_memupdate.data=(void*) dev;
 930
 931         spin_lock_init(&priv->rx_lock);
 932
 933         map_addr=ioremap_nocache(dev_info->base_addr,SZ_4K);
 934         if(!map_addr){
 935                 result = -ENOMEM;
 936                 out_kfree;
 937         }
 938
 939         dev->open=ether00_open;
 940         dev->stop=ether00_stop;
 941         dev->set_multicast_list=ether00_set_multicast;
 942         dev->hard_start_xmit=ether00_tx;
 943         dev->get_stats=ether00_stats;
 944
 945         ether00_get_ethernet_address(dev);
 946
 947         SET_MODULE_OWNER(dev);
 948
 949         dev->base_addr=(unsigned int)map_addr;
 950         dev->irq=dev_info->irq;
 951         dev->features=NETIF_F_DYNALLOC | NETIF_F_HW_CSUM;
 952
 953         result=register_netdev(dev);
 954         if(result){
 955                 printk("Ether00: Error %i registering driver\n",result);
 956                 goto out_unmap;
 957         }
 958         printk("registered ether00 device at %#x\n",dev_info->base_addr);
 959
 960         dev_list[i]=dev;
 961
 962         return result;
 963
 964  out_unmap:
 965         iounmap(map_addr);
 966  out_kfree:
 967         free_netdev(dev);
 968  out_release:
 969         release_mem_region(dev_info->base_addr, MAC_REG_SIZE);
 970         return result;
 971 }
 972
 973
 974 static int ether00_remove_devices(void)
 975 {
 976         int i;
 977
 978         for(i=0;i<ETH_NR;i++){
 979                 if(dev_list[i]){
 980                         netif_device_detach(dev_list[i]);
 981                         unregister_netdev(dev_list[i]);
 982                         iounmap((void*)dev_list[i]->base_addr);
 983                         release_mem_region(dev_list[i]->base_addr, MAC_REG_SIZE);
 984                         free_netdev(dev_list[i]);
 985                         dev_list[i]=0;
 986                 }
 987         }
 988         return 0;
 989 }
 990
 991 static struct pld_hotswap_ops ether00_pldhs_ops={
 992         .name = ETHER00_NAME,
 993         .add_device = ether00_add_device,
 994         .remove_devices = ether00_remove_devices,
 995 };
 996
 997
 998 static void __exit ether00_cleanup_module(void)
 999 {
1000         int result;
1001         result=ether00_remove_devices();
1002         if(result)
1003                 printk(KERN_WARNING "ether00: failed to remove all devices\n");
1004
1005         pldhs_unregister_driver(ETHER00_NAME);
1006 }
1007 module_exit(ether00_cleanup_module);
1008
1009
1010 static int __init ether00_mod_init(void)
1011 {
1012         printk("mod init\n");
1013         return pldhs_register_driver(&ether00_pldhs_ops);
1014
1015 }
1016
1017 module_init(ether00_mod_init);
1018