drivers/net/b44.c

   1 /* b44.c: Broadcom 4400 device driver.
   2  *
   3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   4  * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
   5  *
   6  * Distribute under GPL.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/types.h>
  12 #include <linux/netdevice.h>
  13 #include <linux/ethtool.h>
  14 #include <linux/mii.h>
  15 #include <linux/if_ether.h>
  16 #include <linux/etherdevice.h>
  17 #include <linux/pci.h>
  18 #include <linux/delay.h>
  19 #include <linux/init.h>
  20 #include <linux/version.h>
  21
  22 #include <asm/uaccess.h>
  23 #include <asm/io.h>
  24 #include <asm/irq.h>
  25
  26 #include "b44.h"
  27
  28 #define DRV_MODULE_NAME         "b44"
  29 #define PFX DRV_MODULE_NAME     ": "
  30 #define DRV_MODULE_VERSION      "0.94"
  31 #define DRV_MODULE_RELDATE      "May 4, 2004"
  32
  33 #define B44_DEF_MSG_ENABLE        \
  34         (NETIF_MSG_DRV          | \
  35          NETIF_MSG_PROBE        | \
  36          NETIF_MSG_LINK         | \
  37          NETIF_MSG_TIMER        | \
  38          NETIF_MSG_IFDOWN       | \
  39          NETIF_MSG_IFUP         | \
  40          NETIF_MSG_RX_ERR       | \
  41          NETIF_MSG_TX_ERR)
  42
  43 /* length of time before we decide the hardware is borked,
  44  * and dev->tx_timeout() should be called to fix the problem
  45  */
  46 #define B44_TX_TIMEOUT                  (5 * HZ)
  47
  48 /* hardware minimum and maximum for a single frame's data payload */
  49 #define B44_MIN_MTU                     60
  50 #define B44_MAX_MTU                     1500
  51
  52 #define B44_RX_RING_SIZE                512
  53 #define B44_DEF_RX_RING_PENDING         200
  54 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
  55                                  B44_RX_RING_SIZE)
  56 #define B44_TX_RING_SIZE                512
  57 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
  58 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
  59                                  B44_TX_RING_SIZE)
  60
  61 #define TX_RING_GAP(BP) \
  62         (B44_TX_RING_SIZE - (BP)->tx_pending)
  63 #define TX_BUFFS_AVAIL(BP)                                              \
  64         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
  65           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
  66           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
  67 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
  68
  69 #define RX_PKT_BUF_SZ           (1536 + bp->rx_offset + 64)
  70
  71 /* minimum number of free TX descriptors required to wake up TX process */
  72 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
  73
  74 static char version[] __devinitdata =
  75         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  76
  77 MODULE_AUTHOR("David S. Miller (davem@redhat.com)");
  78 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  79 MODULE_LICENSE("GPL");
  80 MODULE_PARM(b44_debug, "i");
  81 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  82
  83 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
  84
  85 static struct pci_device_id b44_pci_tbl[] = {
  86         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
  87           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  88         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
  89           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  90         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  91           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  92         { }     /* terminate list with empty entry */
  93 };
  94
  95 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
  96
  97 static void b44_halt(struct b44 *);
  98 static void b44_init_rings(struct b44 *);
  99 static void b44_init_hw(struct b44 *);
 100
 101 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 102                         u32 bit, unsigned long timeout, const int clear)
 103 {
 104         unsigned long i;
 105
 106         for (i = 0; i < timeout; i++) {
 107                 u32 val = br32(reg);
 108
 109                 if (clear && !(val & bit))
 110                         break;
 111                 if (!clear && (val & bit))
 112                         break;
 113                 udelay(10);
 114         }
 115         if (i == timeout) {
 116                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
 117                        "%lx to %s.\n",
 118                        bp->dev->name,
 119                        bit, reg,
 120                        (clear ? "clear" : "set"));
 121                 return -ENODEV;
 122         }
 123         return 0;
 124 }
 125
 126 /* Sonics SiliconBackplane support routines.  ROFL, you should see all the
 127  * buzz words used on this company's website :-)
 128  *
 129  * All of these routines must be invoked with bp->lock held and
 130  * interrupts disabled.
 131  */
 132
 133 #define SBID_SDRAM              0
 134 #define SBID_PCI_MEM            1
 135 #define SBID_PCI_CFG            2
 136 #define SBID_PCI_DMA            3
 137 #define SBID_SDRAM_SWAPPED      4
 138 #define SBID_ENUM               5
 139 #define SBID_REG_SDRAM          6
 140 #define SBID_REG_ILINE20        7
 141 #define SBID_REG_EMAC           8
 142 #define SBID_REG_CODEC          9
 143 #define SBID_REG_USB            10
 144 #define SBID_REG_PCI            11
 145 #define SBID_REG_MIPS           12
 146 #define SBID_REG_EXTIF          13
 147 #define SBID_EXTIF              14
 148 #define SBID_EJTAG              15
 149 #define SBID_MAX                16
 150
 151 static u32 ssb_get_addr(struct b44 *bp, u32 id, u32 instance)
 152 {
 153         switch (id) {
 154         case SBID_PCI_DMA:
 155                 return 0x40000000;
 156         case SBID_ENUM:
 157                 return 0x18000000;
 158         case SBID_REG_EMAC:
 159                 return 0x18000000;
 160         case SBID_REG_CODEC:
 161                 return 0x18001000;
 162         case SBID_REG_PCI:
 163                 return 0x18002000;
 164         default:
 165                 return 0;
 166         };
 167 }
 168
 169 static u32 ssb_get_core_rev(struct b44 *bp)
 170 {
 171         return (br32(B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
 172 }
 173
 174 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
 175 {
 176         u32 bar_orig, pci_rev, val;
 177
 178         pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
 179         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN,
 180                                ssb_get_addr(bp, SBID_REG_PCI, 0));
 181         pci_rev = ssb_get_core_rev(bp);
 182
 183         val = br32(B44_SBINTVEC);
 184         val |= cores;
 185         bw32(B44_SBINTVEC, val);
 186
 187         val = br32(SSB_PCI_TRANS_2);
 188         val |= SSB_PCI_PREF | SSB_PCI_BURST;
 189         bw32(SSB_PCI_TRANS_2, val);
 190
 191         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
 192
 193         return pci_rev;
 194 }
 195
 196 static void ssb_core_disable(struct b44 *bp)
 197 {
 198         if (br32(B44_SBTMSLOW) & SBTMSLOW_RESET)
 199                 return;
 200
 201         bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
 202         b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
 203         b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
 204         bw32(B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 205                             SBTMSLOW_REJECT | SBTMSLOW_RESET));
 206         br32(B44_SBTMSLOW);
 207         udelay(1);
 208         bw32(B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 209         br32(B44_SBTMSLOW);
 210         udelay(1);
 211 }
 212
 213 static void ssb_core_reset(struct b44 *bp)
 214 {
 215         u32 val;
 216
 217         ssb_core_disable(bp);
 218         bw32(B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 219         br32(B44_SBTMSLOW);
 220         udelay(1);
 221
 222         /* Clear SERR if set, this is a hw bug workaround.  */
 223         if (br32(B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 224                 bw32(B44_SBTMSHIGH, 0);
 225
 226         val = br32(B44_SBIMSTATE);
 227         if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 228                 bw32(B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 229
 230         bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 231         br32(B44_SBTMSLOW);
 232         udelay(1);
 233
 234         bw32(B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 235         br32(B44_SBTMSLOW);
 236         udelay(1);
 237 }
 238
 239 static int ssb_core_unit(struct b44 *bp)
 240 {
 241 #if 0
 242         u32 val = br32(B44_SBADMATCH0);
 243         u32 base;
 244
 245         type = val & SBADMATCH0_TYPE_MASK;
 246         switch (type) {
 247         case 0:
 248                 base = val & SBADMATCH0_BS0_MASK;
 249                 break;
 250
 251         case 1:
 252                 base = val & SBADMATCH0_BS1_MASK;
 253                 break;
 254
 255         case 2:
 256         default:
 257                 base = val & SBADMATCH0_BS2_MASK;
 258                 break;
 259         };
 260 #endif
 261         return 0;
 262 }
 263
 264 static int ssb_is_core_up(struct b44 *bp)
 265 {
 266         return ((br32(B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 267                 == SBTMSLOW_CLOCK);
 268 }
 269
 270 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 271 {
 272         u32 val;
 273
 274         val  = ((u32) data[2]) << 24;
 275         val |= ((u32) data[3]) << 16;
 276         val |= ((u32) data[4]) <<  8;
 277         val |= ((u32) data[5]) <<  0;
 278         bw32(B44_CAM_DATA_LO, val);
 279         val = (CAM_DATA_HI_VALID |
 280                (((u32) data[0]) << 8) |
 281                (((u32) data[1]) << 0));
 282         bw32(B44_CAM_DATA_HI, val);
 283         bw32(B44_CAM_CTRL, (CAM_CTRL_WRITE |
 284                             (index << CAM_CTRL_INDEX_SHIFT)));
 285         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 286 }
 287
 288 static inline void __b44_disable_ints(struct b44 *bp)
 289 {
 290         bw32(B44_IMASK, 0);
 291 }
 292
 293 static void b44_disable_ints(struct b44 *bp)
 294 {
 295         __b44_disable_ints(bp);
 296
 297         /* Flush posted writes. */
 298         br32(B44_IMASK);
 299 }
 300
 301 static void b44_enable_ints(struct b44 *bp)
 302 {
 303         bw32(B44_IMASK, bp->imask);
 304 }
 305
 306 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 307 {
 308         int err;
 309
 310         bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 311         bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 312                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 313                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 314                              (reg << MDIO_DATA_RA_SHIFT) |
 315                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 316         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 317         *val = br32(B44_MDIO_DATA) & MDIO_DATA_DATA;
 318
 319         return err;
 320 }
 321
 322 static int b44_writephy(struct b44 *bp, int reg, u32 val)
 323 {
 324         bw32(B44_EMAC_ISTAT, EMAC_INT_MII);
 325         bw32(B44_MDIO_DATA, (MDIO_DATA_SB_START |
 326                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 327                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 328                              (reg << MDIO_DATA_RA_SHIFT) |
 329                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 330                              (val & MDIO_DATA_DATA)));
 331         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 332 }
 333
 334 /* miilib interface */
 335 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
 336  * due to code existing before miilib use was added to this driver.
 337  * Someone should remove this artificial driver limitation in
 338  * b44_{read,write}phy.  bp->phy_addr itself is fine (and needed).
 339  */
 340 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
 341 {
 342         u32 val;
 343         struct b44 *bp = netdev_priv(dev);
 344         int rc = b44_readphy(bp, location, &val);
 345         if (rc)
 346                 return 0xffffffff;
 347         return val;
 348 }
 349
 350 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
 351                          int val)
 352 {
 353         struct b44 *bp = netdev_priv(dev);
 354         b44_writephy(bp, location, val);
 355 }
 356
 357 static int b44_phy_reset(struct b44 *bp)
 358 {
 359         u32 val;
 360         int err;
 361
 362         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 363         if (err)
 364                 return err;
 365         udelay(100);
 366         err = b44_readphy(bp, MII_BMCR, &val);
 367         if (!err) {
 368                 if (val & BMCR_RESET) {
 369                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
 370                                bp->dev->name);
 371                         err = -ENODEV;
 372                 }
 373         }
 374
 375         return 0;
 376 }
 377
 378 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
 379 {
 380         u32 val;
 381
 382         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 383         bp->flags |= pause_flags;
 384
 385         val = br32(B44_RXCONFIG);
 386         if (pause_flags & B44_FLAG_RX_PAUSE)
 387                 val |= RXCONFIG_FLOW;
 388         else
 389                 val &= ~RXCONFIG_FLOW;
 390         bw32(B44_RXCONFIG, val);
 391
 392         val = br32(B44_MAC_FLOW);
 393         if (pause_flags & B44_FLAG_TX_PAUSE)
 394                 val |= (MAC_FLOW_PAUSE_ENAB |
 395                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 396         else
 397                 val &= ~MAC_FLOW_PAUSE_ENAB;
 398         bw32(B44_MAC_FLOW, val);
 399 }
 400
 401 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 402 {
 403         u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
 404                                       B44_FLAG_RX_PAUSE);
 405
 406         if (local & ADVERTISE_PAUSE_CAP) {
 407                 if (local & ADVERTISE_PAUSE_ASYM) {
 408                         if (remote & LPA_PAUSE_CAP)
 409                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 410                                                B44_FLAG_RX_PAUSE);
 411                         else if (remote & LPA_PAUSE_ASYM)
 412                                 pause_enab |= B44_FLAG_RX_PAUSE;
 413                 } else {
 414                         if (remote & LPA_PAUSE_CAP)
 415                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 416                                                B44_FLAG_RX_PAUSE);
 417                 }
 418         } else if (local & ADVERTISE_PAUSE_ASYM) {
 419                 if ((remote & LPA_PAUSE_CAP) &&
 420                     (remote & LPA_PAUSE_ASYM))
 421                         pause_enab |= B44_FLAG_TX_PAUSE;
 422         }
 423
 424         __b44_set_flow_ctrl(bp, pause_enab);
 425 }
 426
 427 static int b44_setup_phy(struct b44 *bp)
 428 {
 429         u32 val;
 430         int err;
 431
 432         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 433                 goto out;
 434         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 435                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
 436                 goto out;
 437         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
 438                 goto out;
 439         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
 440                                 val | MII_TLEDCTRL_ENABLE)) != 0)
 441                 goto out;
 442
 443         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
 444                 u32 adv = ADVERTISE_CSMA;
 445
 446                 if (bp->flags & B44_FLAG_ADV_10HALF)
 447                         adv |= ADVERTISE_10HALF;
 448                 if (bp->flags & B44_FLAG_ADV_10FULL)
 449                         adv |= ADVERTISE_10FULL;
 450                 if (bp->flags & B44_FLAG_ADV_100HALF)
 451                         adv |= ADVERTISE_100HALF;
 452                 if (bp->flags & B44_FLAG_ADV_100FULL)
 453                         adv |= ADVERTISE_100FULL;
 454
 455                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
 456                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 457
 458                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
 459                         goto out;
 460                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
 461                                                        BMCR_ANRESTART))) != 0)
 462                         goto out;
 463         } else {
 464                 u32 bmcr;
 465
 466                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
 467                         goto out;
 468                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
 469                 if (bp->flags & B44_FLAG_100_BASE_T)
 470                         bmcr |= BMCR_SPEED100;
 471                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
 472                         bmcr |= BMCR_FULLDPLX;
 473                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
 474                         goto out;
 475
 476                 /* Since we will not be negotiating there is no safe way
 477                  * to determine if the link partner supports flow control
 478                  * or not.  So just disable it completely in this case.
 479                  */
 480                 b44_set_flow_ctrl(bp, 0, 0);
 481         }
 482
 483 out:
 484         return err;
 485 }
 486
 487 static void b44_stats_update(struct b44 *bp)
 488 {
 489         unsigned long reg;
 490         u32 *val;
 491
 492         val = &bp->hw_stats.tx_good_octets;
 493         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 494                 *val++ += br32(reg);
 495         }
 496         val = &bp->hw_stats.rx_good_octets;
 497         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 498                 *val++ += br32(reg);
 499         }
 500 }
 501
 502 static void b44_link_report(struct b44 *bp)
 503 {
 504         if (!netif_carrier_ok(bp->dev)) {
 505                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
 506         } else {
 507                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
 508                        bp->dev->name,
 509                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
 510                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
 511
 512                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
 513                        "%s for RX.\n",
 514                        bp->dev->name,
 515                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
 516                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
 517         }
 518 }
 519
 520 static void b44_check_phy(struct b44 *bp)
 521 {
 522         u32 bmsr, aux;
 523
 524         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 525             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 526             (bmsr != 0xffff)) {
 527                 if (aux & MII_AUXCTRL_SPEED)
 528                         bp->flags |= B44_FLAG_100_BASE_T;
 529                 else
 530                         bp->flags &= ~B44_FLAG_100_BASE_T;
 531                 if (aux & MII_AUXCTRL_DUPLEX)
 532                         bp->flags |= B44_FLAG_FULL_DUPLEX;
 533                 else
 534                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
 535
 536                 if (!netif_carrier_ok(bp->dev) &&
 537                     (bmsr & BMSR_LSTATUS)) {
 538                         u32 val = br32(B44_TX_CTRL);
 539                         u32 local_adv, remote_adv;
 540
 541                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 542                                 val |= TX_CTRL_DUPLEX;
 543                         else
 544                                 val &= ~TX_CTRL_DUPLEX;
 545                         bw32(B44_TX_CTRL, val);
 546
 547                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 548                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 549                             !b44_readphy(bp, MII_LPA, &remote_adv))
 550                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
 551
 552                         /* Link now up */
 553                         netif_carrier_on(bp->dev);
 554                         b44_link_report(bp);
 555                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
 556                         /* Link now down */
 557                         netif_carrier_off(bp->dev);
 558                         b44_link_report(bp);
 559                 }
 560
 561                 if (bmsr & BMSR_RFAULT)
 562                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
 563                                bp->dev->name);
 564                 if (bmsr & BMSR_JCD)
 565                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
 566                                bp->dev->name);
 567         }
 568 }
 569
 570 static void b44_timer(unsigned long __opaque)
 571 {
 572         struct b44 *bp = (struct b44 *) __opaque;
 573
 574         spin_lock_irq(&bp->lock);
 575
 576         b44_check_phy(bp);
 577
 578         b44_stats_update(bp);
 579
 580         spin_unlock_irq(&bp->lock);
 581
 582         bp->timer.expires = jiffies + HZ;
 583         add_timer(&bp->timer);
 584 }
 585
 586 static void b44_tx(struct b44 *bp)
 587 {
 588         u32 cur, cons;
 589
 590         cur  = br32(B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 591         cur /= sizeof(struct dma_desc);
 592
 593         /* XXX needs updating when NETIF_F_SG is supported */
 594         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
 595                 struct ring_info *rp = &bp->tx_buffers[cons];
 596                 struct sk_buff *skb = rp->skb;
 597
 598                 if (unlikely(skb == NULL))
 599                         BUG();
 600
 601                 pci_unmap_single(bp->pdev,
 602                                  pci_unmap_addr(rp, mapping),
 603                                  skb->len,
 604                                  PCI_DMA_TODEVICE);
 605                 rp->skb = NULL;
 606                 dev_kfree_skb_irq(skb);
 607         }
 608
 609         bp->tx_cons = cons;
 610         if (netif_queue_stopped(bp->dev) &&
 611             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 612                 netif_wake_queue(bp->dev);
 613
 614         bw32(B44_GPTIMER, 0);
 615 }
 616
 617 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 618  * before the DMA address you give it.  So we allocate 30 more bytes
 619  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 620  * point the chip at 30 bytes past where the rx_header will go.
 621  */
 622 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 623 {
 624         struct dma_desc *dp;
 625         struct ring_info *src_map, *map;
 626         struct rx_header *rh;
 627         struct sk_buff *skb;
 628         dma_addr_t mapping;
 629         int dest_idx;
 630         u32 ctrl;
 631
 632         src_map = NULL;
 633         if (src_idx >= 0)
 634                 src_map = &bp->rx_buffers[src_idx];
 635         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 636         map = &bp->rx_buffers[dest_idx];
 637         skb = dev_alloc_skb(RX_PKT_BUF_SZ);
 638         if (skb == NULL)
 639                 return -ENOMEM;
 640
 641         skb->dev = bp->dev;
 642         mapping = pci_map_single(bp->pdev, skb->data,
 643                                  RX_PKT_BUF_SZ,
 644                                  PCI_DMA_FROMDEVICE);
 645         skb_reserve(skb, bp->rx_offset);
 646
 647         rh = (struct rx_header *)
 648                 (skb->data - bp->rx_offset);
 649         rh->len = 0;
 650         rh->flags = 0;
 651
 652         map->skb = skb;
 653         pci_unmap_addr_set(map, mapping, mapping);
 654
 655         if (src_map != NULL)
 656                 src_map->skb = NULL;
 657
 658         ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
 659         if (dest_idx == (B44_RX_RING_SIZE - 1))
 660                 ctrl |= DESC_CTRL_EOT;
 661
 662         dp = &bp->rx_ring[dest_idx];
 663         dp->ctrl = cpu_to_le32(ctrl);
 664         dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
 665
 666         return RX_PKT_BUF_SZ;
 667 }
 668
 669 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 670 {
 671         struct dma_desc *src_desc, *dest_desc;
 672         struct ring_info *src_map, *dest_map;
 673         struct rx_header *rh;
 674         int dest_idx;
 675         u32 ctrl;
 676
 677         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 678         dest_desc = &bp->rx_ring[dest_idx];
 679         dest_map = &bp->rx_buffers[dest_idx];
 680         src_desc = &bp->rx_ring[src_idx];
 681         src_map = &bp->rx_buffers[src_idx];
 682
 683         dest_map->skb = src_map->skb;
 684         rh = (struct rx_header *) src_map->skb->data;
 685         rh->len = 0;
 686         rh->flags = 0;
 687         pci_unmap_addr_set(dest_map, mapping,
 688                            pci_unmap_addr(src_map, mapping));
 689
 690         ctrl = src_desc->ctrl;
 691         if (dest_idx == (B44_RX_RING_SIZE - 1))
 692                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
 693         else
 694                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
 695
 696         dest_desc->ctrl = ctrl;
 697         dest_desc->addr = src_desc->addr;
 698         src_map->skb = NULL;
 699
 700         pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
 701                                        RX_PKT_BUF_SZ,
 702                                        PCI_DMA_FROMDEVICE);
 703 }
 704
 705 static int b44_rx(struct b44 *bp, int budget)
 706 {
 707         int received;
 708         u32 cons, prod;
 709
 710         received = 0;
 711         prod  = br32(B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 712         prod /= sizeof(struct dma_desc);
 713         cons = bp->rx_cons;
 714
 715         while (cons != prod && budget > 0) {
 716                 struct ring_info *rp = &bp->rx_buffers[cons];
 717                 struct sk_buff *skb = rp->skb;
 718                 dma_addr_t map = pci_unmap_addr(rp, mapping);
 719                 struct rx_header *rh;
 720                 u16 len;
 721
 722                 pci_dma_sync_single_for_cpu(bp->pdev, map,
 723                                             RX_PKT_BUF_SZ,
 724                                             PCI_DMA_FROMDEVICE);
 725                 rh = (struct rx_header *) skb->data;
 726                 len = cpu_to_le16(rh->len);
 727                 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
 728                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
 729                 drop_it:
 730                         b44_recycle_rx(bp, cons, bp->rx_prod);
 731                 drop_it_no_recycle:
 732                         bp->stats.rx_dropped++;
 733                         goto next_pkt;
 734                 }
 735
 736                 if (len == 0) {
 737                         int i = 0;
 738
 739                         do {
 740                                 udelay(2);
 741                                 barrier();
 742                                 len = cpu_to_le16(rh->len);
 743                         } while (len == 0 && i++ < 5);
 744                         if (len == 0)
 745                                 goto drop_it;
 746                 }
 747
 748                 /* Omit CRC. */
 749                 len -= 4;
 750
 751                 if (len > RX_COPY_THRESHOLD) {
 752                         int skb_size;
 753                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 754                         if (skb_size < 0)
 755                                 goto drop_it;
 756                         pci_unmap_single(bp->pdev, map,
 757                                          skb_size, PCI_DMA_FROMDEVICE);
 758                         /* Leave out rx_header */
 759                         skb_put(skb, len+bp->rx_offset);
 760                         skb_pull(skb,bp->rx_offset);
 761                 } else {
 762                         struct sk_buff *copy_skb;
 763
 764                         b44_recycle_rx(bp, cons, bp->rx_prod);
 765                         copy_skb = dev_alloc_skb(len + 2);
 766                         if (copy_skb == NULL)
 767                                 goto drop_it_no_recycle;
 768
 769                         copy_skb->dev = bp->dev;
 770                         skb_reserve(copy_skb, 2);
 771                         skb_put(copy_skb, len);
 772                         /* DMA sync done above, copy just the actual packet */
 773                         memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
 774
 775                         skb = copy_skb;
 776                 }
 777                 skb->ip_summed = CHECKSUM_NONE;
 778                 skb->protocol = eth_type_trans(skb, bp->dev);
 779                 netif_receive_skb(skb);
 780                 bp->dev->last_rx = jiffies;
 781                 received++;
 782                 budget--;
 783         next_pkt:
 784                 bp->rx_prod = (bp->rx_prod + 1) &
 785                         (B44_RX_RING_SIZE - 1);
 786                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
 787         }
 788
 789         bp->rx_cons = cons;
 790         bw32(B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 791
 792         return received;
 793 }
 794
 795 static int b44_poll(struct net_device *netdev, int *budget)
 796 {
 797         struct b44 *bp = netdev_priv(netdev);
 798         int done;
 799
 800         spin_lock_irq(&bp->lock);
 801
 802         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 803                 /* spin_lock(&bp->tx_lock); */
 804                 b44_tx(bp);
 805                 /* spin_unlock(&bp->tx_lock); */
 806         }
 807         spin_unlock_irq(&bp->lock);
 808
 809         done = 1;
 810         if (bp->istat & ISTAT_RX) {
 811                 int orig_budget = *budget;
 812                 int work_done;
 813
 814                 if (orig_budget > netdev->quota)
 815                         orig_budget = netdev->quota;
 816
 817                 work_done = b44_rx(bp, orig_budget);
 818
 819                 *budget -= work_done;
 820                 netdev->quota -= work_done;
 821
 822                 if (work_done >= orig_budget)
 823                         done = 0;
 824         }
 825
 826         if (bp->istat & ISTAT_ERRORS) {
 827                 spin_lock_irq(&bp->lock);
 828                 b44_halt(bp);
 829                 b44_init_rings(bp);
 830                 b44_init_hw(bp);
 831                 netif_wake_queue(bp->dev);
 832                 spin_unlock_irq(&bp->lock);
 833                 done = 1;
 834         }
 835
 836         if (done) {
 837                 netif_rx_complete(netdev);
 838                 b44_enable_ints(bp);
 839         }
 840
 841         return (done ? 0 : 1);
 842 }
 843
 844 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 845 {
 846         struct net_device *dev = dev_id;
 847         struct b44 *bp = netdev_priv(dev);
 848         unsigned long flags;
 849         u32 istat, imask;
 850         int handled = 0;
 851
 852         spin_lock_irqsave(&bp->lock, flags);
 853
 854         istat = br32(B44_ISTAT);
 855         imask = br32(B44_IMASK);
 856
 857         /* ??? What the fuck is the purpose of the interrupt mask
 858          * ??? register if we have to mask it out by hand anyways?
 859          */
 860         istat &= imask;
 861         if (istat) {
 862                 handled = 1;
 863                 if (netif_rx_schedule_prep(dev)) {
 864                         /* NOTE: These writes are posted by the readback of
 865                          *       the ISTAT register below.
 866                          */
 867                         bp->istat = istat;
 868                         __b44_disable_ints(bp);
 869                         __netif_rx_schedule(dev);
 870                 } else {
 871                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
 872                                dev->name);
 873                 }
 874
 875                 bw32(B44_ISTAT, istat);
 876                 br32(B44_ISTAT);
 877         }
 878         spin_unlock_irqrestore(&bp->lock, flags);
 879         return IRQ_RETVAL(handled);
 880 }
 881
 882 static void b44_tx_timeout(struct net_device *dev)
 883 {
 884         struct b44 *bp = netdev_priv(dev);
 885
 886         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 887                dev->name);
 888
 889         spin_lock_irq(&bp->lock);
 890
 891         b44_halt(bp);
 892         b44_init_rings(bp);
 893         b44_init_hw(bp);
 894
 895         spin_unlock_irq(&bp->lock);
 896
 897         b44_enable_ints(bp);
 898
 899         netif_wake_queue(dev);
 900 }
 901
 902 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
 903 {
 904         struct b44 *bp = netdev_priv(dev);
 905         dma_addr_t mapping;
 906         u32 len, entry, ctrl;
 907
 908         len = skb->len;
 909         spin_lock_irq(&bp->lock);
 910
 911         /* This is a hard error, log it. */
 912         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
 913                 netif_stop_queue(dev);
 914                 spin_unlock_irq(&bp->lock);
 915                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
 916                        dev->name);
 917                 return 1;
 918         }
 919
 920         entry = bp->tx_prod;
 921         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
 922
 923         bp->tx_buffers[entry].skb = skb;
 924         pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
 925
 926         ctrl  = (len & DESC_CTRL_LEN);
 927         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
 928         if (entry == (B44_TX_RING_SIZE - 1))
 929                 ctrl |= DESC_CTRL_EOT;
 930
 931         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
 932         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
 933
 934         entry = NEXT_TX(entry);
 935
 936         bp->tx_prod = entry;
 937
 938         wmb();
 939
 940         bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 941         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
 942                 bw32(B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 943         if (bp->flags & B44_FLAG_REORDER_BUG)
 944                 br32(B44_DMATX_PTR);
 945
 946         if (TX_BUFFS_AVAIL(bp) < 1)
 947                 netif_stop_queue(dev);
 948
 949         spin_unlock_irq(&bp->lock);
 950
 951         dev->trans_start = jiffies;
 952
 953         return 0;
 954 }
 955
 956 static int b44_change_mtu(struct net_device *dev, int new_mtu)
 957 {
 958         struct b44 *bp = netdev_priv(dev);
 959
 960         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
 961                 return -EINVAL;
 962
 963         if (!netif_running(dev)) {
 964                 /* We'll just catch it later when the
 965                  * device is up'd.
 966                  */
 967                 dev->mtu = new_mtu;
 968                 return 0;
 969         }
 970
 971         spin_lock_irq(&bp->lock);
 972         b44_halt(bp);
 973         dev->mtu = new_mtu;
 974         b44_init_rings(bp);
 975         b44_init_hw(bp);
 976         spin_unlock_irq(&bp->lock);
 977
 978         b44_enable_ints(bp);
 979
 980         return 0;
 981 }
 982
 983 /* Free up pending packets in all rx/tx rings.
 984  *
 985  * The chip has been shut down and the driver detached from
 986  * the networking, so no interrupts or new tx packets will
 987  * end up in the driver.  bp->lock is not held and we are not
 988  * in an interrupt context and thus may sleep.
 989  */
 990 static void b44_free_rings(struct b44 *bp)
 991 {
 992         struct ring_info *rp;
 993         int i;
 994
 995         for (i = 0; i < B44_RX_RING_SIZE; i++) {
 996                 rp = &bp->rx_buffers[i];
 997
 998                 if (rp->skb == NULL)
 999                         continue;
1000                 pci_unmap_single(bp->pdev,
1001                                  pci_unmap_addr(rp, mapping),
1002                                  RX_PKT_BUF_SZ,
1003                                  PCI_DMA_FROMDEVICE);
1004                 dev_kfree_skb_any(rp->skb);
1005                 rp->skb = NULL;
1006         }
1007
1008         /* XXX needs changes once NETIF_F_SG is set... */
1009         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1010                 rp = &bp->tx_buffers[i];
1011
1012                 if (rp->skb == NULL)
1013                         continue;
1014                 pci_unmap_single(bp->pdev,
1015                                  pci_unmap_addr(rp, mapping),
1016                                  rp->skb->len,
1017                                  PCI_DMA_TODEVICE);
1018                 dev_kfree_skb_any(rp->skb);
1019                 rp->skb = NULL;
1020         }
1021 }
1022
1023 /* Initialize tx/rx rings for packet processing.
1024  *
1025  * The chip has been shut down and the driver detached from
1026  * the networking, so no interrupts or new tx packets will
1027  * end up in the driver.  bp->lock is not held and we are not
1028  * in an interrupt context and thus may sleep.
1029  */
1030 static void b44_init_rings(struct b44 *bp)
1031 {
1032         int i;
1033
1034         b44_free_rings(bp);
1035
1036         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1037         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1038
1039         for (i = 0; i < bp->rx_pending; i++) {
1040                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1041                         break;
1042         }
1043 }
1044
1045 /*
1046  * Must not be invoked with interrupt sources disabled and
1047  * the hardware shutdown down.
1048  */
1049 static void b44_free_consistent(struct b44 *bp)
1050 {
1051         if (bp->rx_buffers) {
1052                 kfree(bp->rx_buffers);
1053                 bp->rx_buffers = NULL;
1054         }
1055         if (bp->tx_buffers) {
1056                 kfree(bp->tx_buffers);
1057                 bp->tx_buffers = NULL;
1058         }
1059         if (bp->rx_ring) {
1060                 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1061                                     bp->rx_ring, bp->rx_ring_dma);
1062                 bp->rx_ring = NULL;
1063         }
1064         if (bp->tx_ring) {
1065                 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1066                                     bp->tx_ring, bp->tx_ring_dma);
1067                 bp->tx_ring = NULL;
1068         }
1069 }
1070
1071 /*
1072  * Must not be invoked with interrupt sources disabled and
1073  * the hardware shutdown down.  Can sleep.
1074  */
1075 static int b44_alloc_consistent(struct b44 *bp)
1076 {
1077         int size;
1078
1079         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1080         bp->rx_buffers = kmalloc(size, GFP_KERNEL);
1081         if (!bp->rx_buffers)
1082                 goto out_err;
1083         memset(bp->rx_buffers, 0, size);
1084
1085         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1086         bp->tx_buffers = kmalloc(size, GFP_KERNEL);
1087         if (!bp->tx_buffers)
1088                 goto out_err;
1089         memset(bp->tx_buffers, 0, size);
1090
1091         size = DMA_TABLE_BYTES;
1092         bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1093         if (!bp->rx_ring)
1094                 goto out_err;
1095
1096         bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1097         if (!bp->tx_ring)
1098                 goto out_err;
1099
1100         return 0;
1101
1102 out_err:
1103         b44_free_consistent(bp);
1104         return -ENOMEM;
1105 }
1106
1107 /* bp->lock is held. */
1108 static void b44_clear_stats(struct b44 *bp)
1109 {
1110         unsigned long reg;
1111
1112         bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1113         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1114                 br32(reg);
1115         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1116                 br32(reg);
1117 }
1118
1119 /* bp->lock is held. */
1120 static void b44_chip_reset(struct b44 *bp)
1121 {
1122         if (ssb_is_core_up(bp)) {
1123                 bw32(B44_RCV_LAZY, 0);
1124                 bw32(B44_ENET_CTRL, ENET_CTRL_DISABLE);
1125                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1126                 bw32(B44_DMATX_CTRL, 0);
1127                 bp->tx_prod = bp->tx_cons = 0;
1128                 if (br32(B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1129                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1130                                      100, 0);
1131                 }
1132                 bw32(B44_DMARX_CTRL, 0);
1133                 bp->rx_prod = bp->rx_cons = 0;
1134         } else {
1135                 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1136                                    SBINTVEC_ENET0 :
1137                                    SBINTVEC_ENET1));
1138         }
1139
1140         ssb_core_reset(bp);
1141
1142         b44_clear_stats(bp);
1143
1144         /* Make PHY accessible. */
1145         bw32(B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1146                              (0x0d & MDIO_CTRL_MAXF_MASK)));
1147         br32(B44_MDIO_CTRL);
1148
1149         if (!(br32(B44_DEVCTRL) & DEVCTRL_IPP)) {
1150                 bw32(B44_ENET_CTRL, ENET_CTRL_EPSEL);
1151                 br32(B44_ENET_CTRL);
1152                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1153         } else {
1154                 u32 val = br32(B44_DEVCTRL);
1155
1156                 if (val & DEVCTRL_EPR) {
1157                         bw32(B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1158                         br32(B44_DEVCTRL);
1159                         udelay(100);
1160                 }
1161                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1162         }
1163 }
1164
1165 /* bp->lock is held. */
1166 static void b44_halt(struct b44 *bp)
1167 {
1168         b44_disable_ints(bp);
1169         b44_chip_reset(bp);
1170 }
1171
1172 /* bp->lock is held. */
1173 static void __b44_set_mac_addr(struct b44 *bp)
1174 {
1175         bw32(B44_CAM_CTRL, 0);
1176         if (!(bp->dev->flags & IFF_PROMISC)) {
1177                 u32 val;
1178
1179                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1180                 val = br32(B44_CAM_CTRL);
1181                 bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1182         }
1183 }
1184
1185 static int b44_set_mac_addr(struct net_device *dev, void *p)
1186 {
1187         struct b44 *bp = netdev_priv(dev);
1188         struct sockaddr *addr = p;
1189
1190         if (netif_running(dev))
1191                 return -EBUSY;
1192
1193         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1194
1195         spin_lock_irq(&bp->lock);
1196         __b44_set_mac_addr(bp);
1197         spin_unlock_irq(&bp->lock);
1198
1199         return 0;
1200 }
1201
1202 /* Called at device open time to get the chip ready for
1203  * packet processing.  Invoked with bp->lock held.
1204  */
1205 static void __b44_set_rx_mode(struct net_device *);
1206 static void b44_init_hw(struct b44 *bp)
1207 {
1208         u32 val;
1209
1210         b44_chip_reset(bp);
1211         b44_phy_reset(bp);
1212         b44_setup_phy(bp);
1213
1214         /* Enable CRC32, set proper LED modes and power on PHY */
1215         bw32(B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1216         bw32(B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1217
1218         /* This sets the MAC address too.  */
1219         __b44_set_rx_mode(bp->dev);
1220
1221         /* MTU + eth header + possible VLAN tag + struct rx_header */
1222         bw32(B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1223         bw32(B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1224
1225         bw32(B44_TX_WMARK, 56); /* XXX magic */
1226         bw32(B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1227         bw32(B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1228         bw32(B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1229                               (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1230         bw32(B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1231
1232         bw32(B44_DMARX_PTR, bp->rx_pending);
1233         bp->rx_prod = bp->rx_pending;
1234
1235         bw32(B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1236
1237         val = br32(B44_ENET_CTRL);
1238         bw32(B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1239 }
1240
1241 static int b44_open(struct net_device *dev)
1242 {
1243         struct b44 *bp = netdev_priv(dev);
1244         int err;
1245
1246         err = b44_alloc_consistent(bp);
1247         if (err)
1248                 return err;
1249
1250         err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1251         if (err)
1252                 goto err_out_free;
1253
1254         spin_lock_irq(&bp->lock);
1255
1256         b44_init_rings(bp);
1257         b44_init_hw(bp);
1258         bp->flags |= B44_FLAG_INIT_COMPLETE;
1259
1260         spin_unlock_irq(&bp->lock);
1261
1262         init_timer(&bp->timer);
1263         bp->timer.expires = jiffies + HZ;
1264         bp->timer.data = (unsigned long) bp;
1265         bp->timer.function = b44_timer;
1266         add_timer(&bp->timer);
1267
1268         b44_enable_ints(bp);
1269
1270         return 0;
1271
1272 err_out_free:
1273         b44_free_consistent(bp);
1274         return err;
1275 }
1276
1277 #if 0
1278 /*static*/ void b44_dump_state(struct b44 *bp)
1279 {
1280         u32 val32, val32_2, val32_3, val32_4, val32_5;
1281         u16 val16;
1282
1283         pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1284         printk("DEBUG: PCI status [%04x] \n", val16);
1285
1286 }
1287 #endif
1288
1289 static int b44_close(struct net_device *dev)
1290 {
1291         struct b44 *bp = netdev_priv(dev);
1292
1293         netif_stop_queue(dev);
1294
1295         del_timer_sync(&bp->timer);
1296
1297         spin_lock_irq(&bp->lock);
1298
1299 #if 0
1300         b44_dump_state(bp);
1301 #endif
1302         b44_halt(bp);
1303         b44_free_rings(bp);
1304         bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1305         netif_carrier_off(bp->dev);
1306
1307         spin_unlock_irq(&bp->lock);
1308
1309         free_irq(dev->irq, dev);
1310
1311         b44_free_consistent(bp);
1312
1313         return 0;
1314 }
1315
1316 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1317 {
1318         struct b44 *bp = netdev_priv(dev);
1319         struct net_device_stats *nstat = &bp->stats;
1320         struct b44_hw_stats *hwstat = &bp->hw_stats;
1321
1322         /* Convert HW stats into netdevice stats. */
1323         nstat->rx_packets = hwstat->rx_pkts;
1324         nstat->tx_packets = hwstat->tx_pkts;
1325         nstat->rx_bytes   = hwstat->rx_octets;
1326         nstat->tx_bytes   = hwstat->tx_octets;
1327         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1328                              hwstat->tx_oversize_pkts +
1329                              hwstat->tx_underruns +
1330                              hwstat->tx_excessive_cols +
1331                              hwstat->tx_late_cols);
1332         nstat->multicast  = hwstat->tx_multicast_pkts;
1333         nstat->collisions = hwstat->tx_total_cols;
1334
1335         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1336                                    hwstat->rx_undersize);
1337         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1338         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1339         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1340         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1341                                    hwstat->rx_oversize_pkts +
1342                                    hwstat->rx_missed_pkts +
1343                                    hwstat->rx_crc_align_errs +
1344                                    hwstat->rx_undersize +
1345                                    hwstat->rx_crc_errs +
1346                                    hwstat->rx_align_errs +
1347                                    hwstat->rx_symbol_errs);
1348
1349         nstat->tx_aborted_errors = hwstat->tx_underruns;
1350         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1351
1352         return nstat;
1353 }
1354
1355 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1356 {
1357         struct dev_mc_list *mclist;
1358         int i, num_ents;
1359
1360         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1361         mclist = dev->mc_list;
1362         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1363                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1364         }
1365         return i+1;
1366 }
1367
1368 static void __b44_set_rx_mode(struct net_device *dev)
1369 {
1370         struct b44 *bp = netdev_priv(dev);
1371         u32 val;
1372         int i=0;
1373         unsigned char zero[6] = {0,0,0,0,0,0};
1374
1375         val = br32(B44_RXCONFIG);
1376         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1377         if (dev->flags & IFF_PROMISC) {
1378                 val |= RXCONFIG_PROMISC;
1379                 bw32(B44_RXCONFIG, val);
1380         } else {
1381                 __b44_set_mac_addr(bp);
1382
1383                 if (dev->flags & IFF_ALLMULTI)
1384                         val |= RXCONFIG_ALLMULTI;
1385                 else
1386                         i=__b44_load_mcast(bp, dev);
1387
1388                 for(;i<64;i++) {
1389                         __b44_cam_write(bp, zero, i);
1390                 }
1391                 bw32(B44_RXCONFIG, val);
1392                 val = br32(B44_CAM_CTRL);
1393                 bw32(B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1394         }
1395 }
1396
1397 static void b44_set_rx_mode(struct net_device *dev)
1398 {
1399         struct b44 *bp = netdev_priv(dev);
1400
1401         spin_lock_irq(&bp->lock);
1402         __b44_set_rx_mode(dev);
1403         spin_unlock_irq(&bp->lock);
1404 }
1405
1406 static u32 b44_get_msglevel(struct net_device *dev)
1407 {
1408         struct b44 *bp = netdev_priv(dev);
1409         return bp->msg_enable;
1410 }
1411
1412 static void b44_set_msglevel(struct net_device *dev, u32 value)
1413 {
1414         struct b44 *bp = netdev_priv(dev);
1415         bp->msg_enable = value;
1416 }
1417
1418 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1419 {
1420         struct b44 *bp = netdev_priv(dev);
1421         struct pci_dev *pci_dev = bp->pdev;
1422
1423         strcpy (info->driver, DRV_MODULE_NAME);
1424         strcpy (info->version, DRV_MODULE_VERSION);
1425         strcpy (info->bus_info, pci_name(pci_dev));
1426 }
1427
1428 static int b44_nway_reset(struct net_device *dev)
1429 {
1430         struct b44 *bp = netdev_priv(dev);
1431         u32 bmcr;
1432         int r;
1433
1434         spin_lock_irq(&bp->lock);
1435         b44_readphy(bp, MII_BMCR, &bmcr);
1436         b44_readphy(bp, MII_BMCR, &bmcr);
1437         r = -EINVAL;
1438         if (bmcr & BMCR_ANENABLE) {
1439                 b44_writephy(bp, MII_BMCR,
1440                              bmcr | BMCR_ANRESTART);
1441                 r = 0;
1442         }
1443         spin_unlock_irq(&bp->lock);
1444
1445         return r;
1446 }
1447
1448 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1449 {
1450         struct b44 *bp = netdev_priv(dev);
1451
1452         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1453                 return -EAGAIN;
1454         cmd->supported = (SUPPORTED_Autoneg);
1455         cmd->supported |= (SUPPORTED_100baseT_Half |
1456                           SUPPORTED_100baseT_Full |
1457                           SUPPORTED_10baseT_Half |
1458                           SUPPORTED_10baseT_Full |
1459                           SUPPORTED_MII);
1460
1461         cmd->advertising = 0;
1462         if (bp->flags & B44_FLAG_ADV_10HALF)
1463                 cmd->advertising |= ADVERTISE_10HALF;
1464         if (bp->flags & B44_FLAG_ADV_10FULL)
1465                 cmd->advertising |= ADVERTISE_10FULL;
1466         if (bp->flags & B44_FLAG_ADV_100HALF)
1467                 cmd->advertising |= ADVERTISE_100HALF;
1468         if (bp->flags & B44_FLAG_ADV_100FULL)
1469                 cmd->advertising |= ADVERTISE_100FULL;
1470         cmd->advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1471         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1472                 SPEED_100 : SPEED_10;
1473         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1474                 DUPLEX_FULL : DUPLEX_HALF;
1475         cmd->port = 0;
1476         cmd->phy_address = bp->phy_addr;
1477         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1478                 XCVR_INTERNAL : XCVR_EXTERNAL;
1479         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1480                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1481         cmd->maxtxpkt = 0;
1482         cmd->maxrxpkt = 0;
1483         return 0;
1484 }
1485
1486 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1487 {
1488         struct b44 *bp = netdev_priv(dev);
1489
1490         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1491                 return -EAGAIN;
1492
1493         /* We do not support gigabit. */
1494         if (cmd->autoneg == AUTONEG_ENABLE) {
1495                 if (cmd->advertising &
1496                     (ADVERTISED_1000baseT_Half |
1497                      ADVERTISED_1000baseT_Full))
1498                         return -EINVAL;
1499         } else if ((cmd->speed != SPEED_100 &&
1500                     cmd->speed != SPEED_10) ||
1501                    (cmd->duplex != DUPLEX_HALF &&
1502                     cmd->duplex != DUPLEX_FULL)) {
1503                         return -EINVAL;
1504         }
1505
1506         spin_lock_irq(&bp->lock);
1507
1508         if (cmd->autoneg == AUTONEG_ENABLE) {
1509                 bp->flags &= ~B44_FLAG_FORCE_LINK;
1510                 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1511                                B44_FLAG_ADV_10FULL |
1512                                B44_FLAG_ADV_100HALF |
1513                                B44_FLAG_ADV_100FULL);
1514                 if (cmd->advertising & ADVERTISE_10HALF)
1515                         bp->flags |= B44_FLAG_ADV_10HALF;
1516                 if (cmd->advertising & ADVERTISE_10FULL)
1517                         bp->flags |= B44_FLAG_ADV_10FULL;
1518                 if (cmd->advertising & ADVERTISE_100HALF)
1519                         bp->flags |= B44_FLAG_ADV_100HALF;
1520                 if (cmd->advertising & ADVERTISE_100FULL)
1521                         bp->flags |= B44_FLAG_ADV_100FULL;
1522         } else {
1523                 bp->flags |= B44_FLAG_FORCE_LINK;
1524                 if (cmd->speed == SPEED_100)
1525                         bp->flags |= B44_FLAG_100_BASE_T;
1526                 if (cmd->duplex == DUPLEX_FULL)
1527                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1528         }
1529
1530         b44_setup_phy(bp);
1531
1532         spin_unlock_irq(&bp->lock);
1533
1534         return 0;
1535 }
1536
1537 static void b44_get_ringparam(struct net_device *dev,
1538                               struct ethtool_ringparam *ering)
1539 {
1540         struct b44 *bp = netdev_priv(dev);
1541
1542         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1543         ering->rx_pending = bp->rx_pending;
1544
1545         /* XXX ethtool lacks a tx_max_pending, oops... */
1546 }
1547
1548 static int b44_set_ringparam(struct net_device *dev,
1549                              struct ethtool_ringparam *ering)
1550 {
1551         struct b44 *bp = netdev_priv(dev);
1552
1553         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1554             (ering->rx_mini_pending != 0) ||
1555             (ering->rx_jumbo_pending != 0) ||
1556             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1557                 return -EINVAL;
1558
1559         spin_lock_irq(&bp->lock);
1560
1561         bp->rx_pending = ering->rx_pending;
1562         bp->tx_pending = ering->tx_pending;
1563
1564         b44_halt(bp);
1565         b44_init_rings(bp);
1566         b44_init_hw(bp);
1567         netif_wake_queue(bp->dev);
1568         spin_unlock_irq(&bp->lock);
1569
1570         b44_enable_ints(bp);
1571
1572         return 0;
1573 }
1574
1575 static void b44_get_pauseparam(struct net_device *dev,
1576                                 struct ethtool_pauseparam *epause)
1577 {
1578         struct b44 *bp = netdev_priv(dev);
1579
1580         epause->autoneg =
1581                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1582         epause->rx_pause =
1583                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1584         epause->tx_pause =
1585                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1586 }
1587
1588 static int b44_set_pauseparam(struct net_device *dev,
1589                                 struct ethtool_pauseparam *epause)
1590 {
1591         struct b44 *bp = netdev_priv(dev);
1592
1593         spin_lock_irq(&bp->lock);
1594         if (epause->autoneg)
1595                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1596         else
1597                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1598         if (epause->rx_pause)
1599                 bp->flags |= B44_FLAG_RX_PAUSE;
1600         else
1601                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1602         if (epause->tx_pause)
1603                 bp->flags |= B44_FLAG_TX_PAUSE;
1604         else
1605                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1606         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1607                 b44_halt(bp);
1608                 b44_init_rings(bp);
1609                 b44_init_hw(bp);
1610         } else {
1611                 __b44_set_flow_ctrl(bp, bp->flags);
1612         }
1613         spin_unlock_irq(&bp->lock);
1614
1615         b44_enable_ints(bp);
1616
1617         return 0;
1618 }
1619
1620 static struct ethtool_ops b44_ethtool_ops = {
1621         .get_drvinfo            = b44_get_drvinfo,
1622         .get_settings           = b44_get_settings,
1623         .set_settings           = b44_set_settings,
1624         .nway_reset             = b44_nway_reset,
1625         .get_link               = ethtool_op_get_link,
1626         .get_ringparam          = b44_get_ringparam,
1627         .set_ringparam          = b44_set_ringparam,
1628         .get_pauseparam         = b44_get_pauseparam,
1629         .set_pauseparam         = b44_set_pauseparam,
1630         .get_msglevel           = b44_get_msglevel,
1631         .set_msglevel           = b44_set_msglevel,
1632 };
1633
1634 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1635 {
1636         struct mii_ioctl_data *data = if_mii(ifr);
1637         struct b44 *bp = netdev_priv(dev);
1638         int err;
1639
1640         spin_lock_irq(&bp->lock);
1641         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1642         spin_unlock_irq(&bp->lock);
1643
1644         return err;
1645 }
1646
1647 /* Read 128-bytes of EEPROM. */
1648 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1649 {
1650         long i;
1651         u16 *ptr = (u16 *) data;
1652
1653         for (i = 0; i < 128; i += 2)
1654                 ptr[i / 2] = readw(bp->regs + 4096 + i);
1655
1656         return 0;
1657 }
1658
1659 static int __devinit b44_get_invariants(struct b44 *bp)
1660 {
1661         u8 eeprom[128];
1662         int err;
1663
1664         err = b44_read_eeprom(bp, &eeprom[0]);
1665         if (err)
1666                 goto out;
1667
1668         bp->dev->dev_addr[0] = eeprom[79];
1669         bp->dev->dev_addr[1] = eeprom[78];
1670         bp->dev->dev_addr[2] = eeprom[81];
1671         bp->dev->dev_addr[3] = eeprom[80];
1672         bp->dev->dev_addr[4] = eeprom[83];
1673         bp->dev->dev_addr[5] = eeprom[82];
1674
1675         bp->phy_addr = eeprom[90] & 0x1f;
1676         bp->mdc_port = (eeprom[90] >> 14) & 0x1;
1677
1678         /* With this, plus the rx_header prepended to the data by the
1679          * hardware, we'll land the ethernet header on a 2-byte boundary.
1680          */
1681         bp->rx_offset = 30;
1682
1683         bp->imask = IMASK_DEF;
1684
1685         bp->core_unit = ssb_core_unit(bp);
1686         bp->dma_offset = ssb_get_addr(bp, SBID_PCI_DMA, 0);
1687
1688         /* XXX - really required?
1689            bp->flags |= B44_FLAG_BUGGY_TXPTR;
1690          */
1691 out:
1692         return err;
1693 }
1694
1695 static int __devinit b44_init_one(struct pci_dev *pdev,
1696                                   const struct pci_device_id *ent)
1697 {
1698         static int b44_version_printed = 0;
1699         unsigned long b44reg_base, b44reg_len;
1700         struct net_device *dev;
1701         struct b44 *bp;
1702         int err, i;
1703
1704         if (b44_version_printed++ == 0)
1705                 printk(KERN_INFO "%s", version);
1706
1707         err = pci_enable_device(pdev);
1708         if (err) {
1709                 printk(KERN_ERR PFX "Cannot enable PCI device, "
1710                        "aborting.\n");
1711                 return err;
1712         }
1713
1714         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1715                 printk(KERN_ERR PFX "Cannot find proper PCI device "
1716                        "base address, aborting.\n");
1717                 err = -ENODEV;
1718                 goto err_out_disable_pdev;
1719         }
1720
1721         err = pci_request_regions(pdev, DRV_MODULE_NAME);
1722         if (err) {
1723                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1724                        "aborting.\n");
1725                 goto err_out_disable_pdev;
1726         }
1727
1728         pci_set_master(pdev);
1729
1730         err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
1731         if (err) {
1732                 printk(KERN_ERR PFX "No usable DMA configuration, "
1733                        "aborting.\n");
1734                 goto err_out_free_res;
1735         }
1736
1737         b44reg_base = pci_resource_start(pdev, 0);
1738         b44reg_len = pci_resource_len(pdev, 0);
1739
1740         dev = alloc_etherdev(sizeof(*bp));
1741         if (!dev) {
1742                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1743                 err = -ENOMEM;
1744                 goto err_out_free_res;
1745         }
1746
1747         SET_MODULE_OWNER(dev);
1748         SET_NETDEV_DEV(dev,&pdev->dev);
1749
1750         /* No interesting netdevice features in this card... */
1751         dev->features |= 0;
1752
1753         bp = netdev_priv(dev);
1754         bp->pdev = pdev;
1755         bp->dev = dev;
1756         if (b44_debug >= 0)
1757                 bp->msg_enable = (1 << b44_debug) - 1;
1758         else
1759                 bp->msg_enable = B44_DEF_MSG_ENABLE;
1760
1761         spin_lock_init(&bp->lock);
1762
1763         bp->regs = (unsigned long) ioremap(b44reg_base, b44reg_len);
1764         if (bp->regs == 0UL) {
1765                 printk(KERN_ERR PFX "Cannot map device registers, "
1766                        "aborting.\n");
1767                 err = -ENOMEM;
1768                 goto err_out_free_dev;
1769         }
1770
1771         bp->rx_pending = B44_DEF_RX_RING_PENDING;
1772         bp->tx_pending = B44_DEF_TX_RING_PENDING;
1773
1774         dev->open = b44_open;
1775         dev->stop = b44_close;
1776         dev->hard_start_xmit = b44_start_xmit;
1777         dev->get_stats = b44_get_stats;
1778         dev->set_multicast_list = b44_set_rx_mode;
1779         dev->set_mac_address = b44_set_mac_addr;
1780         dev->do_ioctl = b44_ioctl;
1781         dev->tx_timeout = b44_tx_timeout;
1782         dev->poll = b44_poll;
1783         dev->weight = 64;
1784         dev->watchdog_timeo = B44_TX_TIMEOUT;
1785         dev->change_mtu = b44_change_mtu;
1786         dev->irq = pdev->irq;
1787         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1788
1789         err = b44_get_invariants(bp);
1790         if (err) {
1791                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1792                        "aborting.\n");
1793                 goto err_out_iounmap;
1794         }
1795
1796         bp->mii_if.dev = dev;
1797         bp->mii_if.mdio_read = b44_mii_read;
1798         bp->mii_if.mdio_write = b44_mii_write;
1799         bp->mii_if.phy_id = bp->phy_addr;
1800         bp->mii_if.phy_id_mask = 0x1f;
1801         bp->mii_if.reg_num_mask = 0x1f;
1802
1803         /* By default, advertise all speed/duplex settings. */
1804         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1805                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1806
1807         /* By default, auto-negotiate PAUSE. */
1808         bp->flags |= B44_FLAG_PAUSE_AUTO;
1809
1810         err = register_netdev(dev);
1811         if (err) {
1812                 printk(KERN_ERR PFX "Cannot register net device, "
1813                        "aborting.\n");
1814                 goto err_out_iounmap;
1815         }
1816
1817         pci_set_drvdata(pdev, dev);
1818
1819         pci_save_state(bp->pdev, bp->pci_cfg_state);
1820
1821         printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1822         for (i = 0; i < 6; i++)
1823                 printk("%2.2x%c", dev->dev_addr[i],
1824                        i == 5 ? '\n' : ':');
1825
1826         return 0;
1827
1828 err_out_iounmap:
1829         iounmap((void *) bp->regs);
1830
1831 err_out_free_dev:
1832         free_netdev(dev);
1833
1834 err_out_free_res:
1835         pci_release_regions(pdev);
1836
1837 err_out_disable_pdev:
1838         pci_disable_device(pdev);
1839         pci_set_drvdata(pdev, NULL);
1840         return err;
1841 }
1842
1843 static void __devexit b44_remove_one(struct pci_dev *pdev)
1844 {
1845         struct net_device *dev = pci_get_drvdata(pdev);
1846
1847         if (dev) {
1848                 struct b44 *bp = netdev_priv(dev);
1849
1850                 unregister_netdev(dev);
1851                 iounmap((void *) bp->regs);
1852                 free_netdev(dev);
1853                 pci_release_regions(pdev);
1854                 pci_disable_device(pdev);
1855                 pci_set_drvdata(pdev, NULL);
1856         }
1857 }
1858
1859 static int b44_suspend(struct pci_dev *pdev, u32 state)
1860 {
1861         struct net_device *dev = pci_get_drvdata(pdev);
1862         struct b44 *bp = dev->priv;
1863
1864         if (!netif_running(dev))
1865                  return 0;
1866
1867         del_timer_sync(&bp->timer);
1868
1869         spin_lock_irq(&bp->lock);
1870
1871         b44_halt(bp);
1872         netif_carrier_off(bp->dev);
1873         netif_device_detach(bp->dev);
1874         b44_free_rings(bp);
1875
1876         spin_unlock_irq(&bp->lock);
1877         return 0;
1878 }
1879
1880 static int b44_resume(struct pci_dev *pdev)
1881 {
1882         struct net_device *dev = pci_get_drvdata(pdev);
1883         struct b44 *bp = dev->priv;
1884
1885         pci_restore_state(pdev, bp->pci_cfg_state);
1886
1887         if (!netif_running(dev))
1888                 return 0;
1889
1890         spin_lock_irq(&bp->lock);
1891
1892         b44_init_rings(bp);
1893         b44_init_hw(bp);
1894         netif_device_attach(bp->dev);
1895         spin_unlock_irq(&bp->lock);
1896
1897         bp->timer.expires = jiffies + HZ;
1898         add_timer(&bp->timer);
1899
1900         b44_enable_ints(bp);
1901         return 0;
1902 }
1903
1904 static struct pci_driver b44_driver = {
1905         .name           = DRV_MODULE_NAME,
1906         .id_table       = b44_pci_tbl,
1907         .probe          = b44_init_one,
1908         .remove         = __devexit_p(b44_remove_one),
1909         .suspend        = b44_suspend,
1910         .resume         = b44_resume,
1911 };
1912
1913 static int __init b44_init(void)
1914 {
1915         return pci_module_init(&b44_driver);
1916 }
1917
1918 static void __exit b44_cleanup(void)
1919 {
1920         pci_unregister_driver(&b44_driver);
1921 }
1922
1923 module_init(b44_init);
1924 module_exit(b44_cleanup);
1925