drivers/net/b44.c

   1 /* b44.c: Broadcom 4400 device driver.
   2  *
   3  * Copyright (C) 2002 David S. Miller (davem@redhat.com)
   4  * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
   5  *
   6  * Distribute under GPL.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/moduleparam.h>
  12 #include <linux/types.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/mii.h>
  16 #include <linux/if_ether.h>
  17 #include <linux/etherdevice.h>
  18 #include <linux/pci.h>
  19 #include <linux/delay.h>
  20 #include <linux/init.h>
  21 #include <linux/version.h>
  22
  23 #include <asm/uaccess.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26
  27 #include "b44.h"
  28
  29 #define DRV_MODULE_NAME         "b44"
  30 #define PFX DRV_MODULE_NAME     ": "
  31 #define DRV_MODULE_VERSION      "0.95"
  32 #define DRV_MODULE_RELDATE      "Aug 3, 2004"
  33
  34 #define B44_DEF_MSG_ENABLE        \
  35         (NETIF_MSG_DRV          | \
  36          NETIF_MSG_PROBE        | \
  37          NETIF_MSG_LINK         | \
  38          NETIF_MSG_TIMER        | \
  39          NETIF_MSG_IFDOWN       | \
  40          NETIF_MSG_IFUP         | \
  41          NETIF_MSG_RX_ERR       | \
  42          NETIF_MSG_TX_ERR)
  43
  44 /* length of time before we decide the hardware is borked,
  45  * and dev->tx_timeout() should be called to fix the problem
  46  */
  47 #define B44_TX_TIMEOUT                  (5 * HZ)
  48
  49 /* hardware minimum and maximum for a single frame's data payload */
  50 #define B44_MIN_MTU                     60
  51 #define B44_MAX_MTU                     1500
  52
  53 #define B44_RX_RING_SIZE                512
  54 #define B44_DEF_RX_RING_PENDING         200
  55 #define B44_RX_RING_BYTES       (sizeof(struct dma_desc) * \
  56                                  B44_RX_RING_SIZE)
  57 #define B44_TX_RING_SIZE                512
  58 #define B44_DEF_TX_RING_PENDING         (B44_TX_RING_SIZE - 1)
  59 #define B44_TX_RING_BYTES       (sizeof(struct dma_desc) * \
  60                                  B44_TX_RING_SIZE)
  61 #define B44_DMA_MASK 0x3fffffff
  62
  63 #define TX_RING_GAP(BP) \
  64         (B44_TX_RING_SIZE - (BP)->tx_pending)
  65 #define TX_BUFFS_AVAIL(BP)                                              \
  66         (((BP)->tx_cons <= (BP)->tx_prod) ?                             \
  67           (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod :            \
  68           (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
  69 #define NEXT_TX(N)              (((N) + 1) & (B44_TX_RING_SIZE - 1))
  70
  71 #define RX_PKT_BUF_SZ           (1536 + bp->rx_offset + 64)
  72 #define TX_PKT_BUF_SZ           (B44_MAX_MTU + ETH_HLEN + 8)
  73
  74 /* minimum number of free TX descriptors required to wake up TX process */
  75 #define B44_TX_WAKEUP_THRESH            (B44_TX_RING_SIZE / 4)
  76
  77 static char version[] __devinitdata =
  78         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  79
  80 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
  81 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
  82 MODULE_LICENSE("GPL");
  83 MODULE_VERSION(DRV_MODULE_VERSION);
  84
  85 static int b44_debug = -1;      /* -1 == use B44_DEF_MSG_ENABLE as value */
  86 module_param(b44_debug, int, 0);
  87 MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
  88
  89 static struct pci_device_id b44_pci_tbl[] = {
  90         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401,
  91           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  92         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0,
  93           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  94         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1,
  95           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
  96         { }     /* terminate list with empty entry */
  97 };
  98
  99 MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
 100
 101 static void b44_halt(struct b44 *);
 102 static void b44_init_rings(struct b44 *);
 103 static void b44_init_hw(struct b44 *);
 104 static int b44_poll(struct net_device *dev, int *budget);
 105 #ifdef CONFIG_NET_POLL_CONTROLLER
 106 static void b44_poll_controller(struct net_device *dev);
 107 #endif
 108
 109 static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
 110 {
 111         return readl(bp->regs + reg);
 112 }
 113
 114 static inline void bw32(const struct b44 *bp,
 115                         unsigned long reg, unsigned long val)
 116 {
 117         writel(val, bp->regs + reg);
 118 }
 119
 120 static int b44_wait_bit(struct b44 *bp, unsigned long reg,
 121                         u32 bit, unsigned long timeout, const int clear)
 122 {
 123         unsigned long i;
 124
 125         for (i = 0; i < timeout; i++) {
 126                 u32 val = br32(bp, reg);
 127
 128                 if (clear && !(val & bit))
 129                         break;
 130                 if (!clear && (val & bit))
 131                         break;
 132                 udelay(10);
 133         }
 134         if (i == timeout) {
 135                 printk(KERN_ERR PFX "%s: BUG!  Timeout waiting for bit %08x of register "
 136                        "%lx to %s.\n",
 137                        bp->dev->name,
 138                        bit, reg,
 139                        (clear ? "clear" : "set"));
 140                 return -ENODEV;
 141         }
 142         return 0;
 143 }
 144
 145 /* Sonics SiliconBackplane support routines.  ROFL, you should see all the
 146  * buzz words used on this company's website :-)
 147  *
 148  * All of these routines must be invoked with bp->lock held and
 149  * interrupts disabled.
 150  */
 151
 152 #define SB_PCI_DMA             0x40000000      /* Client Mode PCI memory access space (1 GB) */
 153 #define BCM4400_PCI_CORE_ADDR  0x18002000      /* Address of PCI core on BCM4400 cards */
 154
 155 static u32 ssb_get_core_rev(struct b44 *bp)
 156 {
 157         return (br32(bp, B44_SBIDHIGH) & SBIDHIGH_RC_MASK);
 158 }
 159
 160 static u32 ssb_pci_setup(struct b44 *bp, u32 cores)
 161 {
 162         u32 bar_orig, pci_rev, val;
 163
 164         pci_read_config_dword(bp->pdev, SSB_BAR0_WIN, &bar_orig);
 165         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, BCM4400_PCI_CORE_ADDR);
 166         pci_rev = ssb_get_core_rev(bp);
 167
 168         val = br32(bp, B44_SBINTVEC);
 169         val |= cores;
 170         bw32(bp, B44_SBINTVEC, val);
 171
 172         val = br32(bp, SSB_PCI_TRANS_2);
 173         val |= SSB_PCI_PREF | SSB_PCI_BURST;
 174         bw32(bp, SSB_PCI_TRANS_2, val);
 175
 176         pci_write_config_dword(bp->pdev, SSB_BAR0_WIN, bar_orig);
 177
 178         return pci_rev;
 179 }
 180
 181 static void ssb_core_disable(struct b44 *bp)
 182 {
 183         if (br32(bp, B44_SBTMSLOW) & SBTMSLOW_RESET)
 184                 return;
 185
 186         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_CLOCK));
 187         b44_wait_bit(bp, B44_SBTMSLOW, SBTMSLOW_REJECT, 100000, 0);
 188         b44_wait_bit(bp, B44_SBTMSHIGH, SBTMSHIGH_BUSY, 100000, 1);
 189         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_FGC | SBTMSLOW_CLOCK |
 190                             SBTMSLOW_REJECT | SBTMSLOW_RESET));
 191         br32(bp, B44_SBTMSLOW);
 192         udelay(1);
 193         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_REJECT | SBTMSLOW_RESET));
 194         br32(bp, B44_SBTMSLOW);
 195         udelay(1);
 196 }
 197
 198 static void ssb_core_reset(struct b44 *bp)
 199 {
 200         u32 val;
 201
 202         ssb_core_disable(bp);
 203         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_RESET | SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 204         br32(bp, B44_SBTMSLOW);
 205         udelay(1);
 206
 207         /* Clear SERR if set, this is a hw bug workaround.  */
 208         if (br32(bp, B44_SBTMSHIGH) & SBTMSHIGH_SERR)
 209                 bw32(bp, B44_SBTMSHIGH, 0);
 210
 211         val = br32(bp, B44_SBIMSTATE);
 212         if (val & (SBIMSTATE_IBE | SBIMSTATE_TO))
 213                 bw32(bp, B44_SBIMSTATE, val & ~(SBIMSTATE_IBE | SBIMSTATE_TO));
 214
 215         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK | SBTMSLOW_FGC));
 216         br32(bp, B44_SBTMSLOW);
 217         udelay(1);
 218
 219         bw32(bp, B44_SBTMSLOW, (SBTMSLOW_CLOCK));
 220         br32(bp, B44_SBTMSLOW);
 221         udelay(1);
 222 }
 223
 224 static int ssb_core_unit(struct b44 *bp)
 225 {
 226 #if 0
 227         u32 val = br32(bp, B44_SBADMATCH0);
 228         u32 base;
 229
 230         type = val & SBADMATCH0_TYPE_MASK;
 231         switch (type) {
 232         case 0:
 233                 base = val & SBADMATCH0_BS0_MASK;
 234                 break;
 235
 236         case 1:
 237                 base = val & SBADMATCH0_BS1_MASK;
 238                 break;
 239
 240         case 2:
 241         default:
 242                 base = val & SBADMATCH0_BS2_MASK;
 243                 break;
 244         };
 245 #endif
 246         return 0;
 247 }
 248
 249 static int ssb_is_core_up(struct b44 *bp)
 250 {
 251         return ((br32(bp, B44_SBTMSLOW) & (SBTMSLOW_RESET | SBTMSLOW_REJECT | SBTMSLOW_CLOCK))
 252                 == SBTMSLOW_CLOCK);
 253 }
 254
 255 static void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
 256 {
 257         u32 val;
 258
 259         val  = ((u32) data[2]) << 24;
 260         val |= ((u32) data[3]) << 16;
 261         val |= ((u32) data[4]) <<  8;
 262         val |= ((u32) data[5]) <<  0;
 263         bw32(bp, B44_CAM_DATA_LO, val);
 264         val = (CAM_DATA_HI_VALID |
 265                (((u32) data[0]) << 8) |
 266                (((u32) data[1]) << 0));
 267         bw32(bp, B44_CAM_DATA_HI, val);
 268         bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
 269                             (index << CAM_CTRL_INDEX_SHIFT)));
 270         b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
 271 }
 272
 273 static inline void __b44_disable_ints(struct b44 *bp)
 274 {
 275         bw32(bp, B44_IMASK, 0);
 276 }
 277
 278 static void b44_disable_ints(struct b44 *bp)
 279 {
 280         __b44_disable_ints(bp);
 281
 282         /* Flush posted writes. */
 283         br32(bp, B44_IMASK);
 284 }
 285
 286 static void b44_enable_ints(struct b44 *bp)
 287 {
 288         bw32(bp, B44_IMASK, bp->imask);
 289 }
 290
 291 static int b44_readphy(struct b44 *bp, int reg, u32 *val)
 292 {
 293         int err;
 294
 295         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 296         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 297                              (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
 298                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 299                              (reg << MDIO_DATA_RA_SHIFT) |
 300                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
 301         err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 302         *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
 303
 304         return err;
 305 }
 306
 307 static int b44_writephy(struct b44 *bp, int reg, u32 val)
 308 {
 309         bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
 310         bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
 311                              (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
 312                              (bp->phy_addr << MDIO_DATA_PMD_SHIFT) |
 313                              (reg << MDIO_DATA_RA_SHIFT) |
 314                              (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
 315                              (val & MDIO_DATA_DATA)));
 316         return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
 317 }
 318
 319 /* miilib interface */
 320 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
 321  * due to code existing before miilib use was added to this driver.
 322  * Someone should remove this artificial driver limitation in
 323  * b44_{read,write}phy.  bp->phy_addr itself is fine (and needed).
 324  */
 325 static int b44_mii_read(struct net_device *dev, int phy_id, int location)
 326 {
 327         u32 val;
 328         struct b44 *bp = netdev_priv(dev);
 329         int rc = b44_readphy(bp, location, &val);
 330         if (rc)
 331                 return 0xffffffff;
 332         return val;
 333 }
 334
 335 static void b44_mii_write(struct net_device *dev, int phy_id, int location,
 336                          int val)
 337 {
 338         struct b44 *bp = netdev_priv(dev);
 339         b44_writephy(bp, location, val);
 340 }
 341
 342 static int b44_phy_reset(struct b44 *bp)
 343 {
 344         u32 val;
 345         int err;
 346
 347         err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
 348         if (err)
 349                 return err;
 350         udelay(100);
 351         err = b44_readphy(bp, MII_BMCR, &val);
 352         if (!err) {
 353                 if (val & BMCR_RESET) {
 354                         printk(KERN_ERR PFX "%s: PHY Reset would not complete.\n",
 355                                bp->dev->name);
 356                         err = -ENODEV;
 357                 }
 358         }
 359
 360         return 0;
 361 }
 362
 363 static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
 364 {
 365         u32 val;
 366
 367         bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
 368         bp->flags |= pause_flags;
 369
 370         val = br32(bp, B44_RXCONFIG);
 371         if (pause_flags & B44_FLAG_RX_PAUSE)
 372                 val |= RXCONFIG_FLOW;
 373         else
 374                 val &= ~RXCONFIG_FLOW;
 375         bw32(bp, B44_RXCONFIG, val);
 376
 377         val = br32(bp, B44_MAC_FLOW);
 378         if (pause_flags & B44_FLAG_TX_PAUSE)
 379                 val |= (MAC_FLOW_PAUSE_ENAB |
 380                         (0xc0 & MAC_FLOW_RX_HI_WATER));
 381         else
 382                 val &= ~MAC_FLOW_PAUSE_ENAB;
 383         bw32(bp, B44_MAC_FLOW, val);
 384 }
 385
 386 static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
 387 {
 388         u32 pause_enab = bp->flags & (B44_FLAG_TX_PAUSE |
 389                                       B44_FLAG_RX_PAUSE);
 390
 391         if (local & ADVERTISE_PAUSE_CAP) {
 392                 if (local & ADVERTISE_PAUSE_ASYM) {
 393                         if (remote & LPA_PAUSE_CAP)
 394                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 395                                                B44_FLAG_RX_PAUSE);
 396                         else if (remote & LPA_PAUSE_ASYM)
 397                                 pause_enab |= B44_FLAG_RX_PAUSE;
 398                 } else {
 399                         if (remote & LPA_PAUSE_CAP)
 400                                 pause_enab |= (B44_FLAG_TX_PAUSE |
 401                                                B44_FLAG_RX_PAUSE);
 402                 }
 403         } else if (local & ADVERTISE_PAUSE_ASYM) {
 404                 if ((remote & LPA_PAUSE_CAP) &&
 405                     (remote & LPA_PAUSE_ASYM))
 406                         pause_enab |= B44_FLAG_TX_PAUSE;
 407         }
 408
 409         __b44_set_flow_ctrl(bp, pause_enab);
 410 }
 411
 412 static int b44_setup_phy(struct b44 *bp)
 413 {
 414         u32 val;
 415         int err;
 416
 417         if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
 418                 goto out;
 419         if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
 420                                 val & MII_ALEDCTRL_ALLMSK)) != 0)
 421                 goto out;
 422         if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
 423                 goto out;
 424         if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
 425                                 val | MII_TLEDCTRL_ENABLE)) != 0)
 426                 goto out;
 427
 428         if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
 429                 u32 adv = ADVERTISE_CSMA;
 430
 431                 if (bp->flags & B44_FLAG_ADV_10HALF)
 432                         adv |= ADVERTISE_10HALF;
 433                 if (bp->flags & B44_FLAG_ADV_10FULL)
 434                         adv |= ADVERTISE_10FULL;
 435                 if (bp->flags & B44_FLAG_ADV_100HALF)
 436                         adv |= ADVERTISE_100HALF;
 437                 if (bp->flags & B44_FLAG_ADV_100FULL)
 438                         adv |= ADVERTISE_100FULL;
 439
 440                 if (bp->flags & B44_FLAG_PAUSE_AUTO)
 441                         adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 442
 443                 if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
 444                         goto out;
 445                 if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
 446                                                        BMCR_ANRESTART))) != 0)
 447                         goto out;
 448         } else {
 449                 u32 bmcr;
 450
 451                 if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
 452                         goto out;
 453                 bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
 454                 if (bp->flags & B44_FLAG_100_BASE_T)
 455                         bmcr |= BMCR_SPEED100;
 456                 if (bp->flags & B44_FLAG_FULL_DUPLEX)
 457                         bmcr |= BMCR_FULLDPLX;
 458                 if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
 459                         goto out;
 460
 461                 /* Since we will not be negotiating there is no safe way
 462                  * to determine if the link partner supports flow control
 463                  * or not.  So just disable it completely in this case.
 464                  */
 465                 b44_set_flow_ctrl(bp, 0, 0);
 466         }
 467
 468 out:
 469         return err;
 470 }
 471
 472 static void b44_stats_update(struct b44 *bp)
 473 {
 474         unsigned long reg;
 475         u32 *val;
 476
 477         val = &bp->hw_stats.tx_good_octets;
 478         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
 479                 *val++ += br32(bp, reg);
 480         }
 481         val = &bp->hw_stats.rx_good_octets;
 482         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
 483                 *val++ += br32(bp, reg);
 484         }
 485 }
 486
 487 static void b44_link_report(struct b44 *bp)
 488 {
 489         if (!netif_carrier_ok(bp->dev)) {
 490                 printk(KERN_INFO PFX "%s: Link is down.\n", bp->dev->name);
 491         } else {
 492                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
 493                        bp->dev->name,
 494                        (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
 495                        (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
 496
 497                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
 498                        "%s for RX.\n",
 499                        bp->dev->name,
 500                        (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
 501                        (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
 502         }
 503 }
 504
 505 static void b44_check_phy(struct b44 *bp)
 506 {
 507         u32 bmsr, aux;
 508
 509         if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
 510             !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
 511             (bmsr != 0xffff)) {
 512                 if (aux & MII_AUXCTRL_SPEED)
 513                         bp->flags |= B44_FLAG_100_BASE_T;
 514                 else
 515                         bp->flags &= ~B44_FLAG_100_BASE_T;
 516                 if (aux & MII_AUXCTRL_DUPLEX)
 517                         bp->flags |= B44_FLAG_FULL_DUPLEX;
 518                 else
 519                         bp->flags &= ~B44_FLAG_FULL_DUPLEX;
 520
 521                 if (!netif_carrier_ok(bp->dev) &&
 522                     (bmsr & BMSR_LSTATUS)) {
 523                         u32 val = br32(bp, B44_TX_CTRL);
 524                         u32 local_adv, remote_adv;
 525
 526                         if (bp->flags & B44_FLAG_FULL_DUPLEX)
 527                                 val |= TX_CTRL_DUPLEX;
 528                         else
 529                                 val &= ~TX_CTRL_DUPLEX;
 530                         bw32(bp, B44_TX_CTRL, val);
 531
 532                         if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
 533                             !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
 534                             !b44_readphy(bp, MII_LPA, &remote_adv))
 535                                 b44_set_flow_ctrl(bp, local_adv, remote_adv);
 536
 537                         /* Link now up */
 538                         netif_carrier_on(bp->dev);
 539                         b44_link_report(bp);
 540                 } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
 541                         /* Link now down */
 542                         netif_carrier_off(bp->dev);
 543                         b44_link_report(bp);
 544                 }
 545
 546                 if (bmsr & BMSR_RFAULT)
 547                         printk(KERN_WARNING PFX "%s: Remote fault detected in PHY\n",
 548                                bp->dev->name);
 549                 if (bmsr & BMSR_JCD)
 550                         printk(KERN_WARNING PFX "%s: Jabber detected in PHY\n",
 551                                bp->dev->name);
 552         }
 553 }
 554
 555 static void b44_timer(unsigned long __opaque)
 556 {
 557         struct b44 *bp = (struct b44 *) __opaque;
 558
 559         spin_lock_irq(&bp->lock);
 560
 561         b44_check_phy(bp);
 562
 563         b44_stats_update(bp);
 564
 565         spin_unlock_irq(&bp->lock);
 566
 567         bp->timer.expires = jiffies + HZ;
 568         add_timer(&bp->timer);
 569 }
 570
 571 static void b44_tx(struct b44 *bp)
 572 {
 573         u32 cur, cons;
 574
 575         cur  = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
 576         cur /= sizeof(struct dma_desc);
 577
 578         /* XXX needs updating when NETIF_F_SG is supported */
 579         for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
 580                 struct ring_info *rp = &bp->tx_buffers[cons];
 581                 struct sk_buff *skb = rp->skb;
 582
 583                 if (unlikely(skb == NULL))
 584                         BUG();
 585
 586                 pci_unmap_single(bp->pdev,
 587                                  pci_unmap_addr(rp, mapping),
 588                                  skb->len,
 589                                  PCI_DMA_TODEVICE);
 590                 rp->skb = NULL;
 591                 dev_kfree_skb_irq(skb);
 592         }
 593
 594         bp->tx_cons = cons;
 595         if (netif_queue_stopped(bp->dev) &&
 596             TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
 597                 netif_wake_queue(bp->dev);
 598
 599         bw32(bp, B44_GPTIMER, 0);
 600 }
 601
 602 /* Works like this.  This chip writes a 'struct rx_header" 30 bytes
 603  * before the DMA address you give it.  So we allocate 30 more bytes
 604  * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
 605  * point the chip at 30 bytes past where the rx_header will go.
 606  */
 607 static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 608 {
 609         struct dma_desc *dp;
 610         struct ring_info *src_map, *map;
 611         struct rx_header *rh;
 612         struct sk_buff *skb;
 613         dma_addr_t mapping;
 614         int dest_idx;
 615         u32 ctrl;
 616
 617         src_map = NULL;
 618         if (src_idx >= 0)
 619                 src_map = &bp->rx_buffers[src_idx];
 620         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 621         map = &bp->rx_buffers[dest_idx];
 622         skb = dev_alloc_skb(RX_PKT_BUF_SZ);
 623         if (skb == NULL)
 624                 return -ENOMEM;
 625
 626         mapping = pci_map_single(bp->pdev, skb->data,
 627                                  RX_PKT_BUF_SZ,
 628                                  PCI_DMA_FROMDEVICE);
 629
 630         /* Hardware bug work-around, the chip is unable to do PCI DMA
 631            to/from anything above 1GB :-( */
 632         if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
 633                 /* Sigh... */
 634                 pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 635                 dev_kfree_skb_any(skb);
 636                 skb = __dev_alloc_skb(RX_PKT_BUF_SZ,GFP_DMA);
 637                 if (skb == NULL)
 638                         return -ENOMEM;
 639                 mapping = pci_map_single(bp->pdev, skb->data,
 640                                          RX_PKT_BUF_SZ,
 641                                          PCI_DMA_FROMDEVICE);
 642                 if(mapping+RX_PKT_BUF_SZ > B44_DMA_MASK) {
 643                         pci_unmap_single(bp->pdev, mapping, RX_PKT_BUF_SZ,PCI_DMA_FROMDEVICE);
 644                         dev_kfree_skb_any(skb);
 645                         return -ENOMEM;
 646                 }
 647         }
 648
 649         skb->dev = bp->dev;
 650         skb_reserve(skb, bp->rx_offset);
 651
 652         rh = (struct rx_header *)
 653                 (skb->data - bp->rx_offset);
 654         rh->len = 0;
 655         rh->flags = 0;
 656
 657         map->skb = skb;
 658         pci_unmap_addr_set(map, mapping, mapping);
 659
 660         if (src_map != NULL)
 661                 src_map->skb = NULL;
 662
 663         ctrl  = (DESC_CTRL_LEN & (RX_PKT_BUF_SZ - bp->rx_offset));
 664         if (dest_idx == (B44_RX_RING_SIZE - 1))
 665                 ctrl |= DESC_CTRL_EOT;
 666
 667         dp = &bp->rx_ring[dest_idx];
 668         dp->ctrl = cpu_to_le32(ctrl);
 669         dp->addr = cpu_to_le32((u32) mapping + bp->rx_offset + bp->dma_offset);
 670
 671         return RX_PKT_BUF_SZ;
 672 }
 673
 674 static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
 675 {
 676         struct dma_desc *src_desc, *dest_desc;
 677         struct ring_info *src_map, *dest_map;
 678         struct rx_header *rh;
 679         int dest_idx;
 680         u32 ctrl;
 681
 682         dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
 683         dest_desc = &bp->rx_ring[dest_idx];
 684         dest_map = &bp->rx_buffers[dest_idx];
 685         src_desc = &bp->rx_ring[src_idx];
 686         src_map = &bp->rx_buffers[src_idx];
 687
 688         dest_map->skb = src_map->skb;
 689         rh = (struct rx_header *) src_map->skb->data;
 690         rh->len = 0;
 691         rh->flags = 0;
 692         pci_unmap_addr_set(dest_map, mapping,
 693                            pci_unmap_addr(src_map, mapping));
 694
 695         ctrl = src_desc->ctrl;
 696         if (dest_idx == (B44_RX_RING_SIZE - 1))
 697                 ctrl |= cpu_to_le32(DESC_CTRL_EOT);
 698         else
 699                 ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
 700
 701         dest_desc->ctrl = ctrl;
 702         dest_desc->addr = src_desc->addr;
 703         src_map->skb = NULL;
 704
 705         pci_dma_sync_single_for_device(bp->pdev, src_desc->addr,
 706                                        RX_PKT_BUF_SZ,
 707                                        PCI_DMA_FROMDEVICE);
 708 }
 709
 710 static int b44_rx(struct b44 *bp, int budget)
 711 {
 712         int received;
 713         u32 cons, prod;
 714
 715         received = 0;
 716         prod  = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
 717         prod /= sizeof(struct dma_desc);
 718         cons = bp->rx_cons;
 719
 720         while (cons != prod && budget > 0) {
 721                 struct ring_info *rp = &bp->rx_buffers[cons];
 722                 struct sk_buff *skb = rp->skb;
 723                 dma_addr_t map = pci_unmap_addr(rp, mapping);
 724                 struct rx_header *rh;
 725                 u16 len;
 726
 727                 pci_dma_sync_single_for_cpu(bp->pdev, map,
 728                                             RX_PKT_BUF_SZ,
 729                                             PCI_DMA_FROMDEVICE);
 730                 rh = (struct rx_header *) skb->data;
 731                 len = cpu_to_le16(rh->len);
 732                 if ((len > (RX_PKT_BUF_SZ - bp->rx_offset)) ||
 733                     (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
 734                 drop_it:
 735                         b44_recycle_rx(bp, cons, bp->rx_prod);
 736                 drop_it_no_recycle:
 737                         bp->stats.rx_dropped++;
 738                         goto next_pkt;
 739                 }
 740
 741                 if (len == 0) {
 742                         int i = 0;
 743
 744                         do {
 745                                 udelay(2);
 746                                 barrier();
 747                                 len = cpu_to_le16(rh->len);
 748                         } while (len == 0 && i++ < 5);
 749                         if (len == 0)
 750                                 goto drop_it;
 751                 }
 752
 753                 /* Omit CRC. */
 754                 len -= 4;
 755
 756                 if (len > RX_COPY_THRESHOLD) {
 757                         int skb_size;
 758                         skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
 759                         if (skb_size < 0)
 760                                 goto drop_it;
 761                         pci_unmap_single(bp->pdev, map,
 762                                          skb_size, PCI_DMA_FROMDEVICE);
 763                         /* Leave out rx_header */
 764                         skb_put(skb, len+bp->rx_offset);
 765                         skb_pull(skb,bp->rx_offset);
 766                 } else {
 767                         struct sk_buff *copy_skb;
 768
 769                         b44_recycle_rx(bp, cons, bp->rx_prod);
 770                         copy_skb = dev_alloc_skb(len + 2);
 771                         if (copy_skb == NULL)
 772                                 goto drop_it_no_recycle;
 773
 774                         copy_skb->dev = bp->dev;
 775                         skb_reserve(copy_skb, 2);
 776                         skb_put(copy_skb, len);
 777                         /* DMA sync done above, copy just the actual packet */
 778                         memcpy(copy_skb->data, skb->data+bp->rx_offset, len);
 779
 780                         skb = copy_skb;
 781                 }
 782                 skb->ip_summed = CHECKSUM_NONE;
 783                 skb->protocol = eth_type_trans(skb, bp->dev);
 784                 netif_receive_skb(skb);
 785                 bp->dev->last_rx = jiffies;
 786                 received++;
 787                 budget--;
 788         next_pkt:
 789                 bp->rx_prod = (bp->rx_prod + 1) &
 790                         (B44_RX_RING_SIZE - 1);
 791                 cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
 792         }
 793
 794         bp->rx_cons = cons;
 795         bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
 796
 797         return received;
 798 }
 799
 800 static int b44_poll(struct net_device *netdev, int *budget)
 801 {
 802         struct b44 *bp = netdev_priv(netdev);
 803         int done;
 804
 805         spin_lock_irq(&bp->lock);
 806
 807         if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
 808                 /* spin_lock(&bp->tx_lock); */
 809                 b44_tx(bp);
 810                 /* spin_unlock(&bp->tx_lock); */
 811         }
 812         spin_unlock_irq(&bp->lock);
 813
 814         done = 1;
 815         if (bp->istat & ISTAT_RX) {
 816                 int orig_budget = *budget;
 817                 int work_done;
 818
 819                 if (orig_budget > netdev->quota)
 820                         orig_budget = netdev->quota;
 821
 822                 work_done = b44_rx(bp, orig_budget);
 823
 824                 *budget -= work_done;
 825                 netdev->quota -= work_done;
 826
 827                 if (work_done >= orig_budget)
 828                         done = 0;
 829         }
 830
 831         if (bp->istat & ISTAT_ERRORS) {
 832                 spin_lock_irq(&bp->lock);
 833                 b44_halt(bp);
 834                 b44_init_rings(bp);
 835                 b44_init_hw(bp);
 836                 netif_wake_queue(bp->dev);
 837                 spin_unlock_irq(&bp->lock);
 838                 done = 1;
 839         }
 840
 841         if (done) {
 842                 netif_rx_complete(netdev);
 843                 b44_enable_ints(bp);
 844         }
 845
 846         return (done ? 0 : 1);
 847 }
 848
 849 static irqreturn_t b44_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 850 {
 851         struct net_device *dev = dev_id;
 852         struct b44 *bp = netdev_priv(dev);
 853         unsigned long flags;
 854         u32 istat, imask;
 855         int handled = 0;
 856
 857         spin_lock_irqsave(&bp->lock, flags);
 858
 859         istat = br32(bp, B44_ISTAT);
 860         imask = br32(bp, B44_IMASK);
 861
 862         /* ??? What the fuck is the purpose of the interrupt mask
 863          * ??? register if we have to mask it out by hand anyways?
 864          */
 865         istat &= imask;
 866         if (istat) {
 867                 handled = 1;
 868                 if (netif_rx_schedule_prep(dev)) {
 869                         /* NOTE: These writes are posted by the readback of
 870                          *       the ISTAT register below.
 871                          */
 872                         bp->istat = istat;
 873                         __b44_disable_ints(bp);
 874                         __netif_rx_schedule(dev);
 875                 } else {
 876                         printk(KERN_ERR PFX "%s: Error, poll already scheduled\n",
 877                                dev->name);
 878                 }
 879
 880                 bw32(bp, B44_ISTAT, istat);
 881                 br32(bp, B44_ISTAT);
 882         }
 883         spin_unlock_irqrestore(&bp->lock, flags);
 884         return IRQ_RETVAL(handled);
 885 }
 886
 887 static void b44_tx_timeout(struct net_device *dev)
 888 {
 889         struct b44 *bp = netdev_priv(dev);
 890
 891         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
 892                dev->name);
 893
 894         spin_lock_irq(&bp->lock);
 895
 896         b44_halt(bp);
 897         b44_init_rings(bp);
 898         b44_init_hw(bp);
 899
 900         spin_unlock_irq(&bp->lock);
 901
 902         b44_enable_ints(bp);
 903
 904         netif_wake_queue(dev);
 905 }
 906
 907 static int b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
 908 {
 909         struct b44 *bp = netdev_priv(dev);
 910         dma_addr_t mapping;
 911         u32 len, entry, ctrl;
 912
 913         len = skb->len;
 914         spin_lock_irq(&bp->lock);
 915
 916         /* This is a hard error, log it. */
 917         if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
 918                 netif_stop_queue(dev);
 919                 spin_unlock_irq(&bp->lock);
 920                 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
 921                        dev->name);
 922                 return 1;
 923         }
 924
 925         entry = bp->tx_prod;
 926         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
 927         if(mapping+len > B44_DMA_MASK) {
 928                 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
 929                 pci_unmap_single(bp->pdev, mapping, len,PCI_DMA_TODEVICE);
 930                 memcpy(bp->tx_bufs+entry*TX_PKT_BUF_SZ,skb->data,skb->len);
 931                 mapping = pci_map_single(bp->pdev, bp->tx_bufs+entry*TX_PKT_BUF_SZ, len, PCI_DMA_TODEVICE);
 932         }
 933
 934         bp->tx_buffers[entry].skb = skb;
 935         pci_unmap_addr_set(&bp->tx_buffers[entry], mapping, mapping);
 936
 937         ctrl  = (len & DESC_CTRL_LEN);
 938         ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
 939         if (entry == (B44_TX_RING_SIZE - 1))
 940                 ctrl |= DESC_CTRL_EOT;
 941
 942         bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
 943         bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
 944
 945         entry = NEXT_TX(entry);
 946
 947         bp->tx_prod = entry;
 948
 949         wmb();
 950
 951         bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 952         if (bp->flags & B44_FLAG_BUGGY_TXPTR)
 953                 bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
 954         if (bp->flags & B44_FLAG_REORDER_BUG)
 955                 br32(bp, B44_DMATX_PTR);
 956
 957         if (TX_BUFFS_AVAIL(bp) < 1)
 958                 netif_stop_queue(dev);
 959
 960         spin_unlock_irq(&bp->lock);
 961
 962         dev->trans_start = jiffies;
 963
 964         return 0;
 965 }
 966
 967 static int b44_change_mtu(struct net_device *dev, int new_mtu)
 968 {
 969         struct b44 *bp = netdev_priv(dev);
 970
 971         if (new_mtu < B44_MIN_MTU || new_mtu > B44_MAX_MTU)
 972                 return -EINVAL;
 973
 974         if (!netif_running(dev)) {
 975                 /* We'll just catch it later when the
 976                  * device is up'd.
 977                  */
 978                 dev->mtu = new_mtu;
 979                 return 0;
 980         }
 981
 982         spin_lock_irq(&bp->lock);
 983         b44_halt(bp);
 984         dev->mtu = new_mtu;
 985         b44_init_rings(bp);
 986         b44_init_hw(bp);
 987         spin_unlock_irq(&bp->lock);
 988
 989         b44_enable_ints(bp);
 990
 991         return 0;
 992 }
 993
 994 /* Free up pending packets in all rx/tx rings.
 995  *
 996  * The chip has been shut down and the driver detached from
 997  * the networking, so no interrupts or new tx packets will
 998  * end up in the driver.  bp->lock is not held and we are not
 999  * in an interrupt context and thus may sleep.
1000  */
1001 static void b44_free_rings(struct b44 *bp)
1002 {
1003         struct ring_info *rp;
1004         int i;
1005
1006         for (i = 0; i < B44_RX_RING_SIZE; i++) {
1007                 rp = &bp->rx_buffers[i];
1008
1009                 if (rp->skb == NULL)
1010                         continue;
1011                 pci_unmap_single(bp->pdev,
1012                                  pci_unmap_addr(rp, mapping),
1013                                  RX_PKT_BUF_SZ,
1014                                  PCI_DMA_FROMDEVICE);
1015                 dev_kfree_skb_any(rp->skb);
1016                 rp->skb = NULL;
1017         }
1018
1019         /* XXX needs changes once NETIF_F_SG is set... */
1020         for (i = 0; i < B44_TX_RING_SIZE; i++) {
1021                 rp = &bp->tx_buffers[i];
1022
1023                 if (rp->skb == NULL)
1024                         continue;
1025                 pci_unmap_single(bp->pdev,
1026                                  pci_unmap_addr(rp, mapping),
1027                                  rp->skb->len,
1028                                  PCI_DMA_TODEVICE);
1029                 dev_kfree_skb_any(rp->skb);
1030                 rp->skb = NULL;
1031         }
1032 }
1033
1034 /* Initialize tx/rx rings for packet processing.
1035  *
1036  * The chip has been shut down and the driver detached from
1037  * the networking, so no interrupts or new tx packets will
1038  * end up in the driver.  bp->lock is not held and we are not
1039  * in an interrupt context and thus may sleep.
1040  */
1041 static void b44_init_rings(struct b44 *bp)
1042 {
1043         int i;
1044
1045         b44_free_rings(bp);
1046
1047         memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
1048         memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
1049
1050         for (i = 0; i < bp->rx_pending; i++) {
1051                 if (b44_alloc_rx_skb(bp, -1, i) < 0)
1052                         break;
1053         }
1054 }
1055
1056 /*
1057  * Must not be invoked with interrupt sources disabled and
1058  * the hardware shutdown down.
1059  */
1060 static void b44_free_consistent(struct b44 *bp)
1061 {
1062         if (bp->rx_buffers) {
1063                 kfree(bp->rx_buffers);
1064                 bp->rx_buffers = NULL;
1065         }
1066         if (bp->tx_buffers) {
1067                 kfree(bp->tx_buffers);
1068                 bp->tx_buffers = NULL;
1069         }
1070         if (bp->rx_ring) {
1071                 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1072                                     bp->rx_ring, bp->rx_ring_dma);
1073                 bp->rx_ring = NULL;
1074         }
1075         if (bp->tx_ring) {
1076                 pci_free_consistent(bp->pdev, DMA_TABLE_BYTES,
1077                                     bp->tx_ring, bp->tx_ring_dma);
1078                 bp->tx_ring = NULL;
1079         }
1080         if (bp->tx_bufs) {
1081                 pci_free_consistent(bp->pdev, B44_TX_RING_SIZE * TX_PKT_BUF_SZ,
1082                                     bp->tx_bufs, bp->tx_bufs_dma);
1083                 bp->tx_bufs = NULL;
1084         }
1085 }
1086
1087 /*
1088  * Must not be invoked with interrupt sources disabled and
1089  * the hardware shutdown down.  Can sleep.
1090  */
1091 static int b44_alloc_consistent(struct b44 *bp)
1092 {
1093         int size;
1094
1095         size  = B44_RX_RING_SIZE * sizeof(struct ring_info);
1096         bp->rx_buffers = kmalloc(size, GFP_KERNEL);
1097         if (!bp->rx_buffers)
1098                 goto out_err;
1099         memset(bp->rx_buffers, 0, size);
1100
1101         size = B44_TX_RING_SIZE * sizeof(struct ring_info);
1102         bp->tx_buffers = kmalloc(size, GFP_KERNEL);
1103         if (!bp->tx_buffers)
1104                 goto out_err;
1105         memset(bp->tx_buffers, 0, size);
1106
1107         size = B44_TX_RING_SIZE * TX_PKT_BUF_SZ;
1108         bp->tx_bufs = pci_alloc_consistent(bp->pdev, size, &bp->tx_bufs_dma);
1109         if (!bp->tx_bufs)
1110                 goto out_err;
1111         memset(bp->tx_bufs, 0, size);
1112
1113         size = DMA_TABLE_BYTES;
1114         bp->rx_ring = pci_alloc_consistent(bp->pdev, size, &bp->rx_ring_dma);
1115         if (!bp->rx_ring)
1116                 goto out_err;
1117
1118         bp->tx_ring = pci_alloc_consistent(bp->pdev, size, &bp->tx_ring_dma);
1119         if (!bp->tx_ring)
1120                 goto out_err;
1121
1122         return 0;
1123
1124 out_err:
1125         b44_free_consistent(bp);
1126         return -ENOMEM;
1127 }
1128
1129 /* bp->lock is held. */
1130 static void b44_clear_stats(struct b44 *bp)
1131 {
1132         unsigned long reg;
1133
1134         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1135         for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
1136                 br32(bp, reg);
1137         for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
1138                 br32(bp, reg);
1139 }
1140
1141 /* bp->lock is held. */
1142 static void b44_chip_reset(struct b44 *bp)
1143 {
1144         if (ssb_is_core_up(bp)) {
1145                 bw32(bp, B44_RCV_LAZY, 0);
1146                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
1147                 b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 100, 1);
1148                 bw32(bp, B44_DMATX_CTRL, 0);
1149                 bp->tx_prod = bp->tx_cons = 0;
1150                 if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
1151                         b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
1152                                      100, 0);
1153                 }
1154                 bw32(bp, B44_DMARX_CTRL, 0);
1155                 bp->rx_prod = bp->rx_cons = 0;
1156         } else {
1157                 ssb_pci_setup(bp, (bp->core_unit == 0 ?
1158                                    SBINTVEC_ENET0 :
1159                                    SBINTVEC_ENET1));
1160         }
1161
1162         ssb_core_reset(bp);
1163
1164         b44_clear_stats(bp);
1165
1166         /* Make PHY accessible. */
1167         bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
1168                              (0x0d & MDIO_CTRL_MAXF_MASK)));
1169         br32(bp, B44_MDIO_CTRL);
1170
1171         if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
1172                 bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
1173                 br32(bp, B44_ENET_CTRL);
1174                 bp->flags &= ~B44_FLAG_INTERNAL_PHY;
1175         } else {
1176                 u32 val = br32(bp, B44_DEVCTRL);
1177
1178                 if (val & DEVCTRL_EPR) {
1179                         bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
1180                         br32(bp, B44_DEVCTRL);
1181                         udelay(100);
1182                 }
1183                 bp->flags |= B44_FLAG_INTERNAL_PHY;
1184         }
1185 }
1186
1187 /* bp->lock is held. */
1188 static void b44_halt(struct b44 *bp)
1189 {
1190         b44_disable_ints(bp);
1191         b44_chip_reset(bp);
1192 }
1193
1194 /* bp->lock is held. */
1195 static void __b44_set_mac_addr(struct b44 *bp)
1196 {
1197         bw32(bp, B44_CAM_CTRL, 0);
1198         if (!(bp->dev->flags & IFF_PROMISC)) {
1199                 u32 val;
1200
1201                 __b44_cam_write(bp, bp->dev->dev_addr, 0);
1202                 val = br32(bp, B44_CAM_CTRL);
1203                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1204         }
1205 }
1206
1207 static int b44_set_mac_addr(struct net_device *dev, void *p)
1208 {
1209         struct b44 *bp = netdev_priv(dev);
1210         struct sockaddr *addr = p;
1211
1212         if (netif_running(dev))
1213                 return -EBUSY;
1214
1215         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1216
1217         spin_lock_irq(&bp->lock);
1218         __b44_set_mac_addr(bp);
1219         spin_unlock_irq(&bp->lock);
1220
1221         return 0;
1222 }
1223
1224 /* Called at device open time to get the chip ready for
1225  * packet processing.  Invoked with bp->lock held.
1226  */
1227 static void __b44_set_rx_mode(struct net_device *);
1228 static void b44_init_hw(struct b44 *bp)
1229 {
1230         u32 val;
1231
1232         b44_chip_reset(bp);
1233         b44_phy_reset(bp);
1234         b44_setup_phy(bp);
1235
1236         /* Enable CRC32, set proper LED modes and power on PHY */
1237         bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
1238         bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
1239
1240         /* This sets the MAC address too.  */
1241         __b44_set_rx_mode(bp->dev);
1242
1243         /* MTU + eth header + possible VLAN tag + struct rx_header */
1244         bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1245         bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
1246
1247         bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
1248         bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
1249         bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
1250         bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
1251                               (bp->rx_offset << DMARX_CTRL_ROSHIFT)));
1252         bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
1253
1254         bw32(bp, B44_DMARX_PTR, bp->rx_pending);
1255         bp->rx_prod = bp->rx_pending;
1256
1257         bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
1258
1259         val = br32(bp, B44_ENET_CTRL);
1260         bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
1261 }
1262
1263 static int b44_open(struct net_device *dev)
1264 {
1265         struct b44 *bp = netdev_priv(dev);
1266         int err;
1267
1268         err = b44_alloc_consistent(bp);
1269         if (err)
1270                 return err;
1271
1272         err = request_irq(dev->irq, b44_interrupt, SA_SHIRQ, dev->name, dev);
1273         if (err)
1274                 goto err_out_free;
1275
1276         spin_lock_irq(&bp->lock);
1277
1278         b44_init_rings(bp);
1279         b44_init_hw(bp);
1280         bp->flags |= B44_FLAG_INIT_COMPLETE;
1281
1282         spin_unlock_irq(&bp->lock);
1283
1284         init_timer(&bp->timer);
1285         bp->timer.expires = jiffies + HZ;
1286         bp->timer.data = (unsigned long) bp;
1287         bp->timer.function = b44_timer;
1288         add_timer(&bp->timer);
1289
1290         b44_enable_ints(bp);
1291
1292         return 0;
1293
1294 err_out_free:
1295         b44_free_consistent(bp);
1296         return err;
1297 }
1298
1299 #if 0
1300 /*static*/ void b44_dump_state(struct b44 *bp)
1301 {
1302         u32 val32, val32_2, val32_3, val32_4, val32_5;
1303         u16 val16;
1304
1305         pci_read_config_word(bp->pdev, PCI_STATUS, &val16);
1306         printk("DEBUG: PCI status [%04x] \n", val16);
1307
1308 }
1309 #endif
1310
1311 #ifdef CONFIG_NET_POLL_CONTROLLER
1312 /*
1313  * Polling receive - used by netconsole and other diagnostic tools
1314  * to allow network i/o with interrupts disabled.
1315  */
1316 static void b44_poll_controller(struct net_device *dev)
1317 {
1318         disable_irq(dev->irq);
1319         b44_interrupt(dev->irq, dev, NULL);
1320         enable_irq(dev->irq);
1321 }
1322 #endif
1323
1324 static int b44_close(struct net_device *dev)
1325 {
1326         struct b44 *bp = netdev_priv(dev);
1327
1328         netif_stop_queue(dev);
1329
1330         del_timer_sync(&bp->timer);
1331
1332         spin_lock_irq(&bp->lock);
1333
1334 #if 0
1335         b44_dump_state(bp);
1336 #endif
1337         b44_halt(bp);
1338         b44_free_rings(bp);
1339         bp->flags &= ~B44_FLAG_INIT_COMPLETE;
1340         netif_carrier_off(bp->dev);
1341
1342         spin_unlock_irq(&bp->lock);
1343
1344         free_irq(dev->irq, dev);
1345
1346         b44_free_consistent(bp);
1347
1348         return 0;
1349 }
1350
1351 static struct net_device_stats *b44_get_stats(struct net_device *dev)
1352 {
1353         struct b44 *bp = netdev_priv(dev);
1354         struct net_device_stats *nstat = &bp->stats;
1355         struct b44_hw_stats *hwstat = &bp->hw_stats;
1356
1357         /* Convert HW stats into netdevice stats. */
1358         nstat->rx_packets = hwstat->rx_pkts;
1359         nstat->tx_packets = hwstat->tx_pkts;
1360         nstat->rx_bytes   = hwstat->rx_octets;
1361         nstat->tx_bytes   = hwstat->tx_octets;
1362         nstat->tx_errors  = (hwstat->tx_jabber_pkts +
1363                              hwstat->tx_oversize_pkts +
1364                              hwstat->tx_underruns +
1365                              hwstat->tx_excessive_cols +
1366                              hwstat->tx_late_cols);
1367         nstat->multicast  = hwstat->tx_multicast_pkts;
1368         nstat->collisions = hwstat->tx_total_cols;
1369
1370         nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1371                                    hwstat->rx_undersize);
1372         nstat->rx_over_errors   = hwstat->rx_missed_pkts;
1373         nstat->rx_frame_errors  = hwstat->rx_align_errs;
1374         nstat->rx_crc_errors    = hwstat->rx_crc_errs;
1375         nstat->rx_errors        = (hwstat->rx_jabber_pkts +
1376                                    hwstat->rx_oversize_pkts +
1377                                    hwstat->rx_missed_pkts +
1378                                    hwstat->rx_crc_align_errs +
1379                                    hwstat->rx_undersize +
1380                                    hwstat->rx_crc_errs +
1381                                    hwstat->rx_align_errs +
1382                                    hwstat->rx_symbol_errs);
1383
1384         nstat->tx_aborted_errors = hwstat->tx_underruns;
1385 #if 0
1386         /* Carrier lost counter seems to be broken for some devices */
1387         nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
1388 #endif
1389
1390         return nstat;
1391 }
1392
1393 static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
1394 {
1395         struct dev_mc_list *mclist;
1396         int i, num_ents;
1397
1398         num_ents = min_t(int, dev->mc_count, B44_MCAST_TABLE_SIZE);
1399         mclist = dev->mc_list;
1400         for (i = 0; mclist && i < num_ents; i++, mclist = mclist->next) {
1401                 __b44_cam_write(bp, mclist->dmi_addr, i + 1);
1402         }
1403         return i+1;
1404 }
1405
1406 static void __b44_set_rx_mode(struct net_device *dev)
1407 {
1408         struct b44 *bp = netdev_priv(dev);
1409         u32 val;
1410         int i=0;
1411         unsigned char zero[6] = {0,0,0,0,0,0};
1412
1413         val = br32(bp, B44_RXCONFIG);
1414         val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
1415         if (dev->flags & IFF_PROMISC) {
1416                 val |= RXCONFIG_PROMISC;
1417                 bw32(bp, B44_RXCONFIG, val);
1418         } else {
1419                 __b44_set_mac_addr(bp);
1420
1421                 if (dev->flags & IFF_ALLMULTI)
1422                         val |= RXCONFIG_ALLMULTI;
1423                 else
1424                         i=__b44_load_mcast(bp, dev);
1425
1426                 for(;i<64;i++) {
1427                         __b44_cam_write(bp, zero, i);
1428                 }
1429                 bw32(bp, B44_RXCONFIG, val);
1430                 val = br32(bp, B44_CAM_CTRL);
1431                 bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
1432         }
1433 }
1434
1435 static void b44_set_rx_mode(struct net_device *dev)
1436 {
1437         struct b44 *bp = netdev_priv(dev);
1438
1439         spin_lock_irq(&bp->lock);
1440         __b44_set_rx_mode(dev);
1441         spin_unlock_irq(&bp->lock);
1442 }
1443
1444 static u32 b44_get_msglevel(struct net_device *dev)
1445 {
1446         struct b44 *bp = netdev_priv(dev);
1447         return bp->msg_enable;
1448 }
1449
1450 static void b44_set_msglevel(struct net_device *dev, u32 value)
1451 {
1452         struct b44 *bp = netdev_priv(dev);
1453         bp->msg_enable = value;
1454 }
1455
1456 static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1457 {
1458         struct b44 *bp = netdev_priv(dev);
1459         struct pci_dev *pci_dev = bp->pdev;
1460
1461         strcpy (info->driver, DRV_MODULE_NAME);
1462         strcpy (info->version, DRV_MODULE_VERSION);
1463         strcpy (info->bus_info, pci_name(pci_dev));
1464 }
1465
1466 static int b44_nway_reset(struct net_device *dev)
1467 {
1468         struct b44 *bp = netdev_priv(dev);
1469         u32 bmcr;
1470         int r;
1471
1472         spin_lock_irq(&bp->lock);
1473         b44_readphy(bp, MII_BMCR, &bmcr);
1474         b44_readphy(bp, MII_BMCR, &bmcr);
1475         r = -EINVAL;
1476         if (bmcr & BMCR_ANENABLE) {
1477                 b44_writephy(bp, MII_BMCR,
1478                              bmcr | BMCR_ANRESTART);
1479                 r = 0;
1480         }
1481         spin_unlock_irq(&bp->lock);
1482
1483         return r;
1484 }
1485
1486 static int b44_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1487 {
1488         struct b44 *bp = netdev_priv(dev);
1489
1490         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1491                 return -EAGAIN;
1492         cmd->supported = (SUPPORTED_Autoneg);
1493         cmd->supported |= (SUPPORTED_100baseT_Half |
1494                           SUPPORTED_100baseT_Full |
1495                           SUPPORTED_10baseT_Half |
1496                           SUPPORTED_10baseT_Full |
1497                           SUPPORTED_MII);
1498
1499         cmd->advertising = 0;
1500         if (bp->flags & B44_FLAG_ADV_10HALF)
1501                 cmd->advertising |= ADVERTISE_10HALF;
1502         if (bp->flags & B44_FLAG_ADV_10FULL)
1503                 cmd->advertising |= ADVERTISE_10FULL;
1504         if (bp->flags & B44_FLAG_ADV_100HALF)
1505                 cmd->advertising |= ADVERTISE_100HALF;
1506         if (bp->flags & B44_FLAG_ADV_100FULL)
1507                 cmd->advertising |= ADVERTISE_100FULL;
1508         cmd->advertising |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1509         cmd->speed = (bp->flags & B44_FLAG_100_BASE_T) ?
1510                 SPEED_100 : SPEED_10;
1511         cmd->duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
1512                 DUPLEX_FULL : DUPLEX_HALF;
1513         cmd->port = 0;
1514         cmd->phy_address = bp->phy_addr;
1515         cmd->transceiver = (bp->flags & B44_FLAG_INTERNAL_PHY) ?
1516                 XCVR_INTERNAL : XCVR_EXTERNAL;
1517         cmd->autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
1518                 AUTONEG_DISABLE : AUTONEG_ENABLE;
1519         cmd->maxtxpkt = 0;
1520         cmd->maxrxpkt = 0;
1521         return 0;
1522 }
1523
1524 static int b44_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1525 {
1526         struct b44 *bp = netdev_priv(dev);
1527
1528         if (!(bp->flags & B44_FLAG_INIT_COMPLETE))
1529                 return -EAGAIN;
1530
1531         /* We do not support gigabit. */
1532         if (cmd->autoneg == AUTONEG_ENABLE) {
1533                 if (cmd->advertising &
1534                     (ADVERTISED_1000baseT_Half |
1535                      ADVERTISED_1000baseT_Full))
1536                         return -EINVAL;
1537         } else if ((cmd->speed != SPEED_100 &&
1538                     cmd->speed != SPEED_10) ||
1539                    (cmd->duplex != DUPLEX_HALF &&
1540                     cmd->duplex != DUPLEX_FULL)) {
1541                         return -EINVAL;
1542         }
1543
1544         spin_lock_irq(&bp->lock);
1545
1546         if (cmd->autoneg == AUTONEG_ENABLE) {
1547                 bp->flags &= ~B44_FLAG_FORCE_LINK;
1548                 bp->flags &= ~(B44_FLAG_ADV_10HALF |
1549                                B44_FLAG_ADV_10FULL |
1550                                B44_FLAG_ADV_100HALF |
1551                                B44_FLAG_ADV_100FULL);
1552                 if (cmd->advertising & ADVERTISE_10HALF)
1553                         bp->flags |= B44_FLAG_ADV_10HALF;
1554                 if (cmd->advertising & ADVERTISE_10FULL)
1555                         bp->flags |= B44_FLAG_ADV_10FULL;
1556                 if (cmd->advertising & ADVERTISE_100HALF)
1557                         bp->flags |= B44_FLAG_ADV_100HALF;
1558                 if (cmd->advertising & ADVERTISE_100FULL)
1559                         bp->flags |= B44_FLAG_ADV_100FULL;
1560         } else {
1561                 bp->flags |= B44_FLAG_FORCE_LINK;
1562                 if (cmd->speed == SPEED_100)
1563                         bp->flags |= B44_FLAG_100_BASE_T;
1564                 if (cmd->duplex == DUPLEX_FULL)
1565                         bp->flags |= B44_FLAG_FULL_DUPLEX;
1566         }
1567
1568         b44_setup_phy(bp);
1569
1570         spin_unlock_irq(&bp->lock);
1571
1572         return 0;
1573 }
1574
1575 static void b44_get_ringparam(struct net_device *dev,
1576                               struct ethtool_ringparam *ering)
1577 {
1578         struct b44 *bp = netdev_priv(dev);
1579
1580         ering->rx_max_pending = B44_RX_RING_SIZE - 1;
1581         ering->rx_pending = bp->rx_pending;
1582
1583         /* XXX ethtool lacks a tx_max_pending, oops... */
1584 }
1585
1586 static int b44_set_ringparam(struct net_device *dev,
1587                              struct ethtool_ringparam *ering)
1588 {
1589         struct b44 *bp = netdev_priv(dev);
1590
1591         if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
1592             (ering->rx_mini_pending != 0) ||
1593             (ering->rx_jumbo_pending != 0) ||
1594             (ering->tx_pending > B44_TX_RING_SIZE - 1))
1595                 return -EINVAL;
1596
1597         spin_lock_irq(&bp->lock);
1598
1599         bp->rx_pending = ering->rx_pending;
1600         bp->tx_pending = ering->tx_pending;
1601
1602         b44_halt(bp);
1603         b44_init_rings(bp);
1604         b44_init_hw(bp);
1605         netif_wake_queue(bp->dev);
1606         spin_unlock_irq(&bp->lock);
1607
1608         b44_enable_ints(bp);
1609
1610         return 0;
1611 }
1612
1613 static void b44_get_pauseparam(struct net_device *dev,
1614                                 struct ethtool_pauseparam *epause)
1615 {
1616         struct b44 *bp = netdev_priv(dev);
1617
1618         epause->autoneg =
1619                 (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
1620         epause->rx_pause =
1621                 (bp->flags & B44_FLAG_RX_PAUSE) != 0;
1622         epause->tx_pause =
1623                 (bp->flags & B44_FLAG_TX_PAUSE) != 0;
1624 }
1625
1626 static int b44_set_pauseparam(struct net_device *dev,
1627                                 struct ethtool_pauseparam *epause)
1628 {
1629         struct b44 *bp = netdev_priv(dev);
1630
1631         spin_lock_irq(&bp->lock);
1632         if (epause->autoneg)
1633                 bp->flags |= B44_FLAG_PAUSE_AUTO;
1634         else
1635                 bp->flags &= ~B44_FLAG_PAUSE_AUTO;
1636         if (epause->rx_pause)
1637                 bp->flags |= B44_FLAG_RX_PAUSE;
1638         else
1639                 bp->flags &= ~B44_FLAG_RX_PAUSE;
1640         if (epause->tx_pause)
1641                 bp->flags |= B44_FLAG_TX_PAUSE;
1642         else
1643                 bp->flags &= ~B44_FLAG_TX_PAUSE;
1644         if (bp->flags & B44_FLAG_PAUSE_AUTO) {
1645                 b44_halt(bp);
1646                 b44_init_rings(bp);
1647                 b44_init_hw(bp);
1648         } else {
1649                 __b44_set_flow_ctrl(bp, bp->flags);
1650         }
1651         spin_unlock_irq(&bp->lock);
1652
1653         b44_enable_ints(bp);
1654
1655         return 0;
1656 }
1657
1658 static struct ethtool_ops b44_ethtool_ops = {
1659         .get_drvinfo            = b44_get_drvinfo,
1660         .get_settings           = b44_get_settings,
1661         .set_settings           = b44_set_settings,
1662         .nway_reset             = b44_nway_reset,
1663         .get_link               = ethtool_op_get_link,
1664         .get_ringparam          = b44_get_ringparam,
1665         .set_ringparam          = b44_set_ringparam,
1666         .get_pauseparam         = b44_get_pauseparam,
1667         .set_pauseparam         = b44_set_pauseparam,
1668         .get_msglevel           = b44_get_msglevel,
1669         .set_msglevel           = b44_set_msglevel,
1670 };
1671
1672 static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1673 {
1674         struct mii_ioctl_data *data = if_mii(ifr);
1675         struct b44 *bp = netdev_priv(dev);
1676         int err;
1677
1678         spin_lock_irq(&bp->lock);
1679         err = generic_mii_ioctl(&bp->mii_if, data, cmd, NULL);
1680         spin_unlock_irq(&bp->lock);
1681
1682         return err;
1683 }
1684
1685 /* Read 128-bytes of EEPROM. */
1686 static int b44_read_eeprom(struct b44 *bp, u8 *data)
1687 {
1688         long i;
1689         u16 *ptr = (u16 *) data;
1690
1691         for (i = 0; i < 128; i += 2)
1692                 ptr[i / 2] = readw(bp->regs + 4096 + i);
1693
1694         return 0;
1695 }
1696
1697 static int __devinit b44_get_invariants(struct b44 *bp)
1698 {
1699         u8 eeprom[128];
1700         int err;
1701
1702         err = b44_read_eeprom(bp, &eeprom[0]);
1703         if (err)
1704                 goto out;
1705
1706         bp->dev->dev_addr[0] = eeprom[79];
1707         bp->dev->dev_addr[1] = eeprom[78];
1708         bp->dev->dev_addr[2] = eeprom[81];
1709         bp->dev->dev_addr[3] = eeprom[80];
1710         bp->dev->dev_addr[4] = eeprom[83];
1711         bp->dev->dev_addr[5] = eeprom[82];
1712
1713         bp->phy_addr = eeprom[90] & 0x1f;
1714
1715         /* With this, plus the rx_header prepended to the data by the
1716          * hardware, we'll land the ethernet header on a 2-byte boundary.
1717          */
1718         bp->rx_offset = 30;
1719
1720         bp->imask = IMASK_DEF;
1721
1722         bp->core_unit = ssb_core_unit(bp);
1723         bp->dma_offset = SB_PCI_DMA;
1724
1725         /* XXX - really required?
1726            bp->flags |= B44_FLAG_BUGGY_TXPTR;
1727          */
1728 out:
1729         return err;
1730 }
1731
1732 static int __devinit b44_init_one(struct pci_dev *pdev,
1733                                   const struct pci_device_id *ent)
1734 {
1735         static int b44_version_printed = 0;
1736         unsigned long b44reg_base, b44reg_len;
1737         struct net_device *dev;
1738         struct b44 *bp;
1739         int err, i;
1740
1741         if (b44_version_printed++ == 0)
1742                 printk(KERN_INFO "%s", version);
1743
1744         err = pci_enable_device(pdev);
1745         if (err) {
1746                 printk(KERN_ERR PFX "Cannot enable PCI device, "
1747                        "aborting.\n");
1748                 return err;
1749         }
1750
1751         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
1752                 printk(KERN_ERR PFX "Cannot find proper PCI device "
1753                        "base address, aborting.\n");
1754                 err = -ENODEV;
1755                 goto err_out_disable_pdev;
1756         }
1757
1758         err = pci_request_regions(pdev, DRV_MODULE_NAME);
1759         if (err) {
1760                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
1761                        "aborting.\n");
1762                 goto err_out_disable_pdev;
1763         }
1764
1765         pci_set_master(pdev);
1766
1767         err = pci_set_dma_mask(pdev, (u64) B44_DMA_MASK);
1768         if (err) {
1769                 printk(KERN_ERR PFX "No usable DMA configuration, "
1770                        "aborting.\n");
1771                 goto err_out_free_res;
1772         }
1773
1774         err = pci_set_consistent_dma_mask(pdev, (u64) B44_DMA_MASK);
1775         if (err) {
1776           printk(KERN_ERR PFX "No usable DMA configuration, "
1777                  "aborting.\n");
1778           goto err_out_free_res;
1779         }
1780
1781         b44reg_base = pci_resource_start(pdev, 0);
1782         b44reg_len = pci_resource_len(pdev, 0);
1783
1784         dev = alloc_etherdev(sizeof(*bp));
1785         if (!dev) {
1786                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
1787                 err = -ENOMEM;
1788                 goto err_out_free_res;
1789         }
1790
1791         SET_MODULE_OWNER(dev);
1792         SET_NETDEV_DEV(dev,&pdev->dev);
1793
1794         /* No interesting netdevice features in this card... */
1795         dev->features |= 0;
1796
1797         bp = netdev_priv(dev);
1798         bp->pdev = pdev;
1799         bp->dev = dev;
1800         if (b44_debug >= 0)
1801                 bp->msg_enable = (1 << b44_debug) - 1;
1802         else
1803                 bp->msg_enable = B44_DEF_MSG_ENABLE;
1804
1805         spin_lock_init(&bp->lock);
1806
1807         bp->regs = ioremap(b44reg_base, b44reg_len);
1808         if (bp->regs == 0UL) {
1809                 printk(KERN_ERR PFX "Cannot map device registers, "
1810                        "aborting.\n");
1811                 err = -ENOMEM;
1812                 goto err_out_free_dev;
1813         }
1814
1815         bp->rx_pending = B44_DEF_RX_RING_PENDING;
1816         bp->tx_pending = B44_DEF_TX_RING_PENDING;
1817
1818         dev->open = b44_open;
1819         dev->stop = b44_close;
1820         dev->hard_start_xmit = b44_start_xmit;
1821         dev->get_stats = b44_get_stats;
1822         dev->set_multicast_list = b44_set_rx_mode;
1823         dev->set_mac_address = b44_set_mac_addr;
1824         dev->do_ioctl = b44_ioctl;
1825         dev->tx_timeout = b44_tx_timeout;
1826         dev->poll = b44_poll;
1827         dev->weight = 64;
1828         dev->watchdog_timeo = B44_TX_TIMEOUT;
1829 #ifdef CONFIG_NET_POLL_CONTROLLER
1830         dev->poll_controller = b44_poll_controller;
1831 #endif
1832         dev->change_mtu = b44_change_mtu;
1833         dev->irq = pdev->irq;
1834         SET_ETHTOOL_OPS(dev, &b44_ethtool_ops);
1835
1836         err = b44_get_invariants(bp);
1837         if (err) {
1838                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
1839                        "aborting.\n");
1840                 goto err_out_iounmap;
1841         }
1842
1843         bp->mii_if.dev = dev;
1844         bp->mii_if.mdio_read = b44_mii_read;
1845         bp->mii_if.mdio_write = b44_mii_write;
1846         bp->mii_if.phy_id = bp->phy_addr;
1847         bp->mii_if.phy_id_mask = 0x1f;
1848         bp->mii_if.reg_num_mask = 0x1f;
1849
1850         /* By default, advertise all speed/duplex settings. */
1851         bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
1852                       B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
1853
1854         /* By default, auto-negotiate PAUSE. */
1855         bp->flags |= B44_FLAG_PAUSE_AUTO;
1856
1857         err = register_netdev(dev);
1858         if (err) {
1859                 printk(KERN_ERR PFX "Cannot register net device, "
1860                        "aborting.\n");
1861                 goto err_out_iounmap;
1862         }
1863
1864         pci_set_drvdata(pdev, dev);
1865
1866         pci_save_state(bp->pdev);
1867
1868         printk(KERN_INFO "%s: Broadcom 4400 10/100BaseT Ethernet ", dev->name);
1869         for (i = 0; i < 6; i++)
1870                 printk("%2.2x%c", dev->dev_addr[i],
1871                        i == 5 ? '\n' : ':');
1872
1873         return 0;
1874
1875 err_out_iounmap:
1876         iounmap(bp->regs);
1877
1878 err_out_free_dev:
1879         free_netdev(dev);
1880
1881 err_out_free_res:
1882         pci_release_regions(pdev);
1883
1884 err_out_disable_pdev:
1885         pci_disable_device(pdev);
1886         pci_set_drvdata(pdev, NULL);
1887         return err;
1888 }
1889
1890 static void __devexit b44_remove_one(struct pci_dev *pdev)
1891 {
1892         struct net_device *dev = pci_get_drvdata(pdev);
1893
1894         if (dev) {
1895                 struct b44 *bp = netdev_priv(dev);
1896
1897                 unregister_netdev(dev);
1898                 iounmap(bp->regs);
1899                 free_netdev(dev);
1900                 pci_release_regions(pdev);
1901                 pci_disable_device(pdev);
1902                 pci_set_drvdata(pdev, NULL);
1903         }
1904 }
1905
1906 static int b44_suspend(struct pci_dev *pdev, u32 state)
1907 {
1908         struct net_device *dev = pci_get_drvdata(pdev);
1909         struct b44 *bp = netdev_priv(dev);
1910
1911         if (!netif_running(dev))
1912                  return 0;
1913
1914         del_timer_sync(&bp->timer);
1915
1916         spin_lock_irq(&bp->lock);
1917
1918         b44_halt(bp);
1919         netif_carrier_off(bp->dev);
1920         netif_device_detach(bp->dev);
1921         b44_free_rings(bp);
1922
1923         spin_unlock_irq(&bp->lock);
1924         return 0;
1925 }
1926
1927 static int b44_resume(struct pci_dev *pdev)
1928 {
1929         struct net_device *dev = pci_get_drvdata(pdev);
1930         struct b44 *bp = netdev_priv(dev);
1931
1932         pci_restore_state(pdev);
1933
1934         if (!netif_running(dev))
1935                 return 0;
1936
1937         spin_lock_irq(&bp->lock);
1938
1939         b44_init_rings(bp);
1940         b44_init_hw(bp);
1941         netif_device_attach(bp->dev);
1942         spin_unlock_irq(&bp->lock);
1943
1944         bp->timer.expires = jiffies + HZ;
1945         add_timer(&bp->timer);
1946
1947         b44_enable_ints(bp);
1948         return 0;
1949 }
1950
1951 static struct pci_driver b44_driver = {
1952         .name           = DRV_MODULE_NAME,
1953         .id_table       = b44_pci_tbl,
1954         .probe          = b44_init_one,
1955         .remove         = __devexit_p(b44_remove_one),
1956         .suspend        = b44_suspend,
1957         .resume         = b44_resume,
1958 };
1959
1960 static int __init b44_init(void)
1961 {
1962         return pci_module_init(&b44_driver);
1963 }
1964
1965 static void __exit b44_cleanup(void)
1966 {
1967         pci_unregister_driver(&b44_driver);
1968 }
1969
1970 module_init(b44_init);
1971 module_exit(b44_cleanup);
1972