drivers/net/bnx2.c

   1 /* bnx2.c: Broadcom NX2 network driver.
   2  *
   3  * Copyright (c) 2004, 2005, 2006 Broadcom Corporation
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation.
   8  *
   9  * Written by: Michael Chan  (mchan@broadcom.com)
  10  */
  11
  12
  13 #include <linux/module.h>
  14 #include <linux/moduleparam.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/timer.h>
  18 #include <linux/errno.h>
  19 #include <linux/ioport.h>
  20 #include <linux/slab.h>
  21 #include <linux/vmalloc.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/pci.h>
  24 #include <linux/init.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/skbuff.h>
  28 #include <linux/dma-mapping.h>
  29 #include <asm/bitops.h>
  30 #include <asm/io.h>
  31 #include <asm/irq.h>
  32 #include <linux/delay.h>
  33 #include <asm/byteorder.h>
  34 #include <asm/page.h>
  35 #include <linux/time.h>
  36 #include <linux/ethtool.h>
  37 #include <linux/mii.h>
  38 #ifdef NETIF_F_HW_VLAN_TX
  39 #include <linux/if_vlan.h>
  40 #define BCM_VLAN 1
  41 #endif
  42 #ifdef NETIF_F_TSO
  43 #include <net/ip.h>
  44 #include <net/tcp.h>
  45 #include <net/checksum.h>
  46 #define BCM_TSO 1
  47 #endif
  48 #include <linux/workqueue.h>
  49 #include <linux/crc32.h>
  50 #include <linux/prefetch.h>
  51 #include <linux/cache.h>
  52 #include <linux/zlib.h>
  53
  54 #include "bnx2.h"
  55 #include "bnx2_fw.h"
  56 #include "bnx2_fw2.h"
  57
  58 #define DRV_MODULE_NAME         "bnx2"
  59 #define PFX DRV_MODULE_NAME     ": "
  60 #define DRV_MODULE_VERSION      "1.5.5"
  61 #define DRV_MODULE_RELDATE      "February 1, 2007"
  62
  63 #define RUN_AT(x) (jiffies + (x))
  64
  65 /* Time in jiffies before concluding the transmitter is hung. */
  66 #define TX_TIMEOUT  (5*HZ)
  67
  68 static const char version[] __devinitdata =
  69         "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  70
  71 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
  72 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706/5708 Driver");
  73 MODULE_LICENSE("GPL");
  74 MODULE_VERSION(DRV_MODULE_VERSION);
  75
  76 static int disable_msi = 0;
  77
  78 module_param(disable_msi, int, 0);
  79 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
  80
  81 typedef enum {
  82         BCM5706 = 0,
  83         NC370T,
  84         NC370I,
  85         BCM5706S,
  86         NC370F,
  87         BCM5708,
  88         BCM5708S,
  89         BCM5709,
  90 } board_t;
  91
  92 /* indexed by board_t, above */
  93 static const struct {
  94         char *name;
  95 } board_info[] __devinitdata = {
  96         { "Broadcom NetXtreme II BCM5706 1000Base-T" },
  97         { "HP NC370T Multifunction Gigabit Server Adapter" },
  98         { "HP NC370i Multifunction Gigabit Server Adapter" },
  99         { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 100         { "HP NC370F Multifunction Gigabit Server Adapter" },
 101         { "Broadcom NetXtreme II BCM5708 1000Base-T" },
 102         { "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 103         { "Broadcom NetXtreme II BCM5709 1000Base-T" },
 104         };
 105
 106 static struct pci_device_id bnx2_pci_tbl[] = {
 107         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 108           PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
 109         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 110           PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
 111         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
 112           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
 113         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708,
 114           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708 },
 115         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 116           PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
 117         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
 118           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
 119         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5708S,
 120           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5708S },
 121         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5709,
 122           PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5709 },
 123         { 0, }
 124 };
 125
 126 static struct flash_spec flash_table[] =
 127 {
 128         /* Slow EEPROM */
 129         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 130          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 131          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 132          "EEPROM - slow"},
 133         /* Expansion entry 0001 */
 134         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 135          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 136          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 137          "Entry 0001"},
 138         /* Saifun SA25F010 (non-buffered flash) */
 139         /* strap, cfg1, & write1 need updates */
 140         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 141          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 142          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 143          "Non-buffered flash (128kB)"},
 144         /* Saifun SA25F020 (non-buffered flash) */
 145         /* strap, cfg1, & write1 need updates */
 146         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 147          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 148          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 149          "Non-buffered flash (256kB)"},
 150         /* Expansion entry 0100 */
 151         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 152          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 153          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 154          "Entry 0100"},
 155         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 156         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 157          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 158          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 159          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 160         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 161         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 162          0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 163          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 164          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 165         /* Saifun SA25F005 (non-buffered flash) */
 166         /* strap, cfg1, & write1 need updates */
 167         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 168          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 169          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 170          "Non-buffered flash (64kB)"},
 171         /* Fast EEPROM */
 172         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 173          1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 174          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 175          "EEPROM - fast"},
 176         /* Expansion entry 1001 */
 177         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 178          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 179          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 180          "Entry 1001"},
 181         /* Expansion entry 1010 */
 182         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 183          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 184          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 185          "Entry 1010"},
 186         /* ATMEL AT45DB011B (buffered flash) */
 187         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 188          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 189          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 190          "Buffered flash (128kB)"},
 191         /* Expansion entry 1100 */
 192         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 193          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 194          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 195          "Entry 1100"},
 196         /* Expansion entry 1101 */
 197         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 198          0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 199          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 200          "Entry 1101"},
 201         /* Ateml Expansion entry 1110 */
 202         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 203          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 204          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 205          "Entry 1110 (Atmel)"},
 206         /* ATMEL AT45DB021B (buffered flash) */
 207         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 208          1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 209          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 210          "Buffered flash (256kB)"},
 211 };
 212
 213 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
 214
 215 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
 216 {
 217         u32 diff;
 218
 219         smp_mb();
 220
 221         /* The ring uses 256 indices for 255 entries, one of them
 222          * needs to be skipped.
 223          */
 224         diff = bp->tx_prod - bp->tx_cons;
 225         if (unlikely(diff >= TX_DESC_CNT)) {
 226                 diff &= 0xffff;
 227                 if (diff == TX_DESC_CNT)
 228                         diff = MAX_TX_DESC_CNT;
 229         }
 230         return (bp->tx_ring_size - diff);
 231 }
 232
 233 static u32
 234 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
 235 {
 236         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 237         return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
 238 }
 239
 240 static void
 241 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
 242 {
 243         REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
 244         REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
 245 }
 246
 247 static void
 248 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
 249 {
 250         offset += cid_addr;
 251         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 252                 int i;
 253
 254                 REG_WR(bp, BNX2_CTX_CTX_DATA, val);
 255                 REG_WR(bp, BNX2_CTX_CTX_CTRL,
 256                        offset | BNX2_CTX_CTX_CTRL_WRITE_REQ);
 257                 for (i = 0; i < 5; i++) {
 258                         u32 val;
 259                         val = REG_RD(bp, BNX2_CTX_CTX_CTRL);
 260                         if ((val & BNX2_CTX_CTX_CTRL_WRITE_REQ) == 0)
 261                                 break;
 262                         udelay(5);
 263                 }
 264         } else {
 265                 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
 266                 REG_WR(bp, BNX2_CTX_DATA, val);
 267         }
 268 }
 269
 270 static int
 271 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
 272 {
 273         u32 val1;
 274         int i, ret;
 275
 276         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 277                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 278                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 279
 280                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 281                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 282
 283                 udelay(40);
 284         }
 285
 286         val1 = (bp->phy_addr << 21) | (reg << 16) |
 287                 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
 288                 BNX2_EMAC_MDIO_COMM_START_BUSY;
 289         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 290
 291         for (i = 0; i < 50; i++) {
 292                 udelay(10);
 293
 294                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 295                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 296                         udelay(5);
 297
 298                         val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 299                         val1 &= BNX2_EMAC_MDIO_COMM_DATA;
 300
 301                         break;
 302                 }
 303         }
 304
 305         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
 306                 *val = 0x0;
 307                 ret = -EBUSY;
 308         }
 309         else {
 310                 *val = val1;
 311                 ret = 0;
 312         }
 313
 314         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 315                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 316                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 317
 318                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 319                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 320
 321                 udelay(40);
 322         }
 323
 324         return ret;
 325 }
 326
 327 static int
 328 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
 329 {
 330         u32 val1;
 331         int i, ret;
 332
 333         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 334                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 335                 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 336
 337                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 338                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 339
 340                 udelay(40);
 341         }
 342
 343         val1 = (bp->phy_addr << 21) | (reg << 16) | val |
 344                 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
 345                 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
 346         REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
 347
 348         for (i = 0; i < 50; i++) {
 349                 udelay(10);
 350
 351                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
 352                 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
 353                         udelay(5);
 354                         break;
 355                 }
 356         }
 357
 358         if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
 359                 ret = -EBUSY;
 360         else
 361                 ret = 0;
 362
 363         if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
 364                 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 365                 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
 366
 367                 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
 368                 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
 369
 370                 udelay(40);
 371         }
 372
 373         return ret;
 374 }
 375
 376 static void
 377 bnx2_disable_int(struct bnx2 *bp)
 378 {
 379         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 380                BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
 381         REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
 382 }
 383
 384 static void
 385 bnx2_enable_int(struct bnx2 *bp)
 386 {
 387         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 388                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
 389                BNX2_PCICFG_INT_ACK_CMD_MASK_INT | bp->last_status_idx);
 390
 391         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
 392                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
 393
 394         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
 395 }
 396
 397 static void
 398 bnx2_disable_int_sync(struct bnx2 *bp)
 399 {
 400         atomic_inc(&bp->intr_sem);
 401         bnx2_disable_int(bp);
 402         synchronize_irq(bp->pdev->irq);
 403 }
 404
 405 static void
 406 bnx2_netif_stop(struct bnx2 *bp)
 407 {
 408         bnx2_disable_int_sync(bp);
 409         if (netif_running(bp->dev)) {
 410                 netif_poll_disable(bp->dev);
 411                 netif_tx_disable(bp->dev);
 412                 bp->dev->trans_start = jiffies; /* prevent tx timeout */
 413         }
 414 }
 415
 416 static void
 417 bnx2_netif_start(struct bnx2 *bp)
 418 {
 419         if (atomic_dec_and_test(&bp->intr_sem)) {
 420                 if (netif_running(bp->dev)) {
 421                         netif_wake_queue(bp->dev);
 422                         netif_poll_enable(bp->dev);
 423                         bnx2_enable_int(bp);
 424                 }
 425         }
 426 }
 427
 428 static void
 429 bnx2_free_mem(struct bnx2 *bp)
 430 {
 431         int i;
 432
 433         for (i = 0; i < bp->ctx_pages; i++) {
 434                 if (bp->ctx_blk[i]) {
 435                         pci_free_consistent(bp->pdev, BCM_PAGE_SIZE,
 436                                             bp->ctx_blk[i],
 437                                             bp->ctx_blk_mapping[i]);
 438                         bp->ctx_blk[i] = NULL;
 439                 }
 440         }
 441         if (bp->status_blk) {
 442                 pci_free_consistent(bp->pdev, bp->status_stats_size,
 443                                     bp->status_blk, bp->status_blk_mapping);
 444                 bp->status_blk = NULL;
 445                 bp->stats_blk = NULL;
 446         }
 447         if (bp->tx_desc_ring) {
 448                 pci_free_consistent(bp->pdev,
 449                                     sizeof(struct tx_bd) * TX_DESC_CNT,
 450                                     bp->tx_desc_ring, bp->tx_desc_mapping);
 451                 bp->tx_desc_ring = NULL;
 452         }
 453         kfree(bp->tx_buf_ring);
 454         bp->tx_buf_ring = NULL;
 455         for (i = 0; i < bp->rx_max_ring; i++) {
 456                 if (bp->rx_desc_ring[i])
 457                         pci_free_consistent(bp->pdev,
 458                                             sizeof(struct rx_bd) * RX_DESC_CNT,
 459                                             bp->rx_desc_ring[i],
 460                                             bp->rx_desc_mapping[i]);
 461                 bp->rx_desc_ring[i] = NULL;
 462         }
 463         vfree(bp->rx_buf_ring);
 464         bp->rx_buf_ring = NULL;
 465 }
 466
 467 static int
 468 bnx2_alloc_mem(struct bnx2 *bp)
 469 {
 470         int i, status_blk_size;
 471
 472         bp->tx_buf_ring = kzalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
 473                                   GFP_KERNEL);
 474         if (bp->tx_buf_ring == NULL)
 475                 return -ENOMEM;
 476
 477         bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
 478                                                 sizeof(struct tx_bd) *
 479                                                 TX_DESC_CNT,
 480                                                 &bp->tx_desc_mapping);
 481         if (bp->tx_desc_ring == NULL)
 482                 goto alloc_mem_err;
 483
 484         bp->rx_buf_ring = vmalloc(sizeof(struct sw_bd) * RX_DESC_CNT *
 485                                   bp->rx_max_ring);
 486         if (bp->rx_buf_ring == NULL)
 487                 goto alloc_mem_err;
 488
 489         memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT *
 490                                    bp->rx_max_ring);
 491
 492         for (i = 0; i < bp->rx_max_ring; i++) {
 493                 bp->rx_desc_ring[i] =
 494                         pci_alloc_consistent(bp->pdev,
 495                                              sizeof(struct rx_bd) * RX_DESC_CNT,
 496                                              &bp->rx_desc_mapping[i]);
 497                 if (bp->rx_desc_ring[i] == NULL)
 498                         goto alloc_mem_err;
 499
 500         }
 501
 502         /* Combine status and statistics blocks into one allocation. */
 503         status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
 504         bp->status_stats_size = status_blk_size +
 505                                 sizeof(struct statistics_block);
 506
 507         bp->status_blk = pci_alloc_consistent(bp->pdev, bp->status_stats_size,
 508                                               &bp->status_blk_mapping);
 509         if (bp->status_blk == NULL)
 510                 goto alloc_mem_err;
 511
 512         memset(bp->status_blk, 0, bp->status_stats_size);
 513
 514         bp->stats_blk = (void *) ((unsigned long) bp->status_blk +
 515                                   status_blk_size);
 516
 517         bp->stats_blk_mapping = bp->status_blk_mapping + status_blk_size;
 518
 519         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
 520                 bp->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
 521                 if (bp->ctx_pages == 0)
 522                         bp->ctx_pages = 1;
 523                 for (i = 0; i < bp->ctx_pages; i++) {
 524                         bp->ctx_blk[i] = pci_alloc_consistent(bp->pdev,
 525                                                 BCM_PAGE_SIZE,
 526                                                 &bp->ctx_blk_mapping[i]);
 527                         if (bp->ctx_blk[i] == NULL)
 528                                 goto alloc_mem_err;
 529                 }
 530         }
 531         return 0;
 532
 533 alloc_mem_err:
 534         bnx2_free_mem(bp);
 535         return -ENOMEM;
 536 }
 537
 538 static void
 539 bnx2_report_fw_link(struct bnx2 *bp)
 540 {
 541         u32 fw_link_status = 0;
 542
 543         if (bp->link_up) {
 544                 u32 bmsr;
 545
 546                 switch (bp->line_speed) {
 547                 case SPEED_10:
 548                         if (bp->duplex == DUPLEX_HALF)
 549                                 fw_link_status = BNX2_LINK_STATUS_10HALF;
 550                         else
 551                                 fw_link_status = BNX2_LINK_STATUS_10FULL;
 552                         break;
 553                 case SPEED_100:
 554                         if (bp->duplex == DUPLEX_HALF)
 555                                 fw_link_status = BNX2_LINK_STATUS_100HALF;
 556                         else
 557                                 fw_link_status = BNX2_LINK_STATUS_100FULL;
 558                         break;
 559                 case SPEED_1000:
 560                         if (bp->duplex == DUPLEX_HALF)
 561                                 fw_link_status = BNX2_LINK_STATUS_1000HALF;
 562                         else
 563                                 fw_link_status = BNX2_LINK_STATUS_1000FULL;
 564                         break;
 565                 case SPEED_2500:
 566                         if (bp->duplex == DUPLEX_HALF)
 567                                 fw_link_status = BNX2_LINK_STATUS_2500HALF;
 568                         else
 569                                 fw_link_status = BNX2_LINK_STATUS_2500FULL;
 570                         break;
 571                 }
 572
 573                 fw_link_status |= BNX2_LINK_STATUS_LINK_UP;
 574
 575                 if (bp->autoneg) {
 576                         fw_link_status |= BNX2_LINK_STATUS_AN_ENABLED;
 577
 578                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 579                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 580
 581                         if (!(bmsr & BMSR_ANEGCOMPLETE) ||
 582                             bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)
 583                                 fw_link_status |= BNX2_LINK_STATUS_PARALLEL_DET;
 584                         else
 585                                 fw_link_status |= BNX2_LINK_STATUS_AN_COMPLETE;
 586                 }
 587         }
 588         else
 589                 fw_link_status = BNX2_LINK_STATUS_LINK_DOWN;
 590
 591         REG_WR_IND(bp, bp->shmem_base + BNX2_LINK_STATUS, fw_link_status);
 592 }
 593
 594 static void
 595 bnx2_report_link(struct bnx2 *bp)
 596 {
 597         if (bp->link_up) {
 598                 netif_carrier_on(bp->dev);
 599                 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
 600
 601                 printk("%d Mbps ", bp->line_speed);
 602
 603                 if (bp->duplex == DUPLEX_FULL)
 604                         printk("full duplex");
 605                 else
 606                         printk("half duplex");
 607
 608                 if (bp->flow_ctrl) {
 609                         if (bp->flow_ctrl & FLOW_CTRL_RX) {
 610                                 printk(", receive ");
 611                                 if (bp->flow_ctrl & FLOW_CTRL_TX)
 612                                         printk("& transmit ");
 613                         }
 614                         else {
 615                                 printk(", transmit ");
 616                         }
 617                         printk("flow control ON");
 618                 }
 619                 printk("\n");
 620         }
 621         else {
 622                 netif_carrier_off(bp->dev);
 623                 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
 624         }
 625
 626         bnx2_report_fw_link(bp);
 627 }
 628
 629 static void
 630 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
 631 {
 632         u32 local_adv, remote_adv;
 633
 634         bp->flow_ctrl = 0;
 635         if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
 636                 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
 637
 638                 if (bp->duplex == DUPLEX_FULL) {
 639                         bp->flow_ctrl = bp->req_flow_ctrl;
 640                 }
 641                 return;
 642         }
 643
 644         if (bp->duplex != DUPLEX_FULL) {
 645                 return;
 646         }
 647
 648         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 649             (CHIP_NUM(bp) == CHIP_NUM_5708)) {
 650                 u32 val;
 651
 652                 bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 653                 if (val & BCM5708S_1000X_STAT1_TX_PAUSE)
 654                         bp->flow_ctrl |= FLOW_CTRL_TX;
 655                 if (val & BCM5708S_1000X_STAT1_RX_PAUSE)
 656                         bp->flow_ctrl |= FLOW_CTRL_RX;
 657                 return;
 658         }
 659
 660         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 661         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 662
 663         if (bp->phy_flags & PHY_SERDES_FLAG) {
 664                 u32 new_local_adv = 0;
 665                 u32 new_remote_adv = 0;
 666
 667                 if (local_adv & ADVERTISE_1000XPAUSE)
 668                         new_local_adv |= ADVERTISE_PAUSE_CAP;
 669                 if (local_adv & ADVERTISE_1000XPSE_ASYM)
 670                         new_local_adv |= ADVERTISE_PAUSE_ASYM;
 671                 if (remote_adv & ADVERTISE_1000XPAUSE)
 672                         new_remote_adv |= ADVERTISE_PAUSE_CAP;
 673                 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
 674                         new_remote_adv |= ADVERTISE_PAUSE_ASYM;
 675
 676                 local_adv = new_local_adv;
 677                 remote_adv = new_remote_adv;
 678         }
 679
 680         /* See Table 28B-3 of 802.3ab-1999 spec. */
 681         if (local_adv & ADVERTISE_PAUSE_CAP) {
 682                 if(local_adv & ADVERTISE_PAUSE_ASYM) {
 683                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 684                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 685                         }
 686                         else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
 687                                 bp->flow_ctrl = FLOW_CTRL_RX;
 688                         }
 689                 }
 690                 else {
 691                         if (remote_adv & ADVERTISE_PAUSE_CAP) {
 692                                 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 693                         }
 694                 }
 695         }
 696         else if (local_adv & ADVERTISE_PAUSE_ASYM) {
 697                 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
 698                         (remote_adv & ADVERTISE_PAUSE_ASYM)) {
 699
 700                         bp->flow_ctrl = FLOW_CTRL_TX;
 701                 }
 702         }
 703 }
 704
 705 static int
 706 bnx2_5708s_linkup(struct bnx2 *bp)
 707 {
 708         u32 val;
 709
 710         bp->link_up = 1;
 711         bnx2_read_phy(bp, BCM5708S_1000X_STAT1, &val);
 712         switch (val & BCM5708S_1000X_STAT1_SPEED_MASK) {
 713                 case BCM5708S_1000X_STAT1_SPEED_10:
 714                         bp->line_speed = SPEED_10;
 715                         break;
 716                 case BCM5708S_1000X_STAT1_SPEED_100:
 717                         bp->line_speed = SPEED_100;
 718                         break;
 719                 case BCM5708S_1000X_STAT1_SPEED_1G:
 720                         bp->line_speed = SPEED_1000;
 721                         break;
 722                 case BCM5708S_1000X_STAT1_SPEED_2G5:
 723                         bp->line_speed = SPEED_2500;
 724                         break;
 725         }
 726         if (val & BCM5708S_1000X_STAT1_FD)
 727                 bp->duplex = DUPLEX_FULL;
 728         else
 729                 bp->duplex = DUPLEX_HALF;
 730
 731         return 0;
 732 }
 733
 734 static int
 735 bnx2_5706s_linkup(struct bnx2 *bp)
 736 {
 737         u32 bmcr, local_adv, remote_adv, common;
 738
 739         bp->link_up = 1;
 740         bp->line_speed = SPEED_1000;
 741
 742         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 743         if (bmcr & BMCR_FULLDPLX) {
 744                 bp->duplex = DUPLEX_FULL;
 745         }
 746         else {
 747                 bp->duplex = DUPLEX_HALF;
 748         }
 749
 750         if (!(bmcr & BMCR_ANENABLE)) {
 751                 return 0;
 752         }
 753
 754         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 755         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 756
 757         common = local_adv & remote_adv;
 758         if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
 759
 760                 if (common & ADVERTISE_1000XFULL) {
 761                         bp->duplex = DUPLEX_FULL;
 762                 }
 763                 else {
 764                         bp->duplex = DUPLEX_HALF;
 765                 }
 766         }
 767
 768         return 0;
 769 }
 770
 771 static int
 772 bnx2_copper_linkup(struct bnx2 *bp)
 773 {
 774         u32 bmcr;
 775
 776         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 777         if (bmcr & BMCR_ANENABLE) {
 778                 u32 local_adv, remote_adv, common;
 779
 780                 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
 781                 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
 782
 783                 common = local_adv & (remote_adv >> 2);
 784                 if (common & ADVERTISE_1000FULL) {
 785                         bp->line_speed = SPEED_1000;
 786                         bp->duplex = DUPLEX_FULL;
 787                 }
 788                 else if (common & ADVERTISE_1000HALF) {
 789                         bp->line_speed = SPEED_1000;
 790                         bp->duplex = DUPLEX_HALF;
 791                 }
 792                 else {
 793                         bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
 794                         bnx2_read_phy(bp, MII_LPA, &remote_adv);
 795
 796                         common = local_adv & remote_adv;
 797                         if (common & ADVERTISE_100FULL) {
 798                                 bp->line_speed = SPEED_100;
 799                                 bp->duplex = DUPLEX_FULL;
 800                         }
 801                         else if (common & ADVERTISE_100HALF) {
 802                                 bp->line_speed = SPEED_100;
 803                                 bp->duplex = DUPLEX_HALF;
 804                         }
 805                         else if (common & ADVERTISE_10FULL) {
 806                                 bp->line_speed = SPEED_10;
 807                                 bp->duplex = DUPLEX_FULL;
 808                         }
 809                         else if (common & ADVERTISE_10HALF) {
 810                                 bp->line_speed = SPEED_10;
 811                                 bp->duplex = DUPLEX_HALF;
 812                         }
 813                         else {
 814                                 bp->line_speed = 0;
 815                                 bp->link_up = 0;
 816                         }
 817                 }
 818         }
 819         else {
 820                 if (bmcr & BMCR_SPEED100) {
 821                         bp->line_speed = SPEED_100;
 822                 }
 823                 else {
 824                         bp->line_speed = SPEED_10;
 825                 }
 826                 if (bmcr & BMCR_FULLDPLX) {
 827                         bp->duplex = DUPLEX_FULL;
 828                 }
 829                 else {
 830                         bp->duplex = DUPLEX_HALF;
 831                 }
 832         }
 833
 834         return 0;
 835 }
 836
 837 static int
 838 bnx2_set_mac_link(struct bnx2 *bp)
 839 {
 840         u32 val;
 841
 842         REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
 843         if (bp->link_up && (bp->line_speed == SPEED_1000) &&
 844                 (bp->duplex == DUPLEX_HALF)) {
 845                 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
 846         }
 847
 848         /* Configure the EMAC mode register. */
 849         val = REG_RD(bp, BNX2_EMAC_MODE);
 850
 851         val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
 852                 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
 853                 BNX2_EMAC_MODE_25G_MODE);
 854
 855         if (bp->link_up) {
 856                 switch (bp->line_speed) {
 857                         case SPEED_10:
 858                                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
 859                                         val |= BNX2_EMAC_MODE_PORT_MII_10M;
 860                                         break;
 861                                 }
 862                                 /* fall through */
 863                         case SPEED_100:
 864                                 val |= BNX2_EMAC_MODE_PORT_MII;
 865                                 break;
 866                         case SPEED_2500:
 867                                 val |= BNX2_EMAC_MODE_25G_MODE;
 868                                 /* fall through */
 869                         case SPEED_1000:
 870                                 val |= BNX2_EMAC_MODE_PORT_GMII;
 871                                 break;
 872                 }
 873         }
 874         else {
 875                 val |= BNX2_EMAC_MODE_PORT_GMII;
 876         }
 877
 878         /* Set the MAC to operate in the appropriate duplex mode. */
 879         if (bp->duplex == DUPLEX_HALF)
 880                 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
 881         REG_WR(bp, BNX2_EMAC_MODE, val);
 882
 883         /* Enable/disable rx PAUSE. */
 884         bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
 885
 886         if (bp->flow_ctrl & FLOW_CTRL_RX)
 887                 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
 888         REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
 889
 890         /* Enable/disable tx PAUSE. */
 891         val = REG_RD(bp, BNX2_EMAC_TX_MODE);
 892         val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
 893
 894         if (bp->flow_ctrl & FLOW_CTRL_TX)
 895                 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
 896         REG_WR(bp, BNX2_EMAC_TX_MODE, val);
 897
 898         /* Acknowledge the interrupt. */
 899         REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
 900
 901         return 0;
 902 }
 903
 904 static int
 905 bnx2_set_link(struct bnx2 *bp)
 906 {
 907         u32 bmsr;
 908         u8 link_up;
 909
 910         if (bp->loopback == MAC_LOOPBACK || bp->loopback == PHY_LOOPBACK) {
 911                 bp->link_up = 1;
 912                 return 0;
 913         }
 914
 915         link_up = bp->link_up;
 916
 917         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 918         bnx2_read_phy(bp, MII_BMSR, &bmsr);
 919
 920         if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 921             (CHIP_NUM(bp) == CHIP_NUM_5706)) {
 922                 u32 val;
 923
 924                 val = REG_RD(bp, BNX2_EMAC_STATUS);
 925                 if (val & BNX2_EMAC_STATUS_LINK)
 926                         bmsr |= BMSR_LSTATUS;
 927                 else
 928                         bmsr &= ~BMSR_LSTATUS;
 929         }
 930
 931         if (bmsr & BMSR_LSTATUS) {
 932                 bp->link_up = 1;
 933
 934                 if (bp->phy_flags & PHY_SERDES_FLAG) {
 935                         if (CHIP_NUM(bp) == CHIP_NUM_5706)
 936                                 bnx2_5706s_linkup(bp);
 937                         else if (CHIP_NUM(bp) == CHIP_NUM_5708)
 938                                 bnx2_5708s_linkup(bp);
 939                 }
 940                 else {
 941                         bnx2_copper_linkup(bp);
 942                 }
 943                 bnx2_resolve_flow_ctrl(bp);
 944         }
 945         else {
 946                 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
 947                         (bp->autoneg & AUTONEG_SPEED)) {
 948
 949                         u32 bmcr;
 950
 951                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
 952                         bmcr &= ~BCM5708S_BMCR_FORCE_2500;
 953                         if (!(bmcr & BMCR_ANENABLE)) {
 954                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
 955                                         BMCR_ANENABLE);
 956                         }
 957                 }
 958                 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
 959                 bp->link_up = 0;
 960         }
 961
 962         if (bp->link_up != link_up) {
 963                 bnx2_report_link(bp);
 964         }
 965
 966         bnx2_set_mac_link(bp);
 967
 968         return 0;
 969 }
 970
 971 static int
 972 bnx2_reset_phy(struct bnx2 *bp)
 973 {
 974         int i;
 975         u32 reg;
 976
 977         bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
 978
 979 #define PHY_RESET_MAX_WAIT 100
 980         for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
 981                 udelay(10);
 982
 983                 bnx2_read_phy(bp, MII_BMCR, &reg);
 984                 if (!(reg & BMCR_RESET)) {
 985                         udelay(20);
 986                         break;
 987                 }
 988         }
 989         if (i == PHY_RESET_MAX_WAIT) {
 990                 return -EBUSY;
 991         }
 992         return 0;
 993 }
 994
 995 static u32
 996 bnx2_phy_get_pause_adv(struct bnx2 *bp)
 997 {
 998         u32 adv = 0;
 999
1000         if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
1001                 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
1002
1003                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1004                         adv = ADVERTISE_1000XPAUSE;
1005                 }
1006                 else {
1007                         adv = ADVERTISE_PAUSE_CAP;
1008                 }
1009         }
1010         else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
1011                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1012                         adv = ADVERTISE_1000XPSE_ASYM;
1013                 }
1014                 else {
1015                         adv = ADVERTISE_PAUSE_ASYM;
1016                 }
1017         }
1018         else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
1019                 if (bp->phy_flags & PHY_SERDES_FLAG) {
1020                         adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1021                 }
1022                 else {
1023                         adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1024                 }
1025         }
1026         return adv;
1027 }
1028
1029 static int
1030 bnx2_setup_serdes_phy(struct bnx2 *bp)
1031 {
1032         u32 adv, bmcr, up1;
1033         u32 new_adv = 0;
1034
1035         if (!(bp->autoneg & AUTONEG_SPEED)) {
1036                 u32 new_bmcr;
1037                 int force_link_down = 0;
1038
1039                 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1040                 adv &= ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF);
1041
1042                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
1043                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BCM5708S_BMCR_FORCE_2500);
1044                 new_bmcr |= BMCR_SPEED1000;
1045                 if (bp->req_line_speed == SPEED_2500) {
1046                         new_bmcr |= BCM5708S_BMCR_FORCE_2500;
1047                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
1048                         if (!(up1 & BCM5708S_UP1_2G5)) {
1049                                 up1 |= BCM5708S_UP1_2G5;
1050                                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1051                                 force_link_down = 1;
1052                         }
1053                 } else if (CHIP_NUM(bp) == CHIP_NUM_5708) {
1054                         bnx2_read_phy(bp, BCM5708S_UP1, &up1);
1055                         if (up1 & BCM5708S_UP1_2G5) {
1056                                 up1 &= ~BCM5708S_UP1_2G5;
1057                                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1058                                 force_link_down = 1;
1059                         }
1060                 }
1061
1062                 if (bp->req_duplex == DUPLEX_FULL) {
1063                         adv |= ADVERTISE_1000XFULL;
1064                         new_bmcr |= BMCR_FULLDPLX;
1065                 }
1066                 else {
1067                         adv |= ADVERTISE_1000XHALF;
1068                         new_bmcr &= ~BMCR_FULLDPLX;
1069                 }
1070                 if ((new_bmcr != bmcr) || (force_link_down)) {
1071                         /* Force a link down visible on the other side */
1072                         if (bp->link_up) {
1073                                 bnx2_write_phy(bp, MII_ADVERTISE, adv &
1074                                                ~(ADVERTISE_1000XFULL |
1075                                                  ADVERTISE_1000XHALF));
1076                                 bnx2_write_phy(bp, MII_BMCR, bmcr |
1077                                         BMCR_ANRESTART | BMCR_ANENABLE);
1078
1079                                 bp->link_up = 0;
1080                                 netif_carrier_off(bp->dev);
1081                                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1082                                 bnx2_report_link(bp);
1083                         }
1084                         bnx2_write_phy(bp, MII_ADVERTISE, adv);
1085                         bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1086                 }
1087                 return 0;
1088         }
1089
1090         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1091                 bnx2_read_phy(bp, BCM5708S_UP1, &up1);
1092                 up1 |= BCM5708S_UP1_2G5;
1093                 bnx2_write_phy(bp, BCM5708S_UP1, up1);
1094         }
1095
1096         if (bp->advertising & ADVERTISED_1000baseT_Full)
1097                 new_adv |= ADVERTISE_1000XFULL;
1098
1099         new_adv |= bnx2_phy_get_pause_adv(bp);
1100
1101         bnx2_read_phy(bp, MII_ADVERTISE, &adv);
1102         bnx2_read_phy(bp, MII_BMCR, &bmcr);
1103
1104         bp->serdes_an_pending = 0;
1105         if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
1106                 /* Force a link down visible on the other side */
1107                 if (bp->link_up) {
1108                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1109                         spin_unlock_bh(&bp->phy_lock);
1110                         msleep(20);
1111                         spin_lock_bh(&bp->phy_lock);
1112                 }
1113
1114                 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
1115                 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
1116                         BMCR_ANENABLE);
1117                 /* Speed up link-up time when the link partner
1118                  * does not autonegotiate which is very common
1119                  * in blade servers. Some blade servers use
1120                  * IPMI for kerboard input and it's important
1121                  * to minimize link disruptions. Autoneg. involves
1122                  * exchanging base pages plus 3 next pages and
1123                  * normally completes in about 120 msec.
1124                  */
1125                 bp->current_interval = SERDES_AN_TIMEOUT;
1126                 bp->serdes_an_pending = 1;
1127                 mod_timer(&bp->timer, jiffies + bp->current_interval);
1128         }
1129
1130         return 0;
1131 }
1132
1133 #define ETHTOOL_ALL_FIBRE_SPEED                                         \
1134         (ADVERTISED_1000baseT_Full)
1135
1136 #define ETHTOOL_ALL_COPPER_SPEED                                        \
1137         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |            \
1138         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |           \
1139         ADVERTISED_1000baseT_Full)
1140
1141 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
1142         ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
1143
1144 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
1145
1146 static int
1147 bnx2_setup_copper_phy(struct bnx2 *bp)
1148 {
1149         u32 bmcr;
1150         u32 new_bmcr;
1151
1152         bnx2_read_phy(bp, MII_BMCR, &bmcr);
1153
1154         if (bp->autoneg & AUTONEG_SPEED) {
1155                 u32 adv_reg, adv1000_reg;
1156                 u32 new_adv_reg = 0;
1157                 u32 new_adv1000_reg = 0;
1158
1159                 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
1160                 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
1161                         ADVERTISE_PAUSE_ASYM);
1162
1163                 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
1164                 adv1000_reg &= PHY_ALL_1000_SPEED;
1165
1166                 if (bp->advertising & ADVERTISED_10baseT_Half)
1167                         new_adv_reg |= ADVERTISE_10HALF;
1168                 if (bp->advertising & ADVERTISED_10baseT_Full)
1169                         new_adv_reg |= ADVERTISE_10FULL;
1170                 if (bp->advertising & ADVERTISED_100baseT_Half)
1171                         new_adv_reg |= ADVERTISE_100HALF;
1172                 if (bp->advertising & ADVERTISED_100baseT_Full)
1173                         new_adv_reg |= ADVERTISE_100FULL;
1174                 if (bp->advertising & ADVERTISED_1000baseT_Full)
1175                         new_adv1000_reg |= ADVERTISE_1000FULL;
1176
1177                 new_adv_reg |= ADVERTISE_CSMA;
1178
1179                 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
1180
1181                 if ((adv1000_reg != new_adv1000_reg) ||
1182                         (adv_reg != new_adv_reg) ||
1183                         ((bmcr & BMCR_ANENABLE) == 0)) {
1184
1185                         bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
1186                         bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
1187                         bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
1188                                 BMCR_ANENABLE);
1189                 }
1190                 else if (bp->link_up) {
1191                         /* Flow ctrl may have changed from auto to forced */
1192                         /* or vice-versa. */
1193
1194                         bnx2_resolve_flow_ctrl(bp);
1195                         bnx2_set_mac_link(bp);
1196                 }
1197                 return 0;
1198         }
1199
1200         new_bmcr = 0;
1201         if (bp->req_line_speed == SPEED_100) {
1202                 new_bmcr |= BMCR_SPEED100;
1203         }
1204         if (bp->req_duplex == DUPLEX_FULL) {
1205                 new_bmcr |= BMCR_FULLDPLX;
1206         }
1207         if (new_bmcr != bmcr) {
1208                 u32 bmsr;
1209
1210                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1211                 bnx2_read_phy(bp, MII_BMSR, &bmsr);
1212
1213                 if (bmsr & BMSR_LSTATUS) {
1214                         /* Force link down */
1215                         bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
1216                         spin_unlock_bh(&bp->phy_lock);
1217                         msleep(50);
1218                         spin_lock_bh(&bp->phy_lock);
1219
1220                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
1221                         bnx2_read_phy(bp, MII_BMSR, &bmsr);
1222                 }
1223
1224                 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
1225
1226                 /* Normally, the new speed is setup after the link has
1227                  * gone down and up again. In some cases, link will not go
1228                  * down so we need to set up the new speed here.
1229                  */
1230                 if (bmsr & BMSR_LSTATUS) {
1231                         bp->line_speed = bp->req_line_speed;
1232                         bp->duplex = bp->req_duplex;
1233                         bnx2_resolve_flow_ctrl(bp);
1234                         bnx2_set_mac_link(bp);
1235                 }
1236         }
1237         return 0;
1238 }
1239
1240 static int
1241 bnx2_setup_phy(struct bnx2 *bp)
1242 {
1243         if (bp->loopback == MAC_LOOPBACK)
1244                 return 0;
1245
1246         if (bp->phy_flags & PHY_SERDES_FLAG) {
1247                 return (bnx2_setup_serdes_phy(bp));
1248         }
1249         else {
1250                 return (bnx2_setup_copper_phy(bp));
1251         }
1252 }
1253
1254 static int
1255 bnx2_init_5708s_phy(struct bnx2 *bp)
1256 {
1257         u32 val;
1258
1259         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG3);
1260         bnx2_write_phy(bp, BCM5708S_DIG_3_0, BCM5708S_DIG_3_0_USE_IEEE);
1261         bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1262
1263         bnx2_read_phy(bp, BCM5708S_1000X_CTL1, &val);
1264         val |= BCM5708S_1000X_CTL1_FIBER_MODE | BCM5708S_1000X_CTL1_AUTODET_EN;
1265         bnx2_write_phy(bp, BCM5708S_1000X_CTL1, val);
1266
1267         bnx2_read_phy(bp, BCM5708S_1000X_CTL2, &val);
1268         val |= BCM5708S_1000X_CTL2_PLLEL_DET_EN;
1269         bnx2_write_phy(bp, BCM5708S_1000X_CTL2, val);
1270
1271         if (bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) {
1272                 bnx2_read_phy(bp, BCM5708S_UP1, &val);
1273                 val |= BCM5708S_UP1_2G5;
1274                 bnx2_write_phy(bp, BCM5708S_UP1, val);
1275         }
1276
1277         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
1278             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
1279             (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
1280                 /* increase tx signal amplitude */
1281                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1282                                BCM5708S_BLK_ADDR_TX_MISC);
1283                 bnx2_read_phy(bp, BCM5708S_TX_ACTL1, &val);
1284                 val &= ~BCM5708S_TX_ACTL1_DRIVER_VCM;
1285                 bnx2_write_phy(bp, BCM5708S_TX_ACTL1, val);
1286                 bnx2_write_phy(bp, BCM5708S_BLK_ADDR, BCM5708S_BLK_ADDR_DIG);
1287         }
1288
1289         val = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG) &
1290               BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK;
1291
1292         if (val) {
1293                 u32 is_backplane;
1294
1295                 is_backplane = REG_RD_IND(bp, bp->shmem_base +
1296                                           BNX2_SHARED_HW_CFG_CONFIG);
1297                 if (is_backplane & BNX2_SHARED_HW_CFG_PHY_BACKPLANE) {
1298                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1299                                        BCM5708S_BLK_ADDR_TX_MISC);
1300                         bnx2_write_phy(bp, BCM5708S_TX_ACTL3, val);
1301                         bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
1302                                        BCM5708S_BLK_ADDR_DIG);
1303                 }
1304         }
1305         return 0;
1306 }
1307
1308 static int
1309 bnx2_init_5706s_phy(struct bnx2 *bp)
1310 {
1311         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
1312
1313         if (CHIP_NUM(bp) == CHIP_NUM_5706)
1314                 REG_WR(bp, BNX2_MISC_GP_HW_CTL0, 0x300);
1315
1316         if (bp->dev->mtu > 1500) {
1317                 u32 val;
1318
1319                 /* Set extended packet length bit */
1320                 bnx2_write_phy(bp, 0x18, 0x7);
1321                 bnx2_read_phy(bp, 0x18, &val);
1322                 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
1323
1324                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1325                 bnx2_read_phy(bp, 0x1c, &val);
1326                 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
1327         }
1328         else {
1329                 u32 val;
1330
1331                 bnx2_write_phy(bp, 0x18, 0x7);
1332                 bnx2_read_phy(bp, 0x18, &val);
1333                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1334
1335                 bnx2_write_phy(bp, 0x1c, 0x6c00);
1336                 bnx2_read_phy(bp, 0x1c, &val);
1337                 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
1338         }
1339
1340         return 0;
1341 }
1342
1343 static int
1344 bnx2_init_copper_phy(struct bnx2 *bp)
1345 {
1346         u32 val;
1347
1348         if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1349                 bnx2_write_phy(bp, 0x18, 0x0c00);
1350                 bnx2_write_phy(bp, 0x17, 0x000a);
1351                 bnx2_write_phy(bp, 0x15, 0x310b);
1352                 bnx2_write_phy(bp, 0x17, 0x201f);
1353                 bnx2_write_phy(bp, 0x15, 0x9506);
1354                 bnx2_write_phy(bp, 0x17, 0x401f);
1355                 bnx2_write_phy(bp, 0x15, 0x14e2);
1356                 bnx2_write_phy(bp, 0x18, 0x0400);
1357         }
1358
1359         if (bp->phy_flags & PHY_DIS_EARLY_DAC_FLAG) {
1360                 bnx2_write_phy(bp, MII_BNX2_DSP_ADDRESS,
1361                                MII_BNX2_DSP_EXPAND_REG | 0x8);
1362                 bnx2_read_phy(bp, MII_BNX2_DSP_RW_PORT, &val);
1363                 val &= ~(1 << 8);
1364                 bnx2_write_phy(bp, MII_BNX2_DSP_RW_PORT, val);
1365         }
1366
1367         if (bp->dev->mtu > 1500) {
1368                 /* Set extended packet length bit */
1369                 bnx2_write_phy(bp, 0x18, 0x7);
1370                 bnx2_read_phy(bp, 0x18, &val);
1371                 bnx2_write_phy(bp, 0x18, val | 0x4000);
1372
1373                 bnx2_read_phy(bp, 0x10, &val);
1374                 bnx2_write_phy(bp, 0x10, val | 0x1);
1375         }
1376         else {
1377                 bnx2_write_phy(bp, 0x18, 0x7);
1378                 bnx2_read_phy(bp, 0x18, &val);
1379                 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1380
1381                 bnx2_read_phy(bp, 0x10, &val);
1382                 bnx2_write_phy(bp, 0x10, val & ~0x1);
1383         }
1384
1385         /* ethernet@wirespeed */
1386         bnx2_write_phy(bp, 0x18, 0x7007);
1387         bnx2_read_phy(bp, 0x18, &val);
1388         bnx2_write_phy(bp, 0x18, val | (1 << 15) | (1 << 4));
1389         return 0;
1390 }
1391
1392
1393 static int
1394 bnx2_init_phy(struct bnx2 *bp)
1395 {
1396         u32 val;
1397         int rc = 0;
1398
1399         bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1400         bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1401
1402         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1403
1404         bnx2_reset_phy(bp);
1405
1406         bnx2_read_phy(bp, MII_PHYSID1, &val);
1407         bp->phy_id = val << 16;
1408         bnx2_read_phy(bp, MII_PHYSID2, &val);
1409         bp->phy_id |= val & 0xffff;
1410
1411         if (bp->phy_flags & PHY_SERDES_FLAG) {
1412                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
1413                         rc = bnx2_init_5706s_phy(bp);
1414                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
1415                         rc = bnx2_init_5708s_phy(bp);
1416         }
1417         else {
1418                 rc = bnx2_init_copper_phy(bp);
1419         }
1420
1421         bnx2_setup_phy(bp);
1422
1423         return rc;
1424 }
1425
1426 static int
1427 bnx2_set_mac_loopback(struct bnx2 *bp)
1428 {
1429         u32 mac_mode;
1430
1431         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1432         mac_mode &= ~BNX2_EMAC_MODE_PORT;
1433         mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1434         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1435         bp->link_up = 1;
1436         return 0;
1437 }
1438
1439 static int bnx2_test_link(struct bnx2 *);
1440
1441 static int
1442 bnx2_set_phy_loopback(struct bnx2 *bp)
1443 {
1444         u32 mac_mode;
1445         int rc, i;
1446
1447         spin_lock_bh(&bp->phy_lock);
1448         rc = bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
1449                             BMCR_SPEED1000);
1450         spin_unlock_bh(&bp->phy_lock);
1451         if (rc)
1452                 return rc;
1453
1454         for (i = 0; i < 10; i++) {
1455                 if (bnx2_test_link(bp) == 0)
1456                         break;
1457                 msleep(100);
1458         }
1459
1460         mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1461         mac_mode &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
1462                       BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK |
1463                       BNX2_EMAC_MODE_25G_MODE);
1464
1465         mac_mode |= BNX2_EMAC_MODE_PORT_GMII;
1466         REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1467         bp->link_up = 1;
1468         return 0;
1469 }
1470
1471 static int
1472 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
1473 {
1474         int i;
1475         u32 val;
1476
1477         bp->fw_wr_seq++;
1478         msg_data |= bp->fw_wr_seq;
1479
1480         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1481
1482         /* wait for an acknowledgement. */
1483         for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
1484                 msleep(10);
1485
1486                 val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
1487
1488                 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1489                         break;
1490         }
1491         if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
1492                 return 0;
1493
1494         /* If we timed out, inform the firmware that this is the case. */
1495         if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
1496                 if (!silent)
1497                         printk(KERN_ERR PFX "fw sync timeout, reset code = "
1498                                             "%x\n", msg_data);
1499
1500                 msg_data &= ~BNX2_DRV_MSG_CODE;
1501                 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1502
1503                 REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
1504
1505                 return -EBUSY;
1506         }
1507
1508         if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
1509                 return -EIO;
1510
1511         return 0;
1512 }
1513
1514 static int
1515 bnx2_init_5709_context(struct bnx2 *bp)
1516 {
1517         int i, ret = 0;
1518         u32 val;
1519
1520         val = BNX2_CTX_COMMAND_ENABLED | BNX2_CTX_COMMAND_MEM_INIT | (1 << 12);
1521         val |= (BCM_PAGE_BITS - 8) << 16;
1522         REG_WR(bp, BNX2_CTX_COMMAND, val);
1523         for (i = 0; i < bp->ctx_pages; i++) {
1524                 int j;
1525
1526                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA0,
1527                        (bp->ctx_blk_mapping[i] & 0xffffffff) |
1528                        BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID);
1529                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_DATA1,
1530                        (u64) bp->ctx_blk_mapping[i] >> 32);
1531                 REG_WR(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL, i |
1532                        BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
1533                 for (j = 0; j < 10; j++) {
1534
1535                         val = REG_RD(bp, BNX2_CTX_HOST_PAGE_TBL_CTRL);
1536                         if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
1537                                 break;
1538                         udelay(5);
1539                 }
1540                 if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
1541                         ret = -EBUSY;
1542                         break;
1543                 }
1544         }
1545         return ret;
1546 }
1547
1548 static void
1549 bnx2_init_context(struct bnx2 *bp)
1550 {
1551         u32 vcid;
1552
1553         vcid = 96;
1554         while (vcid) {
1555                 u32 vcid_addr, pcid_addr, offset;
1556
1557                 vcid--;
1558
1559                 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1560                         u32 new_vcid;
1561
1562                         vcid_addr = GET_PCID_ADDR(vcid);
1563                         if (vcid & 0x8) {
1564                                 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1565                         }
1566                         else {
1567                                 new_vcid = vcid;
1568                         }
1569                         pcid_addr = GET_PCID_ADDR(new_vcid);
1570                 }
1571                 else {
1572                         vcid_addr = GET_CID_ADDR(vcid);
1573                         pcid_addr = vcid_addr;
1574                 }
1575
1576                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1577                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1578
1579                 /* Zero out the context. */
1580                 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1581                         CTX_WR(bp, 0x00, offset, 0);
1582                 }
1583
1584                 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1585                 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1586         }
1587 }
1588
1589 static int
1590 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1591 {
1592         u16 *good_mbuf;
1593         u32 good_mbuf_cnt;
1594         u32 val;
1595
1596         good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1597         if (good_mbuf == NULL) {
1598                 printk(KERN_ERR PFX "Failed to allocate memory in "
1599                                     "bnx2_alloc_bad_rbuf\n");
1600                 return -ENOMEM;
1601         }
1602
1603         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1604                 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1605
1606         good_mbuf_cnt = 0;
1607
1608         /* Allocate a bunch of mbufs and save the good ones in an array. */
1609         val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1610         while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1611                 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1612
1613                 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1614
1615                 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1616
1617                 /* The addresses with Bit 9 set are bad memory blocks. */
1618                 if (!(val & (1 << 9))) {
1619                         good_mbuf[good_mbuf_cnt] = (u16) val;
1620                         good_mbuf_cnt++;
1621                 }
1622
1623                 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1624         }
1625
1626         /* Free the good ones back to the mbuf pool thus discarding
1627          * all the bad ones. */
1628         while (good_mbuf_cnt) {
1629                 good_mbuf_cnt--;
1630
1631                 val = good_mbuf[good_mbuf_cnt];
1632                 val = (val << 9) | val | 1;
1633
1634                 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1635         }
1636         kfree(good_mbuf);
1637         return 0;
1638 }
1639
1640 static void
1641 bnx2_set_mac_addr(struct bnx2 *bp)
1642 {
1643         u32 val;
1644         u8 *mac_addr = bp->dev->dev_addr;
1645
1646         val = (mac_addr[0] << 8) | mac_addr[1];
1647
1648         REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1649
1650         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1651                 (mac_addr[4] << 8) | mac_addr[5];
1652
1653         REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1654 }
1655
1656 static inline int
1657 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1658 {
1659         struct sk_buff *skb;
1660         struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1661         dma_addr_t mapping;
1662         struct rx_bd *rxbd = &bp->rx_desc_ring[RX_RING(index)][RX_IDX(index)];
1663         unsigned long align;
1664
1665         skb = netdev_alloc_skb(bp->dev, bp->rx_buf_size);
1666         if (skb == NULL) {
1667                 return -ENOMEM;
1668         }
1669
1670         if (unlikely((align = (unsigned long) skb->data & (BNX2_RX_ALIGN - 1))))
1671                 skb_reserve(skb, BNX2_RX_ALIGN - align);
1672
1673         mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1674                 PCI_DMA_FROMDEVICE);
1675
1676         rx_buf->skb = skb;
1677         pci_unmap_addr_set(rx_buf, mapping, mapping);
1678
1679         rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1680         rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1681
1682         bp->rx_prod_bseq += bp->rx_buf_use_size;
1683
1684         return 0;
1685 }
1686
1687 static void
1688 bnx2_phy_int(struct bnx2 *bp)
1689 {
1690         u32 new_link_state, old_link_state;
1691
1692         new_link_state = bp->status_blk->status_attn_bits &
1693                 STATUS_ATTN_BITS_LINK_STATE;
1694         old_link_state = bp->status_blk->status_attn_bits_ack &
1695                 STATUS_ATTN_BITS_LINK_STATE;
1696         if (new_link_state != old_link_state) {
1697                 if (new_link_state) {
1698                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1699                                 STATUS_ATTN_BITS_LINK_STATE);
1700                 }
1701                 else {
1702                         REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1703                                 STATUS_ATTN_BITS_LINK_STATE);
1704                 }
1705                 bnx2_set_link(bp);
1706         }
1707 }
1708
1709 static void
1710 bnx2_tx_int(struct bnx2 *bp)
1711 {
1712         struct status_block *sblk = bp->status_blk;
1713         u16 hw_cons, sw_cons, sw_ring_cons;
1714         int tx_free_bd = 0;
1715
1716         hw_cons = bp->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
1717         if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1718                 hw_cons++;
1719         }
1720         sw_cons = bp->tx_cons;
1721
1722         while (sw_cons != hw_cons) {
1723                 struct sw_bd *tx_buf;
1724                 struct sk_buff *skb;
1725                 int i, last;
1726
1727                 sw_ring_cons = TX_RING_IDX(sw_cons);
1728
1729                 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1730                 skb = tx_buf->skb;
1731 #ifdef BCM_TSO
1732                 /* partial BD completions possible with TSO packets */
1733                 if (skb_is_gso(skb)) {
1734                         u16 last_idx, last_ring_idx;
1735
1736                         last_idx = sw_cons +
1737                                 skb_shinfo(skb)->nr_frags + 1;
1738                         last_ring_idx = sw_ring_cons +
1739                                 skb_shinfo(skb)->nr_frags + 1;
1740                         if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1741                                 last_idx++;
1742                         }
1743                         if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1744                                 break;
1745                         }
1746                 }
1747 #endif
1748                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1749                         skb_headlen(skb), PCI_DMA_TODEVICE);
1750
1751                 tx_buf->skb = NULL;
1752                 last = skb_shinfo(skb)->nr_frags;
1753
1754                 for (i = 0; i < last; i++) {
1755                         sw_cons = NEXT_TX_BD(sw_cons);
1756
1757                         pci_unmap_page(bp->pdev,
1758                                 pci_unmap_addr(
1759                                         &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1760                                         mapping),
1761                                 skb_shinfo(skb)->frags[i].size,
1762                                 PCI_DMA_TODEVICE);
1763                 }
1764
1765                 sw_cons = NEXT_TX_BD(sw_cons);
1766
1767                 tx_free_bd += last + 1;
1768
1769                 dev_kfree_skb(skb);
1770
1771                 hw_cons = bp->hw_tx_cons =
1772                         sblk->status_tx_quick_consumer_index0;
1773
1774                 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1775                         hw_cons++;
1776                 }
1777         }
1778
1779         bp->tx_cons = sw_cons;
1780         /* Need to make the tx_cons update visible to bnx2_start_xmit()
1781          * before checking for netif_queue_stopped().  Without the
1782          * memory barrier, there is a small possibility that bnx2_start_xmit()
1783          * will miss it and cause the queue to be stopped forever.
1784          */
1785         smp_mb();
1786
1787         if (unlikely(netif_queue_stopped(bp->dev)) &&
1788                      (bnx2_tx_avail(bp) > bp->tx_wake_thresh)) {
1789                 netif_tx_lock(bp->dev);
1790                 if ((netif_queue_stopped(bp->dev)) &&
1791                     (bnx2_tx_avail(bp) > bp->tx_wake_thresh))
1792                         netif_wake_queue(bp->dev);
1793                 netif_tx_unlock(bp->dev);
1794         }
1795 }
1796
1797 static inline void
1798 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1799         u16 cons, u16 prod)
1800 {
1801         struct sw_bd *cons_rx_buf, *prod_rx_buf;
1802         struct rx_bd *cons_bd, *prod_bd;
1803
1804         cons_rx_buf = &bp->rx_buf_ring[cons];
1805         prod_rx_buf = &bp->rx_buf_ring[prod];
1806
1807         pci_dma_sync_single_for_device(bp->pdev,
1808                 pci_unmap_addr(cons_rx_buf, mapping),
1809                 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1810
1811         bp->rx_prod_bseq += bp->rx_buf_use_size;
1812
1813         prod_rx_buf->skb = skb;
1814
1815         if (cons == prod)
1816                 return;
1817
1818         pci_unmap_addr_set(prod_rx_buf, mapping,
1819                         pci_unmap_addr(cons_rx_buf, mapping));
1820
1821         cons_bd = &bp->rx_desc_ring[RX_RING(cons)][RX_IDX(cons)];
1822         prod_bd = &bp->rx_desc_ring[RX_RING(prod)][RX_IDX(prod)];
1823         prod_bd->rx_bd_haddr_hi = cons_bd->rx_bd_haddr_hi;
1824         prod_bd->rx_bd_haddr_lo = cons_bd->rx_bd_haddr_lo;
1825 }
1826
1827 static int
1828 bnx2_rx_int(struct bnx2 *bp, int budget)
1829 {
1830         struct status_block *sblk = bp->status_blk;
1831         u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1832         struct l2_fhdr *rx_hdr;
1833         int rx_pkt = 0;
1834
1835         hw_cons = bp->hw_rx_cons = sblk->status_rx_quick_consumer_index0;
1836         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1837                 hw_cons++;
1838         }
1839         sw_cons = bp->rx_cons;
1840         sw_prod = bp->rx_prod;
1841
1842         /* Memory barrier necessary as speculative reads of the rx
1843          * buffer can be ahead of the index in the status block
1844          */
1845         rmb();
1846         while (sw_cons != hw_cons) {
1847                 unsigned int len;
1848                 u32 status;
1849                 struct sw_bd *rx_buf;
1850                 struct sk_buff *skb;
1851                 dma_addr_t dma_addr;
1852
1853                 sw_ring_cons = RX_RING_IDX(sw_cons);
1854                 sw_ring_prod = RX_RING_IDX(sw_prod);
1855
1856                 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1857                 skb = rx_buf->skb;
1858
1859                 rx_buf->skb = NULL;
1860
1861                 dma_addr = pci_unmap_addr(rx_buf, mapping);
1862
1863                 pci_dma_sync_single_for_cpu(bp->pdev, dma_addr,
1864                         bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1865
1866                 rx_hdr = (struct l2_fhdr *) skb->data;
1867                 len = rx_hdr->l2_fhdr_pkt_len - 4;
1868
1869                 if ((status = rx_hdr->l2_fhdr_status) &
1870                         (L2_FHDR_ERRORS_BAD_CRC |
1871                         L2_FHDR_ERRORS_PHY_DECODE |
1872                         L2_FHDR_ERRORS_ALIGNMENT |
1873                         L2_FHDR_ERRORS_TOO_SHORT |
1874                         L2_FHDR_ERRORS_GIANT_FRAME)) {
1875
1876                         goto reuse_rx;
1877                 }
1878
1879                 /* Since we don't have a jumbo ring, copy small packets
1880                  * if mtu > 1500
1881                  */
1882                 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1883                         struct sk_buff *new_skb;
1884
1885                         new_skb = netdev_alloc_skb(bp->dev, len + 2);
1886                         if (new_skb == NULL)
1887                                 goto reuse_rx;
1888
1889                         /* aligned copy */
1890                         memcpy(new_skb->data,
1891                                 skb->data + bp->rx_offset - 2,
1892                                 len + 2);
1893
1894                         skb_reserve(new_skb, 2);
1895                         skb_put(new_skb, len);
1896
1897                         bnx2_reuse_rx_skb(bp, skb,
1898                                 sw_ring_cons, sw_ring_prod);
1899
1900                         skb = new_skb;
1901                 }
1902                 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1903                         pci_unmap_single(bp->pdev, dma_addr,
1904                                 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1905
1906                         skb_reserve(skb, bp->rx_offset);
1907                         skb_put(skb, len);
1908                 }
1909                 else {
1910 reuse_rx:
1911                         bnx2_reuse_rx_skb(bp, skb,
1912                                 sw_ring_cons, sw_ring_prod);
1913                         goto next_rx;
1914                 }
1915
1916                 skb->protocol = eth_type_trans(skb, bp->dev);
1917
1918                 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1919                         (ntohs(skb->protocol) != 0x8100)) {
1920
1921                         dev_kfree_skb(skb);
1922                         goto next_rx;
1923
1924                 }
1925
1926                 skb->ip_summed = CHECKSUM_NONE;
1927                 if (bp->rx_csum &&
1928                         (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1929                         L2_FHDR_STATUS_UDP_DATAGRAM))) {
1930
1931                         if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
1932                                               L2_FHDR_ERRORS_UDP_XSUM)) == 0))
1933                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1934                 }
1935
1936 #ifdef BCM_VLAN
1937                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1938                         vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1939                                 rx_hdr->l2_fhdr_vlan_tag);
1940                 }
1941                 else
1942 #endif
1943                         netif_receive_skb(skb);
1944
1945                 bp->dev->last_rx = jiffies;
1946                 rx_pkt++;
1947
1948 next_rx:
1949                 sw_cons = NEXT_RX_BD(sw_cons);
1950                 sw_prod = NEXT_RX_BD(sw_prod);
1951
1952                 if ((rx_pkt == budget))
1953                         break;
1954
1955                 /* Refresh hw_cons to see if there is new work */
1956                 if (sw_cons == hw_cons) {
1957                         hw_cons = bp->hw_rx_cons =
1958                                 sblk->status_rx_quick_consumer_index0;
1959                         if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT)
1960                                 hw_cons++;
1961                         rmb();
1962                 }
1963         }
1964         bp->rx_cons = sw_cons;
1965         bp->rx_prod = sw_prod;
1966
1967         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1968
1969         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1970
1971         mmiowb();
1972
1973         return rx_pkt;
1974
1975 }
1976
1977 /* MSI ISR - The only difference between this and the INTx ISR
1978  * is that the MSI interrupt is always serviced.
1979  */
1980 static irqreturn_t
1981 bnx2_msi(int irq, void *dev_instance)
1982 {
1983         struct net_device *dev = dev_instance;
1984         struct bnx2 *bp = netdev_priv(dev);
1985
1986         prefetch(bp->status_blk);
1987         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1988                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1989                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1990
1991         /* Return here if interrupt is disabled. */
1992         if (unlikely(atomic_read(&bp->intr_sem) != 0))
1993                 return IRQ_HANDLED;
1994
1995         netif_rx_schedule(dev);
1996
1997         return IRQ_HANDLED;
1998 }
1999
2000 static irqreturn_t
2001 bnx2_interrupt(int irq, void *dev_instance)
2002 {
2003         struct net_device *dev = dev_instance;
2004         struct bnx2 *bp = netdev_priv(dev);
2005
2006         /* When using INTx, it is possible for the interrupt to arrive
2007          * at the CPU before the status block posted prior to the
2008          * interrupt. Reading a register will flush the status block.
2009          * When using MSI, the MSI message will always complete after
2010          * the status block write.
2011          */
2012         if ((bp->status_blk->status_idx == bp->last_status_idx) &&
2013             (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
2014              BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
2015                 return IRQ_NONE;
2016
2017         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2018                 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
2019                 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2020
2021         /* Return here if interrupt is shared and is disabled. */
2022         if (unlikely(atomic_read(&bp->intr_sem) != 0))
2023                 return IRQ_HANDLED;
2024
2025         netif_rx_schedule(dev);
2026
2027         return IRQ_HANDLED;
2028 }
2029
2030 static inline int
2031 bnx2_has_work(struct bnx2 *bp)
2032 {
2033         struct status_block *sblk = bp->status_blk;
2034
2035         if ((sblk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) ||
2036             (sblk->status_tx_quick_consumer_index0 != bp->hw_tx_cons))
2037                 return 1;
2038
2039         if (((sblk->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
2040             bp->link_up)
2041                 return 1;
2042
2043         return 0;
2044 }
2045
2046 static int
2047 bnx2_poll(struct net_device *dev, int *budget)
2048 {
2049         struct bnx2 *bp = netdev_priv(dev);
2050
2051         if ((bp->status_blk->status_attn_bits &
2052                 STATUS_ATTN_BITS_LINK_STATE) !=
2053                 (bp->status_blk->status_attn_bits_ack &
2054                 STATUS_ATTN_BITS_LINK_STATE)) {
2055
2056                 spin_lock(&bp->phy_lock);
2057                 bnx2_phy_int(bp);
2058                 spin_unlock(&bp->phy_lock);
2059
2060                 /* This is needed to take care of transient status
2061                  * during link changes.
2062                  */
2063                 REG_WR(bp, BNX2_HC_COMMAND,
2064                        bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
2065                 REG_RD(bp, BNX2_HC_COMMAND);
2066         }
2067
2068         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->hw_tx_cons)
2069                 bnx2_tx_int(bp);
2070
2071         if (bp->status_blk->status_rx_quick_consumer_index0 != bp->hw_rx_cons) {
2072                 int orig_budget = *budget;
2073                 int work_done;
2074
2075                 if (orig_budget > dev->quota)
2076                         orig_budget = dev->quota;
2077
2078                 work_done = bnx2_rx_int(bp, orig_budget);
2079                 *budget -= work_done;
2080                 dev->quota -= work_done;
2081         }
2082
2083         bp->last_status_idx = bp->status_blk->status_idx;
2084         rmb();
2085
2086         if (!bnx2_has_work(bp)) {
2087                 netif_rx_complete(dev);
2088                 if (likely(bp->flags & USING_MSI_FLAG)) {
2089                         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2090                                BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2091                                bp->last_status_idx);
2092                         return 0;
2093                 }
2094                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2095                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2096                        BNX2_PCICFG_INT_ACK_CMD_MASK_INT |
2097                        bp->last_status_idx);
2098
2099                 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
2100                        BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
2101                        bp->last_status_idx);
2102                 return 0;
2103         }
2104
2105         return 1;
2106 }
2107
2108 /* Called with rtnl_lock from vlan functions and also netif_tx_lock
2109  * from set_multicast.
2110  */
2111 static void
2112 bnx2_set_rx_mode(struct net_device *dev)
2113 {
2114         struct bnx2 *bp = netdev_priv(dev);
2115         u32 rx_mode, sort_mode;
2116         int i;
2117
2118         spin_lock_bh(&bp->phy_lock);
2119
2120         rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
2121                                   BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
2122         sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
2123 #ifdef BCM_VLAN
2124         if (!bp->vlgrp && !(bp->flags & ASF_ENABLE_FLAG))
2125                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2126 #else
2127         if (!(bp->flags & ASF_ENABLE_FLAG))
2128                 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
2129 #endif
2130         if (dev->flags & IFF_PROMISC) {
2131                 /* Promiscuous mode. */
2132                 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
2133                 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN |
2134                              BNX2_RPM_SORT_USER0_PROM_VLAN;
2135         }
2136         else if (dev->flags & IFF_ALLMULTI) {
2137                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2138                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2139                                0xffffffff);
2140                 }
2141                 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
2142         }
2143         else {
2144                 /* Accept one or more multicast(s). */
2145                 struct dev_mc_list *mclist;
2146                 u32 mc_filter[NUM_MC_HASH_REGISTERS];
2147                 u32 regidx;
2148                 u32 bit;
2149                 u32 crc;
2150
2151                 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
2152
2153                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2154                      i++, mclist = mclist->next) {
2155
2156                         crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
2157                         bit = crc & 0xff;
2158                         regidx = (bit & 0xe0) >> 5;
2159                         bit &= 0x1f;
2160                         mc_filter[regidx] |= (1 << bit);
2161                 }
2162
2163                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2164                         REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2165                                mc_filter[i]);
2166                 }
2167
2168                 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
2169         }
2170
2171         if (rx_mode != bp->rx_mode) {
2172                 bp->rx_mode = rx_mode;
2173                 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
2174         }
2175
2176         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2177         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
2178         REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
2179
2180         spin_unlock_bh(&bp->phy_lock);
2181 }
2182
2183 #define FW_BUF_SIZE     0x8000
2184
2185 static int
2186 bnx2_gunzip_init(struct bnx2 *bp)
2187 {
2188         if ((bp->gunzip_buf = vmalloc(FW_BUF_SIZE)) == NULL)
2189                 goto gunzip_nomem1;
2190
2191         if ((bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL)) == NULL)
2192                 goto gunzip_nomem2;
2193
2194         bp->strm->workspace = kmalloc(zlib_inflate_workspacesize(), GFP_KERNEL);
2195         if (bp->strm->workspace == NULL)
2196                 goto gunzip_nomem3;
2197
2198         return 0;
2199
2200 gunzip_nomem3:
2201         kfree(bp->strm);
2202         bp->strm = NULL;
2203
2204 gunzip_nomem2:
2205         vfree(bp->gunzip_buf);
2206         bp->gunzip_buf = NULL;
2207
2208 gunzip_nomem1:
2209         printk(KERN_ERR PFX "%s: Cannot allocate firmware buffer for "
2210                             "uncompression.\n", bp->dev->name);
2211         return -ENOMEM;
2212 }
2213
2214 static void
2215 bnx2_gunzip_end(struct bnx2 *bp)
2216 {
2217         kfree(bp->strm->workspace);
2218
2219         kfree(bp->strm);
2220         bp->strm = NULL;
2221
2222         if (bp->gunzip_buf) {
2223                 vfree(bp->gunzip_buf);
2224                 bp->gunzip_buf = NULL;
2225         }
2226 }
2227
2228 static int
2229 bnx2_gunzip(struct bnx2 *bp, u8 *zbuf, int len, void **outbuf, int *outlen)
2230 {
2231         int n, rc;
2232
2233         /* check gzip header */
2234         if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED))
2235                 return -EINVAL;
2236
2237         n = 10;
2238
2239 #define FNAME   0x8
2240         if (zbuf[3] & FNAME)
2241                 while ((zbuf[n++] != 0) && (n < len));
2242
2243         bp->strm->next_in = zbuf + n;
2244         bp->strm->avail_in = len - n;
2245         bp->strm->next_out = bp->gunzip_buf;
2246         bp->strm->avail_out = FW_BUF_SIZE;
2247
2248         rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
2249         if (rc != Z_OK)
2250                 return rc;
2251
2252         rc = zlib_inflate(bp->strm, Z_FINISH);
2253
2254         *outlen = FW_BUF_SIZE - bp->strm->avail_out;
2255         *outbuf = bp->gunzip_buf;
2256
2257         if ((rc != Z_OK) && (rc != Z_STREAM_END))
2258                 printk(KERN_ERR PFX "%s: Firmware decompression error: %s\n",
2259                        bp->dev->name, bp->strm->msg);
2260
2261         zlib_inflateEnd(bp->strm);
2262
2263         if (rc == Z_STREAM_END)
2264                 return 0;
2265
2266         return rc;
2267 }
2268
2269 static void
2270 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
2271         u32 rv2p_proc)
2272 {
2273         int i;
2274         u32 val;
2275
2276
2277         for (i = 0; i < rv2p_code_len; i += 8) {
2278                 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, cpu_to_le32(*rv2p_code));
2279                 rv2p_code++;
2280                 REG_WR(bp, BNX2_RV2P_INSTR_LOW, cpu_to_le32(*rv2p_code));
2281                 rv2p_code++;
2282
2283                 if (rv2p_proc == RV2P_PROC1) {
2284                         val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
2285                         REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
2286                 }
2287                 else {
2288                         val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
2289                         REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
2290                 }
2291         }
2292
2293         /* Reset the processor, un-stall is done later. */
2294         if (rv2p_proc == RV2P_PROC1) {
2295                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
2296         }
2297         else {
2298                 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
2299         }
2300 }
2301
2302 static int
2303 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
2304 {
2305         u32 offset;
2306         u32 val;
2307         int rc;
2308
2309         /* Halt the CPU. */
2310         val = REG_RD_IND(bp, cpu_reg->mode);
2311         val |= cpu_reg->mode_value_halt;
2312         REG_WR_IND(bp, cpu_reg->mode, val);
2313         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2314
2315         /* Load the Text area. */
2316         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2317         if (fw->gz_text) {
2318                 u32 text_len;
2319                 void *text;
2320
2321                 rc = bnx2_gunzip(bp, fw->gz_text, fw->gz_text_len, &text,
2322                                  &text_len);
2323                 if (rc)
2324                         return rc;
2325
2326                 fw->text = text;
2327         }
2328         if (fw->gz_text) {
2329                 int j;
2330
2331                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
2332                         REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
2333                 }
2334         }
2335
2336         /* Load the Data area. */
2337         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2338         if (fw->data) {
2339                 int j;
2340
2341                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
2342                         REG_WR_IND(bp, offset, fw->data[j]);
2343                 }
2344         }
2345
2346         /* Load the SBSS area. */
2347         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2348         if (fw->sbss) {
2349                 int j;
2350
2351                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
2352                         REG_WR_IND(bp, offset, fw->sbss[j]);
2353                 }
2354         }
2355
2356         /* Load the BSS area. */
2357         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2358         if (fw->bss) {
2359                 int j;
2360
2361                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
2362                         REG_WR_IND(bp, offset, fw->bss[j]);
2363                 }
2364         }
2365
2366         /* Load the Read-Only area. */
2367         offset = cpu_reg->spad_base +
2368                 (fw->rodata_addr - cpu_reg->mips_view_base);
2369         if (fw->rodata) {
2370                 int j;
2371
2372                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
2373                         REG_WR_IND(bp, offset, fw->rodata[j]);
2374                 }
2375         }
2376
2377         /* Clear the pre-fetch instruction. */
2378         REG_WR_IND(bp, cpu_reg->inst, 0);
2379         REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
2380
2381         /* Start the CPU. */
2382         val = REG_RD_IND(bp, cpu_reg->mode);
2383         val &= ~cpu_reg->mode_value_halt;
2384         REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
2385         REG_WR_IND(bp, cpu_reg->mode, val);
2386
2387         return 0;
2388 }
2389
2390 static int
2391 bnx2_init_cpus(struct bnx2 *bp)
2392 {
2393         struct cpu_reg cpu_reg;
2394         struct fw_info *fw;
2395         int rc = 0;
2396         void *text;
2397         u32 text_len;
2398
2399         if ((rc = bnx2_gunzip_init(bp)) != 0)
2400                 return rc;
2401
2402         /* Initialize the RV2P processor. */
2403         rc = bnx2_gunzip(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), &text,
2404                          &text_len);
2405         if (rc)
2406                 goto init_cpu_err;
2407
2408         load_rv2p_fw(bp, text, text_len, RV2P_PROC1);
2409
2410         rc = bnx2_gunzip(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), &text,
2411                          &text_len);
2412         if (rc)
2413                 goto init_cpu_err;
2414
2415         load_rv2p_fw(bp, text, text_len, RV2P_PROC2);
2416
2417         /* Initialize the RX Processor. */
2418         cpu_reg.mode = BNX2_RXP_CPU_MODE;
2419         cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
2420         cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
2421         cpu_reg.state = BNX2_RXP_CPU_STATE;
2422         cpu_reg.state_value_clear = 0xffffff;
2423         cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
2424         cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
2425         cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
2426         cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
2427         cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
2428         cpu_reg.spad_base = BNX2_RXP_SCRATCH;
2429         cpu_reg.mips_view_base = 0x8000000;
2430
2431         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2432                 fw = &bnx2_rxp_fw_09;
2433         else
2434                 fw = &bnx2_rxp_fw_06;
2435
2436         rc = load_cpu_fw(bp, &cpu_reg, fw);
2437         if (rc)
2438                 goto init_cpu_err;
2439
2440         /* Initialize the TX Processor. */
2441         cpu_reg.mode = BNX2_TXP_CPU_MODE;
2442         cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
2443         cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
2444         cpu_reg.state = BNX2_TXP_CPU_STATE;
2445         cpu_reg.state_value_clear = 0xffffff;
2446         cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
2447         cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
2448         cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
2449         cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
2450         cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
2451         cpu_reg.spad_base = BNX2_TXP_SCRATCH;
2452         cpu_reg.mips_view_base = 0x8000000;
2453
2454         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2455                 fw = &bnx2_txp_fw_09;
2456         else
2457                 fw = &bnx2_txp_fw_06;
2458
2459         rc = load_cpu_fw(bp, &cpu_reg, fw);
2460         if (rc)
2461                 goto init_cpu_err;
2462
2463         /* Initialize the TX Patch-up Processor. */
2464         cpu_reg.mode = BNX2_TPAT_CPU_MODE;
2465         cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
2466         cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
2467         cpu_reg.state = BNX2_TPAT_CPU_STATE;
2468         cpu_reg.state_value_clear = 0xffffff;
2469         cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
2470         cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
2471         cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
2472         cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
2473         cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
2474         cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
2475         cpu_reg.mips_view_base = 0x8000000;
2476
2477         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2478                 fw = &bnx2_tpat_fw_09;
2479         else
2480                 fw = &bnx2_tpat_fw_06;
2481
2482         rc = load_cpu_fw(bp, &cpu_reg, fw);
2483         if (rc)
2484                 goto init_cpu_err;
2485
2486         /* Initialize the Completion Processor. */
2487         cpu_reg.mode = BNX2_COM_CPU_MODE;
2488         cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
2489         cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
2490         cpu_reg.state = BNX2_COM_CPU_STATE;
2491         cpu_reg.state_value_clear = 0xffffff;
2492         cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
2493         cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
2494         cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
2495         cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
2496         cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
2497         cpu_reg.spad_base = BNX2_COM_SCRATCH;
2498         cpu_reg.mips_view_base = 0x8000000;
2499
2500         if (CHIP_NUM(bp) == CHIP_NUM_5709)
2501                 fw = &bnx2_com_fw_09;
2502         else
2503                 fw = &bnx2_com_fw_06;
2504
2505         rc = load_cpu_fw(bp, &cpu_reg, fw);
2506         if (rc)
2507                 goto init_cpu_err;
2508
2509         /* Initialize the Command Processor. */
2510         cpu_reg.mode = BNX2_CP_CPU_MODE;
2511         cpu_reg.mode_value_halt = BNX2_CP_CPU_MODE_SOFT_HALT;
2512         cpu_reg.mode_value_sstep = BNX2_CP_CPU_MODE_STEP_ENA;
2513         cpu_reg.state = BNX2_CP_CPU_STATE;
2514         cpu_reg.state_value_clear = 0xffffff;
2515         cpu_reg.gpr0 = BNX2_CP_CPU_REG_FILE;
2516         cpu_reg.evmask = BNX2_CP_CPU_EVENT_MASK;
2517         cpu_reg.pc = BNX2_CP_CPU_PROGRAM_COUNTER;
2518         cpu_reg.inst = BNX2_CP_CPU_INSTRUCTION;
2519         cpu_reg.bp = BNX2_CP_CPU_HW_BREAKPOINT;
2520         cpu_reg.spad_base = BNX2_CP_SCRATCH;
2521         cpu_reg.mips_view_base = 0x8000000;
2522
2523         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
2524                 fw = &bnx2_cp_fw_09;
2525
2526                 rc = load_cpu_fw(bp, &cpu_reg, fw);
2527                 if (rc)
2528                         goto init_cpu_err;
2529         }
2530 init_cpu_err:
2531         bnx2_gunzip_end(bp);
2532         return rc;
2533 }
2534
2535 static int
2536 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2537 {
2538         u16 pmcsr;
2539
2540         pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2541
2542         switch (state) {
2543         case PCI_D0: {
2544                 u32 val;
2545
2546                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2547                         (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2548                         PCI_PM_CTRL_PME_STATUS);
2549
2550                 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2551                         /* delay required during transition out of D3hot */
2552                         msleep(20);
2553
2554                 val = REG_RD(bp, BNX2_EMAC_MODE);
2555                 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2556                 val &= ~BNX2_EMAC_MODE_MPKT;
2557                 REG_WR(bp, BNX2_EMAC_MODE, val);
2558
2559                 val = REG_RD(bp, BNX2_RPM_CONFIG);
2560                 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2561                 REG_WR(bp, BNX2_RPM_CONFIG, val);
2562                 break;
2563         }
2564         case PCI_D3hot: {
2565                 int i;
2566                 u32 val, wol_msg;
2567
2568                 if (bp->wol) {
2569                         u32 advertising;
2570                         u8 autoneg;
2571
2572                         autoneg = bp->autoneg;
2573                         advertising = bp->advertising;
2574
2575                         bp->autoneg = AUTONEG_SPEED;
2576                         bp->advertising = ADVERTISED_10baseT_Half |
2577                                 ADVERTISED_10baseT_Full |
2578                                 ADVERTISED_100baseT_Half |
2579                                 ADVERTISED_100baseT_Full |
2580                                 ADVERTISED_Autoneg;
2581
2582                         bnx2_setup_copper_phy(bp);
2583
2584                         bp->autoneg = autoneg;
2585                         bp->advertising = advertising;
2586
2587                         bnx2_set_mac_addr(bp);
2588
2589                         val = REG_RD(bp, BNX2_EMAC_MODE);
2590
2591                         /* Enable port mode. */
2592                         val &= ~BNX2_EMAC_MODE_PORT;
2593                         val |= BNX2_EMAC_MODE_PORT_MII |
2594                                BNX2_EMAC_MODE_MPKT_RCVD |
2595                                BNX2_EMAC_MODE_ACPI_RCVD |
2596                                BNX2_EMAC_MODE_MPKT;
2597
2598                         REG_WR(bp, BNX2_EMAC_MODE, val);
2599
2600                         /* receive all multicast */
2601                         for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2602                                 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2603                                        0xffffffff);
2604                         }
2605                         REG_WR(bp, BNX2_EMAC_RX_MODE,
2606                                BNX2_EMAC_RX_MODE_SORT_MODE);
2607
2608                         val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2609                               BNX2_RPM_SORT_USER0_MC_EN;
2610                         REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2611                         REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2612                         REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2613                                BNX2_RPM_SORT_USER0_ENA);
2614
2615                         /* Need to enable EMAC and RPM for WOL. */
2616                         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2617                                BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2618                                BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2619                                BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2620
2621                         val = REG_RD(bp, BNX2_RPM_CONFIG);
2622                         val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2623                         REG_WR(bp, BNX2_RPM_CONFIG, val);
2624
2625                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2626                 }
2627                 else {
2628                         wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2629                 }
2630
2631                 if (!(bp->flags & NO_WOL_FLAG))
2632                         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
2633
2634                 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2635                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2636                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2637
2638                         if (bp->wol)
2639                                 pmcsr |= 3;
2640                 }
2641                 else {
2642                         pmcsr |= 3;
2643                 }
2644                 if (bp->wol) {
2645                         pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2646                 }
2647                 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2648                                       pmcsr);
2649
2650                 /* No more memory access after this point until
2651                  * device is brought back to D0.
2652                  */
2653                 udelay(50);
2654                 break;
2655         }
2656         default:
2657                 return -EINVAL;
2658         }
2659         return 0;
2660 }
2661
2662 static int
2663 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2664 {
2665         u32 val;
2666         int j;
2667
2668         /* Request access to the flash interface. */
2669         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2670         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2671                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2672                 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2673                         break;
2674
2675                 udelay(5);
2676         }
2677
2678         if (j >= NVRAM_TIMEOUT_COUNT)
2679                 return -EBUSY;
2680
2681         return 0;
2682 }
2683
2684 static int
2685 bnx2_release_nvram_lock(struct bnx2 *bp)
2686 {
2687         int j;
2688         u32 val;
2689
2690         /* Relinquish nvram interface. */
2691         REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2692
2693         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2694                 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2695                 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2696                         break;
2697
2698                 udelay(5);
2699         }
2700
2701         if (j >= NVRAM_TIMEOUT_COUNT)
2702                 return -EBUSY;
2703
2704         return 0;
2705 }
2706
2707
2708 static int
2709 bnx2_enable_nvram_write(struct bnx2 *bp)
2710 {
2711         u32 val;
2712
2713         val = REG_RD(bp, BNX2_MISC_CFG);
2714         REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2715
2716         if (!bp->flash_info->buffered) {
2717                 int j;
2718
2719                 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2720                 REG_WR(bp, BNX2_NVM_COMMAND,
2721                        BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2722
2723                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2724                         udelay(5);
2725
2726                         val = REG_RD(bp, BNX2_NVM_COMMAND);
2727                         if (val & BNX2_NVM_COMMAND_DONE)
2728                                 break;
2729                 }
2730
2731                 if (j >= NVRAM_TIMEOUT_COUNT)
2732                         return -EBUSY;
2733         }
2734         return 0;
2735 }
2736
2737 static void
2738 bnx2_disable_nvram_write(struct bnx2 *bp)
2739 {
2740         u32 val;
2741
2742         val = REG_RD(bp, BNX2_MISC_CFG);
2743         REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2744 }
2745
2746
2747 static void
2748 bnx2_enable_nvram_access(struct bnx2 *bp)
2749 {
2750         u32 val;
2751
2752         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2753         /* Enable both bits, even on read. */
2754         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2755                val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2756 }
2757
2758 static void
2759 bnx2_disable_nvram_access(struct bnx2 *bp)
2760 {
2761         u32 val;
2762
2763         val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2764         /* Disable both bits, even after read. */
2765         REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2766                 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2767                         BNX2_NVM_ACCESS_ENABLE_WR_EN));
2768 }
2769
2770 static int
2771 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2772 {
2773         u32 cmd;
2774         int j;
2775
2776         if (bp->flash_info->buffered)
2777                 /* Buffered flash, no erase needed */
2778                 return 0;
2779
2780         /* Build an erase command */
2781         cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2782               BNX2_NVM_COMMAND_DOIT;
2783
2784         /* Need to clear DONE bit separately. */
2785         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2786
2787         /* Address of the NVRAM to read from. */
2788         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2789
2790         /* Issue an erase command. */
2791         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2792
2793         /* Wait for completion. */
2794         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2795                 u32 val;
2796
2797                 udelay(5);
2798
2799                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2800                 if (val & BNX2_NVM_COMMAND_DONE)
2801                         break;
2802         }
2803
2804         if (j >= NVRAM_TIMEOUT_COUNT)
2805                 return -EBUSY;
2806
2807         return 0;
2808 }
2809
2810 static int
2811 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2812 {
2813         u32 cmd;
2814         int j;
2815
2816         /* Build the command word. */
2817         cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2818
2819         /* Calculate an offset of a buffered flash. */
2820         if (bp->flash_info->buffered) {
2821                 offset = ((offset / bp->flash_info->page_size) <<
2822                            bp->flash_info->page_bits) +
2823                           (offset % bp->flash_info->page_size);
2824         }
2825
2826         /* Need to clear DONE bit separately. */
2827         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2828
2829         /* Address of the NVRAM to read from. */
2830         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2831
2832         /* Issue a read command. */
2833         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2834
2835         /* Wait for completion. */
2836         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2837                 u32 val;
2838
2839                 udelay(5);
2840
2841                 val = REG_RD(bp, BNX2_NVM_COMMAND);
2842                 if (val & BNX2_NVM_COMMAND_DONE) {
2843                         val = REG_RD(bp, BNX2_NVM_READ);
2844
2845                         val = be32_to_cpu(val);
2846                         memcpy(ret_val, &val, 4);
2847                         break;
2848                 }
2849         }
2850         if (j >= NVRAM_TIMEOUT_COUNT)
2851                 return -EBUSY;
2852
2853         return 0;
2854 }
2855
2856
2857 static int
2858 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2859 {
2860         u32 cmd, val32;
2861         int j;
2862
2863         /* Build the command word. */
2864         cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2865
2866         /* Calculate an offset of a buffered flash. */
2867         if (bp->flash_info->buffered) {
2868                 offset = ((offset / bp->flash_info->page_size) <<
2869                           bp->flash_info->page_bits) +
2870                          (offset % bp->flash_info->page_size);
2871         }
2872
2873         /* Need to clear DONE bit separately. */
2874         REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2875
2876         memcpy(&val32, val, 4);
2877         val32 = cpu_to_be32(val32);
2878
2879         /* Write the data. */
2880         REG_WR(bp, BNX2_NVM_WRITE, val32);
2881
2882         /* Address of the NVRAM to write to. */
2883         REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2884
2885         /* Issue the write command. */
2886         REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2887
2888         /* Wait for completion. */
2889         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2890                 udelay(5);
2891
2892                 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2893                         break;
2894         }
2895         if (j >= NVRAM_TIMEOUT_COUNT)
2896                 return -EBUSY;
2897
2898         return 0;
2899 }
2900
2901 static int
2902 bnx2_init_nvram(struct bnx2 *bp)
2903 {
2904         u32 val;
2905         int j, entry_count, rc;
2906         struct flash_spec *flash;
2907
2908         /* Determine the selected interface. */
2909         val = REG_RD(bp, BNX2_NVM_CFG1);
2910
2911         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2912
2913         rc = 0;
2914         if (val & 0x40000000) {
2915
2916                 /* Flash interface has been reconfigured */
2917                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2918                      j++, flash++) {
2919                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2920                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2921                                 bp->flash_info = flash;
2922                                 break;
2923                         }
2924                 }
2925         }
2926         else {
2927                 u32 mask;
2928                 /* Not yet been reconfigured */
2929
2930                 if (val & (1 << 23))
2931                         mask = FLASH_BACKUP_STRAP_MASK;
2932                 else
2933                         mask = FLASH_STRAP_MASK;
2934
2935                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2936                         j++, flash++) {
2937
2938                         if ((val & mask) == (flash->strapping & mask)) {
2939                                 bp->flash_info = flash;
2940
2941                                 /* Request access to the flash interface. */
2942                                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2943                                         return rc;
2944
2945                                 /* Enable access to flash interface */
2946                                 bnx2_enable_nvram_access(bp);
2947
2948                                 /* Reconfigure the flash interface */
2949                                 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2950                                 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2951                                 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2952                                 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2953
2954                                 /* Disable access to flash interface */
2955                                 bnx2_disable_nvram_access(bp);
2956                                 bnx2_release_nvram_lock(bp);
2957
2958                                 break;
2959                         }
2960                 }
2961         } /* if (val & 0x40000000) */
2962
2963         if (j == entry_count) {
2964                 bp->flash_info = NULL;
2965                 printk(KERN_ALERT PFX "Unknown flash/EEPROM type.\n");
2966                 return -ENODEV;
2967         }
2968
2969         val = REG_RD_IND(bp, bp->shmem_base + BNX2_SHARED_HW_CFG_CONFIG2);
2970         val &= BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK;
2971         if (val)
2972                 bp->flash_size = val;
2973         else
2974                 bp->flash_size = bp->flash_info->total_size;
2975
2976         return rc;
2977 }
2978
2979 static int
2980 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2981                 int buf_size)
2982 {
2983         int rc = 0;
2984         u32 cmd_flags, offset32, len32, extra;
2985
2986         if (buf_size == 0)
2987                 return 0;
2988
2989         /* Request access to the flash interface. */
2990         if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2991                 return rc;
2992
2993         /* Enable access to flash interface */
2994         bnx2_enable_nvram_access(bp);
2995
2996         len32 = buf_size;
2997         offset32 = offset;
2998         extra = 0;
2999
3000         cmd_flags = 0;
3001
3002         if (offset32 & 3) {
3003                 u8 buf[4];
3004                 u32 pre_len;
3005
3006                 offset32 &= ~3;
3007                 pre_len = 4 - (offset & 3);
3008
3009                 if (pre_len >= len32) {
3010                         pre_len = len32;
3011                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3012                                     BNX2_NVM_COMMAND_LAST;
3013                 }
3014                 else {
3015                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3016                 }
3017
3018                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3019
3020                 if (rc)
3021                         return rc;
3022
3023                 memcpy(ret_buf, buf + (offset & 3), pre_len);
3024
3025                 offset32 += 4;
3026                 ret_buf += pre_len;
3027                 len32 -= pre_len;
3028         }
3029         if (len32 & 3) {
3030                 extra = 4 - (len32 & 3);
3031                 len32 = (len32 + 4) & ~3;
3032         }
3033
3034         if (len32 == 4) {
3035                 u8 buf[4];
3036
3037                 if (cmd_flags)
3038                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3039                 else
3040                         cmd_flags = BNX2_NVM_COMMAND_FIRST |
3041                                     BNX2_NVM_COMMAND_LAST;
3042
3043                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3044
3045                 memcpy(ret_buf, buf, 4 - extra);
3046         }
3047         else if (len32 > 0) {
3048                 u8 buf[4];
3049
3050                 /* Read the first word. */
3051                 if (cmd_flags)
3052                         cmd_flags = 0;
3053                 else
3054                         cmd_flags = BNX2_NVM_COMMAND_FIRST;
3055
3056                 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
3057
3058                 /* Advance to the next dword. */
3059                 offset32 += 4;
3060                 ret_buf += 4;
3061                 len32 -= 4;
3062
3063                 while (len32 > 4 && rc == 0) {
3064                         rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
3065
3066                         /* Advance to the next dword. */
3067                         offset32 += 4;
3068                         ret_buf += 4;
3069                         len32 -= 4;
3070                 }
3071
3072                 if (rc)
3073                         return rc;
3074
3075                 cmd_flags = BNX2_NVM_COMMAND_LAST;
3076                 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
3077
3078                 memcpy(ret_buf, buf, 4 - extra);
3079         }
3080
3081         /* Disable access to flash interface */
3082         bnx2_disable_nvram_access(bp);
3083
3084         bnx2_release_nvram_lock(bp);
3085
3086         return rc;
3087 }
3088
3089 static int
3090 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
3091                 int buf_size)
3092 {
3093         u32 written, offset32, len32;
3094         u8 *buf, start[4], end[4], *align_buf = NULL, *flash_buffer = NULL;
3095         int rc = 0;
3096         int align_start, align_end;
3097
3098         buf = data_buf;
3099         offset32 = offset;
3100         len32 = buf_size;
3101         align_start = align_end = 0;
3102
3103         if ((align_start = (offset32 & 3))) {
3104                 offset32 &= ~3;
3105                 len32 += (4 - align_start);
3106                 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
3107                         return rc;
3108         }
3109
3110         if (len32 & 3) {
3111                 if ((len32 > 4) || !align_start) {
3112                         align_end = 4 - (len32 & 3);
3113                         len32 += align_end;
3114                         if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
3115                                 end, 4))) {
3116                                 return rc;
3117                         }
3118                 }
3119         }
3120
3121         if (align_start || align_end) {
3122                 align_buf = kmalloc(len32, GFP_KERNEL);
3123                 if (align_buf == NULL)
3124                         return -ENOMEM;
3125                 if (align_start) {
3126                         memcpy(align_buf, start, 4);
3127                 }
3128                 if (align_end) {
3129                         memcpy(align_buf + len32 - 4, end, 4);
3130                 }
3131                 memcpy(align_buf + align_start, data_buf, buf_size);
3132                 buf = align_buf;
3133         }
3134
3135         if (bp->flash_info->buffered == 0) {
3136                 flash_buffer = kmalloc(264, GFP_KERNEL);
3137                 if (flash_buffer == NULL) {
3138                         rc = -ENOMEM;
3139                         goto nvram_write_end;
3140                 }
3141         }
3142
3143         written = 0;
3144         while ((written < len32) && (rc == 0)) {
3145                 u32 page_start, page_end, data_start, data_end;
3146                 u32 addr, cmd_flags;
3147                 int i;
3148
3149                 /* Find the page_start addr */
3150                 page_start = offset32 + written;
3151                 page_start -= (page_start % bp->flash_info->page_size);
3152                 /* Find the page_end addr */
3153                 page_end = page_start + bp->flash_info->page_size;
3154                 /* Find the data_start addr */
3155                 data_start = (written == 0) ? offset32 : page_start;
3156                 /* Find the data_end addr */
3157                 data_end = (page_end > offset32 + len32) ?
3158                         (offset32 + len32) : page_end;
3159
3160                 /* Request access to the flash interface. */
3161                 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
3162                         goto nvram_write_end;
3163
3164                 /* Enable access to flash interface */
3165                 bnx2_enable_nvram_access(bp);
3166
3167                 cmd_flags = BNX2_NVM_COMMAND_FIRST;
3168                 if (bp->flash_info->buffered == 0) {
3169                         int j;
3170
3171                         /* Read the whole page into the buffer
3172                          * (non-buffer flash only) */
3173                         for (j = 0; j < bp->flash_info->page_size; j += 4) {
3174                                 if (j == (bp->flash_info->page_size - 4)) {
3175                                         cmd_flags |= BNX2_NVM_COMMAND_LAST;
3176                                 }
3177                                 rc = bnx2_nvram_read_dword(bp,
3178                                         page_start + j,
3179                                         &flash_buffer[j],
3180                                         cmd_flags);
3181
3182                                 if (rc)
3183                                         goto nvram_write_end;
3184
3185                                 cmd_flags = 0;
3186                         }
3187                 }
3188
3189                 /* Enable writes to flash interface (unlock write-protect) */
3190                 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
3191                         goto nvram_write_end;
3192
3193                 /* Erase the page */
3194                 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
3195                         goto nvram_write_end;
3196
3197                 /* Re-enable the write again for the actual write */
3198                 bnx2_enable_nvram_write(bp);
3199
3200                 /* Loop to write back the buffer data from page_start to
3201                  * data_start */
3202                 i = 0;
3203                 if (bp->flash_info->buffered == 0) {
3204                         for (addr = page_start; addr < data_start;
3205                                 addr += 4, i += 4) {
3206
3207                                 rc = bnx2_nvram_write_dword(bp, addr,
3208                                         &flash_buffer[i], cmd_flags);
3209
3210                                 if (rc != 0)
3211                                         goto nvram_write_end;
3212
3213                                 cmd_flags = 0;
3214                         }
3215                 }
3216
3217                 /* Loop to write the new data from data_start to data_end */
3218                 for (addr = data_start; addr < data_end; addr += 4, i += 4) {
3219                         if ((addr == page_end - 4) ||
3220                                 ((bp->flash_info->buffered) &&
3221                                  (addr == data_end - 4))) {
3222
3223                                 cmd_flags |= BNX2_NVM_COMMAND_LAST;
3224                         }
3225                         rc = bnx2_nvram_write_dword(bp, addr, buf,
3226                                 cmd_flags);
3227
3228                         if (rc != 0)
3229                                 goto nvram_write_end;
3230
3231                         cmd_flags = 0;
3232                         buf += 4;
3233                 }
3234
3235                 /* Loop to write back the buffer data from data_end
3236                  * to page_end */
3237                 if (bp->flash_info->buffered == 0) {
3238                         for (addr = data_end; addr < page_end;
3239                                 addr += 4, i += 4) {
3240
3241                                 if (addr == page_end-4) {
3242                                         cmd_flags = BNX2_NVM_COMMAND_LAST;
3243                                 }
3244                                 rc = bnx2_nvram_write_dword(bp, addr,
3245                                         &flash_buffer[i], cmd_flags);
3246
3247                                 if (rc != 0)
3248                                         goto nvram_write_end;
3249
3250                                 cmd_flags = 0;
3251                         }
3252                 }
3253
3254                 /* Disable writes to flash interface (lock write-protect) */
3255                 bnx2_disable_nvram_write(bp);
3256
3257                 /* Disable access to flash interface */
3258                 bnx2_disable_nvram_access(bp);
3259                 bnx2_release_nvram_lock(bp);
3260
3261                 /* Increment written */
3262                 written += data_end - data_start;
3263         }
3264
3265 nvram_write_end:
3266         kfree(flash_buffer);
3267         kfree(align_buf);
3268         return rc;
3269 }
3270
3271 static int
3272 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
3273 {
3274         u32 val;
3275         int i, rc = 0;
3276
3277         /* Wait for the current PCI transaction to complete before
3278          * issuing a reset. */
3279         REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
3280                BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3281                BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3282                BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3283                BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3284         val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
3285         udelay(5);
3286
3287         /* Wait for the firmware to tell us it is ok to issue a reset. */
3288         bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
3289
3290         /* Deposit a driver reset signature so the firmware knows that
3291          * this is a soft reset. */
3292         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
3293                    BNX2_DRV_RESET_SIGNATURE_MAGIC);
3294
3295         /* Do a dummy read to force the chip to complete all current transaction
3296          * before we issue a reset. */
3297         val = REG_RD(bp, BNX2_MISC_ID);
3298
3299         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3300                 REG_WR(bp, BNX2_MISC_COMMAND, BNX2_MISC_COMMAND_SW_RESET);
3301                 REG_RD(bp, BNX2_MISC_COMMAND);
3302                 udelay(5);
3303
3304                 val = BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3305                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3306
3307                 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG, val);
3308
3309         } else {
3310                 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3311                       BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3312                       BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3313
3314                 /* Chip reset. */
3315                 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
3316
3317                 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
3318                     (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
3319                         current->state = TASK_UNINTERRUPTIBLE;
3320                         schedule_timeout(HZ / 50);
3321                 }
3322
3323                 /* Reset takes approximate 30 usec */
3324                 for (i = 0; i < 10; i++) {
3325                         val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
3326                         if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3327                                     BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3328                                 break;
3329                         udelay(10);
3330                 }
3331
3332                 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3333                            BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3334                         printk(KERN_ERR PFX "Chip reset did not complete\n");
3335                         return -EBUSY;
3336                 }
3337         }
3338
3339         /* Make sure byte swapping is properly configured. */
3340         val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
3341         if (val != 0x01020304) {
3342                 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
3343                 return -ENODEV;
3344         }
3345
3346         /* Wait for the firmware to finish its initialization. */
3347         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
3348         if (rc)
3349                 return rc;
3350
3351         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3352                 /* Adjust the voltage regular to two steps lower.  The default
3353                  * of this register is 0x0000000e. */
3354                 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
3355
3356                 /* Remove bad rbuf memory from the free pool. */
3357                 rc = bnx2_alloc_bad_rbuf(bp);
3358         }
3359
3360         return rc;
3361 }
3362
3363 static int
3364 bnx2_init_chip(struct bnx2 *bp)
3365 {
3366         u32 val;
3367         int rc;
3368
3369         /* Make sure the interrupt is not active. */
3370         REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
3371
3372         val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
3373               BNX2_DMA_CONFIG_DATA_WORD_SWAP |
3374 #ifdef __BIG_ENDIAN
3375               BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
3376 #endif
3377               BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
3378               DMA_READ_CHANS << 12 |
3379               DMA_WRITE_CHANS << 16;
3380
3381         val |= (0x2 << 20) | (1 << 11);
3382
3383         if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
3384                 val |= (1 << 23);
3385
3386         if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
3387             (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
3388                 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
3389
3390         REG_WR(bp, BNX2_DMA_CONFIG, val);
3391
3392         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
3393                 val = REG_RD(bp, BNX2_TDMA_CONFIG);
3394                 val |= BNX2_TDMA_CONFIG_ONE_DMA;
3395                 REG_WR(bp, BNX2_TDMA_CONFIG, val);
3396         }
3397
3398         if (bp->flags & PCIX_FLAG) {
3399                 u16 val16;
3400
3401                 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3402                                      &val16);
3403                 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
3404                                       val16 & ~PCI_X_CMD_ERO);
3405         }
3406
3407         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
3408                BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3409                BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3410                BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3411
3412         /* Initialize context mapping and zero out the quick contexts.  The
3413          * context block must have already been enabled. */
3414         if (CHIP_NUM(bp) == CHIP_NUM_5709)
3415                 bnx2_init_5709_context(bp);
3416         else
3417                 bnx2_init_context(bp);
3418
3419         if ((rc = bnx2_init_cpus(bp)) != 0)
3420                 return rc;
3421
3422         bnx2_init_nvram(bp);
3423
3424         bnx2_set_mac_addr(bp);
3425
3426         val = REG_RD(bp, BNX2_MQ_CONFIG);
3427         val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3428         val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3429         REG_WR(bp, BNX2_MQ_CONFIG, val);
3430
3431         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3432         REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
3433         REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
3434
3435         val = (BCM_PAGE_BITS - 8) << 24;
3436         REG_WR(bp, BNX2_RV2P_CONFIG, val);
3437
3438         /* Configure page size. */
3439         val = REG_RD(bp, BNX2_TBDR_CONFIG);
3440         val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
3441         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3442         REG_WR(bp, BNX2_TBDR_CONFIG, val);
3443
3444         val = bp->mac_addr[0] +
3445               (bp->mac_addr[1] << 8) +
3446               (bp->mac_addr[2] << 16) +
3447               bp->mac_addr[3] +
3448               (bp->mac_addr[4] << 8) +
3449               (bp->mac_addr[5] << 16);
3450         REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
3451
3452         /* Program the MTU.  Also include 4 bytes for CRC32. */
3453         val = bp->dev->mtu + ETH_HLEN + 4;
3454         if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
3455                 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
3456         REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
3457
3458         bp->last_status_idx = 0;
3459         bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
3460
3461         /* Set up how to generate a link change interrupt. */
3462         REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
3463
3464         REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
3465                (u64) bp->status_blk_mapping & 0xffffffff);
3466         REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
3467
3468         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
3469                (u64) bp->stats_blk_mapping & 0xffffffff);
3470         REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
3471                (u64) bp->stats_blk_mapping >> 32);
3472
3473         REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
3474                (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
3475
3476         REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
3477                (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
3478
3479         REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
3480                (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
3481
3482         REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
3483
3484         REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
3485
3486         REG_WR(bp, BNX2_HC_COM_TICKS,
3487                (bp->com_ticks_int << 16) | bp->com_ticks);
3488
3489         REG_WR(bp, BNX2_HC_CMD_TICKS,
3490                (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
3491
3492         REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
3493         REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
3494
3495         if (CHIP_ID(bp) == CHIP_ID_5706_A1)
3496                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
3497         else {
3498                 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
3499                        BNX2_HC_CONFIG_TX_TMR_MODE |
3500                        BNX2_HC_CONFIG_COLLECT_STATS);
3501         }
3502
3503         /* Clear internal stats counters. */
3504         REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
3505
3506         REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3507
3508         if (REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_FEATURE) &
3509             BNX2_PORT_FEATURE_ASF_ENABLED)
3510                 bp->flags |= ASF_ENABLE_FLAG;
3511
3512         /* Initialize the receive filter. */
3513         bnx2_set_rx_mode(bp->dev);
3514
3515         rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
3516                           0);
3517
3518         REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
3519         REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
3520
3521         udelay(20);
3522
3523         bp->hc_cmd = REG_RD(bp, BNX2_HC_COMMAND);
3524
3525         return rc;
3526 }
3527
3528 static void
3529 bnx2_init_tx_context(struct bnx2 *bp, u32 cid)
3530 {
3531         u32 val, offset0, offset1, offset2, offset3;
3532
3533         if (CHIP_NUM(bp) == CHIP_NUM_5709) {
3534                 offset0 = BNX2_L2CTX_TYPE_XI;
3535                 offset1 = BNX2_L2CTX_CMD_TYPE_XI;
3536                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
3537                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
3538         } else {
3539                 offset0 = BNX2_L2CTX_TYPE;
3540                 offset1 = BNX2_L2CTX_CMD_TYPE;
3541                 offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
3542                 offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
3543         }
3544         val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
3545         CTX_WR(bp, GET_CID_ADDR(cid), offset0, val);
3546
3547         val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
3548         CTX_WR(bp, GET_CID_ADDR(cid), offset1, val);
3549
3550         val = (u64) bp->tx_desc_mapping >> 32;
3551         CTX_WR(bp, GET_CID_ADDR(cid), offset2, val);
3552
3553         val = (u64) bp->tx_desc_mapping & 0xffffffff;
3554         CTX_WR(bp, GET_CID_ADDR(cid), offset3, val);
3555 }
3556
3557 static void
3558 bnx2_init_tx_ring(struct bnx2 *bp)
3559 {
3560         struct tx_bd *txbd;
3561         u32 cid;
3562
3563         bp->tx_wake_thresh = bp->tx_ring_size / 2;
3564
3565         txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
3566
3567         txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
3568         txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
3569
3570         bp->tx_prod = 0;
3571         bp->tx_cons = 0;
3572         bp->hw_tx_cons = 0;
3573         bp->tx_prod_bseq = 0;
3574
3575         cid = TX_CID;
3576         bp->tx_bidx_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BIDX;
3577         bp->tx_bseq_addr = MB_GET_CID_ADDR(cid) + BNX2_L2CTX_TX_HOST_BSEQ;
3578
3579         bnx2_init_tx_context(bp, cid);
3580 }
3581
3582 static void
3583 bnx2_init_rx_ring(struct bnx2 *bp)
3584 {
3585         struct rx_bd *rxbd;
3586         int i;
3587         u16 prod, ring_prod;
3588         u32 val;
3589
3590         /* 8 for CRC and VLAN */
3591         bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
3592         /* hw alignment */
3593         bp->rx_buf_size = bp->rx_buf_use_size + BNX2_RX_ALIGN;
3594
3595         ring_prod = prod = bp->rx_prod = 0;
3596         bp->rx_cons = 0;
3597         bp->hw_rx_cons = 0;
3598         bp->rx_prod_bseq = 0;
3599
3600         for (i = 0; i < bp->rx_max_ring; i++) {
3601                 int j;
3602
3603                 rxbd = &bp->rx_desc_ring[i][0];
3604                 for (j = 0; j < MAX_RX_DESC_CNT; j++, rxbd++) {
3605                         rxbd->rx_bd_len = bp->rx_buf_use_size;
3606                         rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3607                 }
3608                 if (i == (bp->rx_max_ring - 1))
3609                         j = 0;
3610                 else
3611                         j = i + 1;
3612                 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping[j] >> 32;
3613                 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping[j] &
3614                                        0xffffffff;
3615         }
3616
3617         val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3618         val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3619         val |= 0x02 << 8;
3620         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3621
3622         val = (u64) bp->rx_desc_mapping[0] >> 32;
3623         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3624
3625         val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
3626         CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3627
3628         for (i = 0; i < bp->rx_ring_size; i++) {
3629                 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3630                         break;
3631                 }
3632                 prod = NEXT_RX_BD(prod);
3633                 ring_prod = RX_RING_IDX(prod);
3634         }
3635         bp->rx_prod = prod;
3636
3637         REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3638
3639         REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3640 }
3641
3642 static void
3643 bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
3644 {
3645         u32 num_rings, max;
3646
3647         bp->rx_ring_size = size;
3648         num_rings = 1;
3649         while (size > MAX_RX_DESC_CNT) {
3650                 size -= MAX_RX_DESC_CNT;
3651                 num_rings++;
3652         }
3653         /* round to next power of 2 */
3654         max = MAX_RX_RINGS;
3655         while ((max & num_rings) == 0)
3656                 max >>= 1;
3657
3658         if (num_rings != max)
3659                 max <<= 1;
3660
3661         bp->rx_max_ring = max;
3662         bp->rx_max_ring_idx = (bp->rx_max_ring * RX_DESC_CNT) - 1;
3663 }
3664
3665 static void
3666 bnx2_free_tx_skbs(struct bnx2 *bp)
3667 {
3668         int i;
3669
3670         if (bp->tx_buf_ring == NULL)
3671                 return;
3672
3673         for (i = 0; i < TX_DESC_CNT; ) {
3674                 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3675                 struct sk_buff *skb = tx_buf->skb;
3676                 int j, last;
3677
3678                 if (skb == NULL) {
3679                         i++;
3680                         continue;
3681                 }
3682
3683                 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3684                         skb_headlen(skb), PCI_DMA_TODEVICE);
3685
3686                 tx_buf->skb = NULL;
3687
3688                 last = skb_shinfo(skb)->nr_frags;
3689                 for (j = 0; j < last; j++) {
3690                         tx_buf = &bp->tx_buf_ring[i + j + 1];
3691                         pci_unmap_page(bp->pdev,
3692                                 pci_unmap_addr(tx_buf, mapping),
3693                                 skb_shinfo(skb)->frags[j].size,
3694                                 PCI_DMA_TODEVICE);
3695                 }
3696                 dev_kfree_skb(skb);
3697                 i += j + 1;
3698         }
3699
3700 }
3701
3702 static void
3703 bnx2_free_rx_skbs(struct bnx2 *bp)
3704 {
3705         int i;
3706
3707         if (bp->rx_buf_ring == NULL)
3708                 return;
3709
3710         for (i = 0; i < bp->rx_max_ring_idx; i++) {
3711                 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3712                 struct sk_buff *skb = rx_buf->skb;
3713
3714                 if (skb == NULL)
3715                         continue;
3716
3717                 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3718                         bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3719
3720                 rx_buf->skb = NULL;
3721
3722                 dev_kfree_skb(skb);
3723         }
3724 }
3725
3726 static void
3727 bnx2_free_skbs(struct bnx2 *bp)
3728 {
3729         bnx2_free_tx_skbs(bp);
3730         bnx2_free_rx_skbs(bp);
3731 }
3732
3733 static int
3734 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3735 {
3736         int rc;
3737
3738         rc = bnx2_reset_chip(bp, reset_code);
3739         bnx2_free_skbs(bp);
3740         if (rc)
3741                 return rc;
3742
3743         if ((rc = bnx2_init_chip(bp)) != 0)
3744                 return rc;
3745
3746         bnx2_init_tx_ring(bp);
3747         bnx2_init_rx_ring(bp);
3748         return 0;
3749 }
3750
3751 static int
3752 bnx2_init_nic(struct bnx2 *bp)
3753 {
3754         int rc;
3755
3756         if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3757                 return rc;
3758
3759         spin_lock_bh(&bp->phy_lock);
3760         bnx2_init_phy(bp);
3761         spin_unlock_bh(&bp->phy_lock);
3762         bnx2_set_link(bp);
3763         return 0;
3764 }
3765
3766 static int
3767 bnx2_test_registers(struct bnx2 *bp)
3768 {
3769         int ret;
3770         int i;
3771         static const struct {
3772                 u16   offset;
3773                 u16   flags;
3774                 u32   rw_mask;
3775                 u32   ro_mask;
3776         } reg_tbl[] = {
3777                 { 0x006c, 0, 0x00000000, 0x0000003f },
3778                 { 0x0090, 0, 0xffffffff, 0x00000000 },
3779                 { 0x0094, 0, 0x00000000, 0x00000000 },
3780
3781                 { 0x0404, 0, 0x00003f00, 0x00000000 },
3782                 { 0x0418, 0, 0x00000000, 0xffffffff },
3783                 { 0x041c, 0, 0x00000000, 0xffffffff },
3784                 { 0x0420, 0, 0x00000000, 0x80ffffff },
3785                 { 0x0424, 0, 0x00000000, 0x00000000 },
3786                 { 0x0428, 0, 0x00000000, 0x00000001 },
3787                 { 0x0450, 0, 0x00000000, 0x0000ffff },
3788                 { 0x0454, 0, 0x00000000, 0xffffffff },
3789                 { 0x0458, 0, 0x00000000, 0xffffffff },
3790
3791                 { 0x0808, 0, 0x00000000, 0xffffffff },
3792                 { 0x0854, 0, 0x00000000, 0xffffffff },
3793                 { 0x0868, 0, 0x00000000, 0x77777777 },
3794                 { 0x086c, 0, 0x00000000, 0x77777777 },
3795                 { 0x0870, 0, 0x00000000, 0x77777777 },
3796                 { 0x0874, 0, 0x00000000, 0x77777777 },
3797
3798                 { 0x0c00, 0, 0x00000000, 0x00000001 },
3799                 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3800                 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3801
3802                 { 0x1000, 0, 0x00000000, 0x00000001 },
3803                 { 0x1004, 0, 0x00000000, 0x000f0001 },
3804
3805                 { 0x1408, 0, 0x01c00800, 0x00000000 },
3806                 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3807                 { 0x14a8, 0, 0x00000000, 0x000001ff },
3808                 { 0x14ac, 0, 0x0fffffff, 0x10000000 },
3809                 { 0x14b0, 0, 0x00000002, 0x00000001 },
3810                 { 0x14b8, 0, 0x00000000, 0x00000000 },
3811                 { 0x14c0, 0, 0x00000000, 0x00000009 },
3812                 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3813                 { 0x14cc, 0, 0x00000000, 0x00000001 },
3814                 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3815
3816                 { 0x1800, 0, 0x00000000, 0x00000001 },
3817                 { 0x1804, 0, 0x00000000, 0x00000003 },
3818
3819                 { 0x2800, 0, 0x00000000, 0x00000001 },
3820                 { 0x2804, 0, 0x00000000, 0x00003f01 },
3821                 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3822                 { 0x2810, 0, 0xffff0000, 0x00000000 },
3823                 { 0x2814, 0, 0xffff0000, 0x00000000 },
3824                 { 0x2818, 0, 0xffff0000, 0x00000000 },
3825                 { 0x281c, 0, 0xffff0000, 0x00000000 },
3826                 { 0x2834, 0, 0xffffffff, 0x00000000 },
3827                 { 0x2840, 0, 0x00000000, 0xffffffff },
3828                 { 0x2844, 0, 0x00000000, 0xffffffff },
3829                 { 0x2848, 0, 0xffffffff, 0x00000000 },
3830                 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3831
3832                 { 0x2c00, 0, 0x00000000, 0x00000011 },
3833                 { 0x2c04, 0, 0x00000000, 0x00030007 },
3834
3835                 { 0x3c00, 0, 0x00000000, 0x00000001 },
3836                 { 0x3c04, 0, 0x00000000, 0x00070000 },
3837                 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3838                 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3839                 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3840                 { 0x3c14, 0, 0x00000000, 0xffffffff },
3841                 { 0x3c18, 0, 0x00000000, 0xffffffff },
3842                 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3843                 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3844
3845                 { 0x5004, 0, 0x00000000, 0x0000007f },
3846                 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3847                 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3848
3849                 { 0x5c00, 0, 0x00000000, 0x00000001 },
3850                 { 0x5c04, 0, 0x00000000, 0x0003000f },
3851                 { 0x5c08, 0, 0x00000003, 0x00000000 },
3852                 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3853                 { 0x5c10, 0, 0x00000000, 0xffffffff },
3854                 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3855                 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3856                 { 0x5c88, 0, 0x00000000, 0x00077373 },
3857                 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3858
3859                 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3860                 { 0x680c, 0, 0xffffffff, 0x00000000 },
3861                 { 0x6810, 0, 0xffffffff, 0x00000000 },
3862                 { 0x6814, 0, 0xffffffff, 0x00000000 },
3863                 { 0x6818, 0, 0xffffffff, 0x00000000 },
3864                 { 0x681c, 0, 0xffffffff, 0x00000000 },
3865                 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3866                 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3867                 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3868                 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3869                 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3870                 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3871                 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3872                 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3873                 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3874                 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3875                 { 0x684c, 0, 0xffffffff, 0x00000000 },
3876                 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3877                 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3878                 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3879                 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3880                 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3881                 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3882
3883                 { 0xffff, 0, 0x00000000, 0x00000000 },
3884         };
3885
3886         ret = 0;
3887         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3888                 u32 offset, rw_mask, ro_mask, save_val, val;
3889
3890                 offset = (u32) reg_tbl[i].offset;
3891                 rw_mask = reg_tbl[i].rw_mask;
3892                 ro_mask = reg_tbl[i].ro_mask;
3893
3894                 save_val = readl(bp->regview + offset);
3895
3896                 writel(0, bp->regview + offset);
3897
3898                 val = readl(bp->regview + offset);
3899                 if ((val & rw_mask) != 0) {
3900                         goto reg_test_err;
3901                 }
3902
3903                 if ((val & ro_mask) != (save_val & ro_mask)) {
3904                         goto reg_test_err;
3905                 }
3906
3907                 writel(0xffffffff, bp->regview + offset);
3908
3909                 val = readl(bp->regview + offset);
3910                 if ((val & rw_mask) != rw_mask) {
3911                         goto reg_test_err;
3912                 }
3913
3914                 if ((val & ro_mask) != (save_val & ro_mask)) {
3915                         goto reg_test_err;
3916                 }
3917
3918                 writel(save_val, bp->regview + offset);
3919                 continue;
3920
3921 reg_test_err:
3922                 writel(save_val, bp->regview + offset);
3923                 ret = -ENODEV;
3924                 break;
3925         }
3926         return ret;
3927 }
3928
3929 static int
3930 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3931 {
3932         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3933                 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3934         int i;
3935
3936         for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3937                 u32 offset;
3938
3939                 for (offset = 0; offset < size; offset += 4) {
3940
3941                         REG_WR_IND(bp, start + offset, test_pattern[i]);
3942
3943                         if (REG_RD_IND(bp, start + offset) !=
3944                                 test_pattern[i]) {
3945                                 return -ENODEV;
3946                         }
3947                 }
3948         }
3949         return 0;
3950 }
3951
3952 static int
3953 bnx2_test_memory(struct bnx2 *bp)
3954 {
3955         int ret = 0;
3956         int i;
3957         static const struct {
3958                 u32   offset;
3959                 u32   len;
3960         } mem_tbl[] = {
3961                 { 0x60000,  0x4000 },
3962                 { 0xa0000,  0x3000 },
3963                 { 0xe0000,  0x4000 },
3964                 { 0x120000, 0x4000 },
3965                 { 0x1a0000, 0x4000 },
3966                 { 0x160000, 0x4000 },
3967                 { 0xffffffff, 0    },
3968         };
3969
3970         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3971                 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3972                         mem_tbl[i].len)) != 0) {
3973                         return ret;
3974                 }
3975         }
3976
3977         return ret;
3978 }
3979
3980 #define BNX2_MAC_LOOPBACK       0
3981 #define BNX2_PHY_LOOPBACK       1
3982
3983 static int
3984 bnx2_run_loopback(struct bnx2 *bp, int loopback_mode)
3985 {
3986         unsigned int pkt_size, num_pkts, i;
3987         struct sk_buff *skb, *rx_skb;
3988         unsigned char *packet;
3989         u16 rx_start_idx, rx_idx;
3990         dma_addr_t map;
3991         struct tx_bd *txbd;
3992         struct sw_bd *rx_buf;
3993         struct l2_fhdr *rx_hdr;
3994         int ret = -ENODEV;
3995
3996         if (loopback_mode == BNX2_MAC_LOOPBACK) {
3997                 bp->loopback = MAC_LOOPBACK;
3998                 bnx2_set_mac_loopback(bp);
3999         }
4000         else if (loopback_mode == BNX2_PHY_LOOPBACK) {
4001                 bp->loopback = PHY_LOOPBACK;
4002                 bnx2_set_phy_loopback(bp);
4003         }
4004         else
4005                 return -EINVAL;
4006
4007         pkt_size = 1514;
4008         skb = netdev_alloc_skb(bp->dev, pkt_size);
4009         if (!skb)
4010                 return -ENOMEM;
4011         packet = skb_put(skb, pkt_size);
4012         memcpy(packet, bp->dev->dev_addr, 6);
4013         memset(packet + 6, 0x0, 8);
4014         for (i = 14; i < pkt_size; i++)
4015                 packet[i] = (unsigned char) (i & 0xff);
4016
4017         map = pci_map_single(bp->pdev, skb->data, pkt_size,
4018                 PCI_DMA_TODEVICE);
4019
4020         REG_WR(bp, BNX2_HC_COMMAND,
4021                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4022
4023         REG_RD(bp, BNX2_HC_COMMAND);
4024
4025         udelay(5);
4026         rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
4027
4028         num_pkts = 0;
4029
4030         txbd = &bp->tx_desc_ring[TX_RING_IDX(bp->tx_prod)];
4031
4032         txbd->tx_bd_haddr_hi = (u64) map >> 32;
4033         txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
4034         txbd->tx_bd_mss_nbytes = pkt_size;
4035         txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
4036
4037         num_pkts++;
4038         bp->tx_prod = NEXT_TX_BD(bp->tx_prod);
4039         bp->tx_prod_bseq += pkt_size;
4040
4041         REG_WR16(bp, bp->tx_bidx_addr, bp->tx_prod);
4042         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4043
4044         udelay(100);
4045
4046         REG_WR(bp, BNX2_HC_COMMAND,
4047                bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
4048
4049         REG_RD(bp, BNX2_HC_COMMAND);
4050
4051         udelay(5);
4052
4053         pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
4054         dev_kfree_skb(skb);
4055
4056         if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_prod) {
4057                 goto loopback_test_done;
4058         }
4059
4060         rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
4061         if (rx_idx != rx_start_idx + num_pkts) {
4062                 goto loopback_test_done;
4063         }
4064
4065         rx_buf = &bp->rx_buf_ring[rx_start_idx];
4066         rx_skb = rx_buf->skb;
4067
4068         rx_hdr = (struct l2_fhdr *) rx_skb->data;
4069         skb_reserve(rx_skb, bp->rx_offset);
4070
4071         pci_dma_sync_single_for_cpu(bp->pdev,
4072                 pci_unmap_addr(rx_buf, mapping),
4073                 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
4074
4075         if (rx_hdr->l2_fhdr_status &
4076                 (L2_FHDR_ERRORS_BAD_CRC |
4077                 L2_FHDR_ERRORS_PHY_DECODE |
4078                 L2_FHDR_ERRORS_ALIGNMENT |
4079                 L2_FHDR_ERRORS_TOO_SHORT |
4080                 L2_FHDR_ERRORS_GIANT_FRAME)) {
4081
4082                 goto loopback_test_done;
4083         }
4084
4085         if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
4086                 goto loopback_test_done;
4087         }
4088
4089         for (i = 14; i < pkt_size; i++) {
4090                 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
4091                         goto loopback_test_done;
4092                 }
4093         }
4094
4095         ret = 0;
4096
4097 loopback_test_done:
4098         bp->loopback = 0;
4099         return ret;
4100 }
4101
4102 #define BNX2_MAC_LOOPBACK_FAILED        1
4103 #define BNX2_PHY_LOOPBACK_FAILED        2
4104 #define BNX2_LOOPBACK_FAILED            (BNX2_MAC_LOOPBACK_FAILED |     \
4105                                          BNX2_PHY_LOOPBACK_FAILED)
4106
4107 static int
4108 bnx2_test_loopback(struct bnx2 *bp)
4109 {
4110         int rc = 0;
4111
4112         if (!netif_running(bp->dev))
4113                 return BNX2_LOOPBACK_FAILED;
4114
4115         bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET);
4116         spin_lock_bh(&bp->phy_lock);
4117         bnx2_init_phy(bp);
4118         spin_unlock_bh(&bp->phy_lock);
4119         if (bnx2_run_loopback(bp, BNX2_MAC_LOOPBACK))
4120                 rc |= BNX2_MAC_LOOPBACK_FAILED;
4121         if (bnx2_run_loopback(bp, BNX2_PHY_LOOPBACK))
4122                 rc |= BNX2_PHY_LOOPBACK_FAILED;
4123         return rc;
4124 }
4125
4126 #define NVRAM_SIZE 0x200
4127 #define CRC32_RESIDUAL 0xdebb20e3
4128
4129 static int
4130 bnx2_test_nvram(struct bnx2 *bp)
4131 {
4132         u32 buf[NVRAM_SIZE / 4];
4133         u8 *data = (u8 *) buf;
4134         int rc = 0;
4135         u32 magic, csum;
4136
4137         if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
4138                 goto test_nvram_done;
4139
4140         magic = be32_to_cpu(buf[0]);
4141         if (magic != 0x669955aa) {
4142                 rc = -ENODEV;
4143                 goto test_nvram_done;
4144         }
4145
4146         if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
4147                 goto test_nvram_done;
4148
4149         csum = ether_crc_le(0x100, data);
4150         if (csum != CRC32_RESIDUAL) {
4151                 rc = -ENODEV;
4152                 goto test_nvram_done;
4153         }
4154
4155         csum = ether_crc_le(0x100, data + 0x100);
4156         if (csum != CRC32_RESIDUAL) {
4157                 rc = -ENODEV;
4158         }
4159
4160 test_nvram_done:
4161         return rc;
4162 }
4163
4164 static int
4165 bnx2_test_link(struct bnx2 *bp)
4166 {
4167         u32 bmsr;
4168
4169         spin_lock_bh(&bp->phy_lock);
4170         bnx2_read_phy(bp, MII_BMSR, &bmsr);
4171         bnx2_read_phy(bp, MII_BMSR, &bmsr);
4172         spin_unlock_bh(&bp->phy_lock);
4173
4174         if (bmsr & BMSR_LSTATUS) {
4175                 return 0;
4176         }
4177         return -ENODEV;
4178 }
4179
4180 static int
4181 bnx2_test_intr(struct bnx2 *bp)
4182 {
4183         int i;
4184         u16 status_idx;
4185
4186         if (!netif_running(bp->dev))
4187                 return -ENODEV;
4188
4189         status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
4190
4191         /* This register is not touched during run-time. */
4192         REG_WR(bp, BNX2_HC_COMMAND, bp->hc_cmd | BNX2_HC_COMMAND_COAL_NOW);
4193         REG_RD(bp, BNX2_HC_COMMAND);
4194
4195         for (i = 0; i < 10; i++) {
4196                 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
4197                         status_idx) {
4198
4199                         break;
4200                 }
4201
4202                 msleep_interruptible(10);
4203         }
4204         if (i < 10)
4205                 return 0;
4206
4207         return -ENODEV;
4208 }
4209
4210 static void
4211 bnx2_5706_serdes_timer(struct bnx2 *bp)
4212 {
4213         spin_lock(&bp->phy_lock);
4214         if (bp->serdes_an_pending)
4215                 bp->serdes_an_pending--;
4216         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4217                 u32 bmcr;
4218
4219                 bp->current_interval = bp->timer_interval;
4220
4221                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4222
4223                 if (bmcr & BMCR_ANENABLE) {
4224                         u32 phy1, phy2;
4225
4226                         bnx2_write_phy(bp, 0x1c, 0x7c00);
4227                         bnx2_read_phy(bp, 0x1c, &phy1);
4228
4229                         bnx2_write_phy(bp, 0x17, 0x0f01);
4230                         bnx2_read_phy(bp, 0x15, &phy2);
4231                         bnx2_write_phy(bp, 0x17, 0x0f01);
4232                         bnx2_read_phy(bp, 0x15, &phy2);
4233
4234                         if ((phy1 & 0x10) &&    /* SIGNAL DETECT */
4235                                 !(phy2 & 0x20)) {       /* no CONFIG */
4236
4237                                 bmcr &= ~BMCR_ANENABLE;
4238                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4239                                 bnx2_write_phy(bp, MII_BMCR, bmcr);
4240                                 bp->phy_flags |= PHY_PARALLEL_DETECT_FLAG;
4241                         }
4242                 }
4243         }
4244         else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
4245                  (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
4246                 u32 phy2;
4247
4248                 bnx2_write_phy(bp, 0x17, 0x0f01);
4249                 bnx2_read_phy(bp, 0x15, &phy2);
4250                 if (phy2 & 0x20) {
4251                         u32 bmcr;
4252
4253                         bnx2_read_phy(bp, MII_BMCR, &bmcr);
4254                         bmcr |= BMCR_ANENABLE;
4255                         bnx2_write_phy(bp, MII_BMCR, bmcr);
4256
4257                         bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
4258                 }
4259         } else
4260                 bp->current_interval = bp->timer_interval;
4261
4262         spin_unlock(&bp->phy_lock);
4263 }
4264
4265 static void
4266 bnx2_5708_serdes_timer(struct bnx2 *bp)
4267 {
4268         if ((bp->phy_flags & PHY_2_5G_CAPABLE_FLAG) == 0) {
4269                 bp->serdes_an_pending = 0;
4270                 return;
4271         }
4272
4273         spin_lock(&bp->phy_lock);
4274         if (bp->serdes_an_pending)
4275                 bp->serdes_an_pending--;
4276         else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
4277                 u32 bmcr;
4278
4279                 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4280
4281                 if (bmcr & BMCR_ANENABLE) {
4282                         bmcr &= ~BMCR_ANENABLE;
4283                         bmcr |= BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500;
4284                         bnx2_write_phy(bp, MII_BMCR, bmcr);
4285                         bp->current_interval = SERDES_FORCED_TIMEOUT;
4286                 } else {
4287                         bmcr &= ~(BMCR_FULLDPLX | BCM5708S_BMCR_FORCE_2500);
4288                         bmcr |= BMCR_ANENABLE;
4289                         bnx2_write_phy(bp, MII_BMCR, bmcr);
4290                         bp->serdes_an_pending = 2;
4291                         bp->current_interval = bp->timer_interval;
4292                 }
4293
4294         } else
4295                 bp->current_interval = bp->timer_interval;
4296
4297         spin_unlock(&bp->phy_lock);
4298 }
4299
4300 static void
4301 bnx2_timer(unsigned long data)
4302 {
4303         struct bnx2 *bp = (struct bnx2 *) data;
4304         u32 msg;
4305
4306         if (!netif_running(bp->dev))
4307                 return;
4308
4309         if (atomic_read(&bp->intr_sem) != 0)
4310                 goto bnx2_restart_timer;
4311
4312         msg = (u32) ++bp->fw_drv_pulse_wr_seq;
4313         REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_PULSE_MB, msg);
4314
4315         bp->stats_blk->stat_FwRxDrop = REG_RD_IND(bp, BNX2_FW_RX_DROP_COUNT);
4316
4317         if (bp->phy_flags & PHY_SERDES_FLAG) {
4318                 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4319                         bnx2_5706_serdes_timer(bp);
4320                 else if (CHIP_NUM(bp) == CHIP_NUM_5708)
4321                         bnx2_5708_serdes_timer(bp);
4322         }
4323
4324 bnx2_restart_timer:
4325         mod_timer(&bp->timer, jiffies + bp->current_interval);
4326 }
4327
4328 /* Called with rtnl_lock */
4329 static int
4330 bnx2_open(struct net_device *dev)
4331 {
4332         struct bnx2 *bp = netdev_priv(dev);
4333         int rc;
4334
4335         bnx2_set_power_state(bp, PCI_D0);
4336         bnx2_disable_int(bp);
4337
4338         rc = bnx2_alloc_mem(bp);
4339         if (rc)
4340                 return rc;
4341
4342         if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
4343                 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
4344                 !disable_msi) {
4345
4346                 if (pci_enable_msi(bp->pdev) == 0) {
4347                         bp->flags |= USING_MSI_FLAG;
4348                         rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
4349                                         dev);
4350                 }
4351                 else {
4352                         rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4353                                         IRQF_SHARED, dev->name, dev);
4354                 }
4355         }
4356         else {
4357                 rc = request_irq(bp->pdev->irq, bnx2_interrupt, IRQF_SHARED,
4358                                 dev->name, dev);
4359         }
4360         if (rc) {
4361                 bnx2_free_mem(bp);
4362                 return rc;
4363         }
4364
4365         rc = bnx2_init_nic(bp);
4366
4367         if (rc) {
4368                 free_irq(bp->pdev->irq, dev);
4369                 if (bp->flags & USING_MSI_FLAG) {
4370                         pci_disable_msi(bp->pdev);
4371                         bp->flags &= ~USING_MSI_FLAG;
4372                 }
4373                 bnx2_free_skbs(bp);
4374                 bnx2_free_mem(bp);
4375                 return rc;
4376         }
4377
4378         mod_timer(&bp->timer, jiffies + bp->current_interval);
4379
4380         atomic_set(&bp->intr_sem, 0);
4381
4382         bnx2_enable_int(bp);
4383
4384         if (bp->flags & USING_MSI_FLAG) {
4385                 /* Test MSI to make sure it is working
4386                  * If MSI test fails, go back to INTx mode
4387                  */
4388                 if (bnx2_test_intr(bp) != 0) {
4389                         printk(KERN_WARNING PFX "%s: No interrupt was generated"
4390                                " using MSI, switching to INTx mode. Please"
4391                                " report this failure to the PCI maintainer"
4392                                " and include system chipset information.\n",
4393                                bp->dev->name);
4394
4395                         bnx2_disable_int(bp);
4396                         free_irq(bp->pdev->irq, dev);
4397                         pci_disable_msi(bp->pdev);
4398                         bp->flags &= ~USING_MSI_FLAG;
4399
4400                         rc = bnx2_init_nic(bp);
4401
4402                         if (!rc) {
4403                                 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
4404                                         IRQF_SHARED, dev->name, dev);
4405                         }
4406                         if (rc) {
4407                                 bnx2_free_skbs(bp);
4408                                 bnx2_free_mem(bp);
4409                                 del_timer_sync(&bp->timer);
4410                                 return rc;
4411                         }
4412                         bnx2_enable_int(bp);
4413                 }
4414         }
4415         if (bp->flags & USING_MSI_FLAG) {
4416                 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
4417         }
4418
4419         netif_start_queue(dev);
4420
4421         return 0;
4422 }
4423
4424 static void
4425 bnx2_reset_task(struct work_struct *work)
4426 {
4427         struct bnx2 *bp = container_of(work, struct bnx2, reset_task);
4428
4429         if (!netif_running(bp->dev))
4430                 return;
4431
4432         bp->in_reset_task = 1;
4433         bnx2_netif_stop(bp);
4434
4435         bnx2_init_nic(bp);
4436
4437         atomic_set(&bp->intr_sem, 1);
4438         bnx2_netif_start(bp);
4439         bp->in_reset_task = 0;
4440 }
4441
4442 static void
4443 bnx2_tx_timeout(struct net_device *dev)
4444 {
4445         struct bnx2 *bp = netdev_priv(dev);
4446
4447         /* This allows the netif to be shutdown gracefully before resetting */
4448         schedule_work(&bp->reset_task);
4449 }
4450
4451 #ifdef BCM_VLAN
4452 /* Called with rtnl_lock */
4453 static void
4454 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4455 {
4456         struct bnx2 *bp = netdev_priv(dev);
4457
4458         bnx2_netif_stop(bp);
4459
4460         bp->vlgrp = vlgrp;
4461         bnx2_set_rx_mode(dev);
4462
4463         bnx2_netif_start(bp);
4464 }
4465
4466 /* Called with rtnl_lock */
4467 static void
4468 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4469 {
4470         struct bnx2 *bp = netdev_priv(dev);
4471
4472         bnx2_netif_stop(bp);
4473
4474         if (bp->vlgrp)
4475                 bp->vlgrp->vlan_devices[vid] = NULL;
4476         bnx2_set_rx_mode(dev);
4477
4478         bnx2_netif_start(bp);
4479 }
4480 #endif
4481
4482 /* Called with netif_tx_lock.
4483  * bnx2_tx_int() runs without netif_tx_lock unless it needs to call
4484  * netif_wake_queue().
4485  */
4486 static int
4487 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4488 {
4489         struct bnx2 *bp = netdev_priv(dev);
4490         dma_addr_t mapping;
4491         struct tx_bd *txbd;
4492         struct sw_bd *tx_buf;
4493         u32 len, vlan_tag_flags, last_frag, mss;
4494         u16 prod, ring_prod;
4495         int i;
4496
4497         if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4498                 netif_stop_queue(dev);
4499                 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4500                         dev->name);
4501
4502                 return NETDEV_TX_BUSY;
4503         }
4504         len = skb_headlen(skb);
4505         prod = bp->tx_prod;
4506         ring_prod = TX_RING_IDX(prod);
4507
4508         vlan_tag_flags = 0;
4509         if (skb->ip_summed == CHECKSUM_PARTIAL) {
4510                 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4511         }
4512
4513         if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4514                 vlan_tag_flags |=
4515                         (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4516         }
4517 #ifdef BCM_TSO
4518         if ((mss = skb_shinfo(skb)->gso_size) &&
4519                 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4520                 u32 tcp_opt_len, ip_tcp_len;
4521
4522                 if (skb_header_cloned(skb) &&
4523                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4524                         dev_kfree_skb(skb);
4525                         return NETDEV_TX_OK;
4526                 }
4527
4528                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4529                 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4530
4531                 tcp_opt_len = 0;
4532                 if (skb->h.th->doff > 5) {
4533                         tcp_opt_len = (skb->h.th->doff - 5) << 2;
4534                 }
4535                 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4536
4537                 skb->nh.iph->check = 0;
4538                 skb->nh.iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
4539                 skb->h.th->check =
4540                         ~csum_tcpudp_magic(skb->nh.iph->saddr,
4541                                             skb->nh.iph->daddr,
4542                                             0, IPPROTO_TCP, 0);
4543
4544                 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4545                         vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4546                                 (tcp_opt_len >> 2)) << 8;
4547                 }
4548         }
4549         else
4550 #endif
4551         {
4552                 mss = 0;
4553         }
4554
4555         mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4556
4557         tx_buf = &bp->tx_buf_ring[ring_prod];
4558         tx_buf->skb = skb;
4559         pci_unmap_addr_set(tx_buf, mapping, mapping);
4560
4561         txbd = &bp->tx_desc_ring[ring_prod];
4562
4563         txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4564         txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4565         txbd->tx_bd_mss_nbytes = len | (mss << 16);
4566         txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4567
4568         last_frag = skb_shinfo(skb)->nr_frags;
4569
4570         for (i = 0; i < last_frag; i++) {
4571                 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4572
4573                 prod = NEXT_TX_BD(prod);
4574                 ring_prod = TX_RING_IDX(prod);
4575                 txbd = &bp->tx_desc_ring[ring_prod];
4576
4577                 len = frag->size;
4578                 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4579                         len, PCI_DMA_TODEVICE);
4580                 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4581                                 mapping, mapping);
4582
4583                 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4584                 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4585                 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4586                 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4587
4588         }
4589         txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4590
4591         prod = NEXT_TX_BD(prod);
4592         bp->tx_prod_bseq += skb->len;
4593
4594         REG_WR16(bp, bp->tx_bidx_addr, prod);
4595         REG_WR(bp, bp->tx_bseq_addr, bp->tx_prod_bseq);
4596
4597         mmiowb();
4598
4599         bp->tx_prod = prod;
4600         dev->trans_start = jiffies;
4601
4602         if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4603                 netif_stop_queue(dev);
4604                 if (bnx2_tx_avail(bp) > bp->tx_wake_thresh)
4605                         netif_wake_queue(dev);
4606         }
4607
4608         return NETDEV_TX_OK;
4609 }
4610
4611 /* Called with rtnl_lock */
4612 static int
4613 bnx2_close(struct net_device *dev)
4614 {
4615         struct bnx2 *bp = netdev_priv(dev);
4616         u32 reset_code;
4617
4618         /* Calling flush_scheduled_work() may deadlock because
4619          * linkwatch_event() may be on the workqueue and it will try to get
4620          * the rtnl_lock which we are holding.
4621          */
4622         while (bp->in_reset_task)
4623                 msleep(1);
4624
4625         bnx2_netif_stop(bp);
4626         del_timer_sync(&bp->timer);
4627         if (bp->flags & NO_WOL_FLAG)
4628                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
4629         else if (bp->wol)
4630                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4631         else
4632                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4633         bnx2_reset_chip(bp, reset_code);
4634         free_irq(bp->pdev->irq, dev);
4635         if (bp->flags & USING_MSI_FLAG) {
4636                 pci_disable_msi(bp->pdev);
4637                 bp->flags &= ~USING_MSI_FLAG;
4638         }
4639         bnx2_free_skbs(bp);
4640         bnx2_free_mem(bp);
4641         bp->link_up = 0;
4642         netif_carrier_off(bp->dev);
4643         bnx2_set_power_state(bp, PCI_D3hot);
4644         return 0;
4645 }
4646
4647 #define GET_NET_STATS64(ctr)                                    \
4648         (unsigned long) ((unsigned long) (ctr##_hi) << 32) +    \
4649         (unsigned long) (ctr##_lo)
4650
4651 #define GET_NET_STATS32(ctr)            \
4652         (ctr##_lo)
4653
4654 #if (BITS_PER_LONG == 64)
4655 #define GET_NET_STATS   GET_NET_STATS64
4656 #else
4657 #define GET_NET_STATS   GET_NET_STATS32
4658 #endif
4659
4660 static struct net_device_stats *
4661 bnx2_get_stats(struct net_device *dev)
4662 {
4663         struct bnx2 *bp = netdev_priv(dev);
4664         struct statistics_block *stats_blk = bp->stats_blk;
4665         struct net_device_stats *net_stats = &bp->net_stats;
4666
4667         if (bp->stats_blk == NULL) {
4668                 return net_stats;
4669         }
4670         net_stats->rx_packets =
4671                 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4672                 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4673                 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4674
4675         net_stats->tx_packets =
4676                 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4677                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4678                 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4679
4680         net_stats->rx_bytes =
4681                 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4682
4683         net_stats->tx_bytes =
4684                 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4685
4686         net_stats->multicast =
4687                 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4688
4689         net_stats->collisions =
4690                 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4691
4692         net_stats->rx_length_errors =
4693                 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4694                 stats_blk->stat_EtherStatsOverrsizePkts);
4695
4696         net_stats->rx_over_errors =
4697                 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4698
4699         net_stats->rx_frame_errors =
4700                 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4701
4702         net_stats->rx_crc_errors =
4703                 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4704
4705         net_stats->rx_errors = net_stats->rx_length_errors +
4706                 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4707                 net_stats->rx_crc_errors;
4708
4709         net_stats->tx_aborted_errors =
4710                 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4711                 stats_blk->stat_Dot3StatsLateCollisions);
4712
4713         if ((CHIP_NUM(bp) == CHIP_NUM_5706) ||
4714             (CHIP_ID(bp) == CHIP_ID_5708_A0))
4715                 net_stats->tx_carrier_errors = 0;
4716         else {
4717                 net_stats->tx_carrier_errors =
4718                         (unsigned long)
4719                         stats_blk->stat_Dot3StatsCarrierSenseErrors;
4720         }
4721
4722         net_stats->tx_errors =
4723                 (unsigned long)
4724                 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4725                 +
4726                 net_stats->tx_aborted_errors +
4727                 net_stats->tx_carrier_errors;
4728
4729         net_stats->rx_missed_errors =
4730                 (unsigned long) (stats_blk->stat_IfInMBUFDiscards +
4731                 stats_blk->stat_FwRxDrop);
4732
4733         return net_stats;
4734 }
4735
4736 /* All ethtool functions called with rtnl_lock */
4737
4738 static int
4739 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4740 {
4741         struct bnx2 *bp = netdev_priv(dev);
4742
4743         cmd->supported = SUPPORTED_Autoneg;
4744         if (bp->phy_flags & PHY_SERDES_FLAG) {
4745                 cmd->supported |= SUPPORTED_1000baseT_Full |
4746                         SUPPORTED_FIBRE;
4747
4748                 cmd->port = PORT_FIBRE;
4749         }
4750         else {
4751                 cmd->supported |= SUPPORTED_10baseT_Half |
4752                         SUPPORTED_10baseT_Full |
4753                         SUPPORTED_100baseT_Half |
4754                         SUPPORTED_100baseT_Full |
4755                         SUPPORTED_1000baseT_Full |
4756                         SUPPORTED_TP;
4757
4758                 cmd->port = PORT_TP;
4759         }
4760
4761         cmd->advertising = bp->advertising;
4762
4763         if (bp->autoneg & AUTONEG_SPEED) {
4764                 cmd->autoneg = AUTONEG_ENABLE;
4765         }
4766         else {
4767                 cmd->autoneg = AUTONEG_DISABLE;
4768         }
4769
4770         if (netif_carrier_ok(dev)) {
4771                 cmd->speed = bp->line_speed;
4772                 cmd->duplex = bp->duplex;
4773         }
4774         else {
4775                 cmd->speed = -1;
4776                 cmd->duplex = -1;
4777         }
4778
4779         cmd->transceiver = XCVR_INTERNAL;
4780         cmd->phy_address = bp->phy_addr;
4781
4782         return 0;
4783 }
4784
4785 static int
4786 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4787 {
4788         struct bnx2 *bp = netdev_priv(dev);
4789         u8 autoneg = bp->autoneg;
4790         u8 req_duplex = bp->req_duplex;
4791         u16 req_line_speed = bp->req_line_speed;
4792         u32 advertising = bp->advertising;
4793
4794         if (cmd->autoneg == AUTONEG_ENABLE) {
4795                 autoneg |= AUTONEG_SPEED;
4796
4797                 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4798
4799                 /* allow advertising 1 speed */
4800                 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4801                         (cmd->advertising == ADVERTISED_10baseT_Full) ||
4802                         (cmd->advertising == ADVERTISED_100baseT_Half) ||
4803                         (cmd->advertising == ADVERTISED_100baseT_Full)) {
4804
4805                         if (bp->phy_flags & PHY_SERDES_FLAG)
4806                                 return -EINVAL;
4807
4808                         advertising = cmd->advertising;
4809
4810                 }
4811                 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4812                         advertising = cmd->advertising;
4813                 }
4814                 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4815                         return -EINVAL;
4816                 }
4817                 else {
4818                         if (bp->phy_flags & PHY_SERDES_FLAG) {
4819                                 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4820                         }
4821                         else {
4822                                 advertising = ETHTOOL_ALL_COPPER_SPEED;
4823                         }
4824                 }
4825                 advertising |= ADVERTISED_Autoneg;
4826         }
4827         else {
4828                 if (bp->phy_flags & PHY_SERDES_FLAG) {
4829                         if ((cmd->speed != SPEED_1000 &&
4830                              cmd->speed != SPEED_2500) ||
4831                             (cmd->duplex != DUPLEX_FULL))
4832                                 return -EINVAL;
4833
4834                         if (cmd->speed == SPEED_2500 &&
4835                             !(bp->phy_flags & PHY_2_5G_CAPABLE_FLAG))
4836                                 return -EINVAL;
4837                 }
4838                 else if (cmd->speed == SPEED_1000) {
4839                         return -EINVAL;
4840                 }
4841                 autoneg &= ~AUTONEG_SPEED;
4842                 req_line_speed = cmd->speed;
4843                 req_duplex = cmd->duplex;
4844                 advertising = 0;
4845         }
4846
4847         bp->autoneg = autoneg;
4848         bp->advertising = advertising;
4849         bp->req_line_speed = req_line_speed;
4850         bp->req_duplex = req_duplex;
4851
4852         spin_lock_bh(&bp->phy_lock);
4853
4854         bnx2_setup_phy(bp);
4855
4856         spin_unlock_bh(&bp->phy_lock);
4857
4858         return 0;
4859 }
4860
4861 static void
4862 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4863 {
4864         struct bnx2 *bp = netdev_priv(dev);
4865
4866         strcpy(info->driver, DRV_MODULE_NAME);
4867         strcpy(info->version, DRV_MODULE_VERSION);
4868         strcpy(info->bus_info, pci_name(bp->pdev));
4869         info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4870         info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4871         info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4872         info->fw_version[1] = info->fw_version[3] = '.';
4873         info->fw_version[5] = 0;
4874 }
4875
4876 #define BNX2_REGDUMP_LEN                (32 * 1024)
4877
4878 static int
4879 bnx2_get_regs_len(struct net_device *dev)
4880 {
4881         return BNX2_REGDUMP_LEN;
4882 }
4883
4884 static void
4885 bnx2_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *_p)
4886 {
4887         u32 *p = _p, i, offset;
4888         u8 *orig_p = _p;
4889         struct bnx2 *bp = netdev_priv(dev);
4890         u32 reg_boundaries[] = { 0x0000, 0x0098, 0x0400, 0x045c,
4891                                  0x0800, 0x0880, 0x0c00, 0x0c10,
4892                                  0x0c30, 0x0d08, 0x1000, 0x101c,
4893                                  0x1040, 0x1048, 0x1080, 0x10a4,
4894                                  0x1400, 0x1490, 0x1498, 0x14f0,
4895                                  0x1500, 0x155c, 0x1580, 0x15dc,
4896                                  0x1600, 0x1658, 0x1680, 0x16d8,
4897                                  0x1800, 0x1820, 0x1840, 0x1854,
4898                                  0x1880, 0x1894, 0x1900, 0x1984,
4899                                  0x1c00, 0x1c0c, 0x1c40, 0x1c54,
4900                                  0x1c80, 0x1c94, 0x1d00, 0x1d84,
4901                                  0x2000, 0x2030, 0x23c0, 0x2400,
4902                                  0x2800, 0x2820, 0x2830, 0x2850,
4903                                  0x2b40, 0x2c10, 0x2fc0, 0x3058,
4904                                  0x3c00, 0x3c94, 0x4000, 0x4010,
4905                                  0x4080, 0x4090, 0x43c0, 0x4458,
4906                                  0x4c00, 0x4c18, 0x4c40, 0x4c54,
4907                                  0x4fc0, 0x5010, 0x53c0, 0x5444,
4908                                  0x5c00, 0x5c18, 0x5c80, 0x5c90,
4909                                  0x5fc0, 0x6000, 0x6400, 0x6428,
4910                                  0x6800, 0x6848, 0x684c, 0x6860,
4911                                  0x6888, 0x6910, 0x8000 };
4912
4913         regs->version = 0;
4914
4915         memset(p, 0, BNX2_REGDUMP_LEN);
4916
4917         if (!netif_running(bp->dev))
4918                 return;
4919
4920         i = 0;
4921         offset = reg_boundaries[0];
4922         p += offset;
4923         while (offset < BNX2_REGDUMP_LEN) {
4924                 *p++ = REG_RD(bp, offset);
4925                 offset += 4;
4926                 if (offset == reg_boundaries[i + 1]) {
4927                         offset = reg_boundaries[i + 2];
4928                         p = (u32 *) (orig_p + offset);
4929                         i += 2;
4930                 }
4931         }
4932 }
4933
4934 static void
4935 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4936 {
4937         struct bnx2 *bp = netdev_priv(dev);
4938
4939         if (bp->flags & NO_WOL_FLAG) {
4940                 wol->supported = 0;
4941                 wol->wolopts = 0;
4942         }
4943         else {
4944                 wol->supported = WAKE_MAGIC;
4945                 if (bp->wol)
4946                         wol->wolopts = WAKE_MAGIC;
4947                 else
4948                         wol->wolopts = 0;
4949         }
4950         memset(&wol->sopass, 0, sizeof(wol->sopass));
4951 }
4952
4953 static int
4954 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4955 {
4956         struct bnx2 *bp = netdev_priv(dev);
4957
4958         if (wol->wolopts & ~WAKE_MAGIC)
4959                 return -EINVAL;
4960
4961         if (wol->wolopts & WAKE_MAGIC) {
4962                 if (bp->flags & NO_WOL_FLAG)
4963                         return -EINVAL;
4964
4965                 bp->wol = 1;
4966         }
4967         else {
4968                 bp->wol = 0;
4969         }
4970         return 0;
4971 }
4972
4973 static int
4974 bnx2_nway_reset(struct net_device *dev)
4975 {
4976         struct bnx2 *bp = netdev_priv(dev);
4977         u32 bmcr;
4978
4979         if (!(bp->autoneg & AUTONEG_SPEED)) {
4980                 return -EINVAL;
4981         }
4982
4983         spin_lock_bh(&bp->phy_lock);
4984
4985         /* Force a link down visible on the other side */
4986         if (bp->phy_flags & PHY_SERDES_FLAG) {
4987                 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4988                 spin_unlock_bh(&bp->phy_lock);
4989
4990                 msleep(20);
4991
4992                 spin_lock_bh(&bp->phy_lock);
4993
4994                 bp->current_interval = SERDES_AN_TIMEOUT;
4995                 bp->serdes_an_pending = 1;
4996                 mod_timer(&bp->timer, jiffies + bp->current_interval);
4997         }
4998
4999         bnx2_read_phy(bp, MII_BMCR, &bmcr);
5000         bmcr &= ~BMCR_LOOPBACK;
5001         bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
5002
5003         spin_unlock_bh(&bp->phy_lock);
5004
5005         return 0;
5006 }
5007
5008 static int
5009 bnx2_get_eeprom_len(struct net_device *dev)
5010 {
5011         struct bnx2 *bp = netdev_priv(dev);
5012
5013         if (bp->flash_info == NULL)
5014                 return 0;
5015
5016         return (int) bp->flash_size;
5017 }
5018
5019 static int
5020 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5021                 u8 *eebuf)
5022 {
5023         struct bnx2 *bp = netdev_priv(dev);
5024         int rc;
5025
5026         /* parameters already validated in ethtool_get_eeprom */
5027
5028         rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
5029
5030         return rc;
5031 }
5032
5033 static int
5034 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
5035                 u8 *eebuf)
5036 {
5037         struct bnx2 *bp = netdev_priv(dev);
5038         int rc;
5039
5040         /* parameters already validated in ethtool_set_eeprom */
5041
5042         rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
5043
5044         return rc;
5045 }
5046
5047 static int
5048 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5049 {
5050         struct bnx2 *bp = netdev_priv(dev);
5051
5052         memset(coal, 0, sizeof(struct ethtool_coalesce));
5053
5054         coal->rx_coalesce_usecs = bp->rx_ticks;
5055         coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
5056         coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
5057         coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
5058
5059         coal->tx_coalesce_usecs = bp->tx_ticks;
5060         coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
5061         coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
5062         coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
5063
5064         coal->stats_block_coalesce_usecs = bp->stats_ticks;
5065
5066         return 0;
5067 }
5068
5069 static int
5070 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
5071 {
5072         struct bnx2 *bp = netdev_priv(dev);
5073
5074         bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
5075         if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
5076
5077         bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
5078         if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
5079
5080         bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
5081         if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
5082
5083         bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
5084         if (bp->rx_quick_cons_trip_int > 0xff)
5085                 bp->rx_quick_cons_trip_int = 0xff;
5086
5087         bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
5088         if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
5089
5090         bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
5091         if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
5092
5093         bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
5094         if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
5095
5096         bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
5097         if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
5098                 0xff;
5099
5100         bp->stats_ticks = coal->stats_block_coalesce_usecs;
5101         if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
5102         bp->stats_ticks &= 0xffff00;
5103
5104         if (netif_running(bp->dev)) {
5105                 bnx2_netif_stop(bp);
5106                 bnx2_init_nic(bp);
5107                 bnx2_netif_start(bp);
5108         }
5109
5110         return 0;
5111 }
5112
5113 static void
5114 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5115 {
5116         struct bnx2 *bp = netdev_priv(dev);
5117
5118         ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
5119         ering->rx_mini_max_pending = 0;
5120         ering->rx_jumbo_max_pending = 0;
5121
5122         ering->rx_pending = bp->rx_ring_size;
5123         ering->rx_mini_pending = 0;
5124         ering->rx_jumbo_pending = 0;
5125
5126         ering->tx_max_pending = MAX_TX_DESC_CNT;
5127         ering->tx_pending = bp->tx_ring_size;
5128 }
5129
5130 static int
5131 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
5132 {
5133         struct bnx2 *bp = netdev_priv(dev);
5134
5135         if ((ering->rx_pending > MAX_TOTAL_RX_DESC_CNT) ||
5136                 (ering->tx_pending > MAX_TX_DESC_CNT) ||
5137                 (ering->tx_pending <= MAX_SKB_FRAGS)) {
5138
5139                 return -EINVAL;
5140         }
5141         if (netif_running(bp->dev)) {
5142                 bnx2_netif_stop(bp);
5143                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5144                 bnx2_free_skbs(bp);
5145                 bnx2_free_mem(bp);
5146         }
5147
5148         bnx2_set_rx_ring_size(bp, ering->rx_pending);
5149         bp->tx_ring_size = ering->tx_pending;
5150
5151         if (netif_running(bp->dev)) {
5152                 int rc;
5153
5154                 rc = bnx2_alloc_mem(bp);
5155                 if (rc)
5156                         return rc;
5157                 bnx2_init_nic(bp);
5158                 bnx2_netif_start(bp);
5159         }
5160
5161         return 0;
5162 }
5163
5164 static void
5165 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5166 {
5167         struct bnx2 *bp = netdev_priv(dev);
5168
5169         epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
5170         epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
5171         epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
5172 }
5173
5174 static int
5175 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
5176 {
5177         struct bnx2 *bp = netdev_priv(dev);
5178
5179         bp->req_flow_ctrl = 0;
5180         if (epause->rx_pause)
5181                 bp->req_flow_ctrl |= FLOW_CTRL_RX;
5182         if (epause->tx_pause)
5183                 bp->req_flow_ctrl |= FLOW_CTRL_TX;
5184
5185         if (epause->autoneg) {
5186                 bp->autoneg |= AUTONEG_FLOW_CTRL;
5187         }
5188         else {
5189                 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
5190         }
5191
5192         spin_lock_bh(&bp->phy_lock);
5193
5194         bnx2_setup_phy(bp);
5195
5196         spin_unlock_bh(&bp->phy_lock);
5197
5198         return 0;
5199 }
5200
5201 static u32
5202 bnx2_get_rx_csum(struct net_device *dev)
5203 {
5204         struct bnx2 *bp = netdev_priv(dev);
5205
5206         return bp->rx_csum;
5207 }
5208
5209 static int
5210 bnx2_set_rx_csum(struct net_device *dev, u32 data)
5211 {
5212         struct bnx2 *bp = netdev_priv(dev);
5213
5214         bp->rx_csum = data;
5215         return 0;
5216 }
5217
5218 static int
5219 bnx2_set_tso(struct net_device *dev, u32 data)
5220 {
5221         if (data)
5222                 dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
5223         else
5224                 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO_ECN);
5225         return 0;
5226 }
5227
5228 #define BNX2_NUM_STATS 46
5229
5230 static struct {
5231         char string[ETH_GSTRING_LEN];
5232 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
5233         { "rx_bytes" },
5234         { "rx_error_bytes" },
5235         { "tx_bytes" },
5236         { "tx_error_bytes" },
5237         { "rx_ucast_packets" },
5238         { "rx_mcast_packets" },
5239         { "rx_bcast_packets" },
5240         { "tx_ucast_packets" },
5241         { "tx_mcast_packets" },
5242         { "tx_bcast_packets" },
5243         { "tx_mac_errors" },
5244         { "tx_carrier_errors" },
5245         { "rx_crc_errors" },
5246         { "rx_align_errors" },
5247         { "tx_single_collisions" },
5248         { "tx_multi_collisions" },
5249         { "tx_deferred" },
5250         { "tx_excess_collisions" },
5251         { "tx_late_collisions" },
5252         { "tx_total_collisions" },
5253         { "rx_fragments" },
5254         { "rx_jabbers" },
5255         { "rx_undersize_packets" },
5256         { "rx_oversize_packets" },
5257         { "rx_64_byte_packets" },
5258         { "rx_65_to_127_byte_packets" },
5259         { "rx_128_to_255_byte_packets" },
5260         { "rx_256_to_511_byte_packets" },
5261         { "rx_512_to_1023_byte_packets" },
5262         { "rx_1024_to_1522_byte_packets" },
5263         { "rx_1523_to_9022_byte_packets" },
5264         { "tx_64_byte_packets" },
5265         { "tx_65_to_127_byte_packets" },
5266         { "tx_128_to_255_byte_packets" },
5267         { "tx_256_to_511_byte_packets" },
5268         { "tx_512_to_1023_byte_packets" },
5269         { "tx_1024_to_1522_byte_packets" },
5270         { "tx_1523_to_9022_byte_packets" },
5271         { "rx_xon_frames" },
5272         { "rx_xoff_frames" },
5273         { "tx_xon_frames" },
5274         { "tx_xoff_frames" },
5275         { "rx_mac_ctrl_frames" },
5276         { "rx_filtered_packets" },
5277         { "rx_discards" },
5278         { "rx_fw_discards" },
5279 };
5280
5281 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
5282
5283 static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
5284     STATS_OFFSET32(stat_IfHCInOctets_hi),
5285     STATS_OFFSET32(stat_IfHCInBadOctets_hi),
5286     STATS_OFFSET32(stat_IfHCOutOctets_hi),
5287     STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
5288     STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
5289     STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
5290     STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
5291     STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
5292     STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
5293     STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
5294     STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
5295     STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
5296     STATS_OFFSET32(stat_Dot3StatsFCSErrors),
5297     STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
5298     STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
5299     STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
5300     STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
5301     STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
5302     STATS_OFFSET32(stat_Dot3StatsLateCollisions),
5303     STATS_OFFSET32(stat_EtherStatsCollisions),
5304     STATS_OFFSET32(stat_EtherStatsFragments),
5305     STATS_OFFSET32(stat_EtherStatsJabbers),
5306     STATS_OFFSET32(stat_EtherStatsUndersizePkts),
5307     STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
5308     STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
5309     STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
5310     STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
5311     STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
5312     STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
5313     STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
5314     STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
5315     STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
5316     STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
5317     STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
5318     STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
5319     STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
5320     STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
5321     STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
5322     STATS_OFFSET32(stat_XonPauseFramesReceived),
5323     STATS_OFFSET32(stat_XoffPauseFramesReceived),
5324     STATS_OFFSET32(stat_OutXonSent),
5325     STATS_OFFSET32(stat_OutXoffSent),
5326     STATS_OFFSET32(stat_MacControlFramesReceived),
5327     STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
5328     STATS_OFFSET32(stat_IfInMBUFDiscards),
5329     STATS_OFFSET32(stat_FwRxDrop),
5330 };
5331
5332 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
5333  * skipped because of errata.
5334  */
5335 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
5336         8,0,8,8,8,8,8,8,8,8,
5337         4,0,4,4,4,4,4,4,4,4,
5338         4,4,4,4,4,4,4,4,4,4,
5339         4,4,4,4,4,4,4,4,4,4,
5340         4,4,4,4,4,4,
5341 };
5342
5343 static u8 bnx2_5708_stats_len_arr[BNX2_NUM_STATS] = {
5344         8,0,8,8,8,8,8,8,8,8,
5345         4,4,4,4,4,4,4,4,4,4,
5346         4,4,4,4,4,4,4,4,4,4,
5347         4,4,4,4,4,4,4,4,4,4,
5348         4,4,4,4,4,4,
5349 };
5350
5351 #define BNX2_NUM_TESTS 6
5352
5353 static struct {
5354         char string[ETH_GSTRING_LEN];
5355 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
5356         { "register_test (offline)" },
5357         { "memory_test (offline)" },
5358         { "loopback_test (offline)" },
5359         { "nvram_test (online)" },
5360         { "interrupt_test (online)" },
5361         { "link_test (online)" },
5362 };
5363
5364 static int
5365 bnx2_self_test_count(struct net_device *dev)
5366 {
5367         return BNX2_NUM_TESTS;
5368 }
5369
5370 static void
5371 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
5372 {
5373         struct bnx2 *bp = netdev_priv(dev);
5374
5375         memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
5376         if (etest->flags & ETH_TEST_FL_OFFLINE) {
5377                 int i;
5378
5379                 bnx2_netif_stop(bp);
5380                 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
5381                 bnx2_free_skbs(bp);
5382
5383                 if (bnx2_test_registers(bp) != 0) {
5384                         buf[0] = 1;
5385                         etest->flags |= ETH_TEST_FL_FAILED;
5386                 }
5387                 if (bnx2_test_memory(bp) != 0) {
5388                         buf[1] = 1;
5389                         etest->flags |= ETH_TEST_FL_FAILED;
5390                 }
5391                 if ((buf[2] = bnx2_test_loopback(bp)) != 0)
5392                         etest->flags |= ETH_TEST_FL_FAILED;
5393
5394                 if (!netif_running(bp->dev)) {
5395                         bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
5396                 }
5397                 else {
5398                         bnx2_init_nic(bp);
5399                         bnx2_netif_start(bp);
5400                 }
5401
5402                 /* wait for link up */
5403                 for (i = 0; i < 7; i++) {
5404                         if (bp->link_up)
5405                                 break;
5406                         msleep_interruptible(1000);
5407                 }
5408         }
5409
5410         if (bnx2_test_nvram(bp) != 0) {
5411                 buf[3] = 1;
5412                 etest->flags |= ETH_TEST_FL_FAILED;
5413         }
5414         if (bnx2_test_intr(bp) != 0) {
5415                 buf[4] = 1;
5416                 etest->flags |= ETH_TEST_FL_FAILED;
5417         }
5418
5419         if (bnx2_test_link(bp) != 0) {
5420                 buf[5] = 1;
5421                 etest->flags |= ETH_TEST_FL_FAILED;
5422
5423         }
5424 }
5425
5426 static void
5427 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
5428 {
5429         switch (stringset) {
5430         case ETH_SS_STATS:
5431                 memcpy(buf, bnx2_stats_str_arr,
5432                         sizeof(bnx2_stats_str_arr));
5433                 break;
5434         case ETH_SS_TEST:
5435                 memcpy(buf, bnx2_tests_str_arr,
5436                         sizeof(bnx2_tests_str_arr));
5437                 break;
5438         }
5439 }
5440
5441 static int
5442 bnx2_get_stats_count(struct net_device *dev)
5443 {
5444         return BNX2_NUM_STATS;
5445 }
5446
5447 static void
5448 bnx2_get_ethtool_stats(struct net_device *dev,
5449                 struct ethtool_stats *stats, u64 *buf)
5450 {
5451         struct bnx2 *bp = netdev_priv(dev);
5452         int i;
5453         u32 *hw_stats = (u32 *) bp->stats_blk;
5454         u8 *stats_len_arr = NULL;
5455
5456         if (hw_stats == NULL) {
5457                 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
5458                 return;
5459         }
5460
5461         if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
5462             (CHIP_ID(bp) == CHIP_ID_5706_A1) ||
5463             (CHIP_ID(bp) == CHIP_ID_5706_A2) ||
5464             (CHIP_ID(bp) == CHIP_ID_5708_A0))
5465                 stats_len_arr = bnx2_5706_stats_len_arr;
5466         else
5467                 stats_len_arr = bnx2_5708_stats_len_arr;
5468
5469         for (i = 0; i < BNX2_NUM_STATS; i++) {
5470                 if (stats_len_arr[i] == 0) {
5471                         /* skip this counter */
5472                         buf[i] = 0;
5473                         continue;
5474                 }
5475                 if (stats_len_arr[i] == 4) {
5476                         /* 4-byte counter */
5477                         buf[i] = (u64)
5478                                 *(hw_stats + bnx2_stats_offset_arr[i]);
5479                         continue;
5480                 }
5481                 /* 8-byte counter */
5482                 buf[i] = (((u64) *(hw_stats +
5483                                         bnx2_stats_offset_arr[i])) << 32) +
5484                                 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
5485         }
5486 }
5487
5488 static int
5489 bnx2_phys_id(struct net_device *dev, u32 data)
5490 {
5491         struct bnx2 *bp = netdev_priv(dev);
5492         int i;
5493         u32 save;
5494
5495         if (data == 0)
5496                 data = 2;
5497
5498         save = REG_RD(bp, BNX2_MISC_CFG);
5499         REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
5500
5501         for (i = 0; i < (data * 2); i++) {
5502                 if ((i % 2) == 0) {
5503                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
5504                 }
5505                 else {
5506                         REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
5507                                 BNX2_EMAC_LED_1000MB_OVERRIDE |
5508                                 BNX2_EMAC_LED_100MB_OVERRIDE |
5509                                 BNX2_EMAC_LED_10MB_OVERRIDE |
5510                                 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
5511                                 BNX2_EMAC_LED_TRAFFIC);
5512                 }
5513                 msleep_interruptible(500);
5514                 if (signal_pending(current))
5515                         break;
5516         }
5517         REG_WR(bp, BNX2_EMAC_LED, 0);
5518         REG_WR(bp, BNX2_MISC_CFG, save);
5519         return 0;
5520 }
5521
5522 static const struct ethtool_ops bnx2_ethtool_ops = {
5523         .get_settings           = bnx2_get_settings,
5524         .set_settings           = bnx2_set_settings,
5525         .get_drvinfo            = bnx2_get_drvinfo,
5526         .get_regs_len           = bnx2_get_regs_len,
5527         .get_regs               = bnx2_get_regs,
5528         .get_wol                = bnx2_get_wol,
5529         .set_wol                = bnx2_set_wol,
5530         .nway_reset             = bnx2_nway_reset,
5531         .get_link               = ethtool_op_get_link,
5532         .get_eeprom_len         = bnx2_get_eeprom_len,
5533         .get_eeprom             = bnx2_get_eeprom,
5534         .set_eeprom             = bnx2_set_eeprom,
5535         .get_coalesce           = bnx2_get_coalesce,
5536         .set_coalesce           = bnx2_set_coalesce,
5537         .get_ringparam          = bnx2_get_ringparam,
5538         .set_ringparam          = bnx2_set_ringparam,
5539         .get_pauseparam         = bnx2_get_pauseparam,
5540         .set_pauseparam         = bnx2_set_pauseparam,
5541         .get_rx_csum            = bnx2_get_rx_csum,
5542         .set_rx_csum            = bnx2_set_rx_csum,
5543         .get_tx_csum            = ethtool_op_get_tx_csum,
5544         .set_tx_csum            = ethtool_op_set_tx_csum,
5545         .get_sg                 = ethtool_op_get_sg,
5546         .set_sg                 = ethtool_op_set_sg,
5547 #ifdef BCM_TSO
5548         .get_tso                = ethtool_op_get_tso,
5549         .set_tso                = bnx2_set_tso,
5550 #endif
5551         .self_test_count        = bnx2_self_test_count,
5552         .self_test              = bnx2_self_test,
5553         .get_strings            = bnx2_get_strings,
5554         .phys_id                = bnx2_phys_id,
5555         .get_stats_count        = bnx2_get_stats_count,
5556         .get_ethtool_stats      = bnx2_get_ethtool_stats,
5557         .get_perm_addr          = ethtool_op_get_perm_addr,
5558 };
5559
5560 /* Called with rtnl_lock */
5561 static int
5562 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5563 {
5564         struct mii_ioctl_data *data = if_mii(ifr);
5565         struct bnx2 *bp = netdev_priv(dev);
5566         int err;
5567
5568         switch(cmd) {
5569         case SIOCGMIIPHY:
5570                 data->phy_id = bp->phy_addr;
5571
5572                 /* fallthru */
5573         case SIOCGMIIREG: {
5574                 u32 mii_regval;
5575
5576                 spin_lock_bh(&bp->phy_lock);
5577                 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5578                 spin_unlock_bh(&bp->phy_lock);
5579
5580                 data->val_out = mii_regval;
5581
5582                 return err;
5583         }
5584
5585         case SIOCSMIIREG:
5586                 if (!capable(CAP_NET_ADMIN))
5587                         return -EPERM;
5588
5589                 spin_lock_bh(&bp->phy_lock);
5590                 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5591                 spin_unlock_bh(&bp->phy_lock);
5592
5593                 return err;
5594
5595         default:
5596                 /* do nothing */
5597                 break;
5598         }
5599         return -EOPNOTSUPP;
5600 }
5601
5602 /* Called with rtnl_lock */
5603 static int
5604 bnx2_change_mac_addr(struct net_device *dev, void *p)
5605 {
5606         struct sockaddr *addr = p;
5607         struct bnx2 *bp = netdev_priv(dev);
5608
5609         if (!is_valid_ether_addr(addr->sa_data))
5610                 return -EINVAL;
5611
5612         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5613         if (netif_running(dev))
5614                 bnx2_set_mac_addr(bp);
5615
5616         return 0;
5617 }
5618
5619 /* Called with rtnl_lock */
5620 static int
5621 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5622 {
5623         struct bnx2 *bp = netdev_priv(dev);
5624
5625         if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5626                 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5627                 return -EINVAL;
5628
5629         dev->mtu = new_mtu;
5630         if (netif_running(dev)) {
5631                 bnx2_netif_stop(bp);
5632
5633                 bnx2_init_nic(bp);
5634
5635                 bnx2_netif_start(bp);
5636         }
5637         return 0;
5638 }
5639
5640 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5641 static void
5642 poll_bnx2(struct net_device *dev)
5643 {
5644         struct bnx2 *bp = netdev_priv(dev);
5645
5646         disable_irq(bp->pdev->irq);
5647         bnx2_interrupt(bp->pdev->irq, dev);
5648         enable_irq(bp->pdev->irq);
5649 }
5650 #endif
5651
5652 static void __devinit
5653 bnx2_get_5709_media(struct bnx2 *bp)
5654 {
5655         u32 val = REG_RD(bp, BNX2_MISC_DUAL_MEDIA_CTRL);
5656         u32 bond_id = val & BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID;
5657         u32 strap;
5658
5659         if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C)
5660                 return;
5661         else if (bond_id == BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
5662                 bp->phy_flags |= PHY_SERDES_FLAG;
5663                 return;
5664         }
5665
5666         if (val & BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
5667                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
5668         else
5669                 strap = (val & BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
5670
5671         if (PCI_FUNC(bp->pdev->devfn) == 0) {
5672                 switch (strap) {
5673                 case 0x4:
5674                 case 0x5:
5675                 case 0x6:
5676                         bp->phy_flags |= PHY_SERDES_FLAG;
5677                         return;
5678                 }
5679         } else {
5680                 switch (strap) {
5681                 case 0x1:
5682                 case 0x2:
5683                 case 0x4:
5684                         bp->phy_flags |= PHY_SERDES_FLAG;
5685                         return;
5686                 }
5687         }
5688 }
5689
5690 static int __devinit
5691 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5692 {
5693         struct bnx2 *bp;
5694         unsigned long mem_len;
5695         int rc;
5696         u32 reg;
5697
5698         SET_MODULE_OWNER(dev);
5699         SET_NETDEV_DEV(dev, &pdev->dev);
5700         bp = netdev_priv(dev);
5701
5702         bp->flags = 0;
5703         bp->phy_flags = 0;
5704
5705         /* enable device (incl. PCI PM wakeup), and bus-mastering */
5706         rc = pci_enable_device(pdev);
5707         if (rc) {
5708                 dev_err(&pdev->dev, "Cannot enable PCI device, aborting.");
5709                 goto err_out;
5710         }
5711
5712         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5713                 dev_err(&pdev->dev,
5714                         "Cannot find PCI device base address, aborting.\n");
5715                 rc = -ENODEV;
5716                 goto err_out_disable;
5717         }
5718
5719         rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5720         if (rc) {
5721                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting.\n");
5722                 goto err_out_disable;
5723         }
5724
5725         pci_set_master(pdev);
5726
5727         bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5728         if (bp->pm_cap == 0) {
5729                 dev_err(&pdev->dev,
5730                         "Cannot find power management capability, aborting.\n");
5731                 rc = -EIO;
5732                 goto err_out_release;
5733         }
5734
5735         if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5736                 bp->flags |= USING_DAC_FLAG;
5737                 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5738                         dev_err(&pdev->dev,
5739                                 "pci_set_consistent_dma_mask failed, aborting.\n");
5740                         rc = -EIO;
5741                         goto err_out_release;
5742                 }
5743         }
5744         else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5745                 dev_err(&pdev->dev, "System does not support DMA, aborting.\n");
5746                 rc = -EIO;
5747                 goto err_out_release;
5748         }
5749
5750         bp->dev = dev;
5751         bp->pdev = pdev;
5752
5753         spin_lock_init(&bp->phy_lock);
5754         INIT_WORK(&bp->reset_task, bnx2_reset_task);
5755
5756         dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5757         mem_len = MB_GET_CID_ADDR(TX_TSS_CID + 1);
5758         dev->mem_end = dev->mem_start + mem_len;
5759         dev->irq = pdev->irq;
5760
5761         bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5762
5763         if (!bp->regview) {
5764                 dev_err(&pdev->dev, "Cannot map register space, aborting.\n");
5765                 rc = -ENOMEM;
5766                 goto err_out_release;
5767         }
5768
5769         /* Configure byte swap and enable write to the reg_window registers.
5770          * Rely on CPU to do target byte swapping on big endian systems
5771          * The chip's target access swapping will not swap all accesses
5772          */
5773         pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5774                                BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5775                                BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5776
5777         bnx2_set_power_state(bp, PCI_D0);
5778
5779         bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5780
5781         if (CHIP_NUM(bp) != CHIP_NUM_5709) {
5782                 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5783                 if (bp->pcix_cap == 0) {
5784                         dev_err(&pdev->dev,
5785                                 "Cannot find PCIX capability, aborting.\n");
5786                         rc = -EIO;
5787                         goto err_out_unmap;
5788                 }
5789         }
5790
5791         /* Get bus information. */
5792         reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5793         if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5794                 u32 clkreg;
5795
5796                 bp->flags |= PCIX_FLAG;
5797
5798                 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5799
5800                 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5801                 switch (clkreg) {
5802                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5803                         bp->bus_speed_mhz = 133;
5804                         break;
5805
5806                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5807                         bp->bus_speed_mhz = 100;
5808                         break;
5809
5810                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5811                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5812                         bp->bus_speed_mhz = 66;
5813                         break;
5814
5815                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5816                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5817                         bp->bus_speed_mhz = 50;
5818                         break;
5819
5820                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5821                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5822                 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5823                         bp->bus_speed_mhz = 33;
5824                         break;
5825                 }
5826         }
5827         else {
5828                 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5829                         bp->bus_speed_mhz = 66;
5830                 else
5831                         bp->bus_speed_mhz = 33;
5832         }
5833
5834         if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5835                 bp->flags |= PCI_32BIT_FLAG;
5836
5837         /* 5706A0 may falsely detect SERR and PERR. */
5838         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5839                 reg = REG_RD(bp, PCI_COMMAND);
5840                 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5841                 REG_WR(bp, PCI_COMMAND, reg);
5842         }
5843         else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5844                 !(bp->flags & PCIX_FLAG)) {
5845
5846                 dev_err(&pdev->dev,
5847                         "5706 A1 can only be used in a PCIX bus, aborting.\n");
5848                 goto err_out_unmap;
5849         }
5850
5851         bnx2_init_nvram(bp);
5852
5853         reg = REG_RD_IND(bp, BNX2_SHM_HDR_SIGNATURE);
5854
5855         if ((reg & BNX2_SHM_HDR_SIGNATURE_SIG_MASK) ==
5856             BNX2_SHM_HDR_SIGNATURE_SIG) {
5857                 u32 off = PCI_FUNC(pdev->devfn) << 2;
5858
5859                 bp->shmem_base = REG_RD_IND(bp, BNX2_SHM_HDR_ADDR_0 + off);
5860         } else
5861                 bp->shmem_base = HOST_VIEW_SHMEM_BASE;
5862
5863         /* Get the permanent MAC address.  First we need to make sure the
5864          * firmware is actually running.
5865          */
5866         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_SIGNATURE);
5867
5868         if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5869             BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5870                 dev_err(&pdev->dev, "Firmware not running, aborting.\n");
5871                 rc = -ENODEV;
5872                 goto err_out_unmap;
5873         }
5874
5875         bp->fw_ver = REG_RD_IND(bp, bp->shmem_base + BNX2_DEV_INFO_BC_REV);
5876
5877         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_UPPER);
5878         bp->mac_addr[0] = (u8) (reg >> 8);
5879         bp->mac_addr[1] = (u8) reg;
5880
5881         reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_MAC_LOWER);
5882         bp->mac_addr[2] = (u8) (reg >> 24);
5883         bp->mac_addr[3] = (u8) (reg >> 16);
5884         bp->mac_addr[4] = (u8) (reg >> 8);
5885         bp->mac_addr[5] = (u8) reg;
5886
5887         bp->tx_ring_size = MAX_TX_DESC_CNT;
5888         bnx2_set_rx_ring_size(bp, 255);
5889
5890         bp->rx_csum = 1;
5891
5892         bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5893
5894         bp->tx_quick_cons_trip_int = 20;
5895         bp->tx_quick_cons_trip = 20;
5896         bp->tx_ticks_int = 80;
5897         bp->tx_ticks = 80;
5898
5899         bp->rx_quick_cons_trip_int = 6;
5900         bp->rx_quick_cons_trip = 6;
5901         bp->rx_ticks_int = 18;
5902         bp->rx_ticks = 18;
5903
5904         bp->stats_ticks = 1000000 & 0xffff00;
5905
5906         bp->timer_interval =  HZ;
5907         bp->current_interval =  HZ;
5908
5909         bp->phy_addr = 1;
5910
5911         /* Disable WOL support if we are running on a SERDES chip. */
5912         if (CHIP_NUM(bp) == CHIP_NUM_5709)
5913                 bnx2_get_5709_media(bp);
5914         else if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT)
5915                 bp->phy_flags |= PHY_SERDES_FLAG;
5916
5917         if (bp->phy_flags & PHY_SERDES_FLAG) {
5918                 bp->flags |= NO_WOL_FLAG;
5919                 if (CHIP_NUM(bp) != CHIP_NUM_5706) {
5920                         bp->phy_addr = 2;
5921                         reg = REG_RD_IND(bp, bp->shmem_base +
5922                                          BNX2_SHARED_HW_CFG_CONFIG);
5923                         if (reg & BNX2_SHARED_HW_CFG_PHY_2_5G)
5924                                 bp->phy_flags |= PHY_2_5G_CAPABLE_FLAG;
5925                 }
5926         } else if (CHIP_NUM(bp) == CHIP_NUM_5706 ||
5927                    CHIP_NUM(bp) == CHIP_NUM_5708)
5928                 bp->phy_flags |= PHY_CRC_FIX_FLAG;
5929         else if (CHIP_ID(bp) == CHIP_ID_5709_A0)
5930                 bp->phy_flags |= PHY_DIS_EARLY_DAC_FLAG;
5931
5932         if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
5933             (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
5934             (CHIP_ID(bp) == CHIP_ID_5708_B1))
5935                 bp->flags |= NO_WOL_FLAG;
5936
5937         if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5938                 bp->tx_quick_cons_trip_int =
5939                         bp->tx_quick_cons_trip;
5940                 bp->tx_ticks_int = bp->tx_ticks;
5941                 bp->rx_quick_cons_trip_int =
5942                         bp->rx_quick_cons_trip;
5943                 bp->rx_ticks_int = bp->rx_ticks;
5944                 bp->comp_prod_trip_int = bp->comp_prod_trip;
5945                 bp->com_ticks_int = bp->com_ticks;
5946                 bp->cmd_ticks_int = bp->cmd_ticks;
5947         }
5948
5949         /* Disable MSI on 5706 if AMD 8132 bridge is found.
5950          *
5951          * MSI is defined to be 32-bit write.  The 5706 does 64-bit MSI writes
5952          * with byte enables disabled on the unused 32-bit word.  This is legal
5953          * but causes problems on the AMD 8132 which will eventually stop
5954          * responding after a while.
5955          *
5956          * AMD believes this incompatibility is unique to the 5706, and
5957          * prefers to locally disable MSI rather than globally disabling it
5958          * using pci_msi_quirk.
5959          */
5960         if (CHIP_NUM(bp) == CHIP_NUM_5706 && disable_msi == 0) {
5961                 struct pci_dev *amd_8132 = NULL;
5962
5963                 while ((amd_8132 = pci_get_device(PCI_VENDOR_ID_AMD,
5964                                                   PCI_DEVICE_ID_AMD_8132_BRIDGE,
5965                                                   amd_8132))) {
5966                         u8 rev;
5967
5968                         pci_read_config_byte(amd_8132, PCI_REVISION_ID, &rev);
5969                         if (rev >= 0x10 && rev <= 0x13) {
5970                                 disable_msi = 1;
5971                                 pci_dev_put(amd_8132);
5972                                 break;
5973                         }
5974                 }
5975         }
5976
5977         bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5978         bp->req_line_speed = 0;
5979         if (bp->phy_flags & PHY_SERDES_FLAG) {
5980                 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5981
5982                 reg = REG_RD_IND(bp, bp->shmem_base + BNX2_PORT_HW_CFG_CONFIG);
5983                 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5984                 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5985                         bp->autoneg = 0;
5986                         bp->req_line_speed = bp->line_speed = SPEED_1000;
5987                         bp->req_duplex = DUPLEX_FULL;
5988                 }
5989         }
5990         else {
5991                 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5992         }
5993
5994         bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5995
5996         init_timer(&bp->timer);
5997         bp->timer.expires = RUN_AT(bp->timer_interval);
5998         bp->timer.data = (unsigned long) bp;
5999         bp->timer.function = bnx2_timer;
6000
6001         return 0;
6002
6003 err_out_unmap:
6004         if (bp->regview) {
6005                 iounmap(bp->regview);
6006                 bp->regview = NULL;
6007         }
6008
6009 err_out_release:
6010         pci_release_regions(pdev);
6011
6012 err_out_disable:
6013         pci_disable_device(pdev);
6014         pci_set_drvdata(pdev, NULL);
6015
6016 err_out:
6017         return rc;
6018 }
6019
6020 static int __devinit
6021 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
6022 {
6023         static int version_printed = 0;
6024         struct net_device *dev = NULL;
6025         struct bnx2 *bp;
6026         int rc, i;
6027
6028         if (version_printed++ == 0)
6029                 printk(KERN_INFO "%s", version);
6030
6031         /* dev zeroed in init_etherdev */
6032         dev = alloc_etherdev(sizeof(*bp));
6033
6034         if (!dev)
6035                 return -ENOMEM;
6036
6037         rc = bnx2_init_board(pdev, dev);
6038         if (rc < 0) {
6039                 free_netdev(dev);
6040                 return rc;
6041         }
6042
6043         dev->open = bnx2_open;
6044         dev->hard_start_xmit = bnx2_start_xmit;
6045         dev->stop = bnx2_close;
6046         dev->get_stats = bnx2_get_stats;
6047         dev->set_multicast_list = bnx2_set_rx_mode;
6048         dev->do_ioctl = bnx2_ioctl;
6049         dev->set_mac_address = bnx2_change_mac_addr;
6050         dev->change_mtu = bnx2_change_mtu;
6051         dev->tx_timeout = bnx2_tx_timeout;
6052         dev->watchdog_timeo = TX_TIMEOUT;
6053 #ifdef BCM_VLAN
6054         dev->vlan_rx_register = bnx2_vlan_rx_register;
6055         dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
6056 #endif
6057         dev->poll = bnx2_poll;
6058         dev->ethtool_ops = &bnx2_ethtool_ops;
6059         dev->weight = 64;
6060
6061         bp = netdev_priv(dev);
6062
6063 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
6064         dev->poll_controller = poll_bnx2;
6065 #endif
6066
6067         if ((rc = register_netdev(dev))) {
6068                 dev_err(&pdev->dev, "Cannot register net device\n");
6069                 if (bp->regview)
6070                         iounmap(bp->regview);
6071                 pci_release_regions(pdev);
6072                 pci_disable_device(pdev);
6073                 pci_set_drvdata(pdev, NULL);
6074                 free_netdev(dev);
6075                 return rc;
6076         }
6077
6078         pci_set_drvdata(pdev, dev);
6079
6080         memcpy(dev->dev_addr, bp->mac_addr, 6);
6081         memcpy(dev->perm_addr, bp->mac_addr, 6);
6082         bp->name = board_info[ent->driver_data].name,
6083         printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
6084                 "IRQ %d, ",
6085                 dev->name,
6086                 bp->name,
6087                 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
6088                 ((CHIP_ID(bp) & 0x0ff0) >> 4),
6089                 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
6090                 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
6091                 bp->bus_speed_mhz,
6092                 dev->base_addr,
6093                 bp->pdev->irq);
6094
6095         printk("node addr ");
6096         for (i = 0; i < 6; i++)
6097                 printk("%2.2x", dev->dev_addr[i]);
6098         printk("\n");
6099
6100         dev->features |= NETIF_F_SG;
6101         if (bp->flags & USING_DAC_FLAG)
6102                 dev->features |= NETIF_F_HIGHDMA;
6103         dev->features |= NETIF_F_IP_CSUM;
6104 #ifdef BCM_VLAN
6105         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
6106 #endif
6107 #ifdef BCM_TSO
6108         dev->features |= NETIF_F_TSO | NETIF_F_TSO_ECN;
6109 #endif
6110
6111         netif_carrier_off(bp->dev);
6112
6113         return 0;
6114 }
6115
6116 static void __devexit
6117 bnx2_remove_one(struct pci_dev *pdev)
6118 {
6119         struct net_device *dev = pci_get_drvdata(pdev);
6120         struct bnx2 *bp = netdev_priv(dev);
6121
6122         flush_scheduled_work();
6123
6124         unregister_netdev(dev);
6125
6126         if (bp->regview)
6127                 iounmap(bp->regview);
6128
6129         free_netdev(dev);
6130         pci_release_regions(pdev);
6131         pci_disable_device(pdev);
6132         pci_set_drvdata(pdev, NULL);
6133 }
6134
6135 static int
6136 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
6137 {
6138         struct net_device *dev = pci_get_drvdata(pdev);
6139         struct bnx2 *bp = netdev_priv(dev);
6140         u32 reset_code;
6141
6142         if (!netif_running(dev))
6143                 return 0;
6144
6145         flush_scheduled_work();
6146         bnx2_netif_stop(bp);
6147         netif_device_detach(dev);
6148         del_timer_sync(&bp->timer);
6149         if (bp->flags & NO_WOL_FLAG)
6150                 reset_code = BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN;
6151         else if (bp->wol)
6152                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
6153         else
6154                 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
6155         bnx2_reset_chip(bp, reset_code);
6156         bnx2_free_skbs(bp);
6157         bnx2_set_power_state(bp, pci_choose_state(pdev, state));
6158         return 0;
6159 }
6160
6161 static int
6162 bnx2_resume(struct pci_dev *pdev)
6163 {
6164         struct net_device *dev = pci_get_drvdata(pdev);
6165         struct bnx2 *bp = netdev_priv(dev);
6166
6167         if (!netif_running(dev))
6168                 return 0;
6169
6170         bnx2_set_power_state(bp, PCI_D0);
6171         netif_device_attach(dev);
6172         bnx2_init_nic(bp);
6173         bnx2_netif_start(bp);
6174         return 0;
6175 }
6176
6177 static struct pci_driver bnx2_pci_driver = {
6178         .name           = DRV_MODULE_NAME,
6179         .id_table       = bnx2_pci_tbl,
6180         .probe          = bnx2_init_one,
6181         .remove         = __devexit_p(bnx2_remove_one),
6182         .suspend        = bnx2_suspend,
6183         .resume         = bnx2_resume,
6184 };
6185
6186 static int __init bnx2_init(void)
6187 {
6188         return pci_register_driver(&bnx2_pci_driver);
6189 }
6190
6191 static void __exit bnx2_cleanup(void)
6192 {
6193         pci_unregister_driver(&bnx2_pci_driver);
6194 }
6195
6196 module_init(bnx2_init);
6197 module_exit(bnx2_cleanup);
6198
6199
6200