drivers/net/chelsio/vsc8244.c

   1 /*
   2  * This file is part of the Chelsio T2 Ethernet driver.
   3  *
   4  * Copyright (C) 2005 Chelsio Communications.  All rights reserved.
   5  *
   6  * This program is distributed in the hope that it will be useful, but WITHOUT
   7  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   8  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
   9  * release for licensing terms and conditions.
  10  */
  11
  12 #include "common.h"
  13 #include "cphy.h"
  14 #include "elmer0.h"
  15
  16 #ifndef ADVERTISE_PAUSE_CAP
  17 # define ADVERTISE_PAUSE_CAP 0x400
  18 #endif
  19 #ifndef ADVERTISE_PAUSE_ASYM
  20 # define ADVERTISE_PAUSE_ASYM 0x800
  21 #endif
  22
  23 /* Gigabit MII registers */
  24 #ifndef MII_CTRL1000
  25 # define MII_CTRL1000 9
  26 #endif
  27
  28 #ifndef ADVERTISE_1000FULL
  29 # define ADVERTISE_1000FULL 0x200
  30 # define ADVERTISE_1000HALF 0x100
  31 #endif
  32
  33 /* VSC8244 PHY specific registers. */
  34 enum {
  35         VSC8244_INTR_ENABLE   = 25,
  36         VSC8244_INTR_STATUS   = 26,
  37         VSC8244_AUX_CTRL_STAT = 28,
  38 };
  39
  40 enum {
  41         VSC_INTR_RX_ERR     = 1 << 0,
  42         VSC_INTR_MS_ERR     = 1 << 1,  /* master/slave resolution error */
  43         VSC_INTR_CABLE      = 1 << 2,  /* cable impairment */
  44         VSC_INTR_FALSE_CARR = 1 << 3,  /* false carrier */
  45         VSC_INTR_MEDIA_CHG  = 1 << 4,  /* AMS media change */
  46         VSC_INTR_RX_FIFO    = 1 << 5,  /* Rx FIFO over/underflow */
  47         VSC_INTR_TX_FIFO    = 1 << 6,  /* Tx FIFO over/underflow */
  48         VSC_INTR_DESCRAMBL  = 1 << 7,  /* descrambler lock-lost */
  49         VSC_INTR_SYMBOL_ERR = 1 << 8,  /* symbol error */
  50         VSC_INTR_NEG_DONE   = 1 << 10, /* autoneg done */
  51         VSC_INTR_NEG_ERR    = 1 << 11, /* autoneg error */
  52         VSC_INTR_LINK_CHG   = 1 << 13, /* link change */
  53         VSC_INTR_ENABLE     = 1 << 15, /* interrupt enable */
  54 };
  55
  56 #define CFG_CHG_INTR_MASK (VSC_INTR_LINK_CHG | VSC_INTR_NEG_ERR | \
  57                            VSC_INTR_NEG_DONE)
  58 #define INTR_MASK (CFG_CHG_INTR_MASK | VSC_INTR_TX_FIFO | VSC_INTR_RX_FIFO | \
  59                    VSC_INTR_ENABLE)
  60
  61 /* PHY specific auxiliary control & status register fields */
  62 #define S_ACSR_ACTIPHY_TMR    0
  63 #define M_ACSR_ACTIPHY_TMR    0x3
  64 #define V_ACSR_ACTIPHY_TMR(x) ((x) << S_ACSR_ACTIPHY_TMR)
  65
  66 #define S_ACSR_SPEED    3
  67 #define M_ACSR_SPEED    0x3
  68 #define G_ACSR_SPEED(x) (((x) >> S_ACSR_SPEED) & M_ACSR_SPEED)
  69
  70 #define S_ACSR_DUPLEX 5
  71 #define F_ACSR_DUPLEX (1 << S_ACSR_DUPLEX)
  72
  73 #define S_ACSR_ACTIPHY 6
  74 #define F_ACSR_ACTIPHY (1 << S_ACSR_ACTIPHY)
  75
  76 /*
  77  * Reset the PHY.  This PHY completes reset immediately so we never wait.
  78  */
  79 static int vsc8244_reset(struct cphy *cphy, int wait)
  80 {
  81         int err;
  82         unsigned int ctl;
  83
  84         err = simple_mdio_read(cphy, MII_BMCR, &ctl);
  85         if (err)
  86                 return err;
  87
  88         ctl &= ~BMCR_PDOWN;
  89         ctl |= BMCR_RESET;
  90         return simple_mdio_write(cphy, MII_BMCR, ctl);
  91 }
  92
  93 static int vsc8244_intr_enable(struct cphy *cphy)
  94 {
  95         simple_mdio_write(cphy, VSC8244_INTR_ENABLE, INTR_MASK);
  96
  97     /* Enable interrupts through Elmer */
  98         if (t1_is_asic(cphy->adapter)) {
  99                 u32 elmer;
 100
 101                 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
 102                 elmer |= ELMER0_GP_BIT1;
 103                 if (is_T2(cphy->adapter)) {
 104                     elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
 105                 }
 106                 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
 107         }
 108
 109     return 0;
 110 }
 111
 112 static int vsc8244_intr_disable(struct cphy *cphy)
 113 {
 114         simple_mdio_write(cphy, VSC8244_INTR_ENABLE, 0);
 115
 116         if (t1_is_asic(cphy->adapter)) {
 117                 u32 elmer;
 118
 119                 t1_tpi_read(cphy->adapter, A_ELMER0_INT_ENABLE, &elmer);
 120                 elmer &= ~ELMER0_GP_BIT1;
 121                 if (is_T2(cphy->adapter)) {
 122                     elmer &= ~(ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4);
 123                 }
 124                 t1_tpi_write(cphy->adapter, A_ELMER0_INT_ENABLE, elmer);
 125         }
 126
 127     return 0;
 128 }
 129
 130 static int vsc8244_intr_clear(struct cphy *cphy)
 131 {
 132         u32 val;
 133     u32 elmer;
 134
 135         /* Clear PHY interrupts by reading the register. */
 136         simple_mdio_read(cphy, VSC8244_INTR_ENABLE, &val);
 137
 138         if (t1_is_asic(cphy->adapter)) {
 139                 t1_tpi_read(cphy->adapter, A_ELMER0_INT_CAUSE, &elmer);
 140                 elmer |= ELMER0_GP_BIT1;
 141                 if (is_T2(cphy->adapter)) {
 142                     elmer |= ELMER0_GP_BIT2|ELMER0_GP_BIT3|ELMER0_GP_BIT4;
 143                 }
 144                 t1_tpi_write(cphy->adapter, A_ELMER0_INT_CAUSE, elmer);
 145         }
 146
 147     return 0;
 148 }
 149
 150 /*
 151  * Force the PHY speed and duplex.  This also disables auto-negotiation, except
 152  * for 1Gb/s, where auto-negotiation is mandatory.
 153  */
 154 static int vsc8244_set_speed_duplex(struct cphy *phy, int speed, int duplex)
 155 {
 156         int err;
 157         unsigned int ctl;
 158
 159         err = simple_mdio_read(phy, MII_BMCR, &ctl);
 160         if (err)
 161                 return err;
 162
 163         if (speed >= 0) {
 164                 ctl &= ~(BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
 165                 if (speed == SPEED_100)
 166                         ctl |= BMCR_SPEED100;
 167                 else if (speed == SPEED_1000)
 168                         ctl |= BMCR_SPEED1000;
 169         }
 170         if (duplex >= 0) {
 171                 ctl &= ~(BMCR_FULLDPLX | BMCR_ANENABLE);
 172                 if (duplex == DUPLEX_FULL)
 173                         ctl |= BMCR_FULLDPLX;
 174         }
 175         if (ctl & BMCR_SPEED1000)  /* auto-negotiation required for 1Gb/s */
 176                 ctl |= BMCR_ANENABLE;
 177         return simple_mdio_write(phy, MII_BMCR, ctl);
 178 }
 179
 180 int t1_mdio_set_bits(struct cphy *phy, int mmd, int reg, unsigned int bits)
 181 {
 182     int ret;
 183     unsigned int val;
 184
 185     ret = mdio_read(phy, mmd, reg, &val);
 186     if (!ret)
 187         ret = mdio_write(phy, mmd, reg, val | bits);
 188     return ret;
 189 }
 190
 191 static int vsc8244_autoneg_enable(struct cphy *cphy)
 192 {
 193         return t1_mdio_set_bits(cphy, 0, MII_BMCR,
 194                                 BMCR_ANENABLE | BMCR_ANRESTART);
 195 }
 196
 197 static int vsc8244_autoneg_restart(struct cphy *cphy)
 198 {
 199         return t1_mdio_set_bits(cphy, 0, MII_BMCR, BMCR_ANRESTART);
 200 }
 201
 202 static int vsc8244_advertise(struct cphy *phy, unsigned int advertise_map)
 203 {
 204         int err;
 205         unsigned int val = 0;
 206
 207         err = simple_mdio_read(phy, MII_CTRL1000, &val);
 208         if (err)
 209                 return err;
 210
 211         val &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL);
 212         if (advertise_map & ADVERTISED_1000baseT_Half)
 213                 val |= ADVERTISE_1000HALF;
 214         if (advertise_map & ADVERTISED_1000baseT_Full)
 215                 val |= ADVERTISE_1000FULL;
 216
 217         err = simple_mdio_write(phy, MII_CTRL1000, val);
 218         if (err)
 219                 return err;
 220
 221         val = 1;
 222         if (advertise_map & ADVERTISED_10baseT_Half)
 223                 val |= ADVERTISE_10HALF;
 224         if (advertise_map & ADVERTISED_10baseT_Full)
 225                 val |= ADVERTISE_10FULL;
 226         if (advertise_map & ADVERTISED_100baseT_Half)
 227                 val |= ADVERTISE_100HALF;
 228         if (advertise_map & ADVERTISED_100baseT_Full)
 229                 val |= ADVERTISE_100FULL;
 230         if (advertise_map & ADVERTISED_PAUSE)
 231                 val |= ADVERTISE_PAUSE_CAP;
 232         if (advertise_map & ADVERTISED_ASYM_PAUSE)
 233                 val |= ADVERTISE_PAUSE_ASYM;
 234         return simple_mdio_write(phy, MII_ADVERTISE, val);
 235 }
 236
 237 static int vsc8244_get_link_status(struct cphy *cphy, int *link_ok,
 238                                      int *speed, int *duplex, int *fc)
 239 {
 240         unsigned int bmcr, status, lpa, adv;
 241         int err, sp = -1, dplx = -1, pause = 0;
 242
 243         err = simple_mdio_read(cphy, MII_BMCR, &bmcr);
 244         if (!err)
 245                 err = simple_mdio_read(cphy, MII_BMSR, &status);
 246         if (err)
 247                 return err;
 248
 249         if (link_ok) {
 250                 /*
 251                  * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
 252                  * once more to get the current link state.
 253                  */
 254                 if (!(status & BMSR_LSTATUS))
 255                         err = simple_mdio_read(cphy, MII_BMSR, &status);
 256                 if (err)
 257                         return err;
 258                 *link_ok = (status & BMSR_LSTATUS) != 0;
 259         }
 260         if (!(bmcr & BMCR_ANENABLE)) {
 261                 dplx = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
 262                 if (bmcr & BMCR_SPEED1000)
 263                         sp = SPEED_1000;
 264                 else if (bmcr & BMCR_SPEED100)
 265                         sp = SPEED_100;
 266                 else
 267                         sp = SPEED_10;
 268         } else if (status & BMSR_ANEGCOMPLETE) {
 269                 err = simple_mdio_read(cphy, VSC8244_AUX_CTRL_STAT, &status);
 270                 if (err)
 271                         return err;
 272
 273                 dplx = (status & F_ACSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
 274                 sp = G_ACSR_SPEED(status);
 275                 if (sp == 0)
 276                         sp = SPEED_10;
 277                 else if (sp == 1)
 278                         sp = SPEED_100;
 279                 else
 280                         sp = SPEED_1000;
 281
 282                 if (fc && dplx == DUPLEX_FULL) {
 283                         err = simple_mdio_read(cphy, MII_LPA, &lpa);
 284                         if (!err)
 285                                 err = simple_mdio_read(cphy, MII_ADVERTISE,
 286                                                        &adv);
 287                         if (err)
 288                                 return err;
 289
 290                         if (lpa & adv & ADVERTISE_PAUSE_CAP)
 291                                 pause = PAUSE_RX | PAUSE_TX;
 292                         else if ((lpa & ADVERTISE_PAUSE_CAP) &&
 293                                  (lpa & ADVERTISE_PAUSE_ASYM) &&
 294                                  (adv & ADVERTISE_PAUSE_ASYM))
 295                                 pause = PAUSE_TX;
 296                         else if ((lpa & ADVERTISE_PAUSE_ASYM) &&
 297                                  (adv & ADVERTISE_PAUSE_CAP))
 298                                 pause = PAUSE_RX;
 299                 }
 300         }
 301         if (speed)
 302                 *speed = sp;
 303         if (duplex)
 304                 *duplex = dplx;
 305         if (fc)
 306                 *fc = pause;
 307         return 0;
 308 }
 309
 310 static int vsc8244_intr_handler(struct cphy *cphy)
 311 {
 312         unsigned int cause;
 313         int err, cphy_cause = 0;
 314
 315         err = simple_mdio_read(cphy, VSC8244_INTR_STATUS, &cause);
 316         if (err)
 317                 return err;
 318
 319         cause &= INTR_MASK;
 320         if (cause & CFG_CHG_INTR_MASK)
 321                 cphy_cause |= cphy_cause_link_change;
 322         if (cause & (VSC_INTR_RX_FIFO | VSC_INTR_TX_FIFO))
 323                 cphy_cause |= cphy_cause_fifo_error;
 324         return cphy_cause;
 325 }
 326
 327 static void vsc8244_destroy(struct cphy *cphy)
 328 {
 329         kfree(cphy);
 330 }
 331
 332 static struct cphy_ops vsc8244_ops = {
 333         .destroy              = vsc8244_destroy,
 334         .reset                = vsc8244_reset,
 335         .interrupt_enable     = vsc8244_intr_enable,
 336         .interrupt_disable    = vsc8244_intr_disable,
 337         .interrupt_clear      = vsc8244_intr_clear,
 338         .interrupt_handler    = vsc8244_intr_handler,
 339         .autoneg_enable       = vsc8244_autoneg_enable,
 340         .autoneg_restart      = vsc8244_autoneg_restart,
 341         .advertise            = vsc8244_advertise,
 342         .set_speed_duplex     = vsc8244_set_speed_duplex,
 343         .get_link_status      = vsc8244_get_link_status
 344 };
 345
 346 static struct cphy* vsc8244_phy_create(adapter_t *adapter, int phy_addr, struct mdio_ops *mdio_ops)
 347 {
 348         struct cphy *cphy = kzalloc(sizeof(*cphy), GFP_KERNEL);
 349
 350         if (!cphy) return NULL;
 351
 352         cphy_init(cphy, adapter, phy_addr, &vsc8244_ops, mdio_ops);
 353
 354         return cphy;
 355 }
 356
 357
 358 static int vsc8244_phy_reset(adapter_t* adapter)
 359 {
 360         return 0;
 361 }
 362
 363 struct gphy t1_vsc8244_ops = {
 364         vsc8244_phy_create,
 365         vsc8244_phy_reset
 366 };
 367
 368