2 Written 1998-2000 by Donald Becker.
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
21 Version 2.51, Nov 17, 2001 (jgarzik):
23 - Replace some MII-related magic numbers with constants
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.51"
29 #define DRV_RELDATE "Nov-17-2001"
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/slab.h>
78 #include <linux/interrupt.h>
79 #include <linux/pci.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/init.h>
84 #include <linux/mii.h>
85 #include <linux/ethtool.h>
86 #include <linux/crc32.h>
87 #include <linux/delay.h>
89 #include <asm/processor.h> /* Processor type for cache alignment. */
90 #include <asm/bitops.h>
92 #include <asm/uaccess.h>
94 /* These identify the driver base version and may not be removed. */
95 static char version[] __devinitdata =
96 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
99 /* This driver was written to use PCI memory space, however some x86 systems
100 work only with I/O space accesses. */
120 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
121 /* This is only in the support-all-kernels source code. */
123 #define RUN_AT(x) (jiffies + (x))
125 MODULE_AUTHOR("Myson or whoever");
126 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
127 MODULE_LICENSE("GPL");
128 MODULE_PARM(max_interrupt_work, "i");
129 //MODULE_PARM(min_pci_latency, "i");
130 MODULE_PARM(debug, "i");
131 MODULE_PARM(rx_copybreak, "i");
132 MODULE_PARM(multicast_filter_limit, "i");
133 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
134 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
135 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
136 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
137 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
138 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
139 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
140 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
142 #define MIN_REGION_SIZE 136
148 PCI_ADDR0 = 0x10 << 0,
149 PCI_ADDR1 = 0x10 << 1,
150 PCI_ADDR2 = 0x10 << 2,
151 PCI_ADDR3 = 0x10 << 3,
154 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
155 enum chip_capability_flags {
161 /* for different PHY */
162 enum phy_type_flags {
178 static struct chip_info skel_netdrv_tbl[] = {
179 {"100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
180 {"100/10M Ethernet PCI Adapter", 136, HAS_CHIP_XCVR},
181 {"1000/100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
184 /* Offsets to the Command and Status Registers. */
185 enum fealnx_offsets {
186 PAR0 = 0x0, /* physical address 0-3 */
187 PAR1 = 0x04, /* physical address 4-5 */
188 MAR0 = 0x08, /* multicast address 0-3 */
189 MAR1 = 0x0C, /* multicast address 4-7 */
190 FAR0 = 0x10, /* flow-control address 0-3 */
191 FAR1 = 0x14, /* flow-control address 4-5 */
192 TCRRCR = 0x18, /* receive & transmit configuration */
193 BCR = 0x1C, /* bus command */
194 TXPDR = 0x20, /* transmit polling demand */
195 RXPDR = 0x24, /* receive polling demand */
196 RXCWP = 0x28, /* receive current word pointer */
197 TXLBA = 0x2C, /* transmit list base address */
198 RXLBA = 0x30, /* receive list base address */
199 ISR = 0x34, /* interrupt status */
200 IMR = 0x38, /* interrupt mask */
201 FTH = 0x3C, /* flow control high/low threshold */
202 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
203 TALLY = 0x44, /* tally counters for crc and mpa */
204 TSR = 0x48, /* tally counter for transmit status */
205 BMCRSR = 0x4c, /* basic mode control and status */
206 PHYIDENTIFIER = 0x50, /* phy identifier */
207 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
209 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
210 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
213 /* Bits in the interrupt status/enable registers. */
214 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
215 enum intr_status_bits {
216 RFCON = 0x00020000, /* receive flow control xon packet */
217 RFCOFF = 0x00010000, /* receive flow control xoff packet */
218 LSCStatus = 0x00008000, /* link status change */
219 ANCStatus = 0x00004000, /* autonegotiation completed */
220 FBE = 0x00002000, /* fatal bus error */
221 FBEMask = 0x00001800, /* mask bit12-11 */
222 ParityErr = 0x00000000, /* parity error */
223 TargetErr = 0x00001000, /* target abort */
224 MasterErr = 0x00000800, /* master error */
225 TUNF = 0x00000400, /* transmit underflow */
226 ROVF = 0x00000200, /* receive overflow */
227 ETI = 0x00000100, /* transmit early int */
228 ERI = 0x00000080, /* receive early int */
229 CNTOVF = 0x00000040, /* counter overflow */
230 RBU = 0x00000020, /* receive buffer unavailable */
231 TBU = 0x00000010, /* transmit buffer unavilable */
232 TI = 0x00000008, /* transmit interrupt */
233 RI = 0x00000004, /* receive interrupt */
234 RxErr = 0x00000002, /* receive error */
237 /* Bits in the NetworkConfig register, W for writing, R for reading */
238 /* FIXME: some names are invented by me. Marked with (name?) */
239 /* If you have docs and know bit names, please fix 'em */
241 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
242 CR_W_FD = 0x00100000, /* full duplex */
243 CR_W_PS10 = 0x00080000, /* 10 mbit */
244 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
245 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
246 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
247 CR_W_RXMODEMASK = 0x000000e0,
248 CR_W_PROM = 0x00000080, /* promiscuous mode */
249 CR_W_AB = 0x00000040, /* accept broadcast */
250 CR_W_AM = 0x00000020, /* accept mutlicast */
251 CR_W_ARP = 0x00000008, /* receive runt pkt */
252 CR_W_ALP = 0x00000004, /* receive long pkt */
253 CR_W_SEP = 0x00000002, /* receive error pkt */
254 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
256 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
257 CR_R_FD = 0x00100000, /* full duplex detected */
258 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
259 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
262 /* The Tulip Rx and Tx buffer descriptors. */
268 struct fealnx_desc *next_desc_logical;
269 struct sk_buff *skbuff;
274 /* Bits in network_desc.status */
275 enum rx_desc_status_bits {
276 RXOWN = 0x80000000, /* own bit */
277 FLNGMASK = 0x0fff0000, /* frame length */
279 MARSTATUS = 0x00004000, /* multicast address received */
280 BARSTATUS = 0x00002000, /* broadcast address received */
281 PHYSTATUS = 0x00001000, /* physical address received */
282 RXFSD = 0x00000800, /* first descriptor */
283 RXLSD = 0x00000400, /* last descriptor */
284 ErrorSummary = 0x80, /* error summary */
285 RUNT = 0x40, /* runt packet received */
286 LONG = 0x20, /* long packet received */
287 FAE = 0x10, /* frame align error */
288 CRC = 0x08, /* crc error */
289 RXER = 0x04, /* receive error */
292 enum rx_desc_control_bits {
293 RXIC = 0x00800000, /* interrupt control */
297 enum tx_desc_status_bits {
298 TXOWN = 0x80000000, /* own bit */
299 JABTO = 0x00004000, /* jabber timeout */
300 CSL = 0x00002000, /* carrier sense lost */
301 LC = 0x00001000, /* late collision */
302 EC = 0x00000800, /* excessive collision */
303 UDF = 0x00000400, /* fifo underflow */
304 DFR = 0x00000200, /* deferred */
305 HF = 0x00000100, /* heartbeat fail */
306 NCRMask = 0x000000ff, /* collision retry count */
310 enum tx_desc_control_bits {
311 TXIC = 0x80000000, /* interrupt control */
312 ETIControl = 0x40000000, /* early transmit interrupt */
313 TXLD = 0x20000000, /* last descriptor */
314 TXFD = 0x10000000, /* first descriptor */
315 CRCEnable = 0x08000000, /* crc control */
316 PADEnable = 0x04000000, /* padding control */
317 RetryTxLC = 0x02000000, /* retry late collision */
318 PKTSMask = 0x3ff800, /* packet size bit21-11 */
320 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
324 /* BootROM/EEPROM/MII Management Register */
325 #define MASK_MIIR_MII_READ 0x00000000
326 #define MASK_MIIR_MII_WRITE 0x00000008
327 #define MASK_MIIR_MII_MDO 0x00000004
328 #define MASK_MIIR_MII_MDI 0x00000002
329 #define MASK_MIIR_MII_MDC 0x00000001
331 /* ST+OP+PHYAD+REGAD+TA */
332 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
333 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
335 /* ------------------------------------------------------------------------- */
336 /* Constants for Myson PHY */
337 /* ------------------------------------------------------------------------- */
338 #define MysonPHYID 0xd0000302
339 /* 89-7-27 add, (begin) */
340 #define MysonPHYID0 0x0302
341 #define StatusRegister 18
342 #define SPEED100 0x0400 // bit10
343 #define FULLMODE 0x0800 // bit11
344 /* 89-7-27 add, (end) */
346 /* ------------------------------------------------------------------------- */
347 /* Constants for Seeq 80225 PHY */
348 /* ------------------------------------------------------------------------- */
349 #define SeeqPHYID0 0x0016
351 #define MIIRegister18 18
352 #define SPD_DET_100 0x80
353 #define DPLX_DET_FULL 0x40
355 /* ------------------------------------------------------------------------- */
356 /* Constants for Ahdoc 101 PHY */
357 /* ------------------------------------------------------------------------- */
358 #define AhdocPHYID0 0x0022
360 #define DiagnosticReg 18
361 #define DPLX_FULL 0x0800
362 #define Speed_100 0x0400
365 /* -------------------------------------------------------------------------- */
367 /* -------------------------------------------------------------------------- */
368 #define MarvellPHYID0 0x0141
369 #define LevelOnePHYID0 0x0013
371 #define MII1000BaseTControlReg 9
372 #define MII1000BaseTStatusReg 10
373 #define SpecificReg 17
375 /* for 1000BaseT Control Register */
376 #define PHYAbletoPerform1000FullDuplex 0x0200
377 #define PHYAbletoPerform1000HalfDuplex 0x0100
378 #define PHY1000AbilityMask 0x300
380 // for phy specific status register, marvell phy.
381 #define SpeedMask 0x0c000
382 #define Speed_1000M 0x08000
383 #define Speed_100M 0x4000
385 #define Full_Duplex 0x2000
387 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
388 #define LXT1000_100M 0x08000
389 #define LXT1000_1000M 0x0c000
390 #define LXT1000_Full 0x200
391 // 89/12/29 add, for phy specific status register, levelone phy, (end)
393 /* for 3-in-1 case, BMCRSR register */
394 #define LinkIsUp2 0x00040000
397 #define LinkIsUp 0x0004
400 struct netdev_private {
401 /* Descriptor rings first for alignment. */
402 struct fealnx_desc *rx_ring;
403 struct fealnx_desc *tx_ring;
405 dma_addr_t rx_ring_dma;
406 dma_addr_t tx_ring_dma;
410 struct net_device_stats stats;
412 /* Media monitoring timer. */
413 struct timer_list timer;
416 struct timer_list reset_timer;
417 int reset_timer_armed;
418 unsigned long crvalue_sv;
419 unsigned long imrvalue_sv;
421 /* Frequently used values: keep some adjacent for cache effect. */
423 struct pci_dev *pci_dev;
424 unsigned long crvalue;
425 unsigned long bcrvalue;
426 unsigned long imrvalue;
427 struct fealnx_desc *cur_rx;
428 struct fealnx_desc *lack_rxbuf;
430 struct fealnx_desc *cur_tx;
431 struct fealnx_desc *cur_tx_copy;
434 unsigned int rx_buf_sz; /* Based on MTU+slack. */
436 /* These values are keep track of the transceiver/media in use. */
438 unsigned int line_speed;
439 unsigned int duplexmode;
440 unsigned int default_port:4; /* Last dev->if_port value. */
441 unsigned int PHYType;
443 /* MII transceiver section. */
444 int mii_cnt; /* MII device addresses. */
445 unsigned char phys[2]; /* MII device addresses. */
446 struct mii_if_info mii;
450 static int mdio_read(struct net_device *dev, int phy_id, int location);
451 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
452 static int netdev_open(struct net_device *dev);
453 static void getlinktype(struct net_device *dev);
454 static void getlinkstatus(struct net_device *dev);
455 static void netdev_timer(unsigned long data);
456 static void reset_timer(unsigned long data);
457 static void tx_timeout(struct net_device *dev);
458 static void init_ring(struct net_device *dev);
459 static int start_tx(struct sk_buff *skb, struct net_device *dev);
460 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
461 static int netdev_rx(struct net_device *dev);
462 static void set_rx_mode(struct net_device *dev);
463 static void __set_rx_mode(struct net_device *dev);
464 static struct net_device_stats *get_stats(struct net_device *dev);
465 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
466 static struct ethtool_ops netdev_ethtool_ops;
467 static int netdev_close(struct net_device *dev);
468 static void reset_rx_descriptors(struct net_device *dev);
469 static void reset_tx_descriptors(struct net_device *dev);
471 static void stop_nic_rx(long ioaddr, long crvalue)
474 writel(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
476 if ( (readl(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
482 static void stop_nic_rxtx(long ioaddr, long crvalue)
485 writel(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
487 if ( (readl(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
488 == (CR_R_RXSTOP+CR_R_TXSTOP) )
494 static int __devinit fealnx_init_one(struct pci_dev *pdev,
495 const struct pci_device_id *ent)
497 struct netdev_private *np;
498 int i, option, err, irq;
499 static int card_idx = -1;
502 unsigned int chip_id = ent->driver_data;
503 struct net_device *dev;
507 /* when built into the kernel, we only print version if device is found */
509 static int printed_version;
510 if (!printed_version++)
515 sprintf(boardname, "fealnx%d", card_idx);
517 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
519 i = pci_enable_device(pdev);
521 pci_set_master(pdev);
524 ioaddr = pci_resource_len(pdev, 0);
526 ioaddr = pci_resource_len(pdev, 1);
528 if (ioaddr < MIN_REGION_SIZE) {
529 printk(KERN_ERR "%s: region size %ld too small, aborting\n",
534 i = pci_request_regions(pdev, boardname);
540 ioaddr = pci_resource_start(pdev, 0);
542 ioaddr = (long) ioremap(pci_resource_start(pdev, 1),
543 pci_resource_len(pdev, 1));
550 dev = alloc_etherdev(sizeof(struct netdev_private));
555 SET_MODULE_OWNER(dev);
556 SET_NETDEV_DEV(dev, &pdev->dev);
558 /* read ethernet id */
559 for (i = 0; i < 6; ++i)
560 dev->dev_addr[i] = readb(ioaddr + PAR0 + i);
562 /* Reset the chip to erase previous misconfiguration. */
563 writel(0x00000001, ioaddr + BCR);
565 dev->base_addr = ioaddr;
568 /* Make certain the descriptor lists are aligned. */
570 spin_lock_init(&np->lock);
572 np->flags = skel_netdrv_tbl[chip_id].flags;
573 pci_set_drvdata(pdev, dev);
575 np->mii.mdio_read = mdio_read;
576 np->mii.mdio_write = mdio_write;
577 np->mii.phy_id_mask = 0x1f;
578 np->mii.reg_num_mask = 0x1f;
580 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
583 goto err_out_free_dev;
585 np->rx_ring = (struct fealnx_desc *)ring_space;
586 np->rx_ring_dma = ring_dma;
588 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
591 goto err_out_free_rx;
593 np->tx_ring = (struct fealnx_desc *)ring_space;
594 np->tx_ring_dma = ring_dma;
596 /* find the connected MII xcvrs */
597 if (np->flags == HAS_MII_XCVR) {
598 int phy, phy_idx = 0;
600 for (phy = 1; phy < 32 && phy_idx < 4; phy++) {
601 int mii_status = mdio_read(dev, phy, 1);
603 if (mii_status != 0xffff && mii_status != 0x0000) {
604 np->phys[phy_idx++] = phy;
606 "%s: MII PHY found at address %d, status "
607 "0x%4.4x.\n", dev->name, phy, mii_status);
612 data = mdio_read(dev, np->phys[0], 2);
613 if (data == SeeqPHYID0)
614 np->PHYType = SeeqPHY;
615 else if (data == AhdocPHYID0)
616 np->PHYType = AhdocPHY;
617 else if (data == MarvellPHYID0)
618 np->PHYType = MarvellPHY;
619 else if (data == MysonPHYID0)
620 np->PHYType = Myson981;
621 else if (data == LevelOnePHYID0)
622 np->PHYType = LevelOnePHY;
624 np->PHYType = OtherPHY;
629 np->mii_cnt = phy_idx;
631 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
632 "not operate correctly.\n", dev->name);
636 /* 89/6/23 add, (begin) */
638 if (readl(ioaddr + PHYIDENTIFIER) == MysonPHYID)
639 np->PHYType = MysonPHY;
641 np->PHYType = OtherPHY;
643 np->mii.phy_id = np->phys[0];
646 option = dev->mem_start;
648 /* The lower four bits are the media type. */
651 np->mii.full_duplex = 1;
652 np->default_port = option & 15;
655 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
656 np->mii.full_duplex = full_duplex[card_idx];
658 if (np->mii.full_duplex) {
659 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
660 /* 89/6/13 add, (begin) */
661 // if (np->PHYType==MarvellPHY)
662 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
665 data = mdio_read(dev, np->phys[0], 9);
666 data = (data & 0xfcff) | 0x0200;
667 mdio_write(dev, np->phys[0], 9, data);
669 /* 89/6/13 add, (end) */
670 if (np->flags == HAS_MII_XCVR)
671 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
673 writel(ADVERTISE_FULL, ioaddr + ANARANLPAR);
674 np->mii.force_media = 1;
677 /* The chip-specific entries in the device structure. */
678 dev->open = &netdev_open;
679 dev->hard_start_xmit = &start_tx;
680 dev->stop = &netdev_close;
681 dev->get_stats = &get_stats;
682 dev->set_multicast_list = &set_rx_mode;
683 dev->do_ioctl = &mii_ioctl;
684 dev->ethtool_ops = &netdev_ethtool_ops;
685 dev->tx_timeout = &tx_timeout;
686 dev->watchdog_timeo = TX_TIMEOUT;
688 err = register_netdev(dev);
690 goto err_out_free_tx;
692 printk(KERN_INFO "%s: %s at 0x%lx, ",
693 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr);
694 for (i = 0; i < 5; i++)
695 printk("%2.2x:", dev->dev_addr[i]);
696 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
701 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
703 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
708 iounmap((void *)ioaddr);
711 pci_release_regions(pdev);
716 static void __devexit fealnx_remove_one(struct pci_dev *pdev)
718 struct net_device *dev = pci_get_drvdata(pdev);
721 struct netdev_private *np = dev->priv;
723 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
725 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
727 unregister_netdev(dev);
729 iounmap((void *)dev->base_addr);
732 pci_release_regions(pdev);
733 pci_set_drvdata(pdev, NULL);
735 printk(KERN_ERR "fealnx: remove for unknown device\n");
739 static ulong m80x_send_cmd_to_phy(long miiport, int opcode, int phyad, int regad)
743 unsigned int mask, data;
745 /* enable MII output */
746 miir = (ulong) readl(miiport);
749 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
751 /* send 32 1's preamble */
752 for (i = 0; i < 32; i++) {
753 /* low MDC; MDO is already high (miir) */
754 miir &= ~MASK_MIIR_MII_MDC;
755 writel(miir, miiport);
758 miir |= MASK_MIIR_MII_MDC;
759 writel(miir, miiport);
762 /* calculate ST+OP+PHYAD+REGAD+TA */
763 data = opcode | (phyad << 7) | (regad << 2);
768 /* low MDC, prepare MDO */
769 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
771 miir |= MASK_MIIR_MII_MDO;
773 writel(miir, miiport);
775 miir |= MASK_MIIR_MII_MDC;
776 writel(miir, miiport);
781 if (mask == 0x2 && opcode == OP_READ)
782 miir &= ~MASK_MIIR_MII_WRITE;
788 static int mdio_read(struct net_device *dev, int phyad, int regad)
790 long miiport = dev->base_addr + MANAGEMENT;
792 unsigned int mask, data;
794 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
801 miir &= ~MASK_MIIR_MII_MDC;
802 writel(miir, miiport);
805 miir = readl(miiport);
806 if (miir & MASK_MIIR_MII_MDI)
809 /* high MDC, and wait */
810 miir |= MASK_MIIR_MII_MDC;
811 writel(miir, miiport);
819 miir &= ~MASK_MIIR_MII_MDC;
820 writel(miir, miiport);
822 return data & 0xffff;
826 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
828 long miiport = dev->base_addr + MANAGEMENT;
832 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
837 /* low MDC, prepare MDO */
838 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
840 miir |= MASK_MIIR_MII_MDO;
841 writel(miir, miiport);
844 miir |= MASK_MIIR_MII_MDC;
845 writel(miir, miiport);
852 miir &= ~MASK_MIIR_MII_MDC;
853 writel(miir, miiport);
857 static int netdev_open(struct net_device *dev)
859 struct netdev_private *np = dev->priv;
860 long ioaddr = dev->base_addr;
862 writel(0x00000001, ioaddr + BCR); /* Reset */
864 if (request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev))
869 writel(np->rx_ring_dma, ioaddr + RXLBA);
870 writel(np->tx_ring_dma, ioaddr + TXLBA);
872 /* Initialize other registers. */
873 /* Configure the PCI bus bursts and FIFO thresholds.
874 486: Set 8 longword burst.
885 Wait the specified 50 PCI cycles after a reset by initializing
886 Tx and Rx queues and the address filter list.
887 FIXME (Ueimor): optimistic for alpha + posted writes ? */
888 #if defined(__powerpc__) || defined(__sparc__)
890 // np->bcrvalue=0x04 | 0x0x38; /* big-endian, 256 burst length */
891 np->bcrvalue = 0x04 | 0x10; /* big-endian, tx 8 burst length */
892 np->crvalue = 0xe00; /* rx 128 burst length */
893 #elif defined(__alpha__) || defined(__x86_64__)
895 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
896 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
897 np->crvalue = 0xe00; /* rx 128 burst length */
898 #elif defined(__i386__)
901 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
902 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
903 np->crvalue = 0xe00; /* rx 128 burst length */
905 /* When not a module we can work around broken '486 PCI boards. */
906 #define x86 boot_cpu_data.x86
908 // np->bcrvalue=(x86 <= 4 ? 0x10 : 0x38);
910 np->crvalue = (x86 <= 4 ? 0xa00 : 0xe00);
912 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting burst "
913 "length to %x.\n", dev->name, (x86 <= 4 ? 0x10 : 0x38));
917 // np->bcrvalue=0x38;
919 np->crvalue = 0xe00; /* rx 128 burst length */
920 #warning Processor architecture undefined!
924 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
925 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
926 if (np->pci_dev->device == 0x891) {
927 np->bcrvalue |= 0x200; /* set PROG bit */
928 np->crvalue |= CR_W_ENH; /* set enhanced bit */
931 writel(np->bcrvalue, ioaddr + BCR);
933 if (dev->if_port == 0)
934 dev->if_port = np->default_port;
936 writel(0, ioaddr + RXPDR);
938 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
939 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
940 np->mii.full_duplex = np->mii.force_media;
946 netif_start_queue(dev);
948 /* Clear and Enable interrupts by setting the interrupt mask. */
949 writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
950 writel(np->imrvalue, ioaddr + IMR);
953 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
955 /* Set the timer to check for link beat. */
956 init_timer(&np->timer);
957 np->timer.expires = RUN_AT(3 * HZ);
958 np->timer.data = (unsigned long) dev;
959 np->timer.function = &netdev_timer;
962 add_timer(&np->timer);
964 init_timer(&np->reset_timer);
965 np->reset_timer.data = (unsigned long) dev;
966 np->reset_timer.function = &reset_timer;
967 np->reset_timer_armed = 0;
973 static void getlinkstatus(struct net_device *dev)
974 /* function: Routine will read MII Status Register to get link status. */
975 /* input : dev... pointer to the adapter block. */
978 struct netdev_private *np = dev->priv;
979 unsigned int i, DelayTime = 0x1000;
983 if (np->PHYType == MysonPHY) {
984 for (i = 0; i < DelayTime; ++i) {
985 if (readl(dev->base_addr + BMCRSR) & LinkIsUp2) {
992 for (i = 0; i < DelayTime; ++i) {
993 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
1003 static void getlinktype(struct net_device *dev)
1005 struct netdev_private *np = dev->priv;
1007 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
1008 if (readl(dev->base_addr + TCRRCR) & CR_R_FD)
1009 np->duplexmode = 2; /* full duplex */
1011 np->duplexmode = 1; /* half duplex */
1012 if (readl(dev->base_addr + TCRRCR) & CR_R_PS10)
1013 np->line_speed = 1; /* 10M */
1015 np->line_speed = 2; /* 100M */
1017 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
1020 data = mdio_read(dev, np->phys[0], MIIRegister18);
1021 if (data & SPD_DET_100)
1022 np->line_speed = 2; /* 100M */
1024 np->line_speed = 1; /* 10M */
1025 if (data & DPLX_DET_FULL)
1026 np->duplexmode = 2; /* full duplex mode */
1028 np->duplexmode = 1; /* half duplex mode */
1029 } else if (np->PHYType == AhdocPHY) {
1032 data = mdio_read(dev, np->phys[0], DiagnosticReg);
1033 if (data & Speed_100)
1034 np->line_speed = 2; /* 100M */
1036 np->line_speed = 1; /* 10M */
1037 if (data & DPLX_FULL)
1038 np->duplexmode = 2; /* full duplex mode */
1040 np->duplexmode = 1; /* half duplex mode */
1042 /* 89/6/13 add, (begin) */
1043 else if (np->PHYType == MarvellPHY) {
1046 data = mdio_read(dev, np->phys[0], SpecificReg);
1047 if (data & Full_Duplex)
1048 np->duplexmode = 2; /* full duplex mode */
1050 np->duplexmode = 1; /* half duplex mode */
1052 if (data == Speed_1000M)
1053 np->line_speed = 3; /* 1000M */
1054 else if (data == Speed_100M)
1055 np->line_speed = 2; /* 100M */
1057 np->line_speed = 1; /* 10M */
1059 /* 89/6/13 add, (end) */
1060 /* 89/7/27 add, (begin) */
1061 else if (np->PHYType == Myson981) {
1064 data = mdio_read(dev, np->phys[0], StatusRegister);
1066 if (data & SPEED100)
1071 if (data & FULLMODE)
1076 /* 89/7/27 add, (end) */
1078 else if (np->PHYType == LevelOnePHY) {
1081 data = mdio_read(dev, np->phys[0], SpecificReg);
1082 if (data & LXT1000_Full)
1083 np->duplexmode = 2; /* full duplex mode */
1085 np->duplexmode = 1; /* half duplex mode */
1087 if (data == LXT1000_1000M)
1088 np->line_speed = 3; /* 1000M */
1089 else if (data == LXT1000_100M)
1090 np->line_speed = 2; /* 100M */
1092 np->line_speed = 1; /* 10M */
1094 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1095 if (np->line_speed == 1)
1096 np->crvalue |= CR_W_PS10;
1097 else if (np->line_speed == 3)
1098 np->crvalue |= CR_W_PS1000;
1099 if (np->duplexmode == 2)
1100 np->crvalue |= CR_W_FD;
1105 /* Take lock before calling this */
1106 static void allocate_rx_buffers(struct net_device *dev)
1108 struct netdev_private *np = dev->priv;
1110 /* allocate skb for rx buffers */
1111 while (np->really_rx_count != RX_RING_SIZE) {
1112 struct sk_buff *skb;
1114 skb = dev_alloc_skb(np->rx_buf_sz);
1116 break; /* Better luck next round. */
1118 while (np->lack_rxbuf->skbuff)
1119 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1121 skb->dev = dev; /* Mark as being used by this device. */
1122 np->lack_rxbuf->skbuff = skb;
1123 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->tail,
1124 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1125 np->lack_rxbuf->status = RXOWN;
1126 ++np->really_rx_count;
1131 static void netdev_timer(unsigned long data)
1133 struct net_device *dev = (struct net_device *) data;
1134 struct netdev_private *np = dev->priv;
1135 long ioaddr = dev->base_addr;
1136 int old_crvalue = np->crvalue;
1137 unsigned int old_linkok = np->linkok;
1138 unsigned long flags;
1141 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1142 "config %8.8x.\n", dev->name, readl(ioaddr + ISR),
1143 readl(ioaddr + TCRRCR));
1145 spin_lock_irqsave(&np->lock, flags);
1147 if (np->flags == HAS_MII_XCVR) {
1149 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1151 if (np->crvalue != old_crvalue) {
1152 stop_nic_rxtx(ioaddr, np->crvalue);
1153 writel(np->crvalue, ioaddr + TCRRCR);
1158 allocate_rx_buffers(dev);
1160 spin_unlock_irqrestore(&np->lock, flags);
1162 np->timer.expires = RUN_AT(10 * HZ);
1163 add_timer(&np->timer);
1167 /* Take lock before calling */
1168 /* Reset chip and disable rx, tx and interrupts */
1169 static void reset_and_disable_rxtx(struct net_device *dev)
1171 long ioaddr = dev->base_addr;
1174 /* Reset the chip's Tx and Rx processes. */
1175 stop_nic_rxtx(ioaddr, 0);
1177 /* Disable interrupts by clearing the interrupt mask. */
1178 writel(0, ioaddr + IMR);
1180 /* Reset the chip to erase previous misconfiguration. */
1181 writel(0x00000001, ioaddr + BCR);
1183 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1184 We surely wait too long (address+data phase). Who cares? */
1186 readl(ioaddr + BCR);
1192 /* Take lock before calling */
1193 /* Restore chip after reset */
1194 static void enable_rxtx(struct net_device *dev)
1196 struct netdev_private *np = dev->priv;
1197 long ioaddr = dev->base_addr;
1199 reset_rx_descriptors(dev);
1201 writel(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1203 writel(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1206 writel(np->bcrvalue, ioaddr + BCR);
1208 writel(0, ioaddr + RXPDR);
1209 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1211 /* Clear and Enable interrupts by setting the interrupt mask. */
1212 writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1213 writel(np->imrvalue, ioaddr + IMR);
1215 writel(0, ioaddr + TXPDR);
1219 static void reset_timer(unsigned long data)
1221 struct net_device *dev = (struct net_device *) data;
1222 struct netdev_private *np = dev->priv;
1223 unsigned long flags;
1225 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1227 spin_lock_irqsave(&np->lock, flags);
1228 np->crvalue = np->crvalue_sv;
1229 np->imrvalue = np->imrvalue_sv;
1231 reset_and_disable_rxtx(dev);
1232 /* works for me without this:
1233 reset_tx_descriptors(dev); */
1235 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1237 np->reset_timer_armed = 0;
1239 spin_unlock_irqrestore(&np->lock, flags);
1243 static void tx_timeout(struct net_device *dev)
1245 struct netdev_private *np = dev->priv;
1246 long ioaddr = dev->base_addr;
1247 unsigned long flags;
1250 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
1251 " resetting...\n", dev->name, readl(ioaddr + ISR));
1254 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1255 for (i = 0; i < RX_RING_SIZE; i++)
1256 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1257 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1258 for (i = 0; i < TX_RING_SIZE; i++)
1259 printk(" %4.4x", np->tx_ring[i].status);
1263 spin_lock_irqsave(&np->lock, flags);
1265 reset_and_disable_rxtx(dev);
1266 reset_tx_descriptors(dev);
1269 spin_unlock_irqrestore(&np->lock, flags);
1271 dev->trans_start = jiffies;
1272 np->stats.tx_errors++;
1273 netif_wake_queue(dev); /* or .._start_.. ?? */
1277 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1278 static void init_ring(struct net_device *dev)
1280 struct netdev_private *np = dev->priv;
1283 /* initialize rx variables */
1284 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1285 np->cur_rx = &np->rx_ring[0];
1286 np->lack_rxbuf = np->rx_ring;
1287 np->really_rx_count = 0;
1289 /* initial rx descriptors. */
1290 for (i = 0; i < RX_RING_SIZE; i++) {
1291 np->rx_ring[i].status = 0;
1292 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1293 np->rx_ring[i].next_desc = np->rx_ring_dma +
1294 (i + 1)*sizeof(struct fealnx_desc);
1295 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1296 np->rx_ring[i].skbuff = NULL;
1299 /* for the last rx descriptor */
1300 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1301 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1303 /* allocate skb for rx buffers */
1304 for (i = 0; i < RX_RING_SIZE; i++) {
1305 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1308 np->lack_rxbuf = &np->rx_ring[i];
1312 ++np->really_rx_count;
1313 np->rx_ring[i].skbuff = skb;
1314 skb->dev = dev; /* Mark as being used by this device. */
1315 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->tail,
1316 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1317 np->rx_ring[i].status = RXOWN;
1318 np->rx_ring[i].control |= RXIC;
1321 /* initialize tx variables */
1322 np->cur_tx = &np->tx_ring[0];
1323 np->cur_tx_copy = &np->tx_ring[0];
1324 np->really_tx_count = 0;
1325 np->free_tx_count = TX_RING_SIZE;
1327 for (i = 0; i < TX_RING_SIZE; i++) {
1328 np->tx_ring[i].status = 0;
1329 /* do we need np->tx_ring[i].control = XXX; ?? */
1330 np->tx_ring[i].next_desc = np->tx_ring_dma +
1331 (i + 1)*sizeof(struct fealnx_desc);
1332 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1333 np->tx_ring[i].skbuff = NULL;
1336 /* for the last tx descriptor */
1337 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1338 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1342 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1344 struct netdev_private *np = dev->priv;
1345 unsigned long flags;
1347 spin_lock_irqsave(&np->lock, flags);
1349 np->cur_tx_copy->skbuff = skb;
1353 #if defined(one_buffer)
1354 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1355 skb->len, PCI_DMA_TODEVICE);
1356 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1357 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1358 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1360 if (np->pci_dev->device == 0x891)
1361 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1362 np->cur_tx_copy->status = TXOWN;
1363 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1364 --np->free_tx_count;
1365 #elif defined(two_buffer)
1366 if (skb->len > BPT) {
1367 struct fealnx_desc *next;
1369 /* for the first descriptor */
1370 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1371 BPT, PCI_DMA_TODEVICE);
1372 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1373 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1374 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1376 /* for the last descriptor */
1377 next = np->cur_tx_copy->next_desc_logical;
1379 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1380 next->control |= (skb->len << PKTSShift); /* pkt size */
1381 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1383 if (np->pci_dev->device == 0x891)
1384 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1385 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1386 skb->len - BPT, PCI_DMA_TODEVICE);
1388 next->status = TXOWN;
1389 np->cur_tx_copy->status = TXOWN;
1391 np->cur_tx_copy = next->next_desc_logical;
1392 np->free_tx_count -= 2;
1394 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1395 skb->len, PCI_DMA_TODEVICE);
1396 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1397 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1398 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1400 if (np->pci_dev->device == 0x891)
1401 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1402 np->cur_tx_copy->status = TXOWN;
1403 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1404 --np->free_tx_count;
1408 if (np->free_tx_count < 2)
1409 netif_stop_queue(dev);
1410 ++np->really_tx_count;
1411 writel(0, dev->base_addr + TXPDR);
1412 dev->trans_start = jiffies;
1414 spin_unlock_irqrestore(&np->lock, flags);
1419 /* Take lock before calling */
1420 /* Chip probably hosed tx ring. Clean up. */
1421 static void reset_tx_descriptors(struct net_device *dev)
1423 struct netdev_private *np = dev->priv;
1424 struct fealnx_desc *cur;
1427 /* initialize tx variables */
1428 np->cur_tx = &np->tx_ring[0];
1429 np->cur_tx_copy = &np->tx_ring[0];
1430 np->really_tx_count = 0;
1431 np->free_tx_count = TX_RING_SIZE;
1433 for (i = 0; i < TX_RING_SIZE; i++) {
1434 cur = &np->tx_ring[i];
1436 pci_unmap_single(np->pci_dev, cur->buffer,
1437 cur->skbuff->len, PCI_DMA_TODEVICE);
1438 dev_kfree_skb(cur->skbuff);
1439 /* or dev_kfree_skb_irq(cur->skbuff); ? */
1443 cur->control = 0; /* needed? */
1444 /* probably not needed. We do it for purely paranoid reasons */
1445 cur->next_desc = np->tx_ring_dma +
1446 (i + 1)*sizeof(struct fealnx_desc);
1447 cur->next_desc_logical = &np->tx_ring[i + 1];
1449 /* for the last tx descriptor */
1450 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1451 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1455 /* Take lock and stop rx before calling this */
1456 static void reset_rx_descriptors(struct net_device *dev)
1458 struct netdev_private *np = dev->priv;
1459 struct fealnx_desc *cur = np->cur_rx;
1462 allocate_rx_buffers(dev);
1464 for (i = 0; i < RX_RING_SIZE; i++) {
1466 cur->status = RXOWN;
1467 cur = cur->next_desc_logical;
1470 writel(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1471 dev->base_addr + RXLBA);
1475 /* The interrupt handler does all of the Rx thread work and cleans up
1476 after the Tx thread. */
1477 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1479 struct net_device *dev = (struct net_device *) dev_instance;
1480 struct netdev_private *np = dev->priv;
1481 long ioaddr = dev->base_addr;
1482 long boguscnt = max_interrupt_work;
1483 unsigned int num_tx = 0;
1486 spin_lock(&np->lock);
1488 writel(0, ioaddr + IMR);
1491 u32 intr_status = readl(ioaddr + ISR);
1493 /* Acknowledge all of the current interrupt sources ASAP. */
1494 writel(intr_status, ioaddr + ISR);
1497 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1500 if (!(intr_status & np->imrvalue))
1507 // if (intr_status & FBE)
1508 // { /* fatal error */
1509 // stop_nic_tx(ioaddr, 0);
1510 // stop_nic_rx(ioaddr, 0);
1514 if (intr_status & TUNF)
1515 writel(0, ioaddr + TXPDR);
1517 if (intr_status & CNTOVF) {
1519 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1522 np->stats.rx_crc_errors +=
1523 (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1526 if (intr_status & (RI | RBU)) {
1527 if (intr_status & RI)
1530 stop_nic_rx(ioaddr, np->crvalue);
1531 reset_rx_descriptors(dev);
1532 writel(np->crvalue, ioaddr + TCRRCR);
1536 while (np->really_tx_count) {
1537 long tx_status = np->cur_tx->status;
1538 long tx_control = np->cur_tx->control;
1540 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1541 struct fealnx_desc *next;
1543 next = np->cur_tx->next_desc_logical;
1544 tx_status = next->status;
1545 tx_control = next->control;
1548 if (tx_status & TXOWN)
1551 if (!(np->crvalue & CR_W_ENH)) {
1552 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1553 np->stats.tx_errors++;
1555 np->stats.tx_aborted_errors++;
1556 if (tx_status & CSL)
1557 np->stats.tx_carrier_errors++;
1559 np->stats.tx_window_errors++;
1560 if (tx_status & UDF)
1561 np->stats.tx_fifo_errors++;
1562 if ((tx_status & HF) && np->mii.full_duplex == 0)
1563 np->stats.tx_heartbeat_errors++;
1566 np->stats.tx_bytes +=
1567 ((tx_control & PKTSMask) >> PKTSShift);
1569 np->stats.collisions +=
1570 ((tx_status & NCRMask) >> NCRShift);
1571 np->stats.tx_packets++;
1574 np->stats.tx_bytes +=
1575 ((tx_control & PKTSMask) >> PKTSShift);
1576 np->stats.tx_packets++;
1579 /* Free the original skb. */
1580 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1581 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1582 dev_kfree_skb_irq(np->cur_tx->skbuff);
1583 np->cur_tx->skbuff = NULL;
1584 --np->really_tx_count;
1585 if (np->cur_tx->control & TXLD) {
1586 np->cur_tx = np->cur_tx->next_desc_logical;
1587 ++np->free_tx_count;
1589 np->cur_tx = np->cur_tx->next_desc_logical;
1590 np->cur_tx = np->cur_tx->next_desc_logical;
1591 np->free_tx_count += 2;
1594 } /* end of for loop */
1596 if (num_tx && np->free_tx_count >= 2)
1597 netif_wake_queue(dev);
1599 /* read transmit status for enhanced mode only */
1600 if (np->crvalue & CR_W_ENH) {
1603 data = readl(ioaddr + TSR);
1604 np->stats.tx_errors += (data & 0xff000000) >> 24;
1605 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1606 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1607 np->stats.collisions += (data & 0x0000ffff);
1610 if (--boguscnt < 0) {
1611 printk(KERN_WARNING "%s: Too much work at interrupt, "
1612 "status=0x%4.4x.\n", dev->name, intr_status);
1613 if (!np->reset_timer_armed) {
1614 np->reset_timer_armed = 1;
1615 np->reset_timer.expires = RUN_AT(HZ/2);
1616 add_timer(&np->reset_timer);
1617 stop_nic_rxtx(ioaddr, 0);
1618 netif_stop_queue(dev);
1619 /* or netif_tx_disable(dev); ?? */
1620 /* Prevent other paths from enabling tx,rx,intrs */
1621 np->crvalue_sv = np->crvalue;
1622 np->imrvalue_sv = np->imrvalue;
1623 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1631 /* read the tally counters */
1633 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1636 np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1639 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1640 dev->name, readl(ioaddr + ISR));
1642 writel(np->imrvalue, ioaddr + IMR);
1644 spin_unlock(&np->lock);
1646 return IRQ_RETVAL(handled);
1650 /* This routine is logically part of the interrupt handler, but separated
1651 for clarity and better register allocation. */
1652 static int netdev_rx(struct net_device *dev)
1654 struct netdev_private *np = dev->priv;
1655 long ioaddr = dev->base_addr;
1657 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1658 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1659 s32 rx_status = np->cur_rx->status;
1661 if (np->really_rx_count == 0)
1665 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1667 if ((!((rx_status & RXFSD) && (rx_status & RXLSD)))
1668 || (rx_status & ErrorSummary)) {
1669 if (rx_status & ErrorSummary) { /* there was a fatal error */
1672 "%s: Receive error, Rx status %8.8x.\n",
1673 dev->name, rx_status);
1675 np->stats.rx_errors++; /* end of a packet. */
1676 if (rx_status & (LONG | RUNT))
1677 np->stats.rx_length_errors++;
1678 if (rx_status & RXER)
1679 np->stats.rx_frame_errors++;
1680 if (rx_status & CRC)
1681 np->stats.rx_crc_errors++;
1683 int need_to_reset = 0;
1686 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1687 struct fealnx_desc *cur;
1689 /* check this packet is received completely? */
1691 while (desno <= np->really_rx_count) {
1693 if ((!(cur->status & RXOWN))
1694 && (cur->status & RXLSD))
1696 /* goto next rx descriptor */
1697 cur = cur->next_desc_logical;
1699 if (desno > np->really_rx_count)
1701 } else /* RXLSD did not find, something error */
1704 if (need_to_reset == 0) {
1707 np->stats.rx_length_errors++;
1709 /* free all rx descriptors related this long pkt */
1710 for (i = 0; i < desno; ++i) {
1711 if (!np->cur_rx->skbuff) {
1713 "%s: I'm scared\n", dev->name);
1716 np->cur_rx->status = RXOWN;
1717 np->cur_rx = np->cur_rx->next_desc_logical;
1720 } else { /* rx error, need to reset this chip */
1721 stop_nic_rx(ioaddr, np->crvalue);
1722 reset_rx_descriptors(dev);
1723 writel(np->crvalue, ioaddr + TCRRCR);
1725 break; /* exit the while loop */
1727 } else { /* this received pkt is ok */
1729 struct sk_buff *skb;
1730 /* Omit the four octet CRC from the length. */
1731 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1733 #ifndef final_version
1735 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1736 " status %x.\n", pkt_len, rx_status);
1739 /* Check if the packet is long enough to accept without copying
1740 to a minimally-sized skbuff. */
1741 if (pkt_len < rx_copybreak &&
1742 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1744 skb_reserve(skb, 2); /* 16 byte align the IP header */
1745 pci_dma_sync_single_for_cpu(np->pci_dev,
1748 PCI_DMA_FROMDEVICE);
1749 /* Call copy + cksum if available. */
1751 #if ! defined(__alpha__)
1752 eth_copy_and_sum(skb,
1753 np->cur_rx->skbuff->tail, pkt_len, 0);
1754 skb_put(skb, pkt_len);
1756 memcpy(skb_put(skb, pkt_len),
1757 np->cur_rx->skbuff->tail, pkt_len);
1759 pci_dma_sync_single_for_device(np->pci_dev,
1762 PCI_DMA_FROMDEVICE);
1764 pci_unmap_single(np->pci_dev,
1767 PCI_DMA_FROMDEVICE);
1768 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1769 np->cur_rx->skbuff = NULL;
1770 --np->really_rx_count;
1772 skb->protocol = eth_type_trans(skb, dev);
1774 dev->last_rx = jiffies;
1775 np->stats.rx_packets++;
1776 np->stats.rx_bytes += pkt_len;
1779 np->cur_rx = np->cur_rx->next_desc_logical;
1780 } /* end of while loop */
1782 /* allocate skb for rx buffers */
1783 allocate_rx_buffers(dev);
1789 static struct net_device_stats *get_stats(struct net_device *dev)
1791 long ioaddr = dev->base_addr;
1792 struct netdev_private *np = dev->priv;
1794 /* The chip only need report frame silently dropped. */
1795 if (netif_running(dev)) {
1796 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1797 np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1804 /* for dev->set_multicast_list */
1805 static void set_rx_mode(struct net_device *dev)
1807 spinlock_t *lp = &((struct netdev_private *)dev->priv)->lock;
1808 unsigned long flags;
1809 spin_lock_irqsave(lp, flags);
1811 spin_unlock_irqrestore(lp, flags);
1815 /* Take lock before calling */
1816 static void __set_rx_mode(struct net_device *dev)
1818 struct netdev_private *np = dev->priv;
1819 long ioaddr = dev->base_addr;
1820 u32 mc_filter[2]; /* Multicast hash filter */
1823 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1824 /* Unconditionally log net taps. */
1825 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1826 memset(mc_filter, 0xff, sizeof(mc_filter));
1827 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1828 } else if ((dev->mc_count > multicast_filter_limit)
1829 || (dev->flags & IFF_ALLMULTI)) {
1830 /* Too many to match, or accept all multicasts. */
1831 memset(mc_filter, 0xff, sizeof(mc_filter));
1832 rx_mode = CR_W_AB | CR_W_AM;
1834 struct dev_mc_list *mclist;
1837 memset(mc_filter, 0, sizeof(mc_filter));
1838 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1839 i++, mclist = mclist->next) {
1841 bit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1842 mc_filter[bit >> 5] |= (1 << bit);
1844 rx_mode = CR_W_AB | CR_W_AM;
1847 stop_nic_rxtx(ioaddr, np->crvalue);
1849 writel(mc_filter[0], ioaddr + MAR0);
1850 writel(mc_filter[1], ioaddr + MAR1);
1851 np->crvalue &= ~CR_W_RXMODEMASK;
1852 np->crvalue |= rx_mode;
1853 writel(np->crvalue, ioaddr + TCRRCR);
1856 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1858 struct netdev_private *np = dev->priv;
1860 strcpy(info->driver, DRV_NAME);
1861 strcpy(info->version, DRV_VERSION);
1862 strcpy(info->bus_info, pci_name(np->pci_dev));
1865 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1867 struct netdev_private *np = dev->priv;
1870 spin_lock_irq(&np->lock);
1871 rc = mii_ethtool_gset(&np->mii, cmd);
1872 spin_unlock_irq(&np->lock);
1877 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1879 struct netdev_private *np = dev->priv;
1882 spin_lock_irq(&np->lock);
1883 rc = mii_ethtool_sset(&np->mii, cmd);
1884 spin_unlock_irq(&np->lock);
1889 static int netdev_nway_reset(struct net_device *dev)
1891 struct netdev_private *np = dev->priv;
1892 return mii_nway_restart(&np->mii);
1895 static u32 netdev_get_link(struct net_device *dev)
1897 struct netdev_private *np = dev->priv;
1898 return mii_link_ok(&np->mii);
1901 static u32 netdev_get_msglevel(struct net_device *dev)
1906 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1911 static struct ethtool_ops netdev_ethtool_ops = {
1912 .get_drvinfo = netdev_get_drvinfo,
1913 .get_settings = netdev_get_settings,
1914 .set_settings = netdev_set_settings,
1915 .nway_reset = netdev_nway_reset,
1916 .get_link = netdev_get_link,
1917 .get_msglevel = netdev_get_msglevel,
1918 .set_msglevel = netdev_set_msglevel,
1919 .get_sg = ethtool_op_get_sg,
1920 .get_tx_csum = ethtool_op_get_tx_csum,
1923 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1925 struct netdev_private *np = dev->priv;
1928 if (!netif_running(dev))
1931 spin_lock_irq(&np->lock);
1932 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1933 spin_unlock_irq(&np->lock);
1939 static int netdev_close(struct net_device *dev)
1941 long ioaddr = dev->base_addr;
1942 struct netdev_private *np = dev->priv;
1945 netif_stop_queue(dev);
1947 /* Disable interrupts by clearing the interrupt mask. */
1948 writel(0x0000, ioaddr + IMR);
1950 /* Stop the chip's Tx and Rx processes. */
1951 stop_nic_rxtx(ioaddr, 0);
1953 del_timer_sync(&np->timer);
1954 del_timer_sync(&np->reset_timer);
1956 free_irq(dev->irq, dev);
1958 /* Free all the skbuffs in the Rx queue. */
1959 for (i = 0; i < RX_RING_SIZE; i++) {
1960 struct sk_buff *skb = np->rx_ring[i].skbuff;
1962 np->rx_ring[i].status = 0;
1964 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1965 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1967 np->rx_ring[i].skbuff = NULL;
1971 for (i = 0; i < TX_RING_SIZE; i++) {
1972 struct sk_buff *skb = np->tx_ring[i].skbuff;
1975 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1976 skb->len, PCI_DMA_TODEVICE);
1978 np->tx_ring[i].skbuff = NULL;
1985 static struct pci_device_id fealnx_pci_tbl[] = {
1986 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1987 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1988 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1989 {} /* terminate list */
1991 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1994 static struct pci_driver fealnx_driver = {
1996 .id_table = fealnx_pci_tbl,
1997 .probe = fealnx_init_one,
1998 .remove = __devexit_p(fealnx_remove_one),
2001 static int __init fealnx_init(void)
2003 /* when a module, this is printed whether or not devices are found in probe */
2008 return pci_module_init(&fealnx_driver);
2011 static void __exit fealnx_exit(void)
2013 pci_unregister_driver(&fealnx_driver);
2016 module_init(fealnx_init);
2017 module_exit(fealnx_exit);