2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey. It's neither supported nor endorsed
7 * by NVIDIA Corp. Use at your own risk.
9 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
10 * trademarks of NVIDIA Corporation in the United States and other
13 * Copyright (C) 2003,4 Manfred Spraul
14 * Copyright (C) 2004 Andrew de Quincey (wol support)
15 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
16 * IRQ rate fixes, bigendian fixes, cleanups, verification)
17 * Copyright (c) 2004 NVIDIA Corporation
19 * This program is free software; you can redistribute it and/or modify
20 * it under the terms of the GNU General Public License as published by
21 * the Free Software Foundation; either version 2 of the License, or
22 * (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 * 0.01: 05 Oct 2003: First release that compiles without warnings.
35 * 0.02: 05 Oct 2003: Fix bug for nv_drain_tx: do not try to free NULL skbs.
36 * Check all PCI BARs for the register window.
37 * udelay added to mii_rw.
38 * 0.03: 06 Oct 2003: Initialize dev->irq.
39 * 0.04: 07 Oct 2003: Initialize np->lock, reduce handled irqs, add printks.
40 * 0.05: 09 Oct 2003: printk removed again, irq status print tx_timeout.
41 * 0.06: 10 Oct 2003: MAC Address read updated, pff flag generation updated,
43 * 0.07: 14 Oct 2003: Further irq mask updates.
44 * 0.08: 20 Oct 2003: rx_desc.Length initialization added, nv_alloc_rx refill
45 * added into irq handler, NULL check for drain_ring.
46 * 0.09: 20 Oct 2003: Basic link speed irq implementation. Only handle the
47 * requested interrupt sources.
48 * 0.10: 20 Oct 2003: First cleanup for release.
49 * 0.11: 21 Oct 2003: hexdump for tx added, rx buffer sizes increased.
50 * MAC Address init fix, set_multicast cleanup.
51 * 0.12: 23 Oct 2003: Cleanups for release.
52 * 0.13: 25 Oct 2003: Limit for concurrent tx packets increased to 10.
53 * Set link speed correctly. start rx before starting
54 * tx (nv_start_rx sets the link speed).
55 * 0.14: 25 Oct 2003: Nic dependant irq mask.
56 * 0.15: 08 Nov 2003: fix smp deadlock with set_multicast_list during
58 * 0.16: 15 Nov 2003: include file cleanup for ppc64, rx buffer size
59 * increased to 1628 bytes.
60 * 0.17: 16 Nov 2003: undo rx buffer size increase. Substract 1 from
62 * 0.18: 17 Nov 2003: fix oops due to late initialization of dev_stats
63 * 0.19: 29 Nov 2003: Handle RxNoBuf, detect & handle invalid mac
64 * addresses, really stop rx if already running
65 * in nv_start_rx, clean up a bit.
66 * 0.20: 07 Dec 2003: alloc fixes
67 * 0.21: 12 Jan 2004: additional alloc fix, nic polling fix.
68 * 0.22: 19 Jan 2004: reprogram timer to a sane rate, avoid lockup
70 * 0.23: 26 Jan 2004: various small cleanups
71 * 0.24: 27 Feb 2004: make driver even less anonymous in backtraces
72 * 0.25: 09 Mar 2004: wol support
73 * 0.26: 03 Jun 2004: netdriver specific annotation, sparse-related fixes
74 * 0.27: 19 Jun 2004: Gigabit support, new descriptor rings,
75 * added CK804/MCP04 device IDs, code fixes
76 * for registers, link status and other minor fixes.
77 * 0.28: 21 Jun 2004: Big cleanup, making driver mostly endian safe
80 * We suspect that on some hardware no TX done interrupts are generated.
81 * This means recovery from netif_stop_queue only happens if the hw timer
82 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
83 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
84 * If your hardware reliably generates tx done interrupts, then you can remove
85 * DEV_NEED_TIMERIRQ from the driver_data flags.
86 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
87 * superfluous timer interrupts from the nic.
89 #define FORCEDETH_VERSION "0.28"
90 #define DRV_NAME "forcedeth"
92 #include <linux/module.h>
93 #include <linux/types.h>
94 #include <linux/pci.h>
95 #include <linux/interrupt.h>
96 #include <linux/netdevice.h>
97 #include <linux/etherdevice.h>
98 #include <linux/delay.h>
99 #include <linux/spinlock.h>
100 #include <linux/ethtool.h>
101 #include <linux/timer.h>
102 #include <linux/skbuff.h>
103 #include <linux/mii.h>
104 #include <linux/random.h>
105 #include <linux/init.h>
109 #include <asm/uaccess.h>
110 #include <asm/system.h>
113 #define dprintk printk
115 #define dprintk(x...) do { } while (0)
123 #define DEV_NEED_LASTPACKET1 0x0001
124 #define DEV_IRQMASK_1 0x0002
125 #define DEV_IRQMASK_2 0x0004
126 #define DEV_NEED_TIMERIRQ 0x0008
129 NvRegIrqStatus = 0x000,
130 #define NVREG_IRQSTAT_MIIEVENT 0x040
131 #define NVREG_IRQSTAT_MASK 0x1ff
132 NvRegIrqMask = 0x004,
133 #define NVREG_IRQ_RX_ERROR 0x0001
134 #define NVREG_IRQ_RX 0x0002
135 #define NVREG_IRQ_RX_NOBUF 0x0004
136 #define NVREG_IRQ_TX_ERR 0x0008
137 #define NVREG_IRQ_TX2 0x0010
138 #define NVREG_IRQ_TIMER 0x0020
139 #define NVREG_IRQ_LINK 0x0040
140 #define NVREG_IRQ_TX1 0x0100
141 #define NVREG_IRQMASK_WANTED_1 0x005f
142 #define NVREG_IRQMASK_WANTED_2 0x0147
143 #define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
145 NvRegUnknownSetupReg6 = 0x008,
146 #define NVREG_UNKSETUP6_VAL 3
149 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
150 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
152 NvRegPollingInterval = 0x00c,
153 #define NVREG_POLL_DEFAULT 970
155 #define NVREG_MISC1_HD 0x02
156 #define NVREG_MISC1_FORCE 0x3b0f3c
158 NvRegTransmitterControl = 0x084,
159 #define NVREG_XMITCTL_START 0x01
160 NvRegTransmitterStatus = 0x088,
161 #define NVREG_XMITSTAT_BUSY 0x01
163 NvRegPacketFilterFlags = 0x8c,
164 #define NVREG_PFF_ALWAYS 0x7F0008
165 #define NVREG_PFF_PROMISC 0x80
166 #define NVREG_PFF_MYADDR 0x20
168 NvRegOffloadConfig = 0x90,
169 #define NVREG_OFFLOAD_HOMEPHY 0x601
170 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
171 NvRegReceiverControl = 0x094,
172 #define NVREG_RCVCTL_START 0x01
173 NvRegReceiverStatus = 0x98,
174 #define NVREG_RCVSTAT_BUSY 0x01
176 NvRegRandomSeed = 0x9c,
177 #define NVREG_RNDSEED_MASK 0x00ff
178 #define NVREG_RNDSEED_FORCE 0x7f00
179 #define NVREG_RNDSEED_FORCE2 0x2d00
180 #define NVREG_RNDSEED_FORCE3 0x7400
182 NvRegUnknownSetupReg1 = 0xA0,
183 #define NVREG_UNKSETUP1_VAL 0x16070f
184 NvRegUnknownSetupReg2 = 0xA4,
185 #define NVREG_UNKSETUP2_VAL 0x16
186 NvRegMacAddrA = 0xA8,
187 NvRegMacAddrB = 0xAC,
188 NvRegMulticastAddrA = 0xB0,
189 #define NVREG_MCASTADDRA_FORCE 0x01
190 NvRegMulticastAddrB = 0xB4,
191 NvRegMulticastMaskA = 0xB8,
192 NvRegMulticastMaskB = 0xBC,
194 NvRegPhyInterface = 0xC0,
195 #define PHY_RGMII 0x10000000
197 NvRegTxRingPhysAddr = 0x100,
198 NvRegRxRingPhysAddr = 0x104,
199 NvRegRingSizes = 0x108,
200 #define NVREG_RINGSZ_TXSHIFT 0
201 #define NVREG_RINGSZ_RXSHIFT 16
202 NvRegUnknownTransmitterReg = 0x10c,
203 NvRegLinkSpeed = 0x110,
204 #define NVREG_LINKSPEED_FORCE 0x10000
205 #define NVREG_LINKSPEED_10 1000
206 #define NVREG_LINKSPEED_100 100
207 #define NVREG_LINKSPEED_1000 50
208 NvRegUnknownSetupReg5 = 0x130,
209 #define NVREG_UNKSETUP5_BIT31 (1<<31)
210 NvRegUnknownSetupReg3 = 0x13c,
211 #define NVREG_UNKSETUP3_VAL1 0x200010
212 NvRegTxRxControl = 0x144,
213 #define NVREG_TXRXCTL_KICK 0x0001
214 #define NVREG_TXRXCTL_BIT1 0x0002
215 #define NVREG_TXRXCTL_BIT2 0x0004
216 #define NVREG_TXRXCTL_IDLE 0x0008
217 #define NVREG_TXRXCTL_RESET 0x0010
218 NvRegMIIStatus = 0x180,
219 #define NVREG_MIISTAT_ERROR 0x0001
220 #define NVREG_MIISTAT_LINKCHANGE 0x0008
221 #define NVREG_MIISTAT_MASK 0x000f
222 #define NVREG_MIISTAT_MASK2 0x000f
223 NvRegUnknownSetupReg4 = 0x184,
224 #define NVREG_UNKSETUP4_VAL 8
226 NvRegAdapterControl = 0x188,
227 #define NVREG_ADAPTCTL_START 0x02
228 #define NVREG_ADAPTCTL_LINKUP 0x04
229 #define NVREG_ADAPTCTL_PHYVALID 0x40000
230 #define NVREG_ADAPTCTL_RUNNING 0x100000
231 #define NVREG_ADAPTCTL_PHYSHIFT 24
232 NvRegMIISpeed = 0x18c,
233 #define NVREG_MIISPEED_BIT8 (1<<8)
234 #define NVREG_MIIDELAY 5
235 NvRegMIIControl = 0x190,
236 #define NVREG_MIICTL_INUSE 0x08000
237 #define NVREG_MIICTL_WRITE 0x00400
238 #define NVREG_MIICTL_ADDRSHIFT 5
239 NvRegMIIData = 0x194,
240 NvRegWakeUpFlags = 0x200,
241 #define NVREG_WAKEUPFLAGS_VAL 0x7770
242 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
243 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
244 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
245 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
246 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
247 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
248 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
249 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
250 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
251 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
253 NvRegPatternCRC = 0x204,
254 NvRegPatternMask = 0x208,
255 NvRegPowerCap = 0x268,
256 #define NVREG_POWERCAP_D3SUPP (1<<30)
257 #define NVREG_POWERCAP_D2SUPP (1<<26)
258 #define NVREG_POWERCAP_D1SUPP (1<<25)
259 NvRegPowerState = 0x26c,
260 #define NVREG_POWERSTATE_POWEREDUP 0x8000
261 #define NVREG_POWERSTATE_VALID 0x0100
262 #define NVREG_POWERSTATE_MASK 0x0003
263 #define NVREG_POWERSTATE_D0 0x0000
264 #define NVREG_POWERSTATE_D1 0x0001
265 #define NVREG_POWERSTATE_D2 0x0002
266 #define NVREG_POWERSTATE_D3 0x0003
269 /* Big endian: should work, but is untested */
275 #define FLAG_MASK_V1 0xffff0000
276 #define FLAG_MASK_V2 0xffffc000
277 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
278 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
280 #define NV_TX_LASTPACKET (1<<16)
281 #define NV_TX_RETRYERROR (1<<19)
282 #define NV_TX_LASTPACKET1 (1<<24)
283 #define NV_TX_DEFERRED (1<<26)
284 #define NV_TX_CARRIERLOST (1<<27)
285 #define NV_TX_LATECOLLISION (1<<28)
286 #define NV_TX_UNDERFLOW (1<<29)
287 #define NV_TX_ERROR (1<<30)
288 #define NV_TX_VALID (1<<31)
290 #define NV_TX2_LASTPACKET (1<<29)
291 #define NV_TX2_RETRYERROR (1<<18)
292 #define NV_TX2_LASTPACKET1 (1<<23)
293 #define NV_TX2_DEFERRED (1<<25)
294 #define NV_TX2_CARRIERLOST (1<<26)
295 #define NV_TX2_LATECOLLISION (1<<27)
296 #define NV_TX2_UNDERFLOW (1<<28)
297 /* error and valid are the same for both */
298 #define NV_TX2_ERROR (1<<30)
299 #define NV_TX2_VALID (1<<31)
301 #define NV_RX_DESCRIPTORVALID (1<<16)
302 #define NV_RX_MISSEDFRAME (1<<17)
303 #define NV_RX_SUBSTRACT1 (1<<18)
304 #define NV_RX_ERROR1 (1<<23)
305 #define NV_RX_ERROR2 (1<<24)
306 #define NV_RX_ERROR3 (1<<25)
307 #define NV_RX_ERROR4 (1<<26)
308 #define NV_RX_CRCERR (1<<27)
309 #define NV_RX_OVERFLOW (1<<28)
310 #define NV_RX_FRAMINGERR (1<<29)
311 #define NV_RX_ERROR (1<<30)
312 #define NV_RX_AVAIL (1<<31)
314 #define NV_RX2_DESCRIPTORVALID (1<<29)
315 #define NV_RX2_SUBSTRACT1 (1<<25)
316 #define NV_RX2_ERROR1 (1<<18)
317 #define NV_RX2_ERROR2 (1<<19)
318 #define NV_RX2_ERROR3 (1<<20)
319 #define NV_RX2_ERROR4 (1<<21)
320 #define NV_RX2_CRCERR (1<<22)
321 #define NV_RX2_OVERFLOW (1<<23)
322 #define NV_RX2_FRAMINGERR (1<<24)
323 /* error and avail are the same for both */
324 #define NV_RX2_ERROR (1<<30)
325 #define NV_RX2_AVAIL (1<<31)
327 /* Miscelaneous hardware related defines: */
328 #define NV_PCI_REGSZ 0x270
330 /* various timeout delays: all in usec */
331 #define NV_TXRX_RESET_DELAY 4
332 #define NV_TXSTOP_DELAY1 10
333 #define NV_TXSTOP_DELAY1MAX 500000
334 #define NV_TXSTOP_DELAY2 100
335 #define NV_RXSTOP_DELAY1 10
336 #define NV_RXSTOP_DELAY1MAX 500000
337 #define NV_RXSTOP_DELAY2 100
338 #define NV_SETUP5_DELAY 5
339 #define NV_SETUP5_DELAYMAX 50000
340 #define NV_POWERUP_DELAY 5
341 #define NV_POWERUP_DELAYMAX 5000
342 #define NV_MIIBUSY_DELAY 50
343 #define NV_MIIPHY_DELAY 10
344 #define NV_MIIPHY_DELAYMAX 10000
346 #define NV_WAKEUPPATTERNS 5
347 #define NV_WAKEUPMASKENTRIES 4
349 /* General driver defaults */
350 #define NV_WATCHDOG_TIMEO (5*HZ)
355 * If your nic mysteriously hangs then try to reduce the limits
356 * to 1/0: It might be required to set NV_TX_LASTPACKET in the
357 * last valid ring entry. But this would be impossible to
358 * implement - probably a disassembly error.
360 #define TX_LIMIT_STOP 63
361 #define TX_LIMIT_START 62
363 /* rx/tx mac addr + type + vlan + align + slack*/
364 #define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
365 /* even more slack */
366 #define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
368 #define OOM_REFILL (1+HZ/20)
369 #define POLL_WAIT (1+HZ/100)
371 #define DESC_VER_1 0x0
372 #define DESC_VER_2 0x02100
375 #define PHY_OUI_MARVELL 0x5043
376 #define PHY_OUI_CICADA 0x03f1
377 #define PHYID1_OUI_MASK 0x03ff
378 #define PHYID1_OUI_SHFT 6
379 #define PHYID2_OUI_MASK 0xfc00
380 #define PHYID2_OUI_SHFT 10
381 #define PHY_INIT1 0x0f000
382 #define PHY_INIT2 0x0e00
383 #define PHY_INIT3 0x01000
384 #define PHY_INIT4 0x0200
385 #define PHY_INIT5 0x0004
386 #define PHY_INIT6 0x02000
387 #define PHY_GIGABIT 0x0100
389 #define PHY_TIMEOUT 0x1
390 #define PHY_ERROR 0x2
394 #define PHY_HALF 0x100
396 /* FIXME: MII defines that should be added to <linux/mii.h> */
397 #define MII_1000BT_CR 0x09
398 #define MII_1000BT_SR 0x0a
399 #define ADVERTISE_1000FULL 0x0200
400 #define ADVERTISE_1000HALF 0x0100
401 #define LPA_1000FULL 0x0800
402 #define LPA_1000HALF 0x0400
407 * All hardware access under dev->priv->lock, except the performance
409 * - rx is (pseudo-) lockless: it relies on the single-threading provided
410 * by the arch code for interrupts.
411 * - tx setup is lockless: it relies on dev->xmit_lock. Actual submission
412 * needs dev->priv->lock :-(
413 * - set_multicast_list: preparation lockless, relies on dev->xmit_lock.
416 /* in dev: base, irq */
421 * Locking: spin_lock(&np->lock); */
422 struct net_device_stats stats;
428 unsigned int phy_oui;
431 /* General data: RO fields */
432 dma_addr_t ring_addr;
433 struct pci_dev *pci_dev;
438 /* rx specific fields.
439 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
441 struct ring_desc *rx_ring;
442 unsigned int cur_rx, refill_rx;
443 struct sk_buff *rx_skbuff[RX_RING];
444 dma_addr_t rx_dma[RX_RING];
445 unsigned int rx_buf_sz;
446 struct timer_list oom_kick;
447 struct timer_list nic_poll;
450 * tx specific fields.
452 struct ring_desc *tx_ring;
453 unsigned int next_tx, nic_tx;
454 struct sk_buff *tx_skbuff[TX_RING];
455 dma_addr_t tx_dma[TX_RING];
460 * Maximum number of loops until we assume that a bit in the irq mask
461 * is stuck. Overridable with module param.
463 static int max_interrupt_work = 5;
465 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
467 return (struct fe_priv *) dev->priv;
470 static inline u8 *get_hwbase(struct net_device *dev)
472 return (u8 *) dev->base_addr;
475 static inline void pci_push(u8 * base)
477 /* force out pending posted writes */
481 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
483 return le32_to_cpu(prd->FlagLen)
484 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
487 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
488 int delay, int delaymax, const char *msg)
490 u8 *base = get_hwbase(dev);
501 } while ((readl(base + offset) & mask) != target);
505 #define MII_READ (-1)
506 /* mii_rw: read/write a register on the PHY.
508 * Caller must guarantee serialization
510 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
512 u8 *base = get_hwbase(dev);
516 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
518 reg = readl(base + NvRegMIIControl);
519 if (reg & NVREG_MIICTL_INUSE) {
520 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
521 udelay(NV_MIIBUSY_DELAY);
524 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
525 if (value != MII_READ) {
526 writel(value, base + NvRegMIIData);
527 reg |= NVREG_MIICTL_WRITE;
529 writel(reg, base + NvRegMIIControl);
531 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
532 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
533 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d timed out.\n",
534 dev->name, miireg, addr);
536 } else if (value != MII_READ) {
537 /* it was a write operation - fewer failures are detectable */
538 dprintk(KERN_DEBUG "%s: mii_rw wrote 0x%x to reg %d at PHY %d\n",
539 dev->name, value, miireg, addr);
541 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
542 dprintk(KERN_DEBUG "%s: mii_rw of reg %d at PHY %d failed.\n",
543 dev->name, miireg, addr);
546 retval = readl(base + NvRegMIIData);
547 dprintk(KERN_DEBUG "%s: mii_rw read from reg %d at PHY %d: 0x%x.\n",
548 dev->name, miireg, addr, retval);
554 static int phy_reset(struct net_device *dev)
556 struct fe_priv *np = get_nvpriv(dev);
558 unsigned int tries = 0;
560 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
561 miicontrol |= BMCR_RESET;
562 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol)) {
569 /* must wait till reset is deasserted */
570 while (miicontrol & BMCR_RESET) {
572 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
573 /* FIXME: 100 tries seem excessive */
580 static int phy_init(struct net_device *dev)
582 struct fe_priv *np = get_nvpriv(dev);
583 u8 *base = get_hwbase(dev);
584 u32 phyinterface, phy_reserved, mii_status, mii_control, mii_control_1000,reg;
586 /* set advertise register */
587 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
588 reg |= (ADVERTISE_10HALF|ADVERTISE_10FULL|ADVERTISE_100HALF|ADVERTISE_100FULL|0x800|0x400);
589 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
590 printk(KERN_INFO "%s: phy write to advertise failed.\n", pci_name(np->pci_dev));
594 /* get phy interface type */
595 phyinterface = readl(base + NvRegPhyInterface);
597 /* see if gigabit phy */
598 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
599 if (mii_status & PHY_GIGABIT) {
600 np->gigabit = PHY_GIGABIT;
601 mii_control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
602 mii_control_1000 &= ~ADVERTISE_1000HALF;
603 if (phyinterface & PHY_RGMII)
604 mii_control_1000 |= ADVERTISE_1000FULL;
606 mii_control_1000 &= ~ADVERTISE_1000FULL;
608 if (mii_rw(dev, np->phyaddr, MII_1000BT_CR, mii_control_1000)) {
609 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
617 if (phy_reset(dev)) {
618 printk(KERN_INFO "%s: phy reset failed\n", pci_name(np->pci_dev));
622 /* phy vendor specific configuration */
623 if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII) ) {
624 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
625 phy_reserved &= ~(PHY_INIT1 | PHY_INIT2);
626 phy_reserved |= (PHY_INIT3 | PHY_INIT4);
627 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved)) {
628 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
631 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
632 phy_reserved |= PHY_INIT5;
633 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved)) {
634 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
638 if (np->phy_oui == PHY_OUI_CICADA) {
639 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
640 phy_reserved |= PHY_INIT6;
641 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved)) {
642 printk(KERN_INFO "%s: phy init failed.\n", pci_name(np->pci_dev));
647 /* restart auto negotiation */
648 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
649 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
650 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
657 static void nv_start_rx(struct net_device *dev)
659 struct fe_priv *np = get_nvpriv(dev);
660 u8 *base = get_hwbase(dev);
662 dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
663 /* Already running? Stop it. */
664 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
665 writel(0, base + NvRegReceiverControl);
668 writel(np->linkspeed, base + NvRegLinkSpeed);
670 writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
671 dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
672 dev->name, np->duplex, np->linkspeed);
676 static void nv_stop_rx(struct net_device *dev)
678 u8 *base = get_hwbase(dev);
680 dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
681 writel(0, base + NvRegReceiverControl);
682 reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
683 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
684 KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
686 udelay(NV_RXSTOP_DELAY2);
687 writel(0, base + NvRegLinkSpeed);
690 static void nv_start_tx(struct net_device *dev)
692 u8 *base = get_hwbase(dev);
694 dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
695 writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
699 static void nv_stop_tx(struct net_device *dev)
701 u8 *base = get_hwbase(dev);
703 dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
704 writel(0, base + NvRegTransmitterControl);
705 reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
706 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
707 KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
709 udelay(NV_TXSTOP_DELAY2);
710 writel(0, base + NvRegUnknownTransmitterReg);
713 static void nv_txrx_reset(struct net_device *dev)
715 struct fe_priv *np = get_nvpriv(dev);
716 u8 *base = get_hwbase(dev);
718 dprintk(KERN_DEBUG "%s: nv_txrx_reset\n", dev->name);
719 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->desc_ver, base + NvRegTxRxControl);
721 udelay(NV_TXRX_RESET_DELAY);
722 writel(NVREG_TXRXCTL_BIT2 | np->desc_ver, base + NvRegTxRxControl);
727 * nv_get_stats: dev->get_stats function
728 * Get latest stats value from the nic.
729 * Called with read_lock(&dev_base_lock) held for read -
730 * only synchronized against unregister_netdevice.
732 static struct net_device_stats *nv_get_stats(struct net_device *dev)
734 struct fe_priv *np = get_nvpriv(dev);
736 /* It seems that the nic always generates interrupts and doesn't
737 * accumulate errors internally. Thus the current values in np->stats
738 * are already up to date.
743 static int nv_ethtool_ioctl(struct net_device *dev, void __user *useraddr)
745 struct fe_priv *np = get_nvpriv(dev);
746 u8 *base = get_hwbase(dev);
749 if (copy_from_user(ðcmd, useraddr, sizeof (ethcmd)))
753 case ETHTOOL_GDRVINFO:
755 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
756 strcpy(info.driver, "forcedeth");
757 strcpy(info.version, FORCEDETH_VERSION);
758 strcpy(info.bus_info, pci_name(np->pci_dev));
759 if (copy_to_user(useraddr, &info, sizeof (info)))
765 struct ethtool_value edata = { ETHTOOL_GLINK };
767 edata.data = !!netif_carrier_ok(dev);
769 if (copy_to_user(useraddr, &edata, sizeof(edata)))
775 struct ethtool_wolinfo wolinfo;
776 memset(&wolinfo, 0, sizeof(wolinfo));
777 wolinfo.supported = WAKE_MAGIC;
779 spin_lock_irq(&np->lock);
781 wolinfo.wolopts = WAKE_MAGIC;
782 spin_unlock_irq(&np->lock);
784 if (copy_to_user(useraddr, &wolinfo, sizeof(wolinfo)))
790 struct ethtool_wolinfo wolinfo;
791 if (copy_from_user(&wolinfo, useraddr, sizeof(wolinfo)))
794 spin_lock_irq(&np->lock);
795 if (wolinfo.wolopts == 0) {
796 writel(0, base + NvRegWakeUpFlags);
799 if (wolinfo.wolopts & WAKE_MAGIC) {
800 writel(NVREG_WAKEUPFLAGS_ENABLE, base + NvRegWakeUpFlags);
803 spin_unlock_irq(&np->lock);
814 * nv_ioctl: dev->do_ioctl function
815 * Called with rtnl_lock held.
817 static int nv_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
821 return nv_ethtool_ioctl(dev, rq->ifr_data);
829 * nv_alloc_rx: fill rx ring entries.
830 * Return 1 if the allocations for the skbs failed and the
831 * rx engine is without Available descriptors
833 static int nv_alloc_rx(struct net_device *dev)
835 struct fe_priv *np = get_nvpriv(dev);
836 unsigned int refill_rx = np->refill_rx;
839 while (np->cur_rx != refill_rx) {
842 nr = refill_rx % RX_RING;
843 if (np->rx_skbuff[nr] == NULL) {
845 skb = dev_alloc_skb(RX_ALLOC_BUFSIZE);
850 np->rx_skbuff[nr] = skb;
852 skb = np->rx_skbuff[nr];
854 np->rx_dma[nr] = pci_map_single(np->pci_dev, skb->data, skb->len,
856 np->rx_ring[nr].PacketBuffer = cpu_to_le32(np->rx_dma[nr]);
858 np->rx_ring[nr].FlagLen = cpu_to_le32(RX_NIC_BUFSIZE | NV_RX_AVAIL);
859 dprintk(KERN_DEBUG "%s: nv_alloc_rx: Packet %d marked as Available\n",
860 dev->name, refill_rx);
863 np->refill_rx = refill_rx;
864 if (np->cur_rx - refill_rx == RX_RING)
869 static void nv_do_rx_refill(unsigned long data)
871 struct net_device *dev = (struct net_device *) data;
872 struct fe_priv *np = get_nvpriv(dev);
874 disable_irq(dev->irq);
875 if (nv_alloc_rx(dev)) {
876 spin_lock(&np->lock);
877 if (!np->in_shutdown)
878 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
879 spin_unlock(&np->lock);
881 enable_irq(dev->irq);
884 static int nv_init_ring(struct net_device *dev)
886 struct fe_priv *np = get_nvpriv(dev);
889 np->next_tx = np->nic_tx = 0;
890 for (i = 0; i < TX_RING; i++)
891 np->tx_ring[i].FlagLen = 0;
893 np->cur_rx = RX_RING;
895 for (i = 0; i < RX_RING; i++)
896 np->rx_ring[i].FlagLen = 0;
897 return nv_alloc_rx(dev);
900 static void nv_drain_tx(struct net_device *dev)
902 struct fe_priv *np = get_nvpriv(dev);
904 for (i = 0; i < TX_RING; i++) {
905 np->tx_ring[i].FlagLen = 0;
906 if (np->tx_skbuff[i]) {
907 pci_unmap_single(np->pci_dev, np->tx_dma[i],
908 np->tx_skbuff[i]->len,
910 dev_kfree_skb(np->tx_skbuff[i]);
911 np->tx_skbuff[i] = NULL;
912 np->stats.tx_dropped++;
917 static void nv_drain_rx(struct net_device *dev)
919 struct fe_priv *np = get_nvpriv(dev);
921 for (i = 0; i < RX_RING; i++) {
922 np->rx_ring[i].FlagLen = 0;
924 if (np->rx_skbuff[i]) {
925 pci_unmap_single(np->pci_dev, np->rx_dma[i],
926 np->rx_skbuff[i]->len,
928 dev_kfree_skb(np->rx_skbuff[i]);
929 np->rx_skbuff[i] = NULL;
934 static void drain_ring(struct net_device *dev)
941 * nv_start_xmit: dev->hard_start_xmit function
942 * Called with dev->xmit_lock held.
944 static int nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
946 struct fe_priv *np = get_nvpriv(dev);
947 int nr = np->next_tx % TX_RING;
949 np->tx_skbuff[nr] = skb;
950 np->tx_dma[nr] = pci_map_single(np->pci_dev, skb->data,skb->len,
953 np->tx_ring[nr].PacketBuffer = cpu_to_le32(np->tx_dma[nr]);
955 spin_lock_irq(&np->lock);
957 np->tx_ring[nr].FlagLen = cpu_to_le32( (skb->len-1) | np->tx_flags );
958 dprintk(KERN_DEBUG "%s: nv_start_xmit: packet packet %d queued for transmission.\n",
959 dev->name, np->next_tx);
962 for (j=0; j<64; j++) {
964 dprintk("\n%03x:", j);
965 dprintk(" %02x", ((unsigned char*)skb->data)[j]);
972 dev->trans_start = jiffies;
973 if (np->next_tx - np->nic_tx >= TX_LIMIT_STOP)
974 netif_stop_queue(dev);
975 spin_unlock_irq(&np->lock);
976 writel(NVREG_TXRXCTL_KICK|np->desc_ver, get_hwbase(dev) + NvRegTxRxControl);
977 pci_push(get_hwbase(dev));
982 * nv_tx_done: check for completed packets, release the skbs.
984 * Caller must own np->lock.
986 static void nv_tx_done(struct net_device *dev)
988 struct fe_priv *np = get_nvpriv(dev);
992 while (np->nic_tx != np->next_tx) {
993 i = np->nic_tx % TX_RING;
995 Flags = le32_to_cpu(np->tx_ring[i].FlagLen);
997 dprintk(KERN_DEBUG "%s: nv_tx_done: looking at packet %d, Flags 0x%x.\n",
998 dev->name, np->nic_tx, Flags);
999 if (Flags & NV_TX_VALID)
1001 if (np->desc_ver == DESC_VER_1) {
1002 if (Flags & (NV_TX_RETRYERROR|NV_TX_CARRIERLOST|NV_TX_LATECOLLISION|
1003 NV_TX_UNDERFLOW|NV_TX_ERROR)) {
1004 if (Flags & NV_TX_UNDERFLOW)
1005 np->stats.tx_fifo_errors++;
1006 if (Flags & NV_TX_CARRIERLOST)
1007 np->stats.tx_carrier_errors++;
1008 np->stats.tx_errors++;
1010 np->stats.tx_packets++;
1011 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1014 if (Flags & (NV_TX2_RETRYERROR|NV_TX2_CARRIERLOST|NV_TX2_LATECOLLISION|
1015 NV_TX2_UNDERFLOW|NV_TX2_ERROR)) {
1016 if (Flags & NV_TX2_UNDERFLOW)
1017 np->stats.tx_fifo_errors++;
1018 if (Flags & NV_TX2_CARRIERLOST)
1019 np->stats.tx_carrier_errors++;
1020 np->stats.tx_errors++;
1022 np->stats.tx_packets++;
1023 np->stats.tx_bytes += np->tx_skbuff[i]->len;
1026 pci_unmap_single(np->pci_dev, np->tx_dma[i],
1027 np->tx_skbuff[i]->len,
1029 dev_kfree_skb_irq(np->tx_skbuff[i]);
1030 np->tx_skbuff[i] = NULL;
1033 if (np->next_tx - np->nic_tx < TX_LIMIT_START)
1034 netif_wake_queue(dev);
1038 * nv_tx_timeout: dev->tx_timeout function
1039 * Called with dev->xmit_lock held.
1041 static void nv_tx_timeout(struct net_device *dev)
1043 struct fe_priv *np = get_nvpriv(dev);
1044 u8 *base = get_hwbase(dev);
1046 dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
1047 readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
1049 spin_lock_irq(&np->lock);
1051 /* 1) stop tx engine */
1054 /* 2) check that the packets were not sent already: */
1057 /* 3) if there are dead entries: clear everything */
1058 if (np->next_tx != np->nic_tx) {
1059 printk(KERN_DEBUG "%s: tx_timeout: dead entries!\n", dev->name);
1061 np->next_tx = np->nic_tx = 0;
1062 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1063 netif_wake_queue(dev);
1066 /* 4) restart tx engine */
1068 spin_unlock_irq(&np->lock);
1071 static void nv_rx_process(struct net_device *dev)
1073 struct fe_priv *np = get_nvpriv(dev);
1077 struct sk_buff *skb;
1080 if (np->cur_rx - np->refill_rx >= RX_RING)
1081 break; /* we scanned the whole ring - do not continue */
1083 i = np->cur_rx % RX_RING;
1084 Flags = le32_to_cpu(np->rx_ring[i].FlagLen);
1085 len = nv_descr_getlength(&np->rx_ring[i], np->desc_ver);
1087 dprintk(KERN_DEBUG "%s: nv_rx_process: looking at packet %d, Flags 0x%x.\n",
1088 dev->name, np->cur_rx, Flags);
1090 if (Flags & NV_RX_AVAIL)
1091 break; /* still owned by hardware, */
1094 * the packet is for us - immediately tear down the pci mapping.
1095 * TODO: check if a prefetch of the first cacheline improves
1098 pci_unmap_single(np->pci_dev, np->rx_dma[i],
1099 np->rx_skbuff[i]->len,
1100 PCI_DMA_FROMDEVICE);
1104 dprintk(KERN_DEBUG "Dumping packet (flags 0x%x).",Flags);
1105 for (j=0; j<64; j++) {
1107 dprintk("\n%03x:", j);
1108 dprintk(" %02x", ((unsigned char*)np->rx_skbuff[i]->data)[j]);
1112 /* look at what we actually got: */
1113 if (np->desc_ver == DESC_VER_1) {
1114 if (!(Flags & NV_RX_DESCRIPTORVALID))
1117 if (Flags & NV_RX_MISSEDFRAME) {
1118 np->stats.rx_missed_errors++;
1119 np->stats.rx_errors++;
1122 if (Flags & (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4)) {
1123 np->stats.rx_errors++;
1126 if (Flags & NV_RX_CRCERR) {
1127 np->stats.rx_crc_errors++;
1128 np->stats.rx_errors++;
1131 if (Flags & NV_RX_OVERFLOW) {
1132 np->stats.rx_over_errors++;
1133 np->stats.rx_errors++;
1136 if (Flags & NV_RX_ERROR) {
1137 /* framing errors are soft errors, the rest is fatal. */
1138 if (Flags & NV_RX_FRAMINGERR) {
1139 if (Flags & NV_RX_SUBSTRACT1) {
1143 np->stats.rx_errors++;
1148 if (!(Flags & NV_RX2_DESCRIPTORVALID))
1151 if (Flags & (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4)) {
1152 np->stats.rx_errors++;
1155 if (Flags & NV_RX2_CRCERR) {
1156 np->stats.rx_crc_errors++;
1157 np->stats.rx_errors++;
1160 if (Flags & NV_RX2_OVERFLOW) {
1161 np->stats.rx_over_errors++;
1162 np->stats.rx_errors++;
1165 if (Flags & NV_RX2_ERROR) {
1166 /* framing errors are soft errors, the rest is fatal. */
1167 if (Flags & NV_RX2_FRAMINGERR) {
1168 if (Flags & NV_RX2_SUBSTRACT1) {
1172 np->stats.rx_errors++;
1177 /* got a valid packet - forward it to the network core */
1178 skb = np->rx_skbuff[i];
1179 np->rx_skbuff[i] = NULL;
1182 skb->protocol = eth_type_trans(skb, dev);
1183 dprintk(KERN_DEBUG "%s: nv_rx_process: packet %d with %d bytes, proto %d accepted.\n",
1184 dev->name, np->cur_rx, len, skb->protocol);
1186 dev->last_rx = jiffies;
1187 np->stats.rx_packets++;
1188 np->stats.rx_bytes += len;
1195 * nv_change_mtu: dev->change_mtu function
1196 * Called with dev_base_lock held for read.
1198 static int nv_change_mtu(struct net_device *dev, int new_mtu)
1200 if (new_mtu > ETH_DATA_LEN)
1207 * nv_set_multicast: dev->set_multicast function
1208 * Called with dev->xmit_lock held.
1210 static void nv_set_multicast(struct net_device *dev)
1212 struct fe_priv *np = get_nvpriv(dev);
1213 u8 *base = get_hwbase(dev);
1218 memset(addr, 0, sizeof(addr));
1219 memset(mask, 0, sizeof(mask));
1221 if (dev->flags & IFF_PROMISC) {
1222 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1223 pff = NVREG_PFF_PROMISC;
1225 pff = NVREG_PFF_MYADDR;
1227 if (dev->flags & IFF_ALLMULTI || dev->mc_list) {
1231 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
1232 if (dev->flags & IFF_ALLMULTI) {
1233 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
1235 struct dev_mc_list *walk;
1237 walk = dev->mc_list;
1238 while (walk != NULL) {
1240 a = le32_to_cpu(*(u32 *) walk->dmi_addr);
1241 b = le16_to_cpu(*(u16 *) (&walk->dmi_addr[4]));
1249 addr[0] = alwaysOn[0];
1250 addr[1] = alwaysOn[1];
1251 mask[0] = alwaysOn[0] | alwaysOff[0];
1252 mask[1] = alwaysOn[1] | alwaysOff[1];
1255 addr[0] |= NVREG_MCASTADDRA_FORCE;
1256 pff |= NVREG_PFF_ALWAYS;
1257 spin_lock_irq(&np->lock);
1259 writel(addr[0], base + NvRegMulticastAddrA);
1260 writel(addr[1], base + NvRegMulticastAddrB);
1261 writel(mask[0], base + NvRegMulticastMaskA);
1262 writel(mask[1], base + NvRegMulticastMaskB);
1263 writel(pff, base + NvRegPacketFilterFlags);
1264 dprintk(KERN_INFO "%s: reconfiguration for multicast lists.\n",
1267 spin_unlock_irq(&np->lock);
1270 static int nv_update_linkspeed(struct net_device *dev)
1272 struct fe_priv *np = get_nvpriv(dev);
1273 u8 *base = get_hwbase(dev);
1275 int newls = np->linkspeed;
1276 int newdup = np->duplex;
1279 u32 control_1000, status_1000, phyreg;
1281 /* BMSR_LSTATUS is latched, read it twice:
1282 * we want the current value.
1284 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1285 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1287 if (!(mii_status & BMSR_LSTATUS)) {
1288 dprintk(KERN_DEBUG "%s: no link detected by phy - falling back to 10HD.\n",
1290 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1296 /* check auto negotiation is complete */
1297 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
1298 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
1299 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1302 dprintk(KERN_DEBUG "%s: autoneg not completed - falling back to 10HD.\n", dev->name);
1307 if (np->gigabit == PHY_GIGABIT) {
1308 control_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_CR, MII_READ);
1309 status_1000 = mii_rw(dev, np->phyaddr, MII_1000BT_SR, MII_READ);
1311 if ((control_1000 & ADVERTISE_1000FULL) &&
1312 (status_1000 & LPA_1000FULL)) {
1313 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: GBit ethernet detected.\n",
1315 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
1321 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1322 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
1323 dprintk(KERN_DEBUG "%s: nv_update_linkspeed: PHY advertises 0x%04x, lpa 0x%04x.\n",
1324 dev->name, adv, lpa);
1326 /* FIXME: handle parallel detection properly */
1328 if (lpa & LPA_100FULL) {
1329 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1331 } else if (lpa & LPA_100HALF) {
1332 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
1334 } else if (lpa & LPA_10FULL) {
1335 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1337 } else if (lpa & LPA_10HALF) {
1338 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1341 dprintk(KERN_DEBUG "%s: bad ability %04x - falling back to 10HD.\n", dev->name, lpa);
1342 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1347 if (np->duplex == newdup && np->linkspeed == newls)
1350 dprintk(KERN_INFO "%s: changing link setting from %d/%d to %d/%d.\n",
1351 dev->name, np->linkspeed, np->duplex, newls, newdup);
1353 np->duplex = newdup;
1354 np->linkspeed = newls;
1356 if (np->gigabit == PHY_GIGABIT) {
1357 phyreg = readl(base + NvRegRandomSeed);
1358 phyreg &= ~(0x3FF00);
1359 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
1360 phyreg |= NVREG_RNDSEED_FORCE3;
1361 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1362 phyreg |= NVREG_RNDSEED_FORCE2;
1363 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1364 phyreg |= NVREG_RNDSEED_FORCE;
1365 writel(phyreg, base + NvRegRandomSeed);
1368 phyreg = readl(base + NvRegPhyInterface);
1369 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
1370 if (np->duplex == 0)
1372 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
1374 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
1376 writel(phyreg, base + NvRegPhyInterface);
1378 writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD),
1381 writel(np->linkspeed, base + NvRegLinkSpeed);
1387 static void nv_link_irq(struct net_device *dev)
1389 u8 *base = get_hwbase(dev);
1392 miistat = readl(base + NvRegMIIStatus);
1393 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1394 dprintk(KERN_DEBUG "%s: link change notification, status 0x%x.\n", dev->name, miistat);
1396 if (miistat & (NVREG_MIISTAT_LINKCHANGE)) {
1397 if (nv_update_linkspeed(dev)) {
1398 if (netif_carrier_ok(dev)) {
1401 netif_carrier_on(dev);
1402 printk(KERN_INFO "%s: link up.\n", dev->name);
1406 if (netif_carrier_ok(dev)) {
1407 netif_carrier_off(dev);
1408 printk(KERN_INFO "%s: link down.\n", dev->name);
1413 dprintk(KERN_DEBUG "%s: link change notification done.\n", dev->name);
1416 static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
1418 struct net_device *dev = (struct net_device *) data;
1419 struct fe_priv *np = get_nvpriv(dev);
1420 u8 *base = get_hwbase(dev);
1424 dprintk(KERN_DEBUG "%s: nv_nic_irq\n", dev->name);
1427 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
1428 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1430 dprintk(KERN_DEBUG "%s: irq: %08x\n", dev->name, events);
1431 if (!(events & np->irqmask))
1434 if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
1435 spin_lock(&np->lock);
1437 spin_unlock(&np->lock);
1440 if (events & (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF)) {
1442 if (nv_alloc_rx(dev)) {
1443 spin_lock(&np->lock);
1444 if (!np->in_shutdown)
1445 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1446 spin_unlock(&np->lock);
1450 if (events & NVREG_IRQ_LINK) {
1451 spin_lock(&np->lock);
1453 spin_unlock(&np->lock);
1455 if (events & (NVREG_IRQ_TX_ERR)) {
1456 dprintk(KERN_DEBUG "%s: received irq with events 0x%x. Probably TX fail.\n",
1459 if (events & (NVREG_IRQ_UNKNOWN)) {
1460 printk(KERN_DEBUG "%s: received irq with unknown events 0x%x. Please report\n",
1463 if (i > max_interrupt_work) {
1464 spin_lock(&np->lock);
1465 /* disable interrupts on the nic */
1466 writel(0, base + NvRegIrqMask);
1469 if (!np->in_shutdown)
1470 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
1471 printk(KERN_DEBUG "%s: too many iterations (%d) in nv_nic_irq.\n", dev->name, i);
1472 spin_unlock(&np->lock);
1477 dprintk(KERN_DEBUG "%s: nv_nic_irq completed\n", dev->name);
1479 return IRQ_RETVAL(i);
1482 static void nv_do_nic_poll(unsigned long data)
1484 struct net_device *dev = (struct net_device *) data;
1485 struct fe_priv *np = get_nvpriv(dev);
1486 u8 *base = get_hwbase(dev);
1488 disable_irq(dev->irq);
1489 /* FIXME: Do we need synchronize_irq(dev->irq) here? */
1491 * reenable interrupts on the nic, we have to do this before calling
1492 * nv_nic_irq because that may decide to do otherwise
1494 writel(np->irqmask, base + NvRegIrqMask);
1496 nv_nic_irq((int) 0, (void *) data, (struct pt_regs *) NULL);
1497 enable_irq(dev->irq);
1500 static int nv_open(struct net_device *dev)
1502 struct fe_priv *np = get_nvpriv(dev);
1503 u8 *base = get_hwbase(dev);
1506 dprintk(KERN_DEBUG "nv_open: begin\n");
1508 /* 1) erase previous misconfiguration */
1509 /* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
1510 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1511 writel(0, base + NvRegMulticastAddrB);
1512 writel(0, base + NvRegMulticastMaskA);
1513 writel(0, base + NvRegMulticastMaskB);
1514 writel(0, base + NvRegPacketFilterFlags);
1516 writel(0, base + NvRegTransmitterControl);
1517 writel(0, base + NvRegReceiverControl);
1519 writel(0, base + NvRegAdapterControl);
1521 /* 2) initialize descriptor rings */
1522 oom = nv_init_ring(dev);
1524 writel(0, base + NvRegLinkSpeed);
1525 writel(0, base + NvRegUnknownTransmitterReg);
1527 writel(0, base + NvRegUnknownSetupReg6);
1529 np->in_shutdown = 0;
1531 /* 3) set mac address */
1535 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
1536 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
1537 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
1539 writel(mac[0], base + NvRegMacAddrA);
1540 writel(mac[1], base + NvRegMacAddrB);
1543 /* 4) give hw rings */
1544 writel((u32) np->ring_addr, base + NvRegRxRingPhysAddr);
1545 writel((u32) (np->ring_addr + RX_RING*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1546 writel( ((RX_RING-1) << NVREG_RINGSZ_RXSHIFT) + ((TX_RING-1) << NVREG_RINGSZ_TXSHIFT),
1547 base + NvRegRingSizes);
1549 /* 5) continue setup */
1550 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
1553 writel(np->linkspeed, base + NvRegLinkSpeed);
1554 writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
1555 writel(np->desc_ver, base + NvRegTxRxControl);
1557 writel(NVREG_TXRXCTL_BIT1|np->desc_ver, base + NvRegTxRxControl);
1558 reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
1559 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX,
1560 KERN_INFO "open: SetupReg5, Bit 31 remained off\n");
1562 writel(0, base + NvRegUnknownSetupReg4);
1563 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1564 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1566 /* 6) continue setup */
1567 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
1568 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
1569 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
1570 writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
1572 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
1573 get_random_bytes(&i, sizeof(i));
1574 writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed);
1575 writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1576 writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1577 writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1578 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1579 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
1580 base + NvRegAdapterControl);
1581 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
1582 writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1583 writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1585 i = readl(base + NvRegPowerState);
1586 if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0)
1587 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
1591 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
1593 writel(0, base + NvRegIrqMask);
1595 writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1596 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1599 ret = request_irq(dev->irq, &nv_nic_irq, SA_SHIRQ, dev->name, dev);
1603 /* ask for interrupts */
1604 writel(np->irqmask, base + NvRegIrqMask);
1606 spin_lock_irq(&np->lock);
1607 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1608 writel(0, base + NvRegMulticastAddrB);
1609 writel(0, base + NvRegMulticastMaskA);
1610 writel(0, base + NvRegMulticastMaskB);
1611 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
1612 /* One manual link speed update: Interrupts are enabled, future link
1613 * speed changes cause interrupts and are handled by nv_link_irq().
1617 miistat = readl(base + NvRegMIIStatus);
1618 writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1619 dprintk(KERN_INFO "startup: got 0x%08x.\n", miistat);
1621 ret = nv_update_linkspeed(dev);
1624 netif_start_queue(dev);
1626 netif_carrier_on(dev);
1628 printk("%s: no link during initialization.\n", dev->name);
1629 netif_carrier_off(dev);
1632 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
1633 spin_unlock_irq(&np->lock);
1641 static int nv_close(struct net_device *dev)
1643 struct fe_priv *np = get_nvpriv(dev);
1646 spin_lock_irq(&np->lock);
1647 np->in_shutdown = 1;
1648 spin_unlock_irq(&np->lock);
1649 synchronize_irq(dev->irq);
1651 del_timer_sync(&np->oom_kick);
1652 del_timer_sync(&np->nic_poll);
1654 netif_stop_queue(dev);
1655 spin_lock_irq(&np->lock);
1658 base = get_hwbase(dev);
1660 /* disable interrupts on the nic or we will lock up */
1661 writel(0, base + NvRegIrqMask);
1663 dprintk(KERN_INFO "%s: Irqmask is zero again\n", dev->name);
1665 spin_unlock_irq(&np->lock);
1667 free_irq(dev->irq, dev);
1674 /* FIXME: power down nic */
1679 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
1681 struct net_device *dev;
1687 dev = alloc_etherdev(sizeof(struct fe_priv));
1692 np = get_nvpriv(dev);
1693 np->pci_dev = pci_dev;
1694 spin_lock_init(&np->lock);
1695 SET_MODULE_OWNER(dev);
1696 SET_NETDEV_DEV(dev, &pci_dev->dev);
1698 init_timer(&np->oom_kick);
1699 np->oom_kick.data = (unsigned long) dev;
1700 np->oom_kick.function = &nv_do_rx_refill; /* timer handler */
1701 init_timer(&np->nic_poll);
1702 np->nic_poll.data = (unsigned long) dev;
1703 np->nic_poll.function = &nv_do_nic_poll; /* timer handler */
1705 err = pci_enable_device(pci_dev);
1707 printk(KERN_INFO "forcedeth: pci_enable_dev failed (%d) for device %s\n",
1708 err, pci_name(pci_dev));
1712 pci_set_master(pci_dev);
1714 err = pci_request_regions(pci_dev, DRV_NAME);
1720 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1721 dprintk(KERN_DEBUG "%s: resource %d start %p len %ld flags 0x%08lx.\n",
1722 pci_name(pci_dev), i, (void*)pci_resource_start(pci_dev, i),
1723 pci_resource_len(pci_dev, i),
1724 pci_resource_flags(pci_dev, i));
1725 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
1726 pci_resource_len(pci_dev, i) >= NV_PCI_REGSZ) {
1727 addr = pci_resource_start(pci_dev, i);
1731 if (i == DEVICE_COUNT_RESOURCE) {
1732 printk(KERN_INFO "forcedeth: Couldn't find register window for device %s.\n",
1737 /* handle different descriptor versions */
1738 if (pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 ||
1739 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 ||
1740 pci_dev->device == PCI_DEVICE_ID_NVIDIA_NVENET_3)
1741 np->desc_ver = DESC_VER_1;
1743 np->desc_ver = DESC_VER_2;
1746 dev->base_addr = (unsigned long) ioremap(addr, NV_PCI_REGSZ);
1747 if (!dev->base_addr)
1749 dev->irq = pci_dev->irq;
1750 np->rx_ring = pci_alloc_consistent(pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1754 np->tx_ring = &np->rx_ring[RX_RING];
1756 dev->open = nv_open;
1757 dev->stop = nv_close;
1758 dev->hard_start_xmit = nv_start_xmit;
1759 dev->get_stats = nv_get_stats;
1760 dev->change_mtu = nv_change_mtu;
1761 dev->set_multicast_list = nv_set_multicast;
1762 dev->do_ioctl = nv_ioctl;
1763 dev->tx_timeout = nv_tx_timeout;
1764 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
1766 pci_set_drvdata(pci_dev, dev);
1768 /* read the mac address */
1769 base = get_hwbase(dev);
1770 np->orig_mac[0] = readl(base + NvRegMacAddrA);
1771 np->orig_mac[1] = readl(base + NvRegMacAddrB);
1773 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1774 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1775 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1776 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1777 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1778 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1780 if (!is_valid_ether_addr(dev->dev_addr)) {
1782 * Bad mac address. At least one bios sets the mac address
1783 * to 01:23:45:67:89:ab
1785 printk(KERN_ERR "%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1787 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1788 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1789 printk(KERN_ERR "Please complain to your hardware vendor. Switching to a random MAC.\n");
1790 dev->dev_addr[0] = 0x00;
1791 dev->dev_addr[1] = 0x00;
1792 dev->dev_addr[2] = 0x6c;
1793 get_random_bytes(&dev->dev_addr[3], 3);
1796 dprintk(KERN_DEBUG "%s: MAC Address %02x:%02x:%02x:%02x:%02x:%02x\n", pci_name(pci_dev),
1797 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
1798 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
1801 writel(0, base + NvRegWakeUpFlags);
1804 if (np->desc_ver == DESC_VER_1) {
1805 np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
1806 if (id->driver_data & DEV_NEED_LASTPACKET1)
1807 np->tx_flags |= NV_TX_LASTPACKET1;
1809 np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
1810 if (id->driver_data & DEV_NEED_LASTPACKET1)
1811 np->tx_flags |= NV_TX2_LASTPACKET1;
1813 if (id->driver_data & DEV_IRQMASK_1)
1814 np->irqmask = NVREG_IRQMASK_WANTED_1;
1815 if (id->driver_data & DEV_IRQMASK_2)
1816 np->irqmask = NVREG_IRQMASK_WANTED_2;
1817 if (id->driver_data & DEV_NEED_TIMERIRQ)
1818 np->irqmask |= NVREG_IRQ_TIMER;
1820 /* find a suitable phy */
1821 for (i = 1; i < 32; i++) {
1824 spin_lock_irq(&np->lock);
1825 id1 = mii_rw(dev, i, MII_PHYSID1, MII_READ);
1826 spin_unlock_irq(&np->lock);
1827 if (id1 < 0 || id1 == 0xffff)
1829 spin_lock_irq(&np->lock);
1830 id2 = mii_rw(dev, i, MII_PHYSID2, MII_READ);
1831 spin_unlock_irq(&np->lock);
1832 if (id2 < 0 || id2 == 0xffff)
1835 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
1836 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
1837 dprintk(KERN_DEBUG "%s: open: Found PHY %04x:%04x at address %d.\n",
1838 pci_name(pci_dev), id1, id2, i);
1840 np->phy_oui = id1 | id2;
1844 /* PHY in isolate mode? No phy attached and user wants to
1845 * test loopback? Very odd, but can be correct.
1847 printk(KERN_INFO "%s: open: Could not find a valid PHY.\n",
1856 err = register_netdev(dev);
1858 printk(KERN_INFO "forcedeth: unable to register netdev: %d\n", err);
1861 printk(KERN_INFO "%s: forcedeth.c: subsystem: %05x:%04x bound to %s\n",
1862 dev->name, pci_dev->subsystem_vendor, pci_dev->subsystem_device,
1868 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING),
1869 np->rx_ring, np->ring_addr);
1870 pci_set_drvdata(pci_dev, NULL);
1872 iounmap(get_hwbase(dev));
1874 pci_release_regions(pci_dev);
1876 pci_disable_device(pci_dev);
1883 static void __devexit nv_remove(struct pci_dev *pci_dev)
1885 struct net_device *dev = pci_get_drvdata(pci_dev);
1886 struct fe_priv *np = get_nvpriv(dev);
1887 u8 *base = get_hwbase(dev);
1889 unregister_netdev(dev);
1891 /* special op: write back the misordered MAC address - otherwise
1892 * the next nv_probe would see a wrong address.
1894 writel(np->orig_mac[0], base + NvRegMacAddrA);
1895 writel(np->orig_mac[1], base + NvRegMacAddrB);
1897 /* free all structures */
1898 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (RX_RING + TX_RING), np->rx_ring, np->ring_addr);
1899 iounmap(get_hwbase(dev));
1900 pci_release_regions(pci_dev);
1901 pci_disable_device(pci_dev);
1903 pci_set_drvdata(pci_dev, NULL);
1906 static struct pci_device_id pci_tbl[] = {
1907 { /* nForce Ethernet Controller */
1908 .vendor = PCI_VENDOR_ID_NVIDIA,
1909 .device = PCI_DEVICE_ID_NVIDIA_NVENET_1,
1910 .subvendor = PCI_ANY_ID,
1911 .subdevice = PCI_ANY_ID,
1912 .driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ,
1914 { /* nForce2 Ethernet Controller */
1915 .vendor = PCI_VENDOR_ID_NVIDIA,
1916 .device = PCI_DEVICE_ID_NVIDIA_NVENET_2,
1917 .subvendor = PCI_ANY_ID,
1918 .subdevice = PCI_ANY_ID,
1919 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1921 { /* nForce3 Ethernet Controller */
1922 .vendor = PCI_VENDOR_ID_NVIDIA,
1923 .device = PCI_DEVICE_ID_NVIDIA_NVENET_3,
1924 .subvendor = PCI_ANY_ID,
1925 .subdevice = PCI_ANY_ID,
1926 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1928 { /* nForce3 Ethernet Controller */
1929 .vendor = PCI_VENDOR_ID_NVIDIA,
1930 .device = PCI_DEVICE_ID_NVIDIA_NVENET_4,
1931 .subvendor = PCI_ANY_ID,
1932 .subdevice = PCI_ANY_ID,
1933 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1935 { /* nForce3 Ethernet Controller */
1936 .vendor = PCI_VENDOR_ID_NVIDIA,
1937 .device = PCI_DEVICE_ID_NVIDIA_NVENET_5,
1938 .subvendor = PCI_ANY_ID,
1939 .subdevice = PCI_ANY_ID,
1940 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1942 { /* nForce3 Ethernet Controller */
1943 .vendor = PCI_VENDOR_ID_NVIDIA,
1944 .device = PCI_DEVICE_ID_NVIDIA_NVENET_6,
1945 .subvendor = PCI_ANY_ID,
1946 .subdevice = PCI_ANY_ID,
1947 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1949 { /* nForce3 Ethernet Controller */
1950 .vendor = PCI_VENDOR_ID_NVIDIA,
1951 .device = PCI_DEVICE_ID_NVIDIA_NVENET_7,
1952 .subvendor = PCI_ANY_ID,
1953 .subdevice = PCI_ANY_ID,
1954 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1956 { /* CK804 Ethernet Controller */
1957 .vendor = PCI_VENDOR_ID_NVIDIA,
1958 .device = PCI_DEVICE_ID_NVIDIA_NVENET_8,
1959 .subvendor = PCI_ANY_ID,
1960 .subdevice = PCI_ANY_ID,
1961 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1963 { /* CK804 Ethernet Controller */
1964 .vendor = PCI_VENDOR_ID_NVIDIA,
1965 .device = PCI_DEVICE_ID_NVIDIA_NVENET_9,
1966 .subvendor = PCI_ANY_ID,
1967 .subdevice = PCI_ANY_ID,
1968 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1970 { /* MCP04 Ethernet Controller */
1971 .vendor = PCI_VENDOR_ID_NVIDIA,
1972 .device = PCI_DEVICE_ID_NVIDIA_NVENET_10,
1973 .subvendor = PCI_ANY_ID,
1974 .subdevice = PCI_ANY_ID,
1975 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1977 { /* MCP04 Ethernet Controller */
1978 .vendor = PCI_VENDOR_ID_NVIDIA,
1979 .device = PCI_DEVICE_ID_NVIDIA_NVENET_11,
1980 .subvendor = PCI_ANY_ID,
1981 .subdevice = PCI_ANY_ID,
1982 .driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ,
1987 static struct pci_driver driver = {
1988 .name = "forcedeth",
1989 .id_table = pci_tbl,
1991 .remove = __devexit_p(nv_remove),
1995 static int __init init_nic(void)
1997 printk(KERN_INFO "forcedeth.c: Reverse Engineered nForce ethernet driver. Version %s.\n", FORCEDETH_VERSION);
1998 return pci_module_init(&driver);
2001 static void __exit exit_nic(void)
2003 pci_unregister_driver(&driver);
2006 module_param(max_interrupt_work, int, 0);
2007 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
2009 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
2010 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
2011 MODULE_LICENSE("GPL");
2013 MODULE_DEVICE_TABLE(pci, pci_tbl);
2015 module_init(init_nic);
2016 module_exit(exit_nic);