drivers/net/gt96100eth.c

   1 /*
   2  * Copyright 2000, 2001 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              stevel@mvista.com or source@mvista.com
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  * Ethernet driver for the MIPS GT96100 Advanced Communication Controller.
  20  *
  21  *  Revision history
  22  *
  23  *    11.11.2001  Moved to 2.4.14, ppopov@mvista.com.  Modified driver to add
  24  *                proper gt96100A support.
  25  *    12.05.2001  Moved eth port 0 to irq 3 (mapped to GT_SERINT0 on EV96100A)
  26  *                in order for both ports to work. Also cleaned up boot
  27  *                option support (mac address string parsing), fleshed out
  28  *                gt96100_cleanup_module(), and other general code cleanups
  29  *                <stevel@mvista.com>.
  30  */
  31 #include <linux/config.h>
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/string.h>
  35 #include <linux/timer.h>
  36 #include <linux/errno.h>
  37 #include <linux/in.h>
  38 #include <linux/ioport.h>
  39 #include <linux/slab.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/pci.h>
  42 #include <linux/init.h>
  43 #include <linux/netdevice.h>
  44 #include <linux/etherdevice.h>
  45 #include <linux/skbuff.h>
  46 #include <linux/delay.h>
  47 #include <linux/ctype.h>
  48
  49 #include <asm/irq.h>
  50 #include <asm/bitops.h>
  51 #include <asm/io.h>
  52
  53 #define DESC_BE 1
  54 #define DESC_DATA_BE 1
  55
  56 #define GT96100_DEBUG 2
  57
  58 #include "gt96100eth.h"
  59
  60 // prototypes
  61 static void* dmaalloc(size_t size, dma_addr_t *dma_handle);
  62 static void dmafree(size_t size, void *vaddr);
  63 static void gt96100_delay(int msec);
  64 static int gt96100_add_hash_entry(struct net_device *dev,
  65                                   unsigned char* addr);
  66 static void read_mib_counters(struct gt96100_private *gp);
  67 static int read_MII(int phy_addr, u32 reg);
  68 static int write_MII(int phy_addr, u32 reg, u16 data);
  69 #if 0
  70 static void dump_tx_ring(struct net_device *dev);
  71 static void dump_rx_ring(struct net_device *dev);
  72 #endif
  73 static int gt96100_init_module(void);
  74 static void gt96100_cleanup_module(void);
  75 static void dump_MII(int dbg_lvl, struct net_device *dev);
  76 static void dump_tx_desc(int dbg_lvl, struct net_device *dev, int i);
  77 static void dump_rx_desc(int dbg_lvl, struct net_device *dev, int i);
  78 static void dump_skb(int dbg_lvl, struct net_device *dev,
  79                      struct sk_buff *skb);
  80 static void dump_hw_addr(int dbg_lvl, struct net_device *dev,
  81                          const char* pfx, unsigned char* addr_str);
  82 static void update_stats(struct gt96100_private *gp);
  83 static void abort(struct net_device *dev, u32 abort_bits);
  84 static void hard_stop(struct net_device *dev);
  85 static void enable_ether_irq(struct net_device *dev);
  86 static void disable_ether_irq(struct net_device *dev);
  87 static int gt96100_probe1(int port_num);
  88 static void reset_tx(struct net_device *dev);
  89 static void reset_rx(struct net_device *dev);
  90 static int gt96100_check_tx_consistent(struct gt96100_private *gp);
  91 static int gt96100_init(struct net_device *dev);
  92 static int gt96100_open(struct net_device *dev);
  93 static int gt96100_close(struct net_device *dev);
  94 static int gt96100_tx(struct sk_buff *skb, struct net_device *dev);
  95 static int gt96100_rx(struct net_device *dev, u32 status);
  96 static irqreturn_t gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  97 static void gt96100_tx_timeout(struct net_device *dev);
  98 static void gt96100_set_rx_mode(struct net_device *dev);
  99 static struct net_device_stats* gt96100_get_stats(struct net_device *dev);
 100
 101 extern char * __init prom_getcmdline(void);
 102
 103 static int max_interrupt_work = 32;
 104
 105 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
 106
 107 #define RUN_AT(x) (jiffies + (x))
 108
 109 // For reading/writing 32-bit words and half-words from/to DMA memory
 110 #ifdef DESC_BE
 111 #define cpu_to_dma32 cpu_to_be32
 112 #define dma32_to_cpu be32_to_cpu
 113 #define cpu_to_dma16 cpu_to_be16
 114 #define dma16_to_cpu be16_to_cpu
 115 #else
 116 #define cpu_to_dma32 cpu_to_le32
 117 #define dma32_to_cpu le32_to_cpu
 118 #define cpu_to_dma16 cpu_to_le16
 119 #define dma16_to_cpu le16_to_cpu
 120 #endif
 121
 122 static char mac0[18] = "00.02.03.04.05.06";
 123 static char mac1[18] = "00.01.02.03.04.05";
 124 MODULE_PARM(mac0, "c18");
 125 MODULE_PARM(mac1, "c18");
 126 MODULE_PARM_DESC(mac0, "MAC address for GT96100 ethernet port 0");
 127 MODULE_PARM_DESC(mac1, "MAC address for GT96100 ethernet port 1");
 128
 129 /*
 130  * Info for the GT96100 ethernet controller's ports.
 131  */
 132 static struct gt96100_if_t {
 133         struct net_device *dev;
 134         unsigned int  iobase;   // IO Base address of this port
 135         int           irq;      // IRQ number of this port
 136         char         *mac_str;
 137 } gt96100_iflist[NUM_INTERFACES] = {
 138         {
 139                 NULL,
 140                 GT96100_ETH0_BASE, GT96100_ETHER0_IRQ,
 141                 mac0
 142         },
 143         {
 144                 NULL,
 145                 GT96100_ETH1_BASE, GT96100_ETHER1_IRQ,
 146                 mac1
 147         }
 148 };
 149
 150 static inline const char*
 151 chip_name(int chip_rev)
 152 {
 153         switch (chip_rev) {
 154         case REV_GT96100:
 155                 return "GT96100";
 156         case REV_GT96100A_1:
 157         case REV_GT96100A:
 158                 return "GT96100A";
 159         default:
 160                 return "Unknown GT96100";
 161         }
 162 }
 163
 164 /*
 165   DMA memory allocation, derived from pci_alloc_consistent.
 166 */
 167 static void *
 168 dmaalloc(size_t size, dma_addr_t *dma_handle)
 169 {
 170         void *ret;
 171
 172         ret = (void *)__get_free_pages(GFP_ATOMIC | GFP_DMA,
 173                                        get_order(size));
 174
 175         if (ret != NULL) {
 176                 dma_cache_inv((unsigned long)ret, size);
 177                 if (dma_handle != NULL)
 178                         *dma_handle = virt_to_phys(ret);
 179
 180                 /* bump virtual address up to non-cached area */
 181                 ret = (void*)KSEG1ADDR(ret);
 182         }
 183
 184         return ret;
 185 }
 186
 187 static void
 188 dmafree(size_t size, void *vaddr)
 189 {
 190         vaddr = (void*)KSEG0ADDR(vaddr);
 191         free_pages((unsigned long)vaddr, get_order(size));
 192 }
 193
 194
 195
 196 static void
 197 gt96100_delay(int ms)
 198 {
 199         if (in_interrupt())
 200                 return;
 201         else {
 202                 current->state = TASK_INTERRUPTIBLE;
 203                 schedule_timeout(ms*HZ/1000);
 204         }
 205 }
 206
 207 static int
 208 parse_mac_addr(struct net_device *dev, char* macstr)
 209 {
 210         int i, j;
 211         unsigned char result, value;
 212
 213         for (i=0; i<6; i++) {
 214                 result = 0;
 215                 if (i != 5 && *(macstr+2) != '.') {
 216                         err(__FILE__ "invalid mac address format: %d %c\n",
 217                             i, *(macstr+2));
 218                         return -EINVAL;
 219                 }
 220
 221                 for (j=0; j<2; j++) {
 222                         if (isxdigit(*macstr) &&
 223                             (value = isdigit(*macstr) ? *macstr-'0' :
 224                              toupper(*macstr)-'A'+10) < 16) {
 225                                 result = result*16 + value;
 226                                 macstr++;
 227                         } else {
 228                                 err(__FILE__ "invalid mac address "
 229                                     "character: %c\n", *macstr);
 230                                 return -EINVAL;
 231                         }
 232                 }
 233
 234                 macstr++; // step over '.'
 235                 dev->dev_addr[i] = result;
 236         }
 237
 238         return 0;
 239 }
 240
 241
 242 static int
 243 read_MII(int phy_addr, u32 reg)
 244 {
 245         int timedout = 20;
 246         u32 smir = smirOpCode | (phy_addr << smirPhyAdBit) |
 247                 (reg << smirRegAdBit);
 248
 249         // wait for last operation to complete
 250         while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) {
 251                 // snooze for 1 msec and check again
 252                 gt96100_delay(1);
 253
 254                 if (--timedout == 0) {
 255                         printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__);
 256                         return -ENODEV;
 257                 }
 258         }
 259
 260         GT96100_WRITE(GT96100_ETH_SMI_REG, smir);
 261
 262         timedout = 20;
 263         // wait for read to complete
 264         while (!((smir = GT96100_READ(GT96100_ETH_SMI_REG)) & smirReadValid)) {
 265                 // snooze for 1 msec and check again
 266                 gt96100_delay(1);
 267
 268                 if (--timedout == 0) {
 269                         printk(KERN_ERR "%s: timeout!!\n", __FUNCTION__);
 270                         return -ENODEV;
 271                 }
 272         }
 273
 274         return (int)(smir & smirDataMask);
 275 }
 276
 277 static void
 278 dump_tx_desc(int dbg_lvl, struct net_device *dev, int i)
 279 {
 280         struct gt96100_private *gp = netdev_priv(dev);
 281         gt96100_td_t *td = &gp->tx_ring[i];
 282
 283         dbg(dbg_lvl, "Tx descriptor at 0x%08lx:\n", virt_to_phys(td));
 284         dbg(dbg_lvl,
 285             "    cmdstat=%04x, byte_cnt=%04x, buff_ptr=%04x, next=%04x\n",
 286             dma32_to_cpu(td->cmdstat),
 287             dma16_to_cpu(td->byte_cnt),
 288             dma32_to_cpu(td->buff_ptr),
 289             dma32_to_cpu(td->next));
 290 }
 291
 292 static void
 293 dump_rx_desc(int dbg_lvl, struct net_device *dev, int i)
 294 {
 295         struct gt96100_private *gp = netdev_priv(dev);
 296         gt96100_rd_t *rd = &gp->rx_ring[i];
 297
 298         dbg(dbg_lvl, "Rx descriptor at 0x%08lx:\n", virt_to_phys(rd));
 299         dbg(dbg_lvl, "    cmdstat=%04x, buff_sz=%04x, byte_cnt=%04x, "
 300             "buff_ptr=%04x, next=%04x\n",
 301             dma32_to_cpu(rd->cmdstat),
 302             dma16_to_cpu(rd->buff_sz),
 303             dma16_to_cpu(rd->byte_cnt),
 304             dma32_to_cpu(rd->buff_ptr),
 305             dma32_to_cpu(rd->next));
 306 }
 307
 308 static int
 309 write_MII(int phy_addr, u32 reg, u16 data)
 310 {
 311         int timedout = 20;
 312         u32 smir = (phy_addr << smirPhyAdBit) |
 313                 (reg << smirRegAdBit) | data;
 314
 315         // wait for last operation to complete
 316         while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) {
 317                 // snooze for 1 msec and check again
 318                 gt96100_delay(1);
 319
 320                 if (--timedout == 0) {
 321                         printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__);
 322                         return -1;
 323                 }
 324         }
 325
 326         GT96100_WRITE(GT96100_ETH_SMI_REG, smir);
 327         return 0;
 328 }
 329
 330 #if 0
 331 // These routines work, just disabled to avoid compile warnings
 332 static void
 333 dump_tx_ring(struct net_device *dev)
 334 {
 335         struct gt96100_private *gp = netdev_priv(dev);
 336         int i;
 337
 338         dbg(0, "%s: txno/txni/cnt=%d/%d/%d\n", __FUNCTION__,
 339             gp->tx_next_out, gp->tx_next_in, gp->tx_count);
 340
 341         for (i=0; i<TX_RING_SIZE; i++)
 342                 dump_tx_desc(0, dev, i);
 343 }
 344
 345 static void
 346 dump_rx_ring(struct net_device *dev)
 347 {
 348         struct gt96100_private *gp = netdev_priv(dev);
 349         int i;
 350
 351         dbg(0, "%s: rxno=%d\n", __FUNCTION__, gp->rx_next_out);
 352
 353         for (i=0; i<RX_RING_SIZE; i++)
 354                 dump_rx_desc(0, dev, i);
 355 }
 356 #endif
 357
 358 static void
 359 dump_MII(int dbg_lvl, struct net_device *dev)
 360 {
 361         int i, val;
 362         struct gt96100_private *gp = netdev_priv(dev);
 363
 364         if (dbg_lvl <= GT96100_DEBUG) {
 365                 for (i=0; i<7; i++) {
 366                         if ((val = read_MII(gp->phy_addr, i)) >= 0)
 367                                 printk("MII Reg %d=%x\n", i, val);
 368                 }
 369                 for (i=16; i<21; i++) {
 370                         if ((val = read_MII(gp->phy_addr, i)) >= 0)
 371                                 printk("MII Reg %d=%x\n", i, val);
 372                 }
 373         }
 374 }
 375
 376 static void
 377 dump_hw_addr(int dbg_lvl, struct net_device *dev, const char* pfx,
 378              unsigned char* addr_str)
 379 {
 380         int i;
 381         char buf[100], octet[5];
 382
 383         if (dbg_lvl <= GT96100_DEBUG) {
 384                 strcpy(buf, pfx);
 385                 for (i = 0; i < 6; i++) {
 386                         sprintf(octet, "%2.2x%s",
 387                                 addr_str[i], i<5 ? ":" : "\n");
 388                         strcat(buf, octet);
 389                 }
 390                 info("%s", buf);
 391         }
 392 }
 393
 394
 395 static void
 396 dump_skb(int dbg_lvl, struct net_device *dev, struct sk_buff *skb)
 397 {
 398         int i;
 399         unsigned char* skbdata;
 400
 401         if (dbg_lvl <= GT96100_DEBUG) {
 402                 dbg(dbg_lvl, "%s: skb=%p, skb->data=%p, skb->len=%d\n",
 403                     __FUNCTION__, skb, skb->data, skb->len);
 404
 405                 skbdata = (unsigned char*)KSEG1ADDR(skb->data);
 406
 407                 for (i=0; i<skb->len; i++) {
 408                         if (!(i % 16))
 409                                 printk(KERN_DEBUG "\n   %3.3x: %2.2x,",
 410                                        i, skbdata[i]);
 411                         else
 412                                 printk(KERN_DEBUG "%2.2x,", skbdata[i]);
 413                 }
 414                 printk(KERN_DEBUG "\n");
 415         }
 416 }
 417
 418
 419 static int
 420 gt96100_add_hash_entry(struct net_device *dev, unsigned char* addr)
 421 {
 422         struct gt96100_private *gp = netdev_priv(dev);
 423         //u16 hashResult, stmp;
 424         //unsigned char ctmp, hash_ea[6];
 425         u32 tblEntry1, tblEntry0, *tblEntryAddr;
 426         int i;
 427
 428         tblEntry1 = hteValid | hteRD;
 429         tblEntry1 |= (u32)addr[5] << 3;
 430         tblEntry1 |= (u32)addr[4] << 11;
 431         tblEntry1 |= (u32)addr[3] << 19;
 432         tblEntry1 |= ((u32)addr[2] & 0x1f) << 27;
 433         dbg(3, "%s: tblEntry1=%x\n", __FUNCTION__, tblEntry1);
 434         tblEntry0 = ((u32)addr[2] >> 5) & 0x07;
 435         tblEntry0 |= (u32)addr[1] << 3;
 436         tblEntry0 |= (u32)addr[0] << 11;
 437         dbg(3, "%s: tblEntry0=%x\n", __FUNCTION__, tblEntry0);
 438
 439 #if 0
 440
 441         for (i=0; i<6; i++) {
 442                 // nibble swap
 443                 ctmp = nibswap(addr[i]);
 444                 // invert every nibble
 445                 hash_ea[i] = ((ctmp&1)<<3) | ((ctmp&8)>>3) |
 446                         ((ctmp&2)<<1) | ((ctmp&4)>>1);
 447                 hash_ea[i] |= ((ctmp&0x10)<<3) | ((ctmp&0x80)>>3) |
 448                         ((ctmp&0x20)<<1) | ((ctmp&0x40)>>1);
 449         }
 450
 451         dump_hw_addr(3, dev, "%s: nib swap/invt addr=", __FUNCTION__, hash_ea);
 452
 453         if (gp->hash_mode == 0) {
 454                 hashResult = ((u16)hash_ea[0] & 0xfc) << 7;
 455                 stmp = ((u16)hash_ea[0] & 0x03) |
 456                         (((u16)hash_ea[1] & 0x7f) << 2);
 457                 stmp ^= (((u16)hash_ea[1] >> 7) & 0x01) |
 458                         ((u16)hash_ea[2] << 1);
 459                 stmp ^= (u16)hash_ea[3] | (((u16)hash_ea[4] & 1) << 8);
 460                 hashResult |= stmp;
 461         } else {
 462                 return -1; // don't support hash mode 1
 463         }
 464
 465         dbg(3, "%s: hashResult=%x\n", __FUNCTION__, hashResult);
 466
 467         tblEntryAddr =
 468                 (u32 *)(&gp->hash_table[((u32)hashResult & 0x7ff) << 3]);
 469
 470         dbg(3, "%s: tblEntryAddr=%p\n", tblEntryAddr, __FUNCTION__);
 471
 472         for (i=0; i<HASH_HOP_NUMBER; i++) {
 473                 if ((*tblEntryAddr & hteValid) &&
 474                     !(*tblEntryAddr & hteSkip)) {
 475                         // This entry is already occupied, go to next entry
 476                         tblEntryAddr += 2;
 477                         dbg(3, "%s: skipping to %p\n", __FUNCTION__,
 478                             tblEntryAddr);
 479                 } else {
 480                         memset(tblEntryAddr, 0, 8);
 481                         tblEntryAddr[1] = cpu_to_dma32(tblEntry1);
 482                         tblEntryAddr[0] = cpu_to_dma32(tblEntry0);
 483                         break;
 484                 }
 485         }
 486
 487         if (i >= HASH_HOP_NUMBER) {
 488                 err("%s: expired!\n", __FUNCTION__);
 489                 return -1; // Couldn't find an unused entry
 490         }
 491
 492 #else
 493
 494         tblEntryAddr = (u32 *)gp->hash_table;
 495         for (i=0; i<RX_HASH_TABLE_SIZE/4; i+=2) {
 496                 tblEntryAddr[i+1] = cpu_to_dma32(tblEntry1);
 497                 tblEntryAddr[i] = cpu_to_dma32(tblEntry0);
 498         }
 499
 500 #endif
 501
 502         return 0;
 503 }
 504
 505
 506 static void
 507 read_mib_counters(struct gt96100_private *gp)
 508 {
 509         u32* mib_regs = (u32*)&gp->mib;
 510         int i;
 511
 512         for (i=0; i<sizeof(mib_counters_t)/sizeof(u32); i++)
 513                 mib_regs[i] = GT96100ETH_READ(gp, GT96100_ETH_MIB_COUNT_BASE +
 514                                               i*sizeof(u32));
 515 }
 516
 517
 518 static void
 519 update_stats(struct gt96100_private *gp)
 520 {
 521         mib_counters_t *mib = &gp->mib;
 522         struct net_device_stats *stats = &gp->stats;
 523
 524         read_mib_counters(gp);
 525
 526         stats->rx_packets = mib->totalFramesReceived;
 527         stats->tx_packets = mib->framesSent;
 528         stats->rx_bytes = mib->totalByteReceived;
 529         stats->tx_bytes = mib->byteSent;
 530         stats->rx_errors = mib->totalFramesReceived - mib->framesReceived;
 531         //the tx error counters are incremented by the ISR
 532         //rx_dropped incremented by gt96100_rx
 533         //tx_dropped incremented by gt96100_tx
 534         stats->multicast = mib->multicastFramesReceived;
 535         // collisions incremented by gt96100_tx_complete
 536         stats->rx_length_errors = mib->oversizeFrames + mib->fragments;
 537         // The RxError condition means the Rx DMA encountered a
 538         // CPU owned descriptor, which, if things are working as
 539         // they should, means the Rx ring has overflowed.
 540         stats->rx_over_errors = mib->macRxError;
 541         stats->rx_crc_errors = mib->cRCError;
 542 }
 543
 544 static void
 545 abort(struct net_device *dev, u32 abort_bits)
 546 {
 547         struct gt96100_private *gp = netdev_priv(dev);
 548         int timedout = 100; // wait up to 100 msec for hard stop to complete
 549
 550         dbg(3, "%s\n", __FUNCTION__);
 551
 552         // Return if neither Rx or Tx abort bits are set
 553         if (!(abort_bits & (sdcmrAR | sdcmrAT)))
 554                 return;
 555
 556         // make sure only the Rx/Tx abort bits are set
 557         abort_bits &= (sdcmrAR | sdcmrAT);
 558
 559         spin_lock(&gp->lock);
 560
 561         // abort any Rx/Tx DMA immediately
 562         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, abort_bits);
 563
 564         dbg(3, "%s: SDMA comm = %x\n", __FUNCTION__,
 565             GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM));
 566
 567         // wait for abort to complete
 568         while (GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM) & abort_bits) {
 569                 // snooze for 20 msec and check again
 570                 gt96100_delay(1);
 571
 572                 if (--timedout == 0) {
 573                         err("%s: timeout!!\n", __FUNCTION__);
 574                         break;
 575                 }
 576         }
 577
 578         spin_unlock(&gp->lock);
 579 }
 580
 581
 582 static void
 583 hard_stop(struct net_device *dev)
 584 {
 585         struct gt96100_private *gp = netdev_priv(dev);
 586
 587         dbg(3, "%s\n", __FUNCTION__);
 588
 589         disable_ether_irq(dev);
 590
 591         abort(dev, sdcmrAR | sdcmrAT);
 592
 593         // disable port
 594         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, 0);
 595 }
 596
 597
 598 static void
 599 enable_ether_irq(struct net_device *dev)
 600 {
 601         struct gt96100_private *gp = netdev_priv(dev);
 602         u32 intMask;
 603         /*
 604          * route ethernet interrupt to GT_SERINT0 for port 0,
 605          * GT_INT0 for port 1.
 606          */
 607         int intr_mask_reg = (gp->port_num == 0) ?
 608                 GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK;
 609
 610         if (gp->chip_rev >= REV_GT96100A_1) {
 611                 intMask = icrTxBufferLow | icrTxEndLow |
 612                         icrTxErrorLow  | icrRxOVR | icrTxUdr |
 613                         icrRxBufferQ0 | icrRxErrorQ0 |
 614                         icrMIIPhySTC | icrEtherIntSum;
 615         }
 616         else {
 617                 intMask = icrTxBufferLow | icrTxEndLow |
 618                         icrTxErrorLow  | icrRxOVR | icrTxUdr |
 619                         icrRxBuffer | icrRxError |
 620                         icrMIIPhySTC | icrEtherIntSum;
 621         }
 622
 623         // unmask interrupts
 624         GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, intMask);
 625
 626         intMask = GT96100_READ(intr_mask_reg);
 627         intMask |= 1<<gp->port_num;
 628         GT96100_WRITE(intr_mask_reg, intMask);
 629 }
 630
 631 static void
 632 disable_ether_irq(struct net_device *dev)
 633 {
 634         struct gt96100_private *gp = netdev_priv(dev);
 635         u32 intMask;
 636         int intr_mask_reg = (gp->port_num == 0) ?
 637                 GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK;
 638
 639         intMask = GT96100_READ(intr_mask_reg);
 640         intMask &= ~(1<<gp->port_num);
 641         GT96100_WRITE(intr_mask_reg, intMask);
 642
 643         GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, 0);
 644 }
 645
 646
 647 /*
 648  * Init GT96100 ethernet controller driver
 649  */
 650 int gt96100_init_module(void)
 651 {
 652         int i, retval=0;
 653         u16 vendor_id, device_id;
 654         u32 cpuConfig;
 655
 656 #ifndef CONFIG_MIPS_GT96100ETH
 657         return -ENODEV;
 658 #endif
 659
 660         // probe for GT96100 by reading PCI0 vendor/device ID register
 661         pcibios_read_config_word(0, 0, PCI_VENDOR_ID, &vendor_id);
 662         pcibios_read_config_word(0, 0, PCI_DEVICE_ID, &device_id);
 663
 664         if (vendor_id != PCI_VENDOR_ID_MARVELL ||
 665             (device_id != PCI_DEVICE_ID_MARVELL_GT96100 &&
 666              device_id != PCI_DEVICE_ID_MARVELL_GT96100A)) {
 667                 printk(KERN_ERR __FILE__ ": GT96100 not found!\n");
 668                 return -ENODEV;
 669         }
 670
 671         cpuConfig = GT96100_READ(GT96100_CPU_INTERF_CONFIG);
 672         if (cpuConfig & (1<<12)) {
 673                 printk(KERN_ERR __FILE__
 674                        ": must be in Big Endian mode!\n");
 675                 return -ENODEV;
 676         }
 677
 678         for (i=0; i < NUM_INTERFACES; i++) {
 679                 retval |= gt96100_probe1(i);
 680         }
 681
 682         return retval;
 683 }
 684
 685
 686
 687 static int __init
 688 gt96100_probe1(int port_num)
 689 {
 690         struct gt96100_private *gp = NULL;
 691         struct gt96100_if_t *gtif = &gt96100_iflist[port_num];
 692         int phy_addr, phy_id1, phy_id2;
 693         u32 phyAD;
 694         int retval;
 695         unsigned char chip_rev;
 696         struct net_device *dev = NULL;
 697
 698         if (gtif->irq < 0) {
 699                 printk(KERN_ERR "%s: irq unknown - probing not supported\n", __FUNCTION_);
 700                 return -ENODEV;
 701         }
 702
 703         pcibios_read_config_byte(0, 0, PCI_REVISION_ID, &chip_rev);
 704
 705         if (chip_rev >= REV_GT96100A_1) {
 706                 phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG);
 707                 phy_addr = (phyAD >> (5*port_num)) & 0x1f;
 708         } else {
 709                 /*
 710                  * not sure what's this about -- probably
 711                  * a gt bug
 712                  */
 713                 phy_addr = port_num;
 714                 phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG);
 715                 phyAD &= ~(0x1f << (port_num*5));
 716                 phyAD |= phy_addr << (port_num*5);
 717                 GT96100_WRITE(GT96100_ETH_PHY_ADDR_REG, phyAD);
 718         }
 719
 720         // probe for the external PHY
 721         if ((phy_id1 = read_MII(phy_addr, 2)) <= 0 ||
 722             (phy_id2 = read_MII(phy_addr, 3)) <= 0) {
 723                 printk(KERN_ERR "%s: no PHY found on MII%d\n", __FUNCTION__, port_num);
 724                 return -ENODEV;
 725         }
 726
 727         if (!request_region(gtif->iobase, GT96100_ETH_IO_SIZE, "GT96100ETH")) {
 728                 printk(KERN_ERR "%s: request_region failed\n", __FUNCTION__);
 729                 return -EBUSY;
 730         }
 731
 732         dev = alloc_etherdev(sizeof(struct gt96100_private));
 733         if (!dev)
 734                 goto out;
 735         gtif->dev = dev;
 736
 737         /* private struct aligned and zeroed by alloc_etherdev */
 738         /* Fill in the 'dev' fields. */
 739         dev->base_addr = gtif->iobase;
 740         dev->irq = gtif->irq;
 741
 742         if ((retval = parse_mac_addr(dev, gtif->mac_str))) {
 743                 err("%s: MAC address parse failed\n", __FUNCTION__);
 744                 retval = -EINVAL;
 745                 goto out1;
 746         }
 747
 748         gp = netdev_priv(dev);
 749
 750         memset(gp, 0, sizeof(*gp)); // clear it
 751
 752         gp->port_num = port_num;
 753         gp->io_size = GT96100_ETH_IO_SIZE;
 754         gp->port_offset = port_num * GT96100_ETH_IO_SIZE;
 755         gp->phy_addr = phy_addr;
 756         gp->chip_rev = chip_rev;
 757
 758         info("%s found at 0x%x, irq %d\n",
 759              chip_name(gp->chip_rev), gtif->iobase, gtif->irq);
 760         dump_hw_addr(0, dev, "HW Address ", dev->dev_addr);
 761         info("%s chip revision=%d\n", chip_name(gp->chip_rev), gp->chip_rev);
 762         info("%s ethernet port %d\n", chip_name(gp->chip_rev), gp->port_num);
 763         info("external PHY ID1=0x%04x, ID2=0x%04x\n", phy_id1, phy_id2);
 764
 765         // Allocate Rx and Tx descriptor rings
 766         if (gp->rx_ring == NULL) {
 767                 // All descriptors in ring must be 16-byte aligned
 768                 gp->rx_ring = dmaalloc(sizeof(gt96100_rd_t) * RX_RING_SIZE
 769                                        + sizeof(gt96100_td_t) * TX_RING_SIZE,
 770                                        &gp->rx_ring_dma);
 771                 if (gp->rx_ring == NULL) {
 772                         retval = -ENOMEM;
 773                         goto out1;
 774                 }
 775
 776                 gp->tx_ring = (gt96100_td_t *)(gp->rx_ring + RX_RING_SIZE);
 777                 gp->tx_ring_dma =
 778                         gp->rx_ring_dma + sizeof(gt96100_rd_t) * RX_RING_SIZE;
 779         }
 780
 781         // Allocate the Rx Data Buffers
 782         if (gp->rx_buff == NULL) {
 783                 gp->rx_buff = dmaalloc(PKT_BUF_SZ*RX_RING_SIZE,
 784                                        &gp->rx_buff_dma);
 785                 if (gp->rx_buff == NULL) {
 786                         retval = -ENOMEM;
 787                         goto out2;
 788                 }
 789         }
 790
 791         dbg(3, "%s: rx_ring=%p, tx_ring=%p\n", __FUNCTION__,
 792             gp->rx_ring, gp->tx_ring);
 793
 794         // Allocate Rx Hash Table
 795         if (gp->hash_table == NULL) {
 796                 gp->hash_table = (char*)dmaalloc(RX_HASH_TABLE_SIZE,
 797                                                  &gp->hash_table_dma);
 798                 if (gp->hash_table == NULL) {
 799                         retval = -ENOMEM;
 800                         goto out3;
 801                 }
 802         }
 803
 804         dbg(3, "%s: hash=%p\n", __FUNCTION__, gp->hash_table);
 805
 806         spin_lock_init(&gp->lock);
 807
 808         dev->open = gt96100_open;
 809         dev->hard_start_xmit = gt96100_tx;
 810         dev->stop = gt96100_close;
 811         dev->get_stats = gt96100_get_stats;
 812         //dev->do_ioctl = gt96100_ioctl;
 813         dev->set_multicast_list = gt96100_set_rx_mode;
 814         dev->tx_timeout = gt96100_tx_timeout;
 815         dev->watchdog_timeo = GT96100ETH_TX_TIMEOUT;
 816
 817         retval = register_netdev(dev);
 818         if (retval)
 819                 goto out4;
 820         return 0;
 821
 822 out4:
 823         dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma);
 824 out3:
 825         dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff);
 826 out2:
 827         dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE
 828                 + sizeof(gt96100_td_t) * TX_RING_SIZE,
 829                 gp->rx_ring);
 830 out1:
 831         free_netdev (dev);
 832 out:
 833         release_region(gtif->iobase, GT96100_ETH_IO_SIZE);
 834         err("%s failed.  Returns %d\n", __FUNCTION__, retval);
 835         return retval;
 836 }
 837
 838
 839 static void
 840 reset_tx(struct net_device *dev)
 841 {
 842         struct gt96100_private *gp = netdev_priv(dev);
 843         int i;
 844
 845         abort(dev, sdcmrAT);
 846
 847         for (i=0; i<TX_RING_SIZE; i++) {
 848                 if (gp->tx_skbuff[i]) {
 849                         if (in_interrupt())
 850                                 dev_kfree_skb_irq(gp->tx_skbuff[i]);
 851                         else
 852                                 dev_kfree_skb(gp->tx_skbuff[i]);
 853                         gp->tx_skbuff[i] = NULL;
 854                 }
 855
 856                 gp->tx_ring[i].cmdstat = 0; // CPU owns
 857                 gp->tx_ring[i].byte_cnt = 0;
 858                 gp->tx_ring[i].buff_ptr = 0;
 859                 gp->tx_ring[i].next =
 860                         cpu_to_dma32(gp->tx_ring_dma +
 861                                      sizeof(gt96100_td_t) * (i+1));
 862                 dump_tx_desc(4, dev, i);
 863         }
 864         /* Wrap the ring. */
 865         gp->tx_ring[i-1].next = cpu_to_dma32(gp->tx_ring_dma);
 866
 867         // setup only the lowest priority TxCDP reg
 868         GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR0, gp->tx_ring_dma);
 869         GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR1, 0);
 870
 871         // init Tx indeces and pkt counter
 872         gp->tx_next_in = gp->tx_next_out = 0;
 873         gp->tx_count = 0;
 874
 875 }
 876
 877 static void
 878 reset_rx(struct net_device *dev)
 879 {
 880         struct gt96100_private *gp = netdev_priv(dev);
 881         int i;
 882
 883         abort(dev, sdcmrAR);
 884
 885         for (i=0; i<RX_RING_SIZE; i++) {
 886                 gp->rx_ring[i].next =
 887                         cpu_to_dma32(gp->rx_ring_dma +
 888                                      sizeof(gt96100_rd_t) * (i+1));
 889                 gp->rx_ring[i].buff_ptr =
 890                         cpu_to_dma32(gp->rx_buff_dma + i*PKT_BUF_SZ);
 891                 gp->rx_ring[i].buff_sz = cpu_to_dma16(PKT_BUF_SZ);
 892                 // Give ownership to device, set first and last, enable intr
 893                 gp->rx_ring[i].cmdstat =
 894                         cpu_to_dma32((u32)(rxFirst | rxLast | rxOwn | rxEI));
 895                 dump_rx_desc(4, dev, i);
 896         }
 897         /* Wrap the ring. */
 898         gp->rx_ring[i-1].next = cpu_to_dma32(gp->rx_ring_dma);
 899
 900         // Setup only the lowest priority RxFDP and RxCDP regs
 901         for (i=0; i<4; i++) {
 902                 if (i == 0) {
 903                         GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0,
 904                                          gp->rx_ring_dma);
 905                         GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0,
 906                                          gp->rx_ring_dma);
 907                 } else {
 908                         GT96100ETH_WRITE(gp,
 909                                          GT96100_ETH_1ST_RX_DESC_PTR0 + i*4,
 910                                          0);
 911                         GT96100ETH_WRITE(gp,
 912                                          GT96100_ETH_CURR_RX_DESC_PTR0 + i*4,
 913                                          0);
 914                 }
 915         }
 916
 917         // init Rx NextOut index
 918         gp->rx_next_out = 0;
 919 }
 920
 921
 922 // Returns 1 if the Tx counter and indeces don't gel
 923 static int
 924 gt96100_check_tx_consistent(struct gt96100_private *gp)
 925 {
 926         int diff = gp->tx_next_in - gp->tx_next_out;
 927
 928         diff = diff<0 ? TX_RING_SIZE + diff : diff;
 929         diff = gp->tx_count == TX_RING_SIZE ? diff + TX_RING_SIZE : diff;
 930
 931         return (diff != gp->tx_count);
 932 }
 933
 934 static int
 935 gt96100_init(struct net_device *dev)
 936 {
 937         struct gt96100_private *gp = netdev_priv(dev);
 938         u32 tmp;
 939         u16 mii_reg;
 940
 941         dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
 942         dbg(3, "%s: scs10_lo=%4x, scs10_hi=%4x\n", __FUNCTION__,
 943             GT96100_READ(0x8), GT96100_READ(0x10));
 944         dbg(3, "%s: scs32_lo=%4x, scs32_hi=%4x\n", __FUNCTION__,
 945             GT96100_READ(0x18), GT96100_READ(0x20));
 946
 947         // Stop and disable Port
 948         hard_stop(dev);
 949
 950         // Setup CIU Arbiter
 951         tmp = GT96100_READ(GT96100_CIU_ARBITER_CONFIG);
 952         tmp |= (0x0c << (gp->port_num*2)); // set Ether DMA req priority to hi
 953 #ifndef DESC_BE
 954         tmp &= ~(1<<31);                   // set desc endianess to little
 955 #else
 956         tmp |= (1<<31);
 957 #endif
 958         GT96100_WRITE(GT96100_CIU_ARBITER_CONFIG, tmp);
 959         dbg(3, "%s: CIU Config=%x/%x\n", __FUNCTION__,
 960             tmp, GT96100_READ(GT96100_CIU_ARBITER_CONFIG));
 961
 962         // Set routing.
 963         tmp = GT96100_READ(GT96100_ROUTE_MAIN) & (0x3f << 18);
 964         tmp |= (0x07 << (18 + gp->port_num*3));
 965         GT96100_WRITE(GT96100_ROUTE_MAIN, tmp);
 966
 967         /* set MII as peripheral func */
 968         tmp = GT96100_READ(GT96100_GPP_CONFIG2);
 969         tmp |= 0x7fff << (gp->port_num*16);
 970         GT96100_WRITE(GT96100_GPP_CONFIG2, tmp);
 971
 972         /* Set up MII port pin directions */
 973         tmp = GT96100_READ(GT96100_GPP_IO2);
 974         tmp |= 0x003d << (gp->port_num*16);
 975         GT96100_WRITE(GT96100_GPP_IO2, tmp);
 976
 977         // Set-up hash table
 978         memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it
 979         gp->hash_mode = 0;
 980         // Add a single entry to hash table - our ethernet address
 981         gt96100_add_hash_entry(dev, dev->dev_addr);
 982         // Set-up DMA ptr to hash table
 983         GT96100ETH_WRITE(gp, GT96100_ETH_HASH_TBL_PTR, gp->hash_table_dma);
 984         dbg(3, "%s: Hash Tbl Ptr=%x\n", __FUNCTION__,
 985             GT96100ETH_READ(gp, GT96100_ETH_HASH_TBL_PTR));
 986
 987         // Setup Tx
 988         reset_tx(dev);
 989
 990         dbg(3, "%s: Curr Tx Desc Ptr0=%x\n", __FUNCTION__,
 991             GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0));
 992
 993         // Setup Rx
 994         reset_rx(dev);
 995
 996         dbg(3, "%s: 1st/Curr Rx Desc Ptr0=%x/%x\n", __FUNCTION__,
 997             GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0),
 998             GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0));
 999
1000         // eth port config register
1001         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
1002                          pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen);
1003
1004         mii_reg = read_MII(gp->phy_addr, 0x11); /* int enable register */
1005         mii_reg |= 2;  /* enable mii interrupt */
1006         write_MII(gp->phy_addr, 0x11, mii_reg);
1007
1008         dbg(3, "%s: PhyAD=%x\n", __FUNCTION__,
1009             GT96100_READ(GT96100_ETH_PHY_ADDR_REG));
1010
1011         // setup DMA
1012
1013         // We want the Rx/Tx DMA to write/read data to/from memory in
1014         // Big Endian mode. Also set DMA Burst Size to 8 64Bit words.
1015 #ifdef DESC_DATA_BE
1016         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG,
1017                          (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
1018 #else
1019         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG,
1020                          sdcrBLMR | sdcrBLMT |
1021                          (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
1022 #endif
1023         dbg(3, "%s: SDMA Config=%x\n", __FUNCTION__,
1024             GT96100ETH_READ(gp, GT96100_ETH_SDMA_CONFIG));
1025
1026         // start Rx DMA
1027         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD);
1028         dbg(3, "%s: SDMA Comm=%x\n", __FUNCTION__,
1029             GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM));
1030
1031         // enable this port (set hash size to 1/2K)
1032         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, pcrEN | pcrHS);
1033         dbg(3, "%s: Port Config=%x\n", __FUNCTION__,
1034             GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG));
1035
1036         /*
1037          * Disable all Type-of-Service queueing. All Rx packets will be
1038          * treated normally and will be sent to the lowest priority
1039          * queue.
1040          *
1041          * Disable flow-control for now. FIXME: support flow control?
1042          */
1043
1044         // clear all the MIB ctr regs
1045         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
1046                          pcxrFCTL | pcxrFCTLen | pcxrFLP |
1047                          pcxrPRIOrxOverride);
1048         read_mib_counters(gp);
1049         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
1050                          pcxrFCTL | pcxrFCTLen | pcxrFLP |
1051                          pcxrPRIOrxOverride | pcxrMIBclrMode);
1052
1053         dbg(3, "%s: Port Config Ext=%x\n", __FUNCTION__,
1054             GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG_EXT));
1055
1056         netif_start_queue(dev);
1057
1058         dump_MII(4, dev);
1059
1060         // enable interrupts
1061         enable_ether_irq(dev);
1062
1063         // we should now be receiving frames
1064         return 0;
1065 }
1066
1067
1068 static int
1069 gt96100_open(struct net_device *dev)
1070 {
1071         int retval;
1072
1073         dbg(2, "%s: dev=%p\n", __FUNCTION__, dev);
1074
1075         // Initialize and startup the GT-96100 ethernet port
1076         if ((retval = gt96100_init(dev))) {
1077                 err("error in gt96100_init\n");
1078                 free_irq(dev->irq, dev);
1079                 return retval;
1080         }
1081
1082         if ((retval = request_irq(dev->irq, &gt96100_interrupt,
1083                                   SA_SHIRQ, dev->name, dev))) {
1084                 err("unable to get IRQ %d\n", dev->irq);
1085                 return retval;
1086         }
1087
1088         dbg(2, "%s: Initialization done.\n", __FUNCTION__);
1089
1090         return 0;
1091 }
1092
1093 static int
1094 gt96100_close(struct net_device *dev)
1095 {
1096         dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
1097
1098         // stop the device
1099         if (netif_device_present(dev)) {
1100                 netif_stop_queue(dev);
1101                 hard_stop(dev);
1102         }
1103
1104         free_irq(dev->irq, dev);
1105         return 0;
1106 }
1107
1108
1109 static int
1110 gt96100_tx(struct sk_buff *skb, struct net_device *dev)
1111 {
1112         struct gt96100_private *gp = netdev_priv(dev);
1113         unsigned long flags;
1114         int nextIn;
1115
1116         spin_lock_irqsave(&gp->lock, flags);
1117
1118         nextIn = gp->tx_next_in;
1119
1120         dbg(3, "%s: nextIn=%d\n", __FUNCTION__, nextIn);
1121
1122         if (gp->tx_count >= TX_RING_SIZE) {
1123                 warn("Tx Ring full, pkt dropped.\n");
1124                 gp->stats.tx_dropped++;
1125                 spin_unlock_irqrestore(&gp->lock, flags);
1126                 return 1;
1127         }
1128
1129         if (!(gp->last_psr & psrLink)) {
1130                 err("%s: Link down, pkt dropped.\n", __FUNCTION__);
1131                 gp->stats.tx_dropped++;
1132                 spin_unlock_irqrestore(&gp->lock, flags);
1133                 return 1;
1134         }
1135
1136         if (dma32_to_cpu(gp->tx_ring[nextIn].cmdstat) & txOwn) {
1137                 err("%s: device owns descriptor, pkt dropped.\n", __FUNCTION__);
1138                 gp->stats.tx_dropped++;
1139                 // stop the queue, so Tx timeout can fix it
1140                 netif_stop_queue(dev);
1141                 spin_unlock_irqrestore(&gp->lock, flags);
1142                 return 1;
1143         }
1144
1145         // Prepare the Descriptor at tx_next_in
1146         gp->tx_skbuff[nextIn] = skb;
1147         gp->tx_ring[nextIn].byte_cnt = cpu_to_dma16(skb->len);
1148         gp->tx_ring[nextIn].buff_ptr = cpu_to_dma32(virt_to_phys(skb->data));
1149         // make sure packet gets written back to memory
1150         dma_cache_wback_inv((unsigned long)(skb->data), skb->len);
1151         // Give ownership to device, set first and last desc, enable interrupt
1152         // Setting of ownership bit must be *last*!
1153         gp->tx_ring[nextIn].cmdstat =
1154                 cpu_to_dma32((u32)(txOwn | txGenCRC | txEI |
1155                                    txPad | txFirst | txLast));
1156
1157         dump_tx_desc(4, dev, nextIn);
1158         dump_skb(4, dev, skb);
1159
1160         // increment tx_next_in with wrap
1161         gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
1162         // If DMA is stopped, restart
1163         if (!(GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS) & psrTxLow))
1164                 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM,
1165                                  sdcmrERD | sdcmrTXDL);
1166
1167         // increment count and stop queue if full
1168         if (++gp->tx_count == TX_RING_SIZE) {
1169                 gp->tx_full = 1;
1170                 netif_stop_queue(dev);
1171                 dbg(2, "Tx Ring now full, queue stopped.\n");
1172         }
1173
1174         dev->trans_start = jiffies;
1175         spin_unlock_irqrestore(&gp->lock, flags);
1176
1177         return 0;
1178 }
1179
1180
1181 static int
1182 gt96100_rx(struct net_device *dev, u32 status)
1183 {
1184         struct gt96100_private *gp = netdev_priv(dev);
1185         struct sk_buff *skb;
1186         int pkt_len, nextOut, cdp;
1187         gt96100_rd_t *rd;
1188         u32 cmdstat;
1189
1190         dbg(3, "%s: dev=%p, status=%x\n", __FUNCTION__, dev, status);
1191
1192         cdp = (GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0)
1193                - gp->rx_ring_dma) / sizeof(gt96100_rd_t);
1194
1195         // Continue until we reach 1st descriptor pointer
1196         for (nextOut = gp->rx_next_out; nextOut != cdp;
1197              nextOut = (nextOut + 1) % RX_RING_SIZE) {
1198
1199                 if (--gp->intr_work_done == 0)
1200                         break;
1201
1202                 rd = &gp->rx_ring[nextOut];
1203                 cmdstat = dma32_to_cpu(rd->cmdstat);
1204
1205                 dbg(4, "%s: Rx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__,
1206                     cmdstat, nextOut);
1207
1208                 if (cmdstat & (u32)rxOwn) {
1209                         //err("%s: device owns descriptor!\n", __FUNCTION__);
1210                         // DMA is not finished updating descriptor???
1211                         // Leave and come back later to pick-up where
1212                         // we left off.
1213                         break;
1214                 }
1215
1216                 // Drop this received pkt if there were any errors
1217                 if (((cmdstat & (u32)(rxErrorSummary)) &&
1218                      (cmdstat & (u32)(rxFirst))) || (status & icrRxError)) {
1219                         // update the detailed rx error counters that
1220                         // are not covered by the MIB counters.
1221                         if (cmdstat & (u32)rxOverrun)
1222                                 gp->stats.rx_fifo_errors++;
1223                         cmdstat |= (u32)rxOwn;
1224                         rd->cmdstat = cpu_to_dma32(cmdstat);
1225                         continue;
1226                 }
1227
1228                 /*
1229                  * Must be first and last (ie only) descriptor of packet. We
1230                  * ignore (drop) any packets that do not fit in one descriptor.
1231                  * Every descriptor's receive buffer is large enough to hold
1232                  * the maximum 802.3 frame size, so a multi-descriptor packet
1233                  * indicates an error. Most if not all corrupted packets will
1234                  * have already been dropped by the above check for the
1235                  * rxErrorSummary status bit.
1236                  */
1237                 if (!(cmdstat & (u32)rxFirst) || !(cmdstat & (u32)rxLast)) {
1238                         if (cmdstat & (u32)rxFirst) {
1239                                 /*
1240                                  * This is the first descriptor of a
1241                                  * multi-descriptor packet. It isn't corrupted
1242                                  * because the above check for rxErrorSummary
1243                                  * would have dropped it already, so what's
1244                                  * the deal with this packet? Good question,
1245                                  * let's dump it out.
1246                                  */
1247                                 err("%s: desc not first and last!\n", __FUNCTION__);
1248                                 dump_rx_desc(0, dev, nextOut);
1249                         }
1250                         cmdstat |= (u32)rxOwn;
1251                         rd->cmdstat = cpu_to_dma32(cmdstat);
1252                         // continue to drop every descriptor of this packet
1253                         continue;
1254                 }
1255
1256                 pkt_len = dma16_to_cpu(rd->byte_cnt);
1257
1258                 /* Create new skb. */
1259                 skb = dev_alloc_skb(pkt_len+2);
1260                 if (skb == NULL) {
1261                         err("%s: Memory squeeze, dropping packet.\n", __FUNCTION__);
1262                         gp->stats.rx_dropped++;
1263                         cmdstat |= (u32)rxOwn;
1264                         rd->cmdstat = cpu_to_dma32(cmdstat);
1265                         continue;
1266                 }
1267                 skb->dev = dev;
1268                 skb_reserve(skb, 2);   /* 16 byte IP header align */
1269                 memcpy(skb_put(skb, pkt_len),
1270                        &gp->rx_buff[nextOut*PKT_BUF_SZ], pkt_len);
1271                 skb->protocol = eth_type_trans(skb, dev);
1272                 dump_skb(4, dev, skb);
1273
1274                 netif_rx(skb);        /* pass the packet to upper layers */
1275                 dev->last_rx = jiffies;
1276
1277                 // now we can release ownership of this desc back to device
1278                 cmdstat |= (u32)rxOwn;
1279                 rd->cmdstat = cpu_to_dma32(cmdstat);
1280         }
1281
1282         if (nextOut == gp->rx_next_out)
1283                 dbg(3, "%s: RxCDP did not increment?\n", __FUNCTION__);
1284
1285         gp->rx_next_out = nextOut;
1286         return 0;
1287 }
1288
1289
1290 static void
1291 gt96100_tx_complete(struct net_device *dev, u32 status)
1292 {
1293         struct gt96100_private *gp = netdev_priv(dev);
1294         int nextOut, cdp;
1295         gt96100_td_t *td;
1296         u32 cmdstat;
1297
1298         cdp = (GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0)
1299                - gp->tx_ring_dma) / sizeof(gt96100_td_t);
1300
1301         // Continue until we reach the current descriptor pointer
1302         for (nextOut = gp->tx_next_out; nextOut != cdp;
1303              nextOut = (nextOut + 1) % TX_RING_SIZE) {
1304
1305                 if (--gp->intr_work_done == 0)
1306                         break;
1307
1308                 td = &gp->tx_ring[nextOut];
1309                 cmdstat = dma32_to_cpu(td->cmdstat);
1310
1311                 dbg(3, "%s: Tx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__,
1312                     cmdstat, nextOut);
1313
1314                 if (cmdstat & (u32)txOwn) {
1315                         //dump_tx_ring(dev);
1316                         // DMA is not finished writing descriptor???
1317                         // Leave and come back later to pick-up where
1318                         // we left off.
1319                         break;
1320                 }
1321
1322                 // increment Tx error stats
1323                 if (cmdstat & (u32)txErrorSummary) {
1324                         dbg(2, "%s: Tx error, cmdstat = %x\n", __FUNCTION__,
1325                             cmdstat);
1326                         gp->stats.tx_errors++;
1327                         if (cmdstat & (u32)txReTxLimit)
1328                                 gp->stats.tx_aborted_errors++;
1329                         if (cmdstat & (u32)txUnderrun)
1330                                 gp->stats.tx_fifo_errors++;
1331                         if (cmdstat & (u32)txLateCollision)
1332                                 gp->stats.tx_window_errors++;
1333                 }
1334
1335                 if (cmdstat & (u32)txCollision)
1336                         gp->stats.collisions +=
1337                                 (u32)((cmdstat & txReTxCntMask) >>
1338                                       txReTxCntBit);
1339
1340                 // Wake the queue if the ring was full
1341                 if (gp->tx_full) {
1342                         gp->tx_full = 0;
1343                         if (gp->last_psr & psrLink) {
1344                                 netif_wake_queue(dev);
1345                                 dbg(2, "%s: Tx Ring was full, queue waked\n", __FUNCTION_);
1346                         }
1347                 }
1348
1349                 // decrement tx ring buffer count
1350                 if (gp->tx_count) gp->tx_count--;
1351
1352                 // free the skb
1353                 if (gp->tx_skbuff[nextOut]) {
1354                         dbg(3, "%s: good Tx, skb=%p\n", __FUNCTION__,
1355                             gp->tx_skbuff[nextOut]);
1356                         dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
1357                         gp->tx_skbuff[nextOut] = NULL;
1358                 } else {
1359                         err("%s: no skb!\n", __FUNCTION__);
1360                 }
1361         }
1362
1363         gp->tx_next_out = nextOut;
1364
1365         if (gt96100_check_tx_consistent(gp)) {
1366                 err("%s: Tx queue inconsistent!\n", __FUNCTION__);
1367         }
1368
1369         if ((status & icrTxEndLow) && gp->tx_count != 0) {
1370                 // we must restart the DMA
1371                 dbg(3, "%s: Restarting Tx DMA\n", __FUNCTION__);
1372                 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM,
1373                                  sdcmrERD | sdcmrTXDL);
1374         }
1375 }
1376
1377
1378 static irqreturn_t
1379 gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1380 {
1381         struct net_device *dev = (struct net_device *)dev_id;
1382         struct gt96100_private *gp = netdev_priv(dev);
1383         u32 status;
1384         int handled = 0;
1385
1386         if (dev == NULL) {
1387                 err("%s: null dev ptr\n", __FUNCTION__);
1388                 return IRQ_NONE;
1389         }
1390
1391         dbg(3, "%s: entry, icr=%x\n", __FUNCTION__,
1392             GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE));
1393
1394         spin_lock(&gp->lock);
1395
1396         gp->intr_work_done = max_interrupt_work;
1397
1398         while (gp->intr_work_done > 0) {
1399
1400                 status = GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE);
1401                 // ACK interrupts
1402                 GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, ~status);
1403
1404                 if ((status & icrEtherIntSum) == 0 &&
1405                     !(status & (icrTxBufferLow|icrTxBufferHigh|icrRxBuffer)))
1406                         break;
1407
1408                 handled = 1;
1409
1410                 if (status & icrMIIPhySTC) {
1411                         u32 psr = GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS);
1412                         if (gp->last_psr != psr) {
1413                                 dbg(0, "port status:\n");
1414                                 dbg(0, "    %s MBit/s, %s-duplex, "
1415                                     "flow-control %s, link is %s,\n",
1416                                     psr & psrSpeed ? "100":"10",
1417                                     psr & psrDuplex ? "full":"half",
1418                                     psr & psrFctl ? "disabled":"enabled",
1419                                     psr & psrLink ? "up":"down");
1420                                 dbg(0, "    TxLowQ is %s, TxHighQ is %s, "
1421                                     "Transmitter is %s\n",
1422                                     psr & psrTxLow ? "running":"stopped",
1423                                     psr & psrTxHigh ? "running":"stopped",
1424                                     psr & psrTxInProg ? "on":"off");
1425
1426                                 if ((psr & psrLink) && !gp->tx_full &&
1427                                     netif_queue_stopped(dev)) {
1428                                         dbg(0, ": Link up, waking queue.\n",
1429                                             __FUNCTION_);
1430                                         netif_wake_queue(dev);
1431                                 } else if (!(psr & psrLink) &&
1432                                            !netif_queue_stopped(dev)) {
1433                                         dbg(0, "Link down, stopping queue.\n",
1434                                             __FUNCTION__);
1435                                         netif_stop_queue(dev);
1436                                 }
1437
1438                                 gp->last_psr = psr;
1439                         }
1440
1441                         if (--gp->intr_work_done == 0)
1442                                 break;
1443                 }
1444
1445                 if (status & (icrTxBufferLow | icrTxEndLow))
1446                         gt96100_tx_complete(dev, status);
1447
1448                 if (status & (icrRxBuffer | icrRxError)) {
1449                         gt96100_rx(dev, status);
1450                 }
1451
1452                 // Now check TX errors (RX errors were handled in gt96100_rx)
1453                 if (status & icrTxErrorLow) {
1454                         err("%s: Tx resource error\n", __FUNCTION__);
1455                         if (--gp->intr_work_done == 0)
1456                                 break;
1457                 }
1458
1459                 if (status & icrTxUdr) {
1460                         err("%s: Tx underrun error\n", __FUNCTION__);
1461                         if (--gp->intr_work_done == 0)
1462                                 break;
1463                 }
1464         }
1465
1466         if (gp->intr_work_done == 0) {
1467                 // ACK any remaining pending interrupts
1468                 GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, 0);
1469                 dbg(3, "%s: hit max work\n", __FUNCTION__);
1470         }
1471
1472         dbg(3, "%s: exit, icr=%x\n", __FUNCTION__,
1473             GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE));
1474
1475         spin_unlock(&gp->lock);
1476         return IRQ_RETVAL(handled);
1477 }
1478
1479
1480 static void
1481 gt96100_tx_timeout(struct net_device *dev)
1482 {
1483         struct gt96100_private *gp = netdev_priv(dev);
1484         unsigned long flags;
1485
1486         spin_lock_irqsave(&gp->lock, flags);
1487
1488         if (!(gp->last_psr & psrLink)) {
1489                 err("tx_timeout: link down.\n");
1490                 spin_unlock_irqrestore(&gp->lock, flags);
1491         } else {
1492                 if (gt96100_check_tx_consistent(gp))
1493                         err("tx_timeout: Tx ring error.\n");
1494
1495                 disable_ether_irq(dev);
1496                 spin_unlock_irqrestore(&gp->lock, flags);
1497                 reset_tx(dev);
1498                 enable_ether_irq(dev);
1499
1500                 netif_wake_queue(dev);
1501         }
1502 }
1503
1504
1505 static void
1506 gt96100_set_rx_mode(struct net_device *dev)
1507 {
1508         struct gt96100_private *gp = netdev_priv(dev);
1509         unsigned long flags;
1510         //struct dev_mc_list *mcptr;
1511
1512         dbg(3, "%s: dev=%p, flags=%x\n", __FUNCTION__, dev, dev->flags);
1513
1514         // stop the Receiver DMA
1515         abort(dev, sdcmrAR);
1516
1517         spin_lock_irqsave(&gp->lock, flags);
1518
1519         if (dev->flags & IFF_PROMISC) {
1520                 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG,
1521                                  pcrEN | pcrHS | pcrPM);
1522         }
1523
1524 #if 0
1525         /*
1526           FIXME: currently multicast doesn't work - need to get hash table
1527           working first.
1528         */
1529         if (dev->mc_count) {
1530                 // clear hash table
1531                 memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE);
1532                 // Add our ethernet address
1533                 gt96100_add_hash_entry(dev, dev->dev_addr);
1534
1535                 for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) {
1536                         dump_hw_addr(2, dev, __FUNCTION__ ": addr=",
1537                                      mcptr->dmi_addr);
1538                         gt96100_add_hash_entry(dev, mcptr->dmi_addr);
1539                 }
1540         }
1541 #endif
1542
1543         // restart Rx DMA
1544         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD);
1545
1546         spin_unlock_irqrestore(&gp->lock, flags);
1547 }
1548
1549 static struct net_device_stats *
1550 gt96100_get_stats(struct net_device *dev)
1551 {
1552         struct gt96100_private *gp = netdev_priv(dev);
1553         unsigned long flags;
1554
1555         dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
1556
1557         if (netif_device_present(dev)) {
1558                 spin_lock_irqsave (&gp->lock, flags);
1559                 update_stats(gp);
1560                 spin_unlock_irqrestore (&gp->lock, flags);
1561         }
1562
1563         return &gp->stats;
1564 }
1565
1566 static void gt96100_cleanup_module(void)
1567 {
1568         int i;
1569         for (i=0; i<NUM_INTERFACES; i++) {
1570                 struct gt96100_if_t *gtif = &gt96100_iflist[i];
1571                 if (gtif->dev != NULL) {
1572                         struct gt96100_private *gp =
1573                                 (struct gt96100_private *)gtif->dev->priv;
1574                         unregister_netdev(gtif->dev);
1575                         dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma);
1576                         dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff);
1577                         dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE
1578                                 + sizeof(gt96100_td_t) * TX_RING_SIZE,
1579                                 gp->rx_ring);
1580                         free_netdev(gtif->dev);
1581                         release_region(gtif->iobase, gp->io_size);
1582                 }
1583         }
1584 }
1585
1586
1587 #ifndef MODULE
1588
1589 static int __init gt96100_setup(char *options)
1590 {
1591         char *this_opt;
1592
1593         if (!options || !*options)
1594                 return 0;
1595
1596         while ((this_opt = strsep (&options, ",")) != NULL) {
1597                 if (!*this_opt)
1598                         continue;
1599                 if (!strncmp(this_opt, "mac0:", 5)) {
1600                         memcpy(mac0, this_opt+5, 17);
1601                         mac0[17]= '\0';
1602                 } else if (!strncmp(this_opt, "mac1:", 5)) {
1603                         memcpy(mac1, this_opt+5, 17);
1604                         mac1[17]= '\0';
1605                 }
1606         }
1607
1608         return 1;
1609 }
1610
1611 __setup("gt96100eth=", gt96100_setup);
1612
1613 #endif /* !MODULE */
1614
1615
1616 module_init(gt96100_init_module);
1617 module_exit(gt96100_cleanup_module);
1618
1619 MODULE_AUTHOR("Steve Longerbeam <stevel@mvista.com>");
1620 MODULE_DESCRIPTION("GT96100 Ethernet driver");