drivers/net/gt96100eth.c

   1 /*
   2  * Copyright 2000, 2001 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc.
   4  *              stevel@mvista.com or source@mvista.com
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  * Ethernet driver for the MIPS GT96100 Advanced Communication Controller.
  20  *
  21  *  Revision history
  22  *
  23  *    11.11.2001  Moved to 2.4.14, ppopov@mvista.com.  Modified driver to add
  24  *                proper gt96100A support.
  25  *    12.05.2001  Moved eth port 0 to irq 3 (mapped to GT_SERINT0 on EV96100A)
  26  *                in order for both ports to work. Also cleaned up boot
  27  *                option support (mac address string parsing), fleshed out
  28  *                gt96100_cleanup_module(), and other general code cleanups
  29  *                <stevel@mvista.com>.
  30  */
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/string.h>
  34 #include <linux/timer.h>
  35 #include <linux/errno.h>
  36 #include <linux/in.h>
  37 #include <linux/ioport.h>
  38 #include <linux/slab.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/pci.h>
  41 #include <linux/init.h>
  42 #include <linux/netdevice.h>
  43 #include <linux/etherdevice.h>
  44 #include <linux/skbuff.h>
  45 #include <linux/delay.h>
  46 #include <linux/ctype.h>
  47
  48 #include <asm/irq.h>
  49 #include <asm/bitops.h>
  50 #include <asm/io.h>
  51
  52 #define DESC_BE 1
  53 #define DESC_DATA_BE 1
  54
  55 #define GT96100_DEBUG 2
  56
  57 #include "gt96100eth.h"
  58
  59 // prototypes
  60 static void* dmaalloc(size_t size, dma_addr_t *dma_handle);
  61 static void dmafree(size_t size, void *vaddr);
  62 static void gt96100_delay(int msec);
  63 static int gt96100_add_hash_entry(struct net_device *dev,
  64                                   unsigned char* addr);
  65 static void read_mib_counters(struct gt96100_private *gp);
  66 static int read_MII(int phy_addr, u32 reg);
  67 static int write_MII(int phy_addr, u32 reg, u16 data);
  68 static int gt96100_init_module(void);
  69 static void gt96100_cleanup_module(void);
  70 static void dump_MII(int dbg_lvl, struct net_device *dev);
  71 static void dump_tx_desc(int dbg_lvl, struct net_device *dev, int i);
  72 static void dump_rx_desc(int dbg_lvl, struct net_device *dev, int i);
  73 static void dump_skb(int dbg_lvl, struct net_device *dev,
  74                      struct sk_buff *skb);
  75 static void dump_hw_addr(int dbg_lvl, struct net_device *dev,
  76                          const char* pfx, unsigned char* addr_str);
  77 static void update_stats(struct gt96100_private *gp);
  78 static void abort(struct net_device *dev, u32 abort_bits);
  79 static void hard_stop(struct net_device *dev);
  80 static void enable_ether_irq(struct net_device *dev);
  81 static void disable_ether_irq(struct net_device *dev);
  82 static int gt96100_probe1(struct pci_dev *pci, int port_num);
  83 static void reset_tx(struct net_device *dev);
  84 static void reset_rx(struct net_device *dev);
  85 static int gt96100_check_tx_consistent(struct gt96100_private *gp);
  86 static int gt96100_init(struct net_device *dev);
  87 static int gt96100_open(struct net_device *dev);
  88 static int gt96100_close(struct net_device *dev);
  89 static int gt96100_tx(struct sk_buff *skb, struct net_device *dev);
  90 static int gt96100_rx(struct net_device *dev, u32 status);
  91 static irqreturn_t gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs);
  92 static void gt96100_tx_timeout(struct net_device *dev);
  93 static void gt96100_set_rx_mode(struct net_device *dev);
  94 static struct net_device_stats* gt96100_get_stats(struct net_device *dev);
  95
  96 extern char * __init prom_getcmdline(void);
  97
  98 static int max_interrupt_work = 32;
  99
 100 #define nibswap(x) ((((x) >> 4) & 0x0f) | (((x) << 4) & 0xf0))
 101
 102 #define RUN_AT(x) (jiffies + (x))
 103
 104 // For reading/writing 32-bit words and half-words from/to DMA memory
 105 #ifdef DESC_BE
 106 #define cpu_to_dma32 cpu_to_be32
 107 #define dma32_to_cpu be32_to_cpu
 108 #define cpu_to_dma16 cpu_to_be16
 109 #define dma16_to_cpu be16_to_cpu
 110 #else
 111 #define cpu_to_dma32 cpu_to_le32
 112 #define dma32_to_cpu le32_to_cpu
 113 #define cpu_to_dma16 cpu_to_le16
 114 #define dma16_to_cpu le16_to_cpu
 115 #endif
 116
 117 static char mac0[18] = "00.02.03.04.05.06";
 118 static char mac1[18] = "00.01.02.03.04.05";
 119 MODULE_PARM(mac0, "c18");
 120 MODULE_PARM(mac1, "c18");
 121 MODULE_PARM_DESC(mac0, "MAC address for GT96100 ethernet port 0");
 122 MODULE_PARM_DESC(mac1, "MAC address for GT96100 ethernet port 1");
 123
 124 /*
 125  * Info for the GT96100 ethernet controller's ports.
 126  */
 127 static struct gt96100_if_t {
 128         struct net_device *dev;
 129         unsigned int  iobase;   // IO Base address of this port
 130         int           irq;      // IRQ number of this port
 131         char         *mac_str;
 132 } gt96100_iflist[NUM_INTERFACES] = {
 133         {
 134                 NULL,
 135                 GT96100_ETH0_BASE, GT96100_ETHER0_IRQ,
 136                 mac0
 137         },
 138         {
 139                 NULL,
 140                 GT96100_ETH1_BASE, GT96100_ETHER1_IRQ,
 141                 mac1
 142         }
 143 };
 144
 145 static inline const char*
 146 chip_name(int chip_rev)
 147 {
 148         switch (chip_rev) {
 149         case REV_GT96100:
 150                 return "GT96100";
 151         case REV_GT96100A_1:
 152         case REV_GT96100A:
 153                 return "GT96100A";
 154         default:
 155                 return "Unknown GT96100";
 156         }
 157 }
 158
 159 /*
 160   DMA memory allocation, derived from pci_alloc_consistent.
 161 */
 162 static void * dmaalloc(size_t size, dma_addr_t *dma_handle)
 163 {
 164         void *ret;
 165
 166         ret = (void *)__get_free_pages(GFP_ATOMIC | GFP_DMA, get_order(size));
 167
 168         if (ret != NULL) {
 169                 dma_cache_inv((unsigned long)ret, size);
 170                 if (dma_handle != NULL)
 171                         *dma_handle = virt_to_phys(ret);
 172
 173                 /* bump virtual address up to non-cached area */
 174                 ret = (void*)KSEG1ADDR(ret);
 175         }
 176
 177         return ret;
 178 }
 179
 180 static void dmafree(size_t size, void *vaddr)
 181 {
 182         vaddr = (void*)KSEG0ADDR(vaddr);
 183         free_pages((unsigned long)vaddr, get_order(size));
 184 }
 185
 186 static void gt96100_delay(int ms)
 187 {
 188         if (in_interrupt())
 189                 return;
 190         else {
 191                 current->state = TASK_INTERRUPTIBLE;
 192                 schedule_timeout(ms*HZ/1000);
 193         }
 194 }
 195
 196 static int
 197 parse_mac_addr(struct net_device *dev, char* macstr)
 198 {
 199         int i, j;
 200         unsigned char result, value;
 201
 202         for (i=0; i<6; i++) {
 203                 result = 0;
 204                 if (i != 5 && *(macstr+2) != '.') {
 205                         err(__FILE__ "invalid mac address format: %d %c\n",
 206                             i, *(macstr+2));
 207                         return -EINVAL;
 208                 }
 209
 210                 for (j=0; j<2; j++) {
 211                         if (isxdigit(*macstr) &&
 212                             (value = isdigit(*macstr) ? *macstr-'0' :
 213                              toupper(*macstr)-'A'+10) < 16) {
 214                                 result = result*16 + value;
 215                                 macstr++;
 216                         } else {
 217                                 err(__FILE__ "invalid mac address "
 218                                     "character: %c\n", *macstr);
 219                                 return -EINVAL;
 220                         }
 221                 }
 222
 223                 macstr++; // step over '.'
 224                 dev->dev_addr[i] = result;
 225         }
 226
 227         return 0;
 228 }
 229
 230
 231 static int
 232 read_MII(int phy_addr, u32 reg)
 233 {
 234         int timedout = 20;
 235         u32 smir = smirOpCode | (phy_addr << smirPhyAdBit) |
 236                 (reg << smirRegAdBit);
 237
 238         // wait for last operation to complete
 239         while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) {
 240                 // snooze for 1 msec and check again
 241                 gt96100_delay(1);
 242
 243                 if (--timedout == 0) {
 244                         printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__);
 245                         return -ENODEV;
 246                 }
 247         }
 248
 249         GT96100_WRITE(GT96100_ETH_SMI_REG, smir);
 250
 251         timedout = 20;
 252         // wait for read to complete
 253         while (!((smir = GT96100_READ(GT96100_ETH_SMI_REG)) & smirReadValid)) {
 254                 // snooze for 1 msec and check again
 255                 gt96100_delay(1);
 256
 257                 if (--timedout == 0) {
 258                         printk(KERN_ERR "%s: timeout!!\n", __FUNCTION__);
 259                         return -ENODEV;
 260                 }
 261         }
 262
 263         return (int)(smir & smirDataMask);
 264 }
 265
 266 static void
 267 dump_tx_desc(int dbg_lvl, struct net_device *dev, int i)
 268 {
 269         struct gt96100_private *gp = netdev_priv(dev);
 270         gt96100_td_t *td = &gp->tx_ring[i];
 271
 272         dbg(dbg_lvl, "Tx descriptor at 0x%08lx:\n", virt_to_phys(td));
 273         dbg(dbg_lvl,
 274             "    cmdstat=%04x, byte_cnt=%04x, buff_ptr=%04x, next=%04x\n",
 275             dma32_to_cpu(td->cmdstat),
 276             dma16_to_cpu(td->byte_cnt),
 277             dma32_to_cpu(td->buff_ptr),
 278             dma32_to_cpu(td->next));
 279 }
 280
 281 static void
 282 dump_rx_desc(int dbg_lvl, struct net_device *dev, int i)
 283 {
 284         struct gt96100_private *gp = netdev_priv(dev);
 285         gt96100_rd_t *rd = &gp->rx_ring[i];
 286
 287         dbg(dbg_lvl, "Rx descriptor at 0x%08lx:\n", virt_to_phys(rd));
 288         dbg(dbg_lvl, "    cmdstat=%04x, buff_sz=%04x, byte_cnt=%04x, "
 289             "buff_ptr=%04x, next=%04x\n",
 290             dma32_to_cpu(rd->cmdstat),
 291             dma16_to_cpu(rd->buff_sz),
 292             dma16_to_cpu(rd->byte_cnt),
 293             dma32_to_cpu(rd->buff_ptr),
 294             dma32_to_cpu(rd->next));
 295 }
 296
 297 static int
 298 write_MII(int phy_addr, u32 reg, u16 data)
 299 {
 300         int timedout = 20;
 301         u32 smir = (phy_addr << smirPhyAdBit) |
 302                 (reg << smirRegAdBit) | data;
 303
 304         // wait for last operation to complete
 305         while (GT96100_READ(GT96100_ETH_SMI_REG) & smirBusy) {
 306                 // snooze for 1 msec and check again
 307                 gt96100_delay(1);
 308
 309                 if (--timedout == 0) {
 310                         printk(KERN_ERR "%s: busy timeout!!\n", __FUNCTION__);
 311                         return -1;
 312                 }
 313         }
 314
 315         GT96100_WRITE(GT96100_ETH_SMI_REG, smir);
 316         return 0;
 317 }
 318
 319 static void
 320 dump_MII(int dbg_lvl, struct net_device *dev)
 321 {
 322         int i, val;
 323         struct gt96100_private *gp = netdev_priv(dev);
 324
 325         if (dbg_lvl <= GT96100_DEBUG) {
 326                 for (i=0; i<7; i++) {
 327                         if ((val = read_MII(gp->phy_addr, i)) >= 0)
 328                                 printk("MII Reg %d=%x\n", i, val);
 329                 }
 330                 for (i=16; i<21; i++) {
 331                         if ((val = read_MII(gp->phy_addr, i)) >= 0)
 332                                 printk("MII Reg %d=%x\n", i, val);
 333                 }
 334         }
 335 }
 336
 337 static void
 338 dump_hw_addr(int dbg_lvl, struct net_device *dev, const char* pfx,
 339              unsigned char* addr_str)
 340 {
 341         int i;
 342         char buf[100], octet[5];
 343
 344         if (dbg_lvl <= GT96100_DEBUG) {
 345                 strcpy(buf, pfx);
 346                 for (i = 0; i < 6; i++) {
 347                         sprintf(octet, "%2.2x%s",
 348                                 addr_str[i], i<5 ? ":" : "\n");
 349                         strcat(buf, octet);
 350                 }
 351                 info("%s", buf);
 352         }
 353 }
 354
 355
 356 static void
 357 dump_skb(int dbg_lvl, struct net_device *dev, struct sk_buff *skb)
 358 {
 359         int i;
 360         unsigned char* skbdata;
 361
 362         if (dbg_lvl <= GT96100_DEBUG) {
 363                 dbg(dbg_lvl, "%s: skb=%p, skb->data=%p, skb->len=%d\n",
 364                     __FUNCTION__, skb, skb->data, skb->len);
 365
 366                 skbdata = (unsigned char*)KSEG1ADDR(skb->data);
 367
 368                 for (i=0; i<skb->len; i++) {
 369                         if (!(i % 16))
 370                                 printk(KERN_DEBUG "\n   %3.3x: %2.2x,",
 371                                        i, skbdata[i]);
 372                         else
 373                                 printk(KERN_DEBUG "%2.2x,", skbdata[i]);
 374                 }
 375                 printk(KERN_DEBUG "\n");
 376         }
 377 }
 378
 379
 380 static int
 381 gt96100_add_hash_entry(struct net_device *dev, unsigned char* addr)
 382 {
 383         struct gt96100_private *gp = netdev_priv(dev);
 384         //u16 hashResult, stmp;
 385         //unsigned char ctmp, hash_ea[6];
 386         u32 tblEntry1, tblEntry0, *tblEntryAddr;
 387         int i;
 388
 389         tblEntry1 = hteValid | hteRD;
 390         tblEntry1 |= (u32)addr[5] << 3;
 391         tblEntry1 |= (u32)addr[4] << 11;
 392         tblEntry1 |= (u32)addr[3] << 19;
 393         tblEntry1 |= ((u32)addr[2] & 0x1f) << 27;
 394         dbg(3, "%s: tblEntry1=%x\n", __FUNCTION__, tblEntry1);
 395         tblEntry0 = ((u32)addr[2] >> 5) & 0x07;
 396         tblEntry0 |= (u32)addr[1] << 3;
 397         tblEntry0 |= (u32)addr[0] << 11;
 398         dbg(3, "%s: tblEntry0=%x\n", __FUNCTION__, tblEntry0);
 399
 400 #if 0
 401
 402         for (i=0; i<6; i++) {
 403                 // nibble swap
 404                 ctmp = nibswap(addr[i]);
 405                 // invert every nibble
 406                 hash_ea[i] = ((ctmp&1)<<3) | ((ctmp&8)>>3) |
 407                         ((ctmp&2)<<1) | ((ctmp&4)>>1);
 408                 hash_ea[i] |= ((ctmp&0x10)<<3) | ((ctmp&0x80)>>3) |
 409                         ((ctmp&0x20)<<1) | ((ctmp&0x40)>>1);
 410         }
 411
 412         dump_hw_addr(3, dev, "%s: nib swap/invt addr=", __FUNCTION__, hash_ea);
 413
 414         if (gp->hash_mode == 0) {
 415                 hashResult = ((u16)hash_ea[0] & 0xfc) << 7;
 416                 stmp = ((u16)hash_ea[0] & 0x03) |
 417                         (((u16)hash_ea[1] & 0x7f) << 2);
 418                 stmp ^= (((u16)hash_ea[1] >> 7) & 0x01) |
 419                         ((u16)hash_ea[2] << 1);
 420                 stmp ^= (u16)hash_ea[3] | (((u16)hash_ea[4] & 1) << 8);
 421                 hashResult |= stmp;
 422         } else {
 423                 return -1; // don't support hash mode 1
 424         }
 425
 426         dbg(3, "%s: hashResult=%x\n", __FUNCTION__, hashResult);
 427
 428         tblEntryAddr =
 429                 (u32 *)(&gp->hash_table[((u32)hashResult & 0x7ff) << 3]);
 430
 431         dbg(3, "%s: tblEntryAddr=%p\n", tblEntryAddr, __FUNCTION__);
 432
 433         for (i=0; i<HASH_HOP_NUMBER; i++) {
 434                 if ((*tblEntryAddr & hteValid) &&
 435                     !(*tblEntryAddr & hteSkip)) {
 436                         // This entry is already occupied, go to next entry
 437                         tblEntryAddr += 2;
 438                         dbg(3, "%s: skipping to %p\n", __FUNCTION__,
 439                             tblEntryAddr);
 440                 } else {
 441                         memset(tblEntryAddr, 0, 8);
 442                         tblEntryAddr[1] = cpu_to_dma32(tblEntry1);
 443                         tblEntryAddr[0] = cpu_to_dma32(tblEntry0);
 444                         break;
 445                 }
 446         }
 447
 448         if (i >= HASH_HOP_NUMBER) {
 449                 err("%s: expired!\n", __FUNCTION__);
 450                 return -1; // Couldn't find an unused entry
 451         }
 452
 453 #else
 454
 455         tblEntryAddr = (u32 *)gp->hash_table;
 456         for (i=0; i<RX_HASH_TABLE_SIZE/4; i+=2) {
 457                 tblEntryAddr[i+1] = cpu_to_dma32(tblEntry1);
 458                 tblEntryAddr[i] = cpu_to_dma32(tblEntry0);
 459         }
 460
 461 #endif
 462
 463         return 0;
 464 }
 465
 466
 467 static void
 468 read_mib_counters(struct gt96100_private *gp)
 469 {
 470         u32* mib_regs = (u32*)&gp->mib;
 471         int i;
 472
 473         for (i=0; i<sizeof(mib_counters_t)/sizeof(u32); i++)
 474                 mib_regs[i] = GT96100ETH_READ(gp, GT96100_ETH_MIB_COUNT_BASE +
 475                                               i*sizeof(u32));
 476 }
 477
 478
 479 static void
 480 update_stats(struct gt96100_private *gp)
 481 {
 482         mib_counters_t *mib = &gp->mib;
 483         struct net_device_stats *stats = &gp->stats;
 484
 485         read_mib_counters(gp);
 486
 487         stats->rx_packets = mib->totalFramesReceived;
 488         stats->tx_packets = mib->framesSent;
 489         stats->rx_bytes = mib->totalByteReceived;
 490         stats->tx_bytes = mib->byteSent;
 491         stats->rx_errors = mib->totalFramesReceived - mib->framesReceived;
 492         //the tx error counters are incremented by the ISR
 493         //rx_dropped incremented by gt96100_rx
 494         //tx_dropped incremented by gt96100_tx
 495         stats->multicast = mib->multicastFramesReceived;
 496         // collisions incremented by gt96100_tx_complete
 497         stats->rx_length_errors = mib->oversizeFrames + mib->fragments;
 498         // The RxError condition means the Rx DMA encountered a
 499         // CPU owned descriptor, which, if things are working as
 500         // they should, means the Rx ring has overflowed.
 501         stats->rx_over_errors = mib->macRxError;
 502         stats->rx_crc_errors = mib->cRCError;
 503 }
 504
 505 static void
 506 abort(struct net_device *dev, u32 abort_bits)
 507 {
 508         struct gt96100_private *gp = netdev_priv(dev);
 509         int timedout = 100; // wait up to 100 msec for hard stop to complete
 510
 511         dbg(3, "%s\n", __FUNCTION__);
 512
 513         // Return if neither Rx or Tx abort bits are set
 514         if (!(abort_bits & (sdcmrAR | sdcmrAT)))
 515                 return;
 516
 517         // make sure only the Rx/Tx abort bits are set
 518         abort_bits &= (sdcmrAR | sdcmrAT);
 519
 520         spin_lock(&gp->lock);
 521
 522         // abort any Rx/Tx DMA immediately
 523         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, abort_bits);
 524
 525         dbg(3, "%s: SDMA comm = %x\n", __FUNCTION__,
 526             GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM));
 527
 528         // wait for abort to complete
 529         while (GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM) & abort_bits) {
 530                 // snooze for 20 msec and check again
 531                 gt96100_delay(1);
 532
 533                 if (--timedout == 0) {
 534                         err("%s: timeout!!\n", __FUNCTION__);
 535                         break;
 536                 }
 537         }
 538
 539         spin_unlock(&gp->lock);
 540 }
 541
 542
 543 static void
 544 hard_stop(struct net_device *dev)
 545 {
 546         struct gt96100_private *gp = netdev_priv(dev);
 547
 548         dbg(3, "%s\n", __FUNCTION__);
 549
 550         disable_ether_irq(dev);
 551
 552         abort(dev, sdcmrAR | sdcmrAT);
 553
 554         // disable port
 555         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, 0);
 556 }
 557
 558
 559 static void
 560 enable_ether_irq(struct net_device *dev)
 561 {
 562         struct gt96100_private *gp = netdev_priv(dev);
 563         u32 intMask;
 564         /*
 565          * route ethernet interrupt to GT_SERINT0 for port 0,
 566          * GT_INT0 for port 1.
 567          */
 568         int intr_mask_reg = (gp->port_num == 0) ?
 569                 GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK;
 570
 571         if (gp->chip_rev >= REV_GT96100A_1) {
 572                 intMask = icrTxBufferLow | icrTxEndLow |
 573                         icrTxErrorLow  | icrRxOVR | icrTxUdr |
 574                         icrRxBufferQ0 | icrRxErrorQ0 |
 575                         icrMIIPhySTC | icrEtherIntSum;
 576         }
 577         else {
 578                 intMask = icrTxBufferLow | icrTxEndLow |
 579                         icrTxErrorLow  | icrRxOVR | icrTxUdr |
 580                         icrRxBuffer | icrRxError |
 581                         icrMIIPhySTC | icrEtherIntSum;
 582         }
 583
 584         // unmask interrupts
 585         GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, intMask);
 586
 587         intMask = GT96100_READ(intr_mask_reg);
 588         intMask |= 1<<gp->port_num;
 589         GT96100_WRITE(intr_mask_reg, intMask);
 590 }
 591
 592 static void
 593 disable_ether_irq(struct net_device *dev)
 594 {
 595         struct gt96100_private *gp = netdev_priv(dev);
 596         u32 intMask;
 597         int intr_mask_reg = (gp->port_num == 0) ?
 598                 GT96100_SERINT0_MASK : GT96100_INT0_HIGH_MASK;
 599
 600         intMask = GT96100_READ(intr_mask_reg);
 601         intMask &= ~(1<<gp->port_num);
 602         GT96100_WRITE(intr_mask_reg, intMask);
 603
 604         GT96100ETH_WRITE(gp, GT96100_ETH_INT_MASK, 0);
 605 }
 606
 607
 608 /*
 609  * Init GT96100 ethernet controller driver
 610  */
 611 static int gt96100_init_module(void)
 612 {
 613         struct pci_dev *pci;
 614         int i, retval=0;
 615         u32 cpuConfig;
 616
 617         /*
 618          * Stupid probe because this really isn't a PCI device
 619          */
 620         if (!(pci = pci_find_device(PCI_VENDOR_ID_MARVELL,
 621                                     PCI_DEVICE_ID_MARVELL_GT96100, NULL)) &&
 622             !(pci = pci_find_device(PCI_VENDOR_ID_MARVELL,
 623                                     PCI_DEVICE_ID_MARVELL_GT96100A, NULL))) {
 624                 printk(KERN_ERR __FILE__ ": GT96100 not found!\n");
 625                 return -ENODEV;
 626         }
 627
 628         cpuConfig = GT96100_READ(GT96100_CPU_INTERF_CONFIG);
 629         if (cpuConfig & (1<<12)) {
 630                 printk(KERN_ERR __FILE__
 631                        ": must be in Big Endian mode!\n");
 632                 return -ENODEV;
 633         }
 634
 635         for (i=0; i < NUM_INTERFACES; i++)
 636                 retval |= gt96100_probe1(pci, i);
 637
 638         return retval;
 639 }
 640
 641 static int __init gt96100_probe1(struct pci_dev *pci, int port_num)
 642 {
 643         struct gt96100_private *gp = NULL;
 644         struct gt96100_if_t *gtif = &gt96100_iflist[port_num];
 645         int phy_addr, phy_id1, phy_id2;
 646         u32 phyAD;
 647         int retval;
 648         unsigned char chip_rev;
 649         struct net_device *dev = NULL;
 650
 651         if (gtif->irq < 0) {
 652                 printk(KERN_ERR "%s: irq unknown - probing not supported\n",
 653                       __FUNCTION__);
 654                 return -ENODEV;
 655         }
 656
 657         pci_read_config_byte(pci, PCI_REVISION_ID, &chip_rev);
 658
 659         if (chip_rev >= REV_GT96100A_1) {
 660                 phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG);
 661                 phy_addr = (phyAD >> (5*port_num)) & 0x1f;
 662         } else {
 663                 /*
 664                  * not sure what's this about -- probably a gt bug
 665                  */
 666                 phy_addr = port_num;
 667                 phyAD = GT96100_READ(GT96100_ETH_PHY_ADDR_REG);
 668                 phyAD &= ~(0x1f << (port_num*5));
 669                 phyAD |= phy_addr << (port_num*5);
 670                 GT96100_WRITE(GT96100_ETH_PHY_ADDR_REG, phyAD);
 671         }
 672
 673         // probe for the external PHY
 674         if ((phy_id1 = read_MII(phy_addr, 2)) <= 0 ||
 675             (phy_id2 = read_MII(phy_addr, 3)) <= 0) {
 676                 printk(KERN_ERR "%s: no PHY found on MII%d\n", __FUNCTION__, port_num);
 677                 return -ENODEV;
 678         }
 679
 680         if (!request_region(gtif->iobase, GT96100_ETH_IO_SIZE, "GT96100ETH")) {
 681                 printk(KERN_ERR "%s: request_region failed\n", __FUNCTION__);
 682                 return -EBUSY;
 683         }
 684
 685         dev = alloc_etherdev(sizeof(struct gt96100_private));
 686         if (!dev)
 687                 goto out;
 688         gtif->dev = dev;
 689
 690         /* private struct aligned and zeroed by alloc_etherdev */
 691         /* Fill in the 'dev' fields. */
 692         dev->base_addr = gtif->iobase;
 693         dev->irq = gtif->irq;
 694
 695         if ((retval = parse_mac_addr(dev, gtif->mac_str))) {
 696                 err("%s: MAC address parse failed\n", __FUNCTION__);
 697                 retval = -EINVAL;
 698                 goto out1;
 699         }
 700
 701         gp = netdev_priv(dev);
 702
 703         memset(gp, 0, sizeof(*gp)); // clear it
 704
 705         gp->port_num = port_num;
 706         gp->io_size = GT96100_ETH_IO_SIZE;
 707         gp->port_offset = port_num * GT96100_ETH_IO_SIZE;
 708         gp->phy_addr = phy_addr;
 709         gp->chip_rev = chip_rev;
 710
 711         info("%s found at 0x%x, irq %d\n",
 712              chip_name(gp->chip_rev), gtif->iobase, gtif->irq);
 713         dump_hw_addr(0, dev, "HW Address ", dev->dev_addr);
 714         info("%s chip revision=%d\n", chip_name(gp->chip_rev), gp->chip_rev);
 715         info("%s ethernet port %d\n", chip_name(gp->chip_rev), gp->port_num);
 716         info("external PHY ID1=0x%04x, ID2=0x%04x\n", phy_id1, phy_id2);
 717
 718         // Allocate Rx and Tx descriptor rings
 719         if (gp->rx_ring == NULL) {
 720                 // All descriptors in ring must be 16-byte aligned
 721                 gp->rx_ring = dmaalloc(sizeof(gt96100_rd_t) * RX_RING_SIZE
 722                                        + sizeof(gt96100_td_t) * TX_RING_SIZE,
 723                                        &gp->rx_ring_dma);
 724                 if (gp->rx_ring == NULL) {
 725                         retval = -ENOMEM;
 726                         goto out1;
 727                 }
 728
 729                 gp->tx_ring = (gt96100_td_t *)(gp->rx_ring + RX_RING_SIZE);
 730                 gp->tx_ring_dma =
 731                         gp->rx_ring_dma + sizeof(gt96100_rd_t) * RX_RING_SIZE;
 732         }
 733
 734         // Allocate the Rx Data Buffers
 735         if (gp->rx_buff == NULL) {
 736                 gp->rx_buff = dmaalloc(PKT_BUF_SZ*RX_RING_SIZE,
 737                                        &gp->rx_buff_dma);
 738                 if (gp->rx_buff == NULL) {
 739                         retval = -ENOMEM;
 740                         goto out2;
 741                 }
 742         }
 743
 744         dbg(3, "%s: rx_ring=%p, tx_ring=%p\n", __FUNCTION__,
 745             gp->rx_ring, gp->tx_ring);
 746
 747         // Allocate Rx Hash Table
 748         if (gp->hash_table == NULL) {
 749                 gp->hash_table = (char*)dmaalloc(RX_HASH_TABLE_SIZE,
 750                                                  &gp->hash_table_dma);
 751                 if (gp->hash_table == NULL) {
 752                         retval = -ENOMEM;
 753                         goto out3;
 754                 }
 755         }
 756
 757         dbg(3, "%s: hash=%p\n", __FUNCTION__, gp->hash_table);
 758
 759         spin_lock_init(&gp->lock);
 760
 761         dev->open = gt96100_open;
 762         dev->hard_start_xmit = gt96100_tx;
 763         dev->stop = gt96100_close;
 764         dev->get_stats = gt96100_get_stats;
 765         //dev->do_ioctl = gt96100_ioctl;
 766         dev->set_multicast_list = gt96100_set_rx_mode;
 767         dev->tx_timeout = gt96100_tx_timeout;
 768         dev->watchdog_timeo = GT96100ETH_TX_TIMEOUT;
 769
 770         retval = register_netdev(dev);
 771         if (retval)
 772                 goto out4;
 773         return 0;
 774
 775 out4:
 776         dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma);
 777 out3:
 778         dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff);
 779 out2:
 780         dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE
 781                 + sizeof(gt96100_td_t) * TX_RING_SIZE,
 782                 gp->rx_ring);
 783 out1:
 784         free_netdev (dev);
 785 out:
 786         release_region(gtif->iobase, GT96100_ETH_IO_SIZE);
 787
 788         err("%s failed.  Returns %d\n", __FUNCTION__, retval);
 789         return retval;
 790 }
 791
 792
 793 static void
 794 reset_tx(struct net_device *dev)
 795 {
 796         struct gt96100_private *gp = netdev_priv(dev);
 797         int i;
 798
 799         abort(dev, sdcmrAT);
 800
 801         for (i=0; i<TX_RING_SIZE; i++) {
 802                 if (gp->tx_skbuff[i]) {
 803                         if (in_interrupt())
 804                                 dev_kfree_skb_irq(gp->tx_skbuff[i]);
 805                         else
 806                                 dev_kfree_skb(gp->tx_skbuff[i]);
 807                         gp->tx_skbuff[i] = NULL;
 808                 }
 809
 810                 gp->tx_ring[i].cmdstat = 0; // CPU owns
 811                 gp->tx_ring[i].byte_cnt = 0;
 812                 gp->tx_ring[i].buff_ptr = 0;
 813                 gp->tx_ring[i].next =
 814                         cpu_to_dma32(gp->tx_ring_dma +
 815                                      sizeof(gt96100_td_t) * (i+1));
 816                 dump_tx_desc(4, dev, i);
 817         }
 818         /* Wrap the ring. */
 819         gp->tx_ring[i-1].next = cpu_to_dma32(gp->tx_ring_dma);
 820
 821         // setup only the lowest priority TxCDP reg
 822         GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR0, gp->tx_ring_dma);
 823         GT96100ETH_WRITE(gp, GT96100_ETH_CURR_TX_DESC_PTR1, 0);
 824
 825         // init Tx indeces and pkt counter
 826         gp->tx_next_in = gp->tx_next_out = 0;
 827         gp->tx_count = 0;
 828
 829 }
 830
 831 static void
 832 reset_rx(struct net_device *dev)
 833 {
 834         struct gt96100_private *gp = netdev_priv(dev);
 835         int i;
 836
 837         abort(dev, sdcmrAR);
 838
 839         for (i=0; i<RX_RING_SIZE; i++) {
 840                 gp->rx_ring[i].next =
 841                         cpu_to_dma32(gp->rx_ring_dma +
 842                                      sizeof(gt96100_rd_t) * (i+1));
 843                 gp->rx_ring[i].buff_ptr =
 844                         cpu_to_dma32(gp->rx_buff_dma + i*PKT_BUF_SZ);
 845                 gp->rx_ring[i].buff_sz = cpu_to_dma16(PKT_BUF_SZ);
 846                 // Give ownership to device, set first and last, enable intr
 847                 gp->rx_ring[i].cmdstat =
 848                         cpu_to_dma32((u32)(rxFirst | rxLast | rxOwn | rxEI));
 849                 dump_rx_desc(4, dev, i);
 850         }
 851         /* Wrap the ring. */
 852         gp->rx_ring[i-1].next = cpu_to_dma32(gp->rx_ring_dma);
 853
 854         // Setup only the lowest priority RxFDP and RxCDP regs
 855         for (i=0; i<4; i++) {
 856                 if (i == 0) {
 857                         GT96100ETH_WRITE(gp, GT96100_ETH_1ST_RX_DESC_PTR0,
 858                                          gp->rx_ring_dma);
 859                         GT96100ETH_WRITE(gp, GT96100_ETH_CURR_RX_DESC_PTR0,
 860                                          gp->rx_ring_dma);
 861                 } else {
 862                         GT96100ETH_WRITE(gp,
 863                                          GT96100_ETH_1ST_RX_DESC_PTR0 + i*4,
 864                                          0);
 865                         GT96100ETH_WRITE(gp,
 866                                          GT96100_ETH_CURR_RX_DESC_PTR0 + i*4,
 867                                          0);
 868                 }
 869         }
 870
 871         // init Rx NextOut index
 872         gp->rx_next_out = 0;
 873 }
 874
 875
 876 // Returns 1 if the Tx counter and indeces don't gel
 877 static int
 878 gt96100_check_tx_consistent(struct gt96100_private *gp)
 879 {
 880         int diff = gp->tx_next_in - gp->tx_next_out;
 881
 882         diff = diff<0 ? TX_RING_SIZE + diff : diff;
 883         diff = gp->tx_count == TX_RING_SIZE ? diff + TX_RING_SIZE : diff;
 884
 885         return (diff != gp->tx_count);
 886 }
 887
 888 static int
 889 gt96100_init(struct net_device *dev)
 890 {
 891         struct gt96100_private *gp = netdev_priv(dev);
 892         u32 tmp;
 893         u16 mii_reg;
 894
 895         dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
 896         dbg(3, "%s: scs10_lo=%4x, scs10_hi=%4x\n", __FUNCTION__,
 897             GT96100_READ(0x8), GT96100_READ(0x10));
 898         dbg(3, "%s: scs32_lo=%4x, scs32_hi=%4x\n", __FUNCTION__,
 899             GT96100_READ(0x18), GT96100_READ(0x20));
 900
 901         // Stop and disable Port
 902         hard_stop(dev);
 903
 904         // Setup CIU Arbiter
 905         tmp = GT96100_READ(GT96100_CIU_ARBITER_CONFIG);
 906         tmp |= (0x0c << (gp->port_num*2)); // set Ether DMA req priority to hi
 907 #ifndef DESC_BE
 908         tmp &= ~(1<<31);                   // set desc endianess to little
 909 #else
 910         tmp |= (1<<31);
 911 #endif
 912         GT96100_WRITE(GT96100_CIU_ARBITER_CONFIG, tmp);
 913         dbg(3, "%s: CIU Config=%x/%x\n", __FUNCTION__,
 914             tmp, GT96100_READ(GT96100_CIU_ARBITER_CONFIG));
 915
 916         // Set routing.
 917         tmp = GT96100_READ(GT96100_ROUTE_MAIN) & (0x3f << 18);
 918         tmp |= (0x07 << (18 + gp->port_num*3));
 919         GT96100_WRITE(GT96100_ROUTE_MAIN, tmp);
 920
 921         /* set MII as peripheral func */
 922         tmp = GT96100_READ(GT96100_GPP_CONFIG2);
 923         tmp |= 0x7fff << (gp->port_num*16);
 924         GT96100_WRITE(GT96100_GPP_CONFIG2, tmp);
 925
 926         /* Set up MII port pin directions */
 927         tmp = GT96100_READ(GT96100_GPP_IO2);
 928         tmp |= 0x003d << (gp->port_num*16);
 929         GT96100_WRITE(GT96100_GPP_IO2, tmp);
 930
 931         // Set-up hash table
 932         memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE); // clear it
 933         gp->hash_mode = 0;
 934         // Add a single entry to hash table - our ethernet address
 935         gt96100_add_hash_entry(dev, dev->dev_addr);
 936         // Set-up DMA ptr to hash table
 937         GT96100ETH_WRITE(gp, GT96100_ETH_HASH_TBL_PTR, gp->hash_table_dma);
 938         dbg(3, "%s: Hash Tbl Ptr=%x\n", __FUNCTION__,
 939             GT96100ETH_READ(gp, GT96100_ETH_HASH_TBL_PTR));
 940
 941         // Setup Tx
 942         reset_tx(dev);
 943
 944         dbg(3, "%s: Curr Tx Desc Ptr0=%x\n", __FUNCTION__,
 945             GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0));
 946
 947         // Setup Rx
 948         reset_rx(dev);
 949
 950         dbg(3, "%s: 1st/Curr Rx Desc Ptr0=%x/%x\n", __FUNCTION__,
 951             GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0),
 952             GT96100ETH_READ(gp, GT96100_ETH_CURR_RX_DESC_PTR0));
 953
 954         // eth port config register
 955         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
 956                          pcxrFCTL | pcxrFCTLen | pcxrFLP | pcxrDPLXen);
 957
 958         mii_reg = read_MII(gp->phy_addr, 0x11); /* int enable register */
 959         mii_reg |= 2;  /* enable mii interrupt */
 960         write_MII(gp->phy_addr, 0x11, mii_reg);
 961
 962         dbg(3, "%s: PhyAD=%x\n", __FUNCTION__,
 963             GT96100_READ(GT96100_ETH_PHY_ADDR_REG));
 964
 965         // setup DMA
 966
 967         // We want the Rx/Tx DMA to write/read data to/from memory in
 968         // Big Endian mode. Also set DMA Burst Size to 8 64Bit words.
 969 #ifdef DESC_DATA_BE
 970         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG,
 971                          (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
 972 #else
 973         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_CONFIG,
 974                          sdcrBLMR | sdcrBLMT |
 975                          (0xf<<sdcrRCBit) | sdcrRIFB | (3<<sdcrBSZBit));
 976 #endif
 977         dbg(3, "%s: SDMA Config=%x\n", __FUNCTION__,
 978             GT96100ETH_READ(gp, GT96100_ETH_SDMA_CONFIG));
 979
 980         // start Rx DMA
 981         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD);
 982         dbg(3, "%s: SDMA Comm=%x\n", __FUNCTION__,
 983             GT96100ETH_READ(gp, GT96100_ETH_SDMA_COMM));
 984
 985         // enable this port (set hash size to 1/2K)
 986         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG, pcrEN | pcrHS);
 987         dbg(3, "%s: Port Config=%x\n", __FUNCTION__,
 988             GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG));
 989
 990         /*
 991          * Disable all Type-of-Service queueing. All Rx packets will be
 992          * treated normally and will be sent to the lowest priority
 993          * queue.
 994          *
 995          * Disable flow-control for now. FIXME: support flow control?
 996          */
 997
 998         // clear all the MIB ctr regs
 999         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
1000                          pcxrFCTL | pcxrFCTLen | pcxrFLP |
1001                          pcxrPRIOrxOverride);
1002         read_mib_counters(gp);
1003         GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG_EXT,
1004                          pcxrFCTL | pcxrFCTLen | pcxrFLP |
1005                          pcxrPRIOrxOverride | pcxrMIBclrMode);
1006
1007         dbg(3, "%s: Port Config Ext=%x\n", __FUNCTION__,
1008             GT96100ETH_READ(gp, GT96100_ETH_PORT_CONFIG_EXT));
1009
1010         netif_start_queue(dev);
1011
1012         dump_MII(4, dev);
1013
1014         // enable interrupts
1015         enable_ether_irq(dev);
1016
1017         // we should now be receiving frames
1018         return 0;
1019 }
1020
1021
1022 static int
1023 gt96100_open(struct net_device *dev)
1024 {
1025         int retval;
1026
1027         dbg(2, "%s: dev=%p\n", __FUNCTION__, dev);
1028
1029         // Initialize and startup the GT-96100 ethernet port
1030         if ((retval = gt96100_init(dev))) {
1031                 err("error in gt96100_init\n");
1032                 free_irq(dev->irq, dev);
1033                 return retval;
1034         }
1035
1036         if ((retval = request_irq(dev->irq, &gt96100_interrupt,
1037                                   SA_SHIRQ, dev->name, dev))) {
1038                 err("unable to get IRQ %d\n", dev->irq);
1039                 return retval;
1040         }
1041
1042         dbg(2, "%s: Initialization done.\n", __FUNCTION__);
1043
1044         return 0;
1045 }
1046
1047 static int
1048 gt96100_close(struct net_device *dev)
1049 {
1050         dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
1051
1052         // stop the device
1053         if (netif_device_present(dev)) {
1054                 netif_stop_queue(dev);
1055                 hard_stop(dev);
1056         }
1057
1058         free_irq(dev->irq, dev);
1059
1060         return 0;
1061 }
1062
1063
1064 static int
1065 gt96100_tx(struct sk_buff *skb, struct net_device *dev)
1066 {
1067         struct gt96100_private *gp = netdev_priv(dev);
1068         unsigned long flags;
1069         int nextIn;
1070
1071         spin_lock_irqsave(&gp->lock, flags);
1072
1073         nextIn = gp->tx_next_in;
1074
1075         dbg(3, "%s: nextIn=%d\n", __FUNCTION__, nextIn);
1076
1077         if (gp->tx_count >= TX_RING_SIZE) {
1078                 warn("Tx Ring full, pkt dropped.\n");
1079                 gp->stats.tx_dropped++;
1080                 spin_unlock_irqrestore(&gp->lock, flags);
1081                 return 1;
1082         }
1083
1084         if (!(gp->last_psr & psrLink)) {
1085                 err("%s: Link down, pkt dropped.\n", __FUNCTION__);
1086                 gp->stats.tx_dropped++;
1087                 spin_unlock_irqrestore(&gp->lock, flags);
1088                 return 1;
1089         }
1090
1091         if (dma32_to_cpu(gp->tx_ring[nextIn].cmdstat) & txOwn) {
1092                 err("%s: device owns descriptor, pkt dropped.\n", __FUNCTION__);
1093                 gp->stats.tx_dropped++;
1094                 // stop the queue, so Tx timeout can fix it
1095                 netif_stop_queue(dev);
1096                 spin_unlock_irqrestore(&gp->lock, flags);
1097                 return 1;
1098         }
1099
1100         // Prepare the Descriptor at tx_next_in
1101         gp->tx_skbuff[nextIn] = skb;
1102         gp->tx_ring[nextIn].byte_cnt = cpu_to_dma16(skb->len);
1103         gp->tx_ring[nextIn].buff_ptr = cpu_to_dma32(virt_to_phys(skb->data));
1104         // make sure packet gets written back to memory
1105         dma_cache_wback_inv((unsigned long)(skb->data), skb->len);
1106         // Give ownership to device, set first and last desc, enable interrupt
1107         // Setting of ownership bit must be *last*!
1108         gp->tx_ring[nextIn].cmdstat =
1109                 cpu_to_dma32((u32)(txOwn | txGenCRC | txEI |
1110                                    txPad | txFirst | txLast));
1111
1112         dump_tx_desc(4, dev, nextIn);
1113         dump_skb(4, dev, skb);
1114
1115         // increment tx_next_in with wrap
1116         gp->tx_next_in = (nextIn + 1) % TX_RING_SIZE;
1117         // If DMA is stopped, restart
1118         if (!(GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS) & psrTxLow))
1119                 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM,
1120                                  sdcmrERD | sdcmrTXDL);
1121
1122         // increment count and stop queue if full
1123         if (++gp->tx_count == TX_RING_SIZE) {
1124                 gp->tx_full = 1;
1125                 netif_stop_queue(dev);
1126                 dbg(2, "Tx Ring now full, queue stopped.\n");
1127         }
1128
1129         dev->trans_start = jiffies;
1130         spin_unlock_irqrestore(&gp->lock, flags);
1131
1132         return 0;
1133 }
1134
1135
1136 static int
1137 gt96100_rx(struct net_device *dev, u32 status)
1138 {
1139         struct gt96100_private *gp = netdev_priv(dev);
1140         struct sk_buff *skb;
1141         int pkt_len, nextOut, cdp;
1142         gt96100_rd_t *rd;
1143         u32 cmdstat;
1144
1145         dbg(3, "%s: dev=%p, status=%x\n", __FUNCTION__, dev, status);
1146
1147         cdp = (GT96100ETH_READ(gp, GT96100_ETH_1ST_RX_DESC_PTR0)
1148                - gp->rx_ring_dma) / sizeof(gt96100_rd_t);
1149
1150         // Continue until we reach 1st descriptor pointer
1151         for (nextOut = gp->rx_next_out; nextOut != cdp;
1152              nextOut = (nextOut + 1) % RX_RING_SIZE) {
1153
1154                 if (--gp->intr_work_done == 0)
1155                         break;
1156
1157                 rd = &gp->rx_ring[nextOut];
1158                 cmdstat = dma32_to_cpu(rd->cmdstat);
1159
1160                 dbg(4, "%s: Rx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__,
1161                     cmdstat, nextOut);
1162
1163                 if (cmdstat & (u32)rxOwn) {
1164                         //err("%s: device owns descriptor!\n", __FUNCTION__);
1165                         // DMA is not finished updating descriptor???
1166                         // Leave and come back later to pick-up where
1167                         // we left off.
1168                         break;
1169                 }
1170
1171                 // Drop this received pkt if there were any errors
1172                 if (((cmdstat & (u32)(rxErrorSummary)) &&
1173                      (cmdstat & (u32)(rxFirst))) || (status & icrRxError)) {
1174                         // update the detailed rx error counters that
1175                         // are not covered by the MIB counters.
1176                         if (cmdstat & (u32)rxOverrun)
1177                                 gp->stats.rx_fifo_errors++;
1178                         cmdstat |= (u32)rxOwn;
1179                         rd->cmdstat = cpu_to_dma32(cmdstat);
1180                         continue;
1181                 }
1182
1183                 /*
1184                  * Must be first and last (ie only) descriptor of packet. We
1185                  * ignore (drop) any packets that do not fit in one descriptor.
1186                  * Every descriptor's receive buffer is large enough to hold
1187                  * the maximum 802.3 frame size, so a multi-descriptor packet
1188                  * indicates an error. Most if not all corrupted packets will
1189                  * have already been dropped by the above check for the
1190                  * rxErrorSummary status bit.
1191                  */
1192                 if (!(cmdstat & (u32)rxFirst) || !(cmdstat & (u32)rxLast)) {
1193                         if (cmdstat & (u32)rxFirst) {
1194                                 /*
1195                                  * This is the first descriptor of a
1196                                  * multi-descriptor packet. It isn't corrupted
1197                                  * because the above check for rxErrorSummary
1198                                  * would have dropped it already, so what's
1199                                  * the deal with this packet? Good question,
1200                                  * let's dump it out.
1201                                  */
1202                                 err("%s: desc not first and last!\n", __FUNCTION__);
1203                                 dump_rx_desc(0, dev, nextOut);
1204                         }
1205                         cmdstat |= (u32)rxOwn;
1206                         rd->cmdstat = cpu_to_dma32(cmdstat);
1207                         // continue to drop every descriptor of this packet
1208                         continue;
1209                 }
1210
1211                 pkt_len = dma16_to_cpu(rd->byte_cnt);
1212
1213                 /* Create new skb. */
1214                 skb = dev_alloc_skb(pkt_len+2);
1215                 if (skb == NULL) {
1216                         err("%s: Memory squeeze, dropping packet.\n", __FUNCTION__);
1217                         gp->stats.rx_dropped++;
1218                         cmdstat |= (u32)rxOwn;
1219                         rd->cmdstat = cpu_to_dma32(cmdstat);
1220                         continue;
1221                 }
1222                 skb->dev = dev;
1223                 skb_reserve(skb, 2);   /* 16 byte IP header align */
1224                 memcpy(skb_put(skb, pkt_len),
1225                        &gp->rx_buff[nextOut*PKT_BUF_SZ], pkt_len);
1226                 skb->protocol = eth_type_trans(skb, dev);
1227                 dump_skb(4, dev, skb);
1228
1229                 netif_rx(skb);        /* pass the packet to upper layers */
1230                 dev->last_rx = jiffies;
1231
1232                 // now we can release ownership of this desc back to device
1233                 cmdstat |= (u32)rxOwn;
1234                 rd->cmdstat = cpu_to_dma32(cmdstat);
1235         }
1236
1237         if (nextOut == gp->rx_next_out)
1238                 dbg(3, "%s: RxCDP did not increment?\n", __FUNCTION__);
1239
1240         gp->rx_next_out = nextOut;
1241         return 0;
1242 }
1243
1244
1245 static void
1246 gt96100_tx_complete(struct net_device *dev, u32 status)
1247 {
1248         struct gt96100_private *gp = netdev_priv(dev);
1249         int nextOut, cdp;
1250         gt96100_td_t *td;
1251         u32 cmdstat;
1252
1253         cdp = (GT96100ETH_READ(gp, GT96100_ETH_CURR_TX_DESC_PTR0)
1254                - gp->tx_ring_dma) / sizeof(gt96100_td_t);
1255
1256         // Continue until we reach the current descriptor pointer
1257         for (nextOut = gp->tx_next_out; nextOut != cdp;
1258              nextOut = (nextOut + 1) % TX_RING_SIZE) {
1259
1260                 if (--gp->intr_work_done == 0)
1261                         break;
1262
1263                 td = &gp->tx_ring[nextOut];
1264                 cmdstat = dma32_to_cpu(td->cmdstat);
1265
1266                 dbg(3, "%s: Tx desc cmdstat=%x, nextOut=%d\n", __FUNCTION__,
1267                     cmdstat, nextOut);
1268
1269                 if (cmdstat & (u32)txOwn) {
1270                         /*
1271                          * DMA is not finished writing descriptor???
1272                          * Leave and come back later to pick-up where
1273                          * we left off.
1274                          */
1275                         break;
1276                 }
1277
1278                 // increment Tx error stats
1279                 if (cmdstat & (u32)txErrorSummary) {
1280                         dbg(2, "%s: Tx error, cmdstat = %x\n", __FUNCTION__,
1281                             cmdstat);
1282                         gp->stats.tx_errors++;
1283                         if (cmdstat & (u32)txReTxLimit)
1284                                 gp->stats.tx_aborted_errors++;
1285                         if (cmdstat & (u32)txUnderrun)
1286                                 gp->stats.tx_fifo_errors++;
1287                         if (cmdstat & (u32)txLateCollision)
1288                                 gp->stats.tx_window_errors++;
1289                 }
1290
1291                 if (cmdstat & (u32)txCollision)
1292                         gp->stats.collisions +=
1293                                 (u32)((cmdstat & txReTxCntMask) >>
1294                                       txReTxCntBit);
1295
1296                 // Wake the queue if the ring was full
1297                 if (gp->tx_full) {
1298                         gp->tx_full = 0;
1299                         if (gp->last_psr & psrLink) {
1300                                 netif_wake_queue(dev);
1301                                 dbg(2, "%s: Tx Ring was full, queue waked\n",
1302                                     __FUNCTION__);
1303                         }
1304                 }
1305
1306                 // decrement tx ring buffer count
1307                 if (gp->tx_count) gp->tx_count--;
1308
1309                 // free the skb
1310                 if (gp->tx_skbuff[nextOut]) {
1311                         dbg(3, "%s: good Tx, skb=%p\n", __FUNCTION__,
1312                             gp->tx_skbuff[nextOut]);
1313                         dev_kfree_skb_irq(gp->tx_skbuff[nextOut]);
1314                         gp->tx_skbuff[nextOut] = NULL;
1315                 } else {
1316                         err("%s: no skb!\n", __FUNCTION__);
1317                 }
1318         }
1319
1320         gp->tx_next_out = nextOut;
1321
1322         if (gt96100_check_tx_consistent(gp)) {
1323                 err("%s: Tx queue inconsistent!\n", __FUNCTION__);
1324         }
1325
1326         if ((status & icrTxEndLow) && gp->tx_count != 0) {
1327                 // we must restart the DMA
1328                 dbg(3, "%s: Restarting Tx DMA\n", __FUNCTION__);
1329                 GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM,
1330                                  sdcmrERD | sdcmrTXDL);
1331         }
1332 }
1333
1334
1335 static irqreturn_t
1336 gt96100_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1337 {
1338         struct net_device *dev = (struct net_device *)dev_id;
1339         struct gt96100_private *gp = netdev_priv(dev);
1340         u32 status;
1341         int handled = 0;
1342
1343         if (dev == NULL) {
1344                 err("%s: null dev ptr\n", __FUNCTION__);
1345                 return IRQ_NONE;
1346         }
1347
1348         dbg(3, "%s: entry, icr=%x\n", __FUNCTION__,
1349             GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE));
1350
1351         spin_lock(&gp->lock);
1352
1353         gp->intr_work_done = max_interrupt_work;
1354
1355         while (gp->intr_work_done > 0) {
1356
1357                 status = GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE);
1358                 // ACK interrupts
1359                 GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, ~status);
1360
1361                 if ((status & icrEtherIntSum) == 0 &&
1362                     !(status & (icrTxBufferLow|icrTxBufferHigh|icrRxBuffer)))
1363                         break;
1364
1365                 handled = 1;
1366
1367                 if (status & icrMIIPhySTC) {
1368                         u32 psr = GT96100ETH_READ(gp, GT96100_ETH_PORT_STATUS);
1369                         if (gp->last_psr != psr) {
1370                                 dbg(0, "port status:\n");
1371                                 dbg(0, "    %s MBit/s, %s-duplex, "
1372                                     "flow-control %s, link is %s,\n",
1373                                     psr & psrSpeed ? "100":"10",
1374                                     psr & psrDuplex ? "full":"half",
1375                                     psr & psrFctl ? "disabled":"enabled",
1376                                     psr & psrLink ? "up":"down");
1377                                 dbg(0, "    TxLowQ is %s, TxHighQ is %s, "
1378                                     "Transmitter is %s\n",
1379                                     psr & psrTxLow ? "running":"stopped",
1380                                     psr & psrTxHigh ? "running":"stopped",
1381                                     psr & psrTxInProg ? "on":"off");
1382
1383                                 if ((psr & psrLink) && !gp->tx_full &&
1384                                     netif_queue_stopped(dev)) {
1385                                         dbg(0, "%s: Link up, waking queue.\n",
1386                                             __FUNCTION__);
1387                                         netif_wake_queue(dev);
1388                                 } else if (!(psr & psrLink) &&
1389                                            !netif_queue_stopped(dev)) {
1390                                         dbg(0, "%s: Link down, stopping queue.\n",
1391                                             __FUNCTION__);
1392                                         netif_stop_queue(dev);
1393                                 }
1394
1395                                 gp->last_psr = psr;
1396                         }
1397
1398                         if (--gp->intr_work_done == 0)
1399                                 break;
1400                 }
1401
1402                 if (status & (icrTxBufferLow | icrTxEndLow))
1403                         gt96100_tx_complete(dev, status);
1404
1405                 if (status & (icrRxBuffer | icrRxError)) {
1406                         gt96100_rx(dev, status);
1407                 }
1408
1409                 // Now check TX errors (RX errors were handled in gt96100_rx)
1410                 if (status & icrTxErrorLow) {
1411                         err("%s: Tx resource error\n", __FUNCTION__);
1412                         if (--gp->intr_work_done == 0)
1413                                 break;
1414                 }
1415
1416                 if (status & icrTxUdr) {
1417                         err("%s: Tx underrun error\n", __FUNCTION__);
1418                         if (--gp->intr_work_done == 0)
1419                                 break;
1420                 }
1421         }
1422
1423         if (gp->intr_work_done == 0) {
1424                 // ACK any remaining pending interrupts
1425                 GT96100ETH_WRITE(gp, GT96100_ETH_INT_CAUSE, 0);
1426                 dbg(3, "%s: hit max work\n", __FUNCTION__);
1427         }
1428
1429         dbg(3, "%s: exit, icr=%x\n", __FUNCTION__,
1430             GT96100ETH_READ(gp, GT96100_ETH_INT_CAUSE));
1431
1432         spin_unlock(&gp->lock);
1433         return IRQ_RETVAL(handled);
1434 }
1435
1436
1437 static void
1438 gt96100_tx_timeout(struct net_device *dev)
1439 {
1440         struct gt96100_private *gp = netdev_priv(dev);
1441         unsigned long flags;
1442
1443         spin_lock_irqsave(&gp->lock, flags);
1444
1445         if (!(gp->last_psr & psrLink)) {
1446                 err("tx_timeout: link down.\n");
1447                 spin_unlock_irqrestore(&gp->lock, flags);
1448         } else {
1449                 if (gt96100_check_tx_consistent(gp))
1450                         err("tx_timeout: Tx ring error.\n");
1451
1452                 disable_ether_irq(dev);
1453                 spin_unlock_irqrestore(&gp->lock, flags);
1454                 reset_tx(dev);
1455                 enable_ether_irq(dev);
1456
1457                 netif_wake_queue(dev);
1458         }
1459 }
1460
1461
1462 static void
1463 gt96100_set_rx_mode(struct net_device *dev)
1464 {
1465         struct gt96100_private *gp = netdev_priv(dev);
1466         unsigned long flags;
1467         //struct dev_mc_list *mcptr;
1468
1469         dbg(3, "%s: dev=%p, flags=%x\n", __FUNCTION__, dev, dev->flags);
1470
1471         // stop the Receiver DMA
1472         abort(dev, sdcmrAR);
1473
1474         spin_lock_irqsave(&gp->lock, flags);
1475
1476         if (dev->flags & IFF_PROMISC) {
1477                 GT96100ETH_WRITE(gp, GT96100_ETH_PORT_CONFIG,
1478                                  pcrEN | pcrHS | pcrPM);
1479         }
1480
1481 #if 0
1482         /*
1483           FIXME: currently multicast doesn't work - need to get hash table
1484           working first.
1485         */
1486         if (dev->mc_count) {
1487                 // clear hash table
1488                 memset(gp->hash_table, 0, RX_HASH_TABLE_SIZE);
1489                 // Add our ethernet address
1490                 gt96100_add_hash_entry(dev, dev->dev_addr);
1491
1492                 for (mcptr = dev->mc_list; mcptr; mcptr = mcptr->next) {
1493                         dump_hw_addr(2, dev, __FUNCTION__ ": addr=",
1494                                      mcptr->dmi_addr);
1495                         gt96100_add_hash_entry(dev, mcptr->dmi_addr);
1496                 }
1497         }
1498 #endif
1499
1500         // restart Rx DMA
1501         GT96100ETH_WRITE(gp, GT96100_ETH_SDMA_COMM, sdcmrERD);
1502
1503         spin_unlock_irqrestore(&gp->lock, flags);
1504 }
1505
1506 static struct net_device_stats *
1507 gt96100_get_stats(struct net_device *dev)
1508 {
1509         struct gt96100_private *gp = netdev_priv(dev);
1510         unsigned long flags;
1511
1512         dbg(3, "%s: dev=%p\n", __FUNCTION__, dev);
1513
1514         if (netif_device_present(dev)) {
1515                 spin_lock_irqsave (&gp->lock, flags);
1516                 update_stats(gp);
1517                 spin_unlock_irqrestore (&gp->lock, flags);
1518         }
1519
1520         return &gp->stats;
1521 }
1522
1523 static void gt96100_cleanup_module(void)
1524 {
1525         int i;
1526         for (i=0; i<NUM_INTERFACES; i++) {
1527                 struct gt96100_if_t *gtif = &gt96100_iflist[i];
1528                 if (gtif->dev != NULL) {
1529                         struct gt96100_private *gp = (struct gt96100_private *)
1530                                 netdev_priv(gtif->dev);
1531                         unregister_netdev(gtif->dev);
1532                         dmafree(RX_HASH_TABLE_SIZE, gp->hash_table_dma);
1533                         dmafree(PKT_BUF_SZ*RX_RING_SIZE, gp->rx_buff);
1534                         dmafree(sizeof(gt96100_rd_t) * RX_RING_SIZE
1535                                 + sizeof(gt96100_td_t) * TX_RING_SIZE,
1536                                 gp->rx_ring);
1537                         free_netdev(gtif->dev);
1538                         release_region(gtif->iobase, gp->io_size);
1539                 }
1540         }
1541 }
1542
1543 static int __init gt96100_setup(char *options)
1544 {
1545         char *this_opt;
1546
1547         if (!options || !*options)
1548                 return 0;
1549
1550         while ((this_opt = strsep (&options, ",")) != NULL) {
1551                 if (!*this_opt)
1552                         continue;
1553                 if (!strncmp(this_opt, "mac0:", 5)) {
1554                         memcpy(mac0, this_opt+5, 17);
1555                         mac0[17]= '\0';
1556                 } else if (!strncmp(this_opt, "mac1:", 5)) {
1557                         memcpy(mac1, this_opt+5, 17);
1558                         mac1[17]= '\0';
1559                 }
1560         }
1561
1562         return 1;
1563 }
1564
1565 __setup("gt96100eth=", gt96100_setup);
1566
1567 module_init(gt96100_init_module);
1568 module_exit(gt96100_cleanup_module);
1569
1570 MODULE_AUTHOR("Steve Longerbeam <stevel@mvista.com>");
1571 MODULE_DESCRIPTION("GT96100 Ethernet driver");