drivers/net/irda/smsc-ircc2.c

   1 /*********************************************************************
   2  * $Id: smsc-ircc2.c,v 1.19.2.5 2002/10/27 11:34:26 dip Exp $
   3  *
   4  * Description:   Driver for the SMC Infrared Communications Controller
   5  * Status:        Experimental.
   6  * Author:        Daniele Peri (peri@csai.unipa.it)
   7  * Created at:
   8  * Modified at:
   9  * Modified by:
  10  *
  11  *     Copyright (c) 2002      Daniele Peri
  12  *     All Rights Reserved.
  13  *     Copyright (c) 2002      Jean Tourrilhes
  14  *
  15  *
  16  * Based on smc-ircc.c:
  17  *
  18  *     Copyright (c) 2001      Stefani Seibold
  19  *     Copyright (c) 1999-2001 Dag Brattli
  20  *     Copyright (c) 1998-1999 Thomas Davis,
  21  *
  22  *      and irport.c:
  23  *
  24  *     Copyright (c) 1997, 1998, 1999-2000 Dag Brattli, All Rights Reserved.
  25  *
  26  *
  27  *     This program is free software; you can redistribute it and/or
  28  *     modify it under the terms of the GNU General Public License as
  29  *     published by the Free Software Foundation; either version 2 of
  30  *     the License, or (at your option) any later version.
  31  *
  32  *     This program is distributed in the hope that it will be useful,
  33  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  34  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  35  *     GNU General Public License for more details.
  36  *
  37  *     You should have received a copy of the GNU General Public License
  38  *     along with this program; if not, write to the Free Software
  39  *     Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  40  *     MA 02111-1307 USA
  41  *
  42  ********************************************************************/
  43
  44 #include <linux/module.h>
  45 #include <linux/kernel.h>
  46 #include <linux/types.h>
  47 #include <linux/skbuff.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/ioport.h>
  50 #include <linux/delay.h>
  51 #include <linux/slab.h>
  52 #include <linux/init.h>
  53 #include <linux/rtnetlink.h>
  54 #include <linux/serial_reg.h>
  55
  56 #include <asm/io.h>
  57 #include <asm/dma.h>
  58 #include <asm/byteorder.h>
  59
  60 #include <linux/spinlock.h>
  61 #include <linux/pm.h>
  62
  63 #include <net/irda/wrapper.h>
  64 #include <net/irda/irda.h>
  65 #include <net/irda/irda_device.h>
  66
  67 #include "smsc-ircc2.h"
  68 #include "smsc-sio.h"
  69
  70 /* Types */
  71
  72 struct smsc_transceiver {
  73         char *name;
  74         void (*set_for_speed)(int fir_base, u32 speed);
  75         int  (*probe)(int fir_base);
  76 };
  77 typedef struct smsc_transceiver smsc_transceiver_t;
  78
  79 #if 0
  80 struct smc_chip {
  81         char *name;
  82         u16 flags;
  83         u8 devid;
  84         u8 rev;
  85 };
  86 typedef struct smc_chip smc_chip_t;
  87 #endif
  88
  89 struct smsc_chip {
  90         char *name;
  91         #if 0
  92         u8      type;
  93         #endif
  94         u16 flags;
  95         u8 devid;
  96         u8 rev;
  97 };
  98 typedef struct smsc_chip smsc_chip_t;
  99
 100 struct smsc_chip_address {
 101         unsigned int cfg_base;
 102         unsigned int type;
 103 };
 104 typedef struct smsc_chip_address smsc_chip_address_t;
 105
 106 /* Private data for each instance */
 107 struct smsc_ircc_cb {
 108         struct net_device *netdev;     /* Yes! we are some kind of netdevice */
 109         struct net_device_stats stats;
 110         struct irlap_cb    *irlap; /* The link layer we are binded to */
 111
 112         chipio_t io;               /* IrDA controller information */
 113         iobuff_t tx_buff;          /* Transmit buffer */
 114         iobuff_t rx_buff;          /* Receive buffer */
 115
 116         struct qos_info qos;       /* QoS capabilities for this device */
 117
 118         spinlock_t lock;           /* For serializing operations */
 119
 120         __u32 new_speed;
 121         __u32 flags;               /* Interface flags */
 122
 123         int tx_buff_offsets[10];   /* Offsets between frames in tx_buff */
 124         int tx_len;                /* Number of frames in tx_buff */
 125
 126         int transceiver;
 127         struct pm_dev *pmdev;
 128 };
 129
 130 /* Constants */
 131
 132 static const char *driver_name = "smsc-ircc2";
 133 #define DIM(x)  (sizeof(x)/(sizeof(*(x))))
 134 #define SMSC_IRCC2_C_IRDA_FALLBACK_SPEED        9600
 135 #define SMSC_IRCC2_C_DEFAULT_TRANSCEIVER        1
 136 #define SMSC_IRCC2_C_NET_TIMEOUT                        0
 137 #define SMSC_IRCC2_C_SIR_STOP                   0
 138
 139 /* Prototypes */
 140
 141 static int smsc_ircc_open(unsigned int firbase, unsigned int sirbase, u8 dma, u8 irq);
 142 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base);
 143 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self, unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq);
 144 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self);
 145 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self);
 146 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self);
 147 static int  smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase);
 148 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase);
 149 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self);
 150 static int  smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev);
 151 static int  smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev);
 152 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs);
 153 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase);
 154 static void smsc_ircc_change_speed(void *priv, u32 speed);
 155 static void smsc_ircc_set_sir_speed(void *priv, u32 speed);
 156 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 157 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev);
 158 static void smsc_ircc_sir_start(struct smsc_ircc_cb *self);
 159 #if SMSC_IRCC2_C_SIR_STOP
 160 static void smsc_ircc_sir_stop(struct smsc_ircc_cb *self);
 161 #endif
 162 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self);
 163 static int  smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len);
 164 static int  smsc_ircc_net_open(struct net_device *dev);
 165 static int  smsc_ircc_net_close(struct net_device *dev);
 166 static int  smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 167 #if SMSC_IRCC2_C_NET_TIMEOUT
 168 static void smsc_ircc_timeout(struct net_device *dev);
 169 #endif
 170 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev);
 171 static int  smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
 172 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self);
 173 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self);
 174 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed);
 175 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self);
 176
 177 /* Probing */
 178 static int __init smsc_ircc_look_for_chips(void);
 179 static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg,const smsc_chip_t *chip,char *type);
 180 static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfg_base, char *type);
 181 static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type);
 182 static int __init smsc_superio_fdc(unsigned short cfg_base);
 183 static int __init smsc_superio_lpc(unsigned short cfg_base);
 184
 185 /* Transceivers specific functions */
 186
 187 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed);
 188 static int  smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base);
 189 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed);
 190 static int  smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base);
 191 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed);
 192 static int  smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base);
 193
 194 /* Power Management */
 195
 196 static void smsc_ircc_suspend(struct smsc_ircc_cb *self);
 197 static void smsc_ircc_wakeup(struct smsc_ircc_cb *self);
 198 static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data);
 199
 200
 201 /* Transceivers for SMSC-ircc */
 202
 203 smsc_transceiver_t smsc_transceivers[]=
 204 {
 205         { "Toshiba Satellite 1800 (GP data pin select)", smsc_ircc_set_transceiver_toshiba_sat1800, smsc_ircc_probe_transceiver_toshiba_sat1800},
 206         { "Fast pin select", smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select, smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select},
 207         { "ATC IRMode", smsc_ircc_set_transceiver_smsc_ircc_atc, smsc_ircc_probe_transceiver_smsc_ircc_atc},
 208         { NULL, NULL}
 209 };
 210 #define SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS (DIM(smsc_transceivers)-1)
 211
 212 /*  SMC SuperIO chipsets definitions */
 213
 214 #define KEY55_1 0       /* SuperIO Configuration mode with Key <0x55> */
 215 #define KEY55_2 1       /* SuperIO Configuration mode with Key <0x55,0x55> */
 216 #define NoIRDA  2       /* SuperIO Chip has no IRDA Port */
 217 #define SIR     0       /* SuperIO Chip has only slow IRDA */
 218 #define FIR     4       /* SuperIO Chip has fast IRDA */
 219 #define SERx4   8       /* SuperIO Chip supports 115,2 KBaud * 4=460,8 KBaud */
 220
 221 static smsc_chip_t __initdata fdc_chips_flat[]=
 222 {
 223         /* Base address 0x3f0 or 0x370 */
 224         { "37C44",      KEY55_1|NoIRDA,         0x00, 0x00 }, /* This chip cannot be detected */
 225         { "37C665GT",   KEY55_2|NoIRDA,         0x65, 0x01 },
 226         { "37C665GT",   KEY55_2|NoIRDA,         0x66, 0x01 },
 227         { "37C669",     KEY55_2|SIR|SERx4,      0x03, 0x02 },
 228         { "37C669",     KEY55_2|SIR|SERx4,      0x04, 0x02 }, /* ID? */
 229         { "37C78",      KEY55_2|NoIRDA,         0x78, 0x00 },
 230         { "37N769",     KEY55_1|FIR|SERx4,      0x28, 0x00 },
 231         { "37N869",     KEY55_1|FIR|SERx4,      0x29, 0x00 },
 232         { NULL }
 233 };
 234
 235 static smsc_chip_t __initdata fdc_chips_paged[]=
 236 {
 237         /* Base address 0x3f0 or 0x370 */
 238         { "37B72X",     KEY55_1|SIR|SERx4,      0x4c, 0x00 },
 239         { "37B77X",     KEY55_1|SIR|SERx4,      0x43, 0x00 },
 240         { "37B78X",     KEY55_1|SIR|SERx4,      0x44, 0x00 },
 241         { "37B80X",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 242         { "37C67X",     KEY55_1|FIR|SERx4,      0x40, 0x00 },
 243         { "37C93X",     KEY55_2|SIR|SERx4,      0x02, 0x01 },
 244         { "37C93XAPM",  KEY55_1|SIR|SERx4,      0x30, 0x01 },
 245         { "37C93XFR",   KEY55_2|FIR|SERx4,      0x03, 0x01 },
 246         { "37M707",     KEY55_1|SIR|SERx4,      0x42, 0x00 },
 247         { "37M81X",     KEY55_1|SIR|SERx4,      0x4d, 0x00 },
 248         { "37N958FR",   KEY55_1|FIR|SERx4,      0x09, 0x04 },
 249         { "37N971",     KEY55_1|FIR|SERx4,      0x0a, 0x00 },
 250         { "37N972",     KEY55_1|FIR|SERx4,      0x0b, 0x00 },
 251         { NULL }
 252 };
 253
 254 static smsc_chip_t __initdata lpc_chips_flat[]=
 255 {
 256         /* Base address 0x2E or 0x4E */
 257         { "47N227",     KEY55_1|FIR|SERx4,      0x5a, 0x00 },
 258         { "47N267",     KEY55_1|FIR|SERx4,      0x5e, 0x00 },
 259         { NULL }
 260 };
 261
 262 static smsc_chip_t __initdata lpc_chips_paged[]=
 263 {
 264         /* Base address 0x2E or 0x4E */
 265         { "47B27X",     KEY55_1|SIR|SERx4,      0x51, 0x00 },
 266         { "47B37X",     KEY55_1|SIR|SERx4,      0x52, 0x00 },
 267         { "47M10X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 268         { "47M120",     KEY55_1|NoIRDA|SERx4,   0x5c, 0x00 },
 269         { "47M13X",     KEY55_1|SIR|SERx4,      0x59, 0x00 },
 270         { "47M14X",     KEY55_1|SIR|SERx4,      0x5f, 0x00 },
 271         { "47N252",     KEY55_1|FIR|SERx4,      0x0e, 0x00 },
 272         { "47S42X",     KEY55_1|SIR|SERx4,      0x57, 0x00 },
 273         { NULL }
 274 };
 275
 276 #define SMSCSIO_TYPE_FDC        1
 277 #define SMSCSIO_TYPE_LPC        2
 278 #define SMSCSIO_TYPE_FLAT       4
 279 #define SMSCSIO_TYPE_PAGED      8
 280
 281 static smsc_chip_address_t __initdata possible_addresses[]=
 282 {
 283         {0x3f0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
 284         {0x370, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
 285         {0xe0, SMSCSIO_TYPE_FDC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
 286         {0x2e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
 287         {0x4e, SMSCSIO_TYPE_LPC|SMSCSIO_TYPE_FLAT|SMSCSIO_TYPE_PAGED},
 288         {0,0}
 289 };
 290
 291 /* Globals */
 292
 293 static struct smsc_ircc_cb *dev_self[] = { NULL, NULL};
 294
 295 static int ircc_irq=255;
 296 static int ircc_dma=255;
 297 static int ircc_fir=0;
 298 static int ircc_sir=0;
 299 static int ircc_cfg=0;
 300 static int ircc_transceiver=0;
 301
 302 static unsigned short   dev_count=0;
 303
 304 static inline void register_bank(int iobase, int bank)
 305 {
 306         outb(((inb(iobase+IRCC_MASTER) & 0xf0) | (bank & 0x07)),
 307                iobase+IRCC_MASTER);
 308 }
 309
 310
 311 /*******************************************************************************
 312  *
 313  *
 314  * SMSC-ircc stuff
 315  *
 316  *
 317  *******************************************************************************/
 318
 319 /*
 320  * Function smsc_ircc_init ()
 321  *
 322  *    Initialize chip. Just try to find out how many chips we are dealing with
 323  *    and where they are
 324  */
 325 static int __init smsc_ircc_init(void)
 326 {
 327         int ret=-ENODEV;
 328
 329         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 330
 331         dev_count=0;
 332
 333         if ((ircc_fir>0)&&(ircc_sir>0)) {
 334                 MESSAGE(" Overriding FIR address 0x%04x\n", ircc_fir);
 335                 MESSAGE(" Overriding SIR address 0x%04x\n", ircc_sir);
 336
 337                 if (smsc_ircc_open(ircc_fir, ircc_sir, ircc_dma, ircc_irq) == 0)
 338                         return 0;
 339
 340                 return -ENODEV;
 341         }
 342
 343         /* try user provided configuration register base address */
 344         if (ircc_cfg>0) {
 345                 MESSAGE(" Overriding configuration address 0x%04x\n", ircc_cfg);
 346                 if (!smsc_superio_fdc(ircc_cfg))
 347                         ret = 0;
 348                 if (!smsc_superio_lpc(ircc_cfg))
 349                         ret = 0;
 350         }
 351
 352         if(smsc_ircc_look_for_chips()>0) ret = 0;
 353
 354         return ret;
 355 }
 356
 357 /*
 358  * Function smsc_ircc_open (firbase, sirbase, dma, irq)
 359  *
 360  *    Try to open driver instance
 361  *
 362  */
 363 static int __init smsc_ircc_open(unsigned int fir_base, unsigned int sir_base, u8 dma, u8 irq)
 364 {
 365         struct smsc_ircc_cb *self;
 366         struct net_device *dev;
 367         int err;
 368
 369         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 370
 371         err = smsc_ircc_present(fir_base, sir_base);
 372         if(err)
 373                 goto err_out;
 374
 375         err = -ENOMEM;
 376         if (dev_count > DIM(dev_self)) {
 377                 WARNING("%s(), too many devices!\n", __FUNCTION__);
 378                 goto err_out1;
 379         }
 380
 381         /*
 382          *  Allocate new instance of the driver
 383          */
 384         dev = alloc_irdadev(sizeof(struct smsc_ircc_cb));
 385         if (!dev) {
 386                 WARNING("%s() can't allocate net device\n", __FUNCTION__);
 387                 goto err_out1;
 388         }
 389
 390         SET_MODULE_OWNER(dev);
 391
 392         dev->hard_start_xmit = smsc_ircc_hard_xmit_sir;
 393 #if SMSC_IRCC2_C_NET_TIMEOUT
 394         dev->tx_timeout      = smsc_ircc_timeout;
 395         dev->watchdog_timeo  = HZ*2;  /* Allow enough time for speed change */
 396 #endif
 397         dev->open            = smsc_ircc_net_open;
 398         dev->stop            = smsc_ircc_net_close;
 399         dev->do_ioctl        = smsc_ircc_net_ioctl;
 400         dev->get_stats       = smsc_ircc_net_get_stats;
 401
 402         self = dev->priv;
 403         self->netdev = dev;
 404
 405         /* Make ifconfig display some details */
 406         dev->base_addr = self->io.fir_base = fir_base;
 407         dev->irq = self->io.irq = irq;
 408
 409         /* Need to store self somewhere */
 410         dev_self[dev_count++] = self;
 411         spin_lock_init(&self->lock);
 412
 413         self->rx_buff.truesize = SMSC_IRCC2_RX_BUFF_TRUESIZE;
 414         self->tx_buff.truesize = SMSC_IRCC2_TX_BUFF_TRUESIZE;
 415
 416         self->rx_buff.head = (u8 *) kmalloc(self->rx_buff.truesize,
 417                                               GFP_KERNEL|GFP_DMA);
 418         if (self->rx_buff.head == NULL) {
 419                 ERROR("%s, Can't allocate memory for receive buffer!\n",
 420                       driver_name);
 421                 goto err_out2;
 422         }
 423
 424         self->tx_buff.head = (u8 *) kmalloc(self->tx_buff.truesize,
 425                                               GFP_KERNEL|GFP_DMA);
 426         if (self->tx_buff.head == NULL) {
 427                 ERROR("%s, Can't allocate memory for transmit buffer!\n",
 428                       driver_name);
 429                 goto err_out3;
 430         }
 431
 432         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 433         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 434
 435         self->rx_buff.in_frame = FALSE;
 436         self->rx_buff.state = OUTSIDE_FRAME;
 437         self->tx_buff.data = self->tx_buff.head;
 438         self->rx_buff.data = self->rx_buff.head;
 439
 440         smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq);
 441
 442         smsc_ircc_setup_qos(self);
 443
 444         smsc_ircc_init_chip(self);
 445
 446         if(ircc_transceiver > 0  &&
 447            ircc_transceiver < SMSC_IRCC2_C_NUMBER_OF_TRANSCEIVERS)
 448                 self->transceiver = ircc_transceiver;
 449         else
 450                 smsc_ircc_probe_transceiver(self);
 451
 452         err = register_netdev(self->netdev);
 453         if(err) {
 454                 ERROR("%s, Network device registration failed!\n",
 455                       driver_name);
 456                 goto err_out4;
 457         }
 458
 459         self->pmdev = pm_register(PM_SYS_DEV, PM_SYS_IRDA, smsc_ircc_pmproc);
 460         if (self->pmdev)
 461                 self->pmdev->data = self;
 462
 463         MESSAGE("IrDA: Registered device %s\n", dev->name);
 464
 465         return 0;
 466  err_out4:
 467         kfree(self->tx_buff.head);
 468  err_out3:
 469         kfree(self->rx_buff.head);
 470  err_out2:
 471         free_netdev(self->netdev);
 472         dev_self[--dev_count] = NULL;
 473  err_out1:
 474         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 475         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 476  err_out:
 477         return err;
 478 }
 479
 480 /*
 481  * Function smsc_ircc_present(fir_base, sir_base)
 482  *
 483  *    Check the smsc-ircc chip presence
 484  *
 485  */
 486 static int smsc_ircc_present(unsigned int fir_base, unsigned int sir_base)
 487 {
 488         unsigned char low, high, chip, config, dma, irq, version;
 489
 490         if (!request_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT,
 491                             driver_name)) {
 492                 WARNING("%s: can't get fir_base of 0x%03x\n",
 493                         __FUNCTION__, fir_base);
 494                 goto out1;
 495         }
 496
 497         if (!request_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT,
 498                             driver_name)) {
 499                 WARNING("%s: can't get sir_base of 0x%03x\n",
 500                         __FUNCTION__, sir_base);
 501                 goto out2;
 502         }
 503
 504         register_bank(fir_base, 3);
 505
 506         high    = inb(fir_base+IRCC_ID_HIGH);
 507         low     = inb(fir_base+IRCC_ID_LOW);
 508         chip    = inb(fir_base+IRCC_CHIP_ID);
 509         version = inb(fir_base+IRCC_VERSION);
 510         config  = inb(fir_base+IRCC_INTERFACE);
 511         dma     = config & IRCC_INTERFACE_DMA_MASK;
 512         irq     = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 513
 514         if (high != 0x10 || low != 0xb8 || (chip != 0xf1 && chip != 0xf2)) {
 515                 WARNING("%s(), addr 0x%04x - no device found!\n",
 516                         __FUNCTION__, fir_base);
 517                 goto out3;
 518         }
 519         MESSAGE("SMsC IrDA Controller found\n IrCC version %d.%d, "
 520                 "firport 0x%03x, sirport 0x%03x dma=%d, irq=%d\n",
 521                 chip & 0x0f, version, fir_base, sir_base, dma, irq);
 522
 523         return 0;
 524  out3:
 525         release_region(sir_base, SMSC_IRCC2_SIR_CHIP_IO_EXTENT);
 526  out2:
 527         release_region(fir_base, SMSC_IRCC2_FIR_CHIP_IO_EXTENT);
 528  out1:
 529         return -ENODEV;
 530 }
 531
 532 /*
 533  * Function smsc_ircc_setup_io(self, fir_base, sir_base, dma, irq)
 534  *
 535  *    Setup I/O
 536  *
 537  */
 538 static void smsc_ircc_setup_io(struct smsc_ircc_cb *self,
 539                                unsigned int fir_base, unsigned int sir_base,
 540                                u8 dma, u8 irq)
 541 {
 542         unsigned char config, chip_dma, chip_irq;
 543
 544         register_bank(fir_base, 3);
 545         config  = inb(fir_base+IRCC_INTERFACE);
 546         chip_dma     = config & IRCC_INTERFACE_DMA_MASK;
 547         chip_irq     = (config & IRCC_INTERFACE_IRQ_MASK) >> 4;
 548
 549         self->io.fir_base  = fir_base;
 550         self->io.sir_base  = sir_base;
 551         self->io.fir_ext   = SMSC_IRCC2_FIR_CHIP_IO_EXTENT;
 552         self->io.sir_ext   = SMSC_IRCC2_SIR_CHIP_IO_EXTENT;
 553         self->io.fifo_size = SMSC_IRCC2_FIFO_SIZE;
 554         self->io.speed = SMSC_IRCC2_C_IRDA_FALLBACK_SPEED;
 555
 556         if (irq < 255) {
 557                 if (irq != chip_irq)
 558                         MESSAGE("%s, Overriding IRQ - chip says %d, using %d\n",
 559                                 driver_name, chip_irq, irq);
 560                 self->io.irq = irq;
 561         }
 562         else
 563                 self->io.irq = chip_irq;
 564
 565         if (dma < 255) {
 566                 if (dma != chip_dma)
 567                         MESSAGE("%s, Overriding DMA - chip says %d, using %d\n",
 568                                 driver_name, chip_dma, dma);
 569                 self->io.dma = dma;
 570         }
 571         else
 572                 self->io.dma = chip_dma;
 573
 574 }
 575
 576 /*
 577  * Function smsc_ircc_setup_qos(self)
 578  *
 579  *    Setup qos
 580  *
 581  */
 582 static void smsc_ircc_setup_qos(struct smsc_ircc_cb *self)
 583 {
 584         /* Initialize QoS for this device */
 585         irda_init_max_qos_capabilies(&self->qos);
 586
 587         self->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600|
 588                 IR_115200|IR_576000|IR_1152000|(IR_4000000 << 8);
 589
 590         self->qos.min_turn_time.bits = SMSC_IRCC2_MIN_TURN_TIME;
 591         self->qos.window_size.bits = SMSC_IRCC2_WINDOW_SIZE;
 592         irda_qos_bits_to_value(&self->qos);
 593 }
 594
 595 /*
 596  * Function smsc_ircc_init_chip(self)
 597  *
 598  *    Init chip
 599  *
 600  */
 601 static void smsc_ircc_init_chip(struct smsc_ircc_cb *self)
 602 {
 603         int iobase, ir_mode, ctrl, fast;
 604
 605         ASSERT( self != NULL, return; );
 606         iobase = self->io.fir_base;
 607
 608         ir_mode = IRCC_CFGA_IRDA_SIR_A;
 609         ctrl = 0;
 610         fast = 0;
 611
 612         register_bank(iobase, 0);
 613         outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER);
 614         outb(0x00, iobase+IRCC_MASTER);
 615
 616         register_bank(iobase, 1);
 617         outb(((inb(iobase+IRCC_SCE_CFGA) & 0x87) | ir_mode),
 618              iobase+IRCC_SCE_CFGA);
 619
 620 #ifdef smsc_669 /* Uses pin 88/89 for Rx/Tx */
 621         outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
 622              iobase+IRCC_SCE_CFGB);
 623 #else
 624         outb(((inb(iobase+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
 625              iobase+IRCC_SCE_CFGB);
 626 #endif
 627         (void) inb(iobase+IRCC_FIFO_THRESHOLD);
 628         outb(SMSC_IRCC2_FIFO_THRESHOLD, iobase+IRCC_FIFO_THRESHOLD);
 629
 630         register_bank(iobase, 4);
 631         outb((inb(iobase+IRCC_CONTROL) & 0x30) | ctrl, iobase+IRCC_CONTROL);
 632
 633         register_bank(iobase, 0);
 634         outb(fast, iobase+IRCC_LCR_A);
 635
 636         smsc_ircc_set_sir_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
 637
 638         /* Power on device */
 639         outb(0x00, iobase+IRCC_MASTER);
 640 }
 641
 642 /*
 643  * Function smsc_ircc_net_ioctl (dev, rq, cmd)
 644  *
 645  *    Process IOCTL commands for this device
 646  *
 647  */
 648 static int smsc_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 649 {
 650         struct if_irda_req *irq = (struct if_irda_req *) rq;
 651         struct smsc_ircc_cb *self;
 652         unsigned long flags;
 653         int ret = 0;
 654
 655         ASSERT(dev != NULL, return -1;);
 656
 657         self = dev->priv;
 658
 659         ASSERT(self != NULL, return -1;);
 660
 661         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name, cmd);
 662
 663         switch (cmd) {
 664         case SIOCSBANDWIDTH: /* Set bandwidth */
 665                 if (!capable(CAP_NET_ADMIN))
 666                         ret = -EPERM;
 667                 else {
 668                         /* Make sure we are the only one touching
 669                          * self->io.speed and the hardware - Jean II */
 670                         spin_lock_irqsave(&self->lock, flags);
 671                         smsc_ircc_change_speed(self, irq->ifr_baudrate);
 672                         spin_unlock_irqrestore(&self->lock, flags);
 673                 }
 674                 break;
 675         case SIOCSMEDIABUSY: /* Set media busy */
 676                 if (!capable(CAP_NET_ADMIN)) {
 677                         ret = -EPERM;
 678                         break;
 679                 }
 680
 681                 irda_device_set_media_busy(self->netdev, TRUE);
 682                 break;
 683         case SIOCGRECEIVING: /* Check if we are receiving right now */
 684                 irq->ifr_receiving = smsc_ircc_is_receiving(self);
 685                 break;
 686         #if 0
 687         case SIOCSDTRRTS:
 688                 if (!capable(CAP_NET_ADMIN)) {
 689                         ret = -EPERM;
 690                         break;
 691                 }
 692                 smsc_ircc_sir_set_dtr_rts(dev, irq->ifr_dtr, irq->ifr_rts);
 693                 break;
 694         #endif
 695         default:
 696                 ret = -EOPNOTSUPP;
 697         }
 698
 699         return ret;
 700 }
 701
 702 static struct net_device_stats *smsc_ircc_net_get_stats(struct net_device *dev)
 703 {
 704         struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) dev->priv;
 705
 706         return &self->stats;
 707 }
 708
 709 #if SMSC_IRCC2_C_NET_TIMEOUT
 710 /*
 711  * Function smsc_ircc_timeout (struct net_device *dev)
 712  *
 713  *    The networking timeout management.
 714  *
 715  */
 716
 717 static void smsc_ircc_timeout(struct net_device *dev)
 718 {
 719         struct smsc_ircc_cb *self;
 720         unsigned long flags;
 721
 722         self = (struct smsc_ircc_cb *) dev->priv;
 723
 724         WARNING("%s: transmit timed out, changing speed to: %d\n", dev->name, self->io.speed);
 725         spin_lock_irqsave(&self->lock, flags);
 726         smsc_ircc_sir_start(self);
 727         smsc_ircc_change_speed(self, self->io.speed);
 728         dev->trans_start = jiffies;
 729         netif_wake_queue(dev);
 730         spin_unlock_irqrestore(&self->lock, flags);
 731 }
 732 #endif
 733
 734 /*
 735  * Function smsc_ircc_hard_xmit_sir (struct sk_buff *skb, struct net_device *dev)
 736  *
 737  *    Transmits the current frame until FIFO is full, then
 738  *    waits until the next transmit interrupt, and continues until the
 739  *    frame is transmitted.
 740  */
 741 int smsc_ircc_hard_xmit_sir(struct sk_buff *skb, struct net_device *dev)
 742 {
 743         struct smsc_ircc_cb *self;
 744         unsigned long flags;
 745         int iobase;
 746         s32 speed;
 747
 748         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 749
 750         ASSERT(dev != NULL, return 0;);
 751
 752         self = (struct smsc_ircc_cb *) dev->priv;
 753         ASSERT(self != NULL, return 0;);
 754
 755         iobase = self->io.sir_base;
 756
 757         netif_stop_queue(dev);
 758
 759         /* Make sure test of self->io.speed & speed change are atomic */
 760         spin_lock_irqsave(&self->lock, flags);
 761
 762         /* Check if we need to change the speed */
 763         speed = irda_get_next_speed(skb);
 764         if ((speed != self->io.speed) && (speed != -1)) {
 765                 /* Check for empty frame */
 766                 if (!skb->len) {
 767                         /*
 768                          * We send frames one by one in SIR mode (no
 769                          * pipelining), so at this point, if we were sending
 770                          * a previous frame, we just received the interrupt
 771                          * telling us it is finished (UART_IIR_THRI).
 772                          * Therefore, waiting for the transmitter to really
 773                          * finish draining the fifo won't take too long.
 774                          * And the interrupt handler is not expected to run.
 775                          * - Jean II */
 776                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
 777                         smsc_ircc_change_speed(self, speed);
 778                         spin_unlock_irqrestore(&self->lock, flags);
 779                         dev_kfree_skb(skb);
 780                         return 0;
 781                 } else {
 782                         self->new_speed = speed;
 783                 }
 784         }
 785
 786         /* Init tx buffer */
 787         self->tx_buff.data = self->tx_buff.head;
 788
 789         /* Copy skb to tx_buff while wrapping, stuffing and making CRC */
 790         self->tx_buff.len = async_wrap_skb(skb, self->tx_buff.data,
 791                                            self->tx_buff.truesize);
 792
 793         self->stats.tx_bytes += self->tx_buff.len;
 794
 795         /* Turn on transmit finished interrupt. Will fire immediately!  */
 796         outb(UART_IER_THRI, iobase+UART_IER);
 797
 798         spin_unlock_irqrestore(&self->lock, flags);
 799
 800         dev_kfree_skb(skb);
 801
 802         return 0;
 803 }
 804
 805 /*
 806  * Function smsc_ircc_set_fir_speed (self, baud)
 807  *
 808  *    Change the speed of the device
 809  *
 810  */
 811 static void smsc_ircc_set_fir_speed(struct smsc_ircc_cb *self, u32 speed)
 812 {
 813         int fir_base, ir_mode, ctrl, fast;
 814
 815         ASSERT(self != NULL, return;);
 816         fir_base = self->io.fir_base;
 817
 818         self->io.speed = speed;
 819
 820         switch(speed) {
 821         default:
 822         case 576000:
 823                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 824                 ctrl = IRCC_CRC;
 825                 fast = 0;
 826                 IRDA_DEBUG(0, "%s(), handling baud of 576000\n", __FUNCTION__);
 827                 break;
 828         case 1152000:
 829                 ir_mode = IRCC_CFGA_IRDA_HDLC;
 830                 ctrl = IRCC_1152 | IRCC_CRC;
 831                 fast = IRCC_LCR_A_FAST | IRCC_LCR_A_GP_DATA;
 832                 IRDA_DEBUG(0, "%s(), handling baud of 1152000\n",
 833                            __FUNCTION__);
 834                 break;
 835         case 4000000:
 836                 ir_mode = IRCC_CFGA_IRDA_4PPM;
 837                 ctrl = IRCC_CRC;
 838                 fast = IRCC_LCR_A_FAST;
 839                 IRDA_DEBUG(0, "%s(), handling baud of 4000000\n",
 840                            __FUNCTION__);
 841                 break;
 842         }
 843         #if 0
 844         Now in tranceiver!
 845         /* This causes an interrupt */
 846         register_bank(fir_base, 0);
 847         outb((inb(fir_base+IRCC_LCR_A) &  0xbf) | fast, fir_base+IRCC_LCR_A);
 848         #endif
 849
 850         register_bank(fir_base, 1);
 851         outb(((inb(fir_base+IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | ir_mode), fir_base+IRCC_SCE_CFGA);
 852
 853         register_bank(fir_base, 4);
 854         outb((inb(fir_base+IRCC_CONTROL) & 0x30) | ctrl, fir_base+IRCC_CONTROL);
 855 }
 856
 857 /*
 858  * Function smsc_ircc_fir_start(self)
 859  *
 860  *    Change the speed of the device
 861  *
 862  */
 863 static void smsc_ircc_fir_start(struct smsc_ircc_cb *self)
 864 {
 865         struct net_device *dev;
 866         int fir_base;
 867
 868         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 869
 870         ASSERT(self != NULL, return;);
 871         dev = self->netdev;
 872         ASSERT(dev != NULL, return;);
 873
 874         fir_base = self->io.fir_base;
 875
 876         /* Reset everything */
 877
 878         /* Install FIR transmit handler */
 879         dev->hard_start_xmit = smsc_ircc_hard_xmit_fir;
 880
 881         /* Clear FIFO */
 882         outb(inb(fir_base+IRCC_LCR_A)|IRCC_LCR_A_FIFO_RESET, fir_base+IRCC_LCR_A);
 883
 884         /* Enable interrupt */
 885         /*outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base+IRCC_IER);*/
 886
 887         register_bank(fir_base, 1);
 888
 889         /* Select the TX/RX interface */
 890 #ifdef SMSC_669 /* Uses pin 88/89 for Rx/Tx */
 891         outb(((inb(fir_base+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_COM),
 892              fir_base+IRCC_SCE_CFGB);
 893 #else
 894         outb(((inb(fir_base+IRCC_SCE_CFGB) & 0x3f) | IRCC_CFGB_MUX_IR),
 895              fir_base+IRCC_SCE_CFGB);
 896 #endif
 897         (void) inb(fir_base+IRCC_FIFO_THRESHOLD);
 898
 899         /* Enable SCE interrupts */
 900         outb(0, fir_base+IRCC_MASTER);
 901         register_bank(fir_base, 0);
 902         outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, fir_base+IRCC_IER);
 903         outb(IRCC_MASTER_INT_EN, fir_base+IRCC_MASTER);
 904 }
 905
 906 /*
 907  * Function smsc_ircc_fir_stop(self, baud)
 908  *
 909  *    Change the speed of the device
 910  *
 911  */
 912 static void smsc_ircc_fir_stop(struct smsc_ircc_cb *self)
 913 {
 914         int fir_base;
 915
 916         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
 917
 918         ASSERT(self != NULL, return;);
 919
 920         fir_base = self->io.fir_base;
 921         register_bank(fir_base, 0);
 922         /*outb(IRCC_MASTER_RESET, fir_base+IRCC_MASTER);*/
 923         outb(inb(fir_base+IRCC_LCR_B) & IRCC_LCR_B_SIP_ENABLE, fir_base+IRCC_LCR_B);
 924 }
 925
 926
 927 /*
 928  * Function smsc_ircc_change_speed(self, baud)
 929  *
 930  *    Change the speed of the device
 931  *
 932  * This function *must* be called with spinlock held, because it may
 933  * be called from the irq handler. - Jean II
 934  */
 935 static void smsc_ircc_change_speed(void *priv, u32 speed)
 936 {
 937         struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
 938         struct net_device *dev;
 939         int iobase;
 940         int last_speed_was_sir;
 941
 942         IRDA_DEBUG(0, "%s() changing speed to: %d\n", __FUNCTION__, speed);
 943
 944         ASSERT(self != NULL, return;);
 945         dev = self->netdev;
 946         iobase = self->io.fir_base;
 947
 948         last_speed_was_sir = self->io.speed <= SMSC_IRCC2_MAX_SIR_SPEED;
 949
 950         #if 0
 951         /* Temp Hack */
 952         speed= 1152000;
 953         self->io.speed = speed;
 954         last_speed_was_sir = 0;
 955         smsc_ircc_fir_start(self);
 956         #endif
 957
 958         if(self->io.speed == 0)
 959                 smsc_ircc_sir_start(self);
 960
 961         #if 0
 962         if(!last_speed_was_sir) speed = self->io.speed;
 963         #endif
 964
 965         if(self->io.speed != speed) smsc_ircc_set_transceiver_for_speed(self, speed);
 966
 967         self->io.speed = speed;
 968
 969         if(speed <= SMSC_IRCC2_MAX_SIR_SPEED) {
 970                 if(!last_speed_was_sir) {
 971                         smsc_ircc_fir_stop(self);
 972                         smsc_ircc_sir_start(self);
 973                 }
 974                 smsc_ircc_set_sir_speed(self, speed);
 975         }
 976         else {
 977                 if(last_speed_was_sir) {
 978                         #if SMSC_IRCC2_C_SIR_STOP
 979                         smsc_ircc_sir_stop(self);
 980                         #endif
 981                         smsc_ircc_fir_start(self);
 982                 }
 983                 smsc_ircc_set_fir_speed(self, speed);
 984
 985                 #if 0
 986                 self->tx_buff.len = 10;
 987                 self->tx_buff.data = self->tx_buff.head;
 988
 989                 smsc_ircc_dma_xmit(self, iobase, 4000);
 990                 #endif
 991                 /* Be ready for incoming frames */
 992                 smsc_ircc_dma_receive(self, iobase);
 993         }
 994
 995         netif_wake_queue(dev);
 996 }
 997
 998 /*
 999  * Function smsc_ircc_set_sir_speed (self, speed)
1000  *
1001  *    Set speed of IrDA port to specified baudrate
1002  *
1003  */
1004 void smsc_ircc_set_sir_speed(void *priv, __u32 speed)
1005 {
1006         struct smsc_ircc_cb *self = (struct smsc_ircc_cb *) priv;
1007         int iobase;
1008         int fcr;    /* FIFO control reg */
1009         int lcr;    /* Line control reg */
1010         int divisor;
1011
1012         IRDA_DEBUG(0, "%s(), Setting speed to: %d\n", __FUNCTION__, speed);
1013
1014         ASSERT(self != NULL, return;);
1015         iobase = self->io.sir_base;
1016
1017         /* Update accounting for new speed */
1018         self->io.speed = speed;
1019
1020         /* Turn off interrupts */
1021         outb(0, iobase+UART_IER);
1022
1023         divisor = SMSC_IRCC2_MAX_SIR_SPEED/speed;
1024
1025         fcr = UART_FCR_ENABLE_FIFO;
1026
1027         /*
1028          * Use trigger level 1 to avoid 3 ms. timeout delay at 9600 bps, and
1029          * almost 1,7 ms at 19200 bps. At speeds above that we can just forget
1030          * about this timeout since it will always be fast enough.
1031          */
1032         if (self->io.speed < 38400)
1033                 fcr |= UART_FCR_TRIGGER_1;
1034         else
1035                 fcr |= UART_FCR_TRIGGER_14;
1036
1037         /* IrDA ports use 8N1 */
1038         lcr = UART_LCR_WLEN8;
1039
1040         outb(UART_LCR_DLAB | lcr, iobase+UART_LCR); /* Set DLAB */
1041         outb(divisor & 0xff,      iobase+UART_DLL); /* Set speed */
1042         outb(divisor >> 8,        iobase+UART_DLM);
1043         outb(lcr,                 iobase+UART_LCR); /* Set 8N1  */
1044         outb(fcr,                 iobase+UART_FCR); /* Enable FIFO's */
1045
1046         /* Turn on interrups */
1047         outb(UART_IER_RLSI|UART_IER_RDI|UART_IER_THRI, iobase+UART_IER);
1048
1049         IRDA_DEBUG(2, "%s() speed changed to: %d\n", __FUNCTION__, speed);
1050 }
1051
1052
1053 /*
1054  * Function smsc_ircc_hard_xmit_fir (skb, dev)
1055  *
1056  *    Transmit the frame!
1057  *
1058  */
1059 static int smsc_ircc_hard_xmit_fir(struct sk_buff *skb, struct net_device *dev)
1060 {
1061         struct smsc_ircc_cb *self;
1062         unsigned long flags;
1063         s32 speed;
1064         int iobase;
1065         int mtt;
1066
1067         ASSERT(dev != NULL, return 0;);
1068         self = (struct smsc_ircc_cb *) dev->priv;
1069         ASSERT(self != NULL, return 0;);
1070
1071         iobase = self->io.fir_base;
1072
1073         netif_stop_queue(dev);
1074
1075         /* Make sure test of self->io.speed & speed change are atomic */
1076         spin_lock_irqsave(&self->lock, flags);
1077
1078         /* Check if we need to change the speed after this frame */
1079         speed = irda_get_next_speed(skb);
1080         if ((speed != self->io.speed) && (speed != -1)) {
1081                 /* Check for empty frame */
1082                 if (!skb->len) {
1083                         /* Note : you should make sure that speed changes
1084                          * are not going to corrupt any outgoing frame.
1085                          * Look at nsc-ircc for the gory details - Jean II */
1086                         smsc_ircc_change_speed(self, speed);
1087                         spin_unlock_irqrestore(&self->lock, flags);
1088                         dev_kfree_skb(skb);
1089                         return 0;
1090                 } else
1091                         self->new_speed = speed;
1092         }
1093
1094         memcpy(self->tx_buff.head, skb->data, skb->len);
1095
1096         self->tx_buff.len = skb->len;
1097         self->tx_buff.data = self->tx_buff.head;
1098
1099         mtt = irda_get_mtt(skb);
1100         if (mtt) {
1101                 int bofs;
1102
1103                 /*
1104                  * Compute how many BOFs (STA or PA's) we need to waste the
1105                  * min turn time given the speed of the link.
1106                  */
1107                 bofs = mtt * (self->io.speed / 1000) / 8000;
1108                 if (bofs > 4095)
1109                         bofs = 4095;
1110
1111                 smsc_ircc_dma_xmit(self, iobase, bofs);
1112         } else {
1113                 /* Transmit frame */
1114                 smsc_ircc_dma_xmit(self, iobase, 0);
1115         }
1116         spin_unlock_irqrestore(&self->lock, flags);
1117         dev_kfree_skb(skb);
1118
1119         return 0;
1120 }
1121
1122 /*
1123  * Function smsc_ircc_dma_xmit (self, iobase)
1124  *
1125  *    Transmit data using DMA
1126  *
1127  */
1128 static void smsc_ircc_dma_xmit(struct smsc_ircc_cb *self, int iobase, int bofs)
1129 {
1130         u8 ctrl;
1131
1132         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1133 #if 1
1134         /* Disable Rx */
1135         register_bank(iobase, 0);
1136         outb(0x00, iobase+IRCC_LCR_B);
1137 #endif
1138         register_bank(iobase, 1);
1139         outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1140              iobase+IRCC_SCE_CFGB);
1141
1142         self->io.direction = IO_XMIT;
1143
1144         /* Set BOF additional count for generating the min turn time */
1145         register_bank(iobase, 4);
1146         outb(bofs & 0xff, iobase+IRCC_BOF_COUNT_LO);
1147         ctrl = inb(iobase+IRCC_CONTROL) & 0xf0;
1148         outb(ctrl | ((bofs >> 8) & 0x0f), iobase+IRCC_BOF_COUNT_HI);
1149
1150         /* Set max Tx frame size */
1151         outb(self->tx_buff.len >> 8, iobase+IRCC_TX_SIZE_HI);
1152         outb(self->tx_buff.len & 0xff, iobase+IRCC_TX_SIZE_LO);
1153
1154         /*outb(UART_MCR_OUT2, self->io.sir_base + UART_MCR);*/
1155
1156         /* Enable burst mode chip Tx DMA */
1157         register_bank(iobase, 1);
1158         outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1159              IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);
1160
1161         /* Setup DMA controller (must be done after enabling chip DMA) */
1162         irda_setup_dma(self->io.dma, self->tx_buff.data, self->tx_buff.len,
1163                        DMA_TX_MODE);
1164
1165         /* Enable interrupt */
1166
1167         register_bank(iobase, 0);
1168         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);
1169         outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);
1170
1171         /* Enable transmit */
1172         outb(IRCC_LCR_B_SCE_TRANSMIT | IRCC_LCR_B_SIP_ENABLE, iobase+IRCC_LCR_B);
1173 }
1174
1175 /*
1176  * Function smsc_ircc_dma_xmit_complete (self)
1177  *
1178  *    The transfer of a frame in finished. This function will only be called
1179  *    by the interrupt handler
1180  *
1181  */
1182 static void smsc_ircc_dma_xmit_complete(struct smsc_ircc_cb *self, int iobase)
1183 {
1184         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1185 #if 0
1186         /* Disable Tx */
1187         register_bank(iobase, 0);
1188         outb(0x00, iobase+IRCC_LCR_B);
1189 #endif
1190         register_bank(self->io.fir_base, 1);
1191         outb(inb(self->io.fir_base+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1192              self->io.fir_base+IRCC_SCE_CFGB);
1193
1194         /* Check for underrun! */
1195         register_bank(iobase, 0);
1196         if (inb(iobase+IRCC_LSR) & IRCC_LSR_UNDERRUN) {
1197                 self->stats.tx_errors++;
1198                 self->stats.tx_fifo_errors++;
1199
1200                 /* Reset error condition */
1201                 register_bank(iobase, 0);
1202                 outb(IRCC_MASTER_ERROR_RESET, iobase+IRCC_MASTER);
1203                 outb(0x00, iobase+IRCC_MASTER);
1204         } else {
1205                 self->stats.tx_packets++;
1206                 self->stats.tx_bytes +=  self->tx_buff.len;
1207         }
1208
1209         /* Check if it's time to change the speed */
1210         if (self->new_speed) {
1211                 smsc_ircc_change_speed(self, self->new_speed);
1212                 self->new_speed = 0;
1213         }
1214
1215         netif_wake_queue(self->netdev);
1216 }
1217
1218 /*
1219  * Function smsc_ircc_dma_receive(self)
1220  *
1221  *    Get ready for receiving a frame. The device will initiate a DMA
1222  *    if it starts to receive a frame.
1223  *
1224  */
1225 static int smsc_ircc_dma_receive(struct smsc_ircc_cb *self, int iobase)
1226 {
1227 #if 0
1228         /* Turn off chip DMA */
1229         register_bank(iobase, 1);
1230         outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1231              iobase+IRCC_SCE_CFGB);
1232 #endif
1233
1234         /* Disable Tx */
1235         register_bank(iobase, 0);
1236         outb(0x00, iobase+IRCC_LCR_B);
1237
1238         /* Turn off chip DMA */
1239         register_bank(iobase, 1);
1240         outb(inb(iobase+IRCC_SCE_CFGB) & ~IRCC_CFGB_DMA_ENABLE,
1241              iobase+IRCC_SCE_CFGB);
1242
1243         self->io.direction = IO_RECV;
1244         self->rx_buff.data = self->rx_buff.head;
1245
1246         /* Set max Rx frame size */
1247         register_bank(iobase, 4);
1248         outb((2050 >> 8) & 0x0f, iobase+IRCC_RX_SIZE_HI);
1249         outb(2050 & 0xff, iobase+IRCC_RX_SIZE_LO);
1250
1251         /* Setup DMA controller */
1252         irda_setup_dma(self->io.dma, self->rx_buff.data,
1253                        self->rx_buff.truesize, DMA_RX_MODE);
1254
1255         /* Enable burst mode chip Rx DMA */
1256         register_bank(iobase, 1);
1257         outb(inb(iobase+IRCC_SCE_CFGB) | IRCC_CFGB_DMA_ENABLE |
1258              IRCC_CFGB_DMA_BURST, iobase+IRCC_SCE_CFGB);
1259
1260         /* Enable interrupt */
1261         register_bank(iobase, 0);
1262         outb(IRCC_IER_ACTIVE_FRAME | IRCC_IER_EOM, iobase+IRCC_IER);
1263         outb(IRCC_MASTER_INT_EN, iobase+IRCC_MASTER);
1264
1265
1266         /* Enable receiver */
1267         register_bank(iobase, 0);
1268         outb(IRCC_LCR_B_SCE_RECEIVE | IRCC_LCR_B_SIP_ENABLE,
1269              iobase+IRCC_LCR_B);
1270
1271         return 0;
1272 }
1273
1274 /*
1275  * Function smsc_ircc_dma_receive_complete(self, iobase)
1276  *
1277  *    Finished with receiving frames
1278  *
1279  */
1280 static void smsc_ircc_dma_receive_complete(struct smsc_ircc_cb *self, int iobase)
1281 {
1282         struct sk_buff *skb;
1283         int len, msgcnt, lsr;
1284
1285         register_bank(iobase, 0);
1286
1287         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1288 #if 0
1289         /* Disable Rx */
1290         register_bank(iobase, 0);
1291         outb(0x00, iobase+IRCC_LCR_B);
1292 #endif
1293         register_bank(iobase, 0);
1294         outb(inb(iobase+IRCC_LSAR) & ~IRCC_LSAR_ADDRESS_MASK, iobase+IRCC_LSAR);
1295         lsr= inb(iobase+IRCC_LSR);
1296         msgcnt = inb(iobase+IRCC_LCR_B) & 0x08;
1297
1298         IRDA_DEBUG(2, "%s: dma count = %d\n", __FUNCTION__,
1299                    get_dma_residue(self->io.dma));
1300
1301         len = self->rx_buff.truesize - get_dma_residue(self->io.dma);
1302
1303         /* Look for errors
1304          */
1305
1306         if(lsr & (IRCC_LSR_FRAME_ERROR | IRCC_LSR_CRC_ERROR | IRCC_LSR_SIZE_ERROR)) {
1307                 self->stats.rx_errors++;
1308                 if(lsr & IRCC_LSR_FRAME_ERROR) self->stats.rx_frame_errors++;
1309                 if(lsr & IRCC_LSR_CRC_ERROR) self->stats.rx_crc_errors++;
1310                 if(lsr & IRCC_LSR_SIZE_ERROR) self->stats.rx_length_errors++;
1311                 if(lsr & (IRCC_LSR_UNDERRUN | IRCC_LSR_OVERRUN)) self->stats.rx_length_errors++;
1312                 return;
1313         }
1314         /* Remove CRC */
1315         if (self->io.speed < 4000000)
1316                 len -= 2;
1317         else
1318                 len -= 4;
1319
1320         if ((len < 2) || (len > 2050)) {
1321                 WARNING("%s(), bogus len=%d\n", __FUNCTION__, len);
1322                 return;
1323         }
1324         IRDA_DEBUG(2, "%s: msgcnt = %d, len=%d\n", __FUNCTION__, msgcnt, len);
1325
1326         skb = dev_alloc_skb(len+1);
1327         if (!skb)  {
1328                 WARNING("%s(), memory squeeze, dropping frame.\n",
1329                         __FUNCTION__);
1330                 return;
1331         }
1332         /* Make sure IP header gets aligned */
1333         skb_reserve(skb, 1);
1334
1335         memcpy(skb_put(skb, len), self->rx_buff.data, len);
1336         self->stats.rx_packets++;
1337         self->stats.rx_bytes += len;
1338
1339         skb->dev = self->netdev;
1340         skb->mac.raw  = skb->data;
1341         skb->protocol = htons(ETH_P_IRDA);
1342         netif_rx(skb);
1343 }
1344
1345 /*
1346  * Function smsc_ircc_sir_receive (self)
1347  *
1348  *    Receive one frame from the infrared port
1349  *
1350  */
1351 static void smsc_ircc_sir_receive(struct smsc_ircc_cb *self)
1352 {
1353         int boguscount = 0;
1354         int iobase;
1355
1356         ASSERT(self != NULL, return;);
1357
1358         iobase = self->io.sir_base;
1359
1360         /*
1361          * Receive all characters in Rx FIFO, unwrap and unstuff them.
1362          * async_unwrap_char will deliver all found frames
1363          */
1364         do {
1365                 async_unwrap_char(self->netdev, &self->stats, &self->rx_buff,
1366                                   inb(iobase+UART_RX));
1367
1368                 /* Make sure we don't stay here to long */
1369                 if (boguscount++ > 32) {
1370                         IRDA_DEBUG(2, "%s(), breaking!\n", __FUNCTION__);
1371                         break;
1372                 }
1373         } while (inb(iobase+UART_LSR) & UART_LSR_DR);
1374 }
1375
1376
1377 /*
1378  * Function smsc_ircc_interrupt (irq, dev_id, regs)
1379  *
1380  *    An interrupt from the chip has arrived. Time to do some work
1381  *
1382  */
1383 static irqreturn_t smsc_ircc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1384 {
1385         struct net_device *dev = (struct net_device *) dev_id;
1386         struct smsc_ircc_cb *self;
1387         int iobase, iir, lcra, lsr;
1388         irqreturn_t ret = IRQ_NONE;
1389
1390         if (dev == NULL) {
1391                 printk(KERN_WARNING "%s: irq %d for unknown device.\n",
1392                        driver_name, irq);
1393                 goto irq_ret;
1394         }
1395         self = (struct smsc_ircc_cb *) dev->priv;
1396         ASSERT(self != NULL, return IRQ_NONE;);
1397
1398         /* Serialise the interrupt handler in various CPUs, stop Tx path */
1399         spin_lock(&self->lock);
1400
1401         /* Check if we should use the SIR interrupt handler */
1402         if (self->io.speed <=  SMSC_IRCC2_MAX_SIR_SPEED) {
1403                 ret = smsc_ircc_interrupt_sir(dev);
1404                 goto irq_ret_unlock;
1405         }
1406
1407         iobase = self->io.fir_base;
1408
1409         register_bank(iobase, 0);
1410         iir = inb(iobase+IRCC_IIR);
1411         if (iir == 0)
1412                 goto irq_ret_unlock;
1413         ret = IRQ_HANDLED;
1414
1415         /* Disable interrupts */
1416         outb(0, iobase+IRCC_IER);
1417         lcra = inb(iobase+IRCC_LCR_A);
1418         lsr = inb(iobase+IRCC_LSR);
1419
1420         IRDA_DEBUG(2, "%s(), iir = 0x%02x\n", __FUNCTION__, iir);
1421
1422         if (iir & IRCC_IIR_EOM) {
1423                 if (self->io.direction == IO_RECV)
1424                         smsc_ircc_dma_receive_complete(self, iobase);
1425                 else
1426                         smsc_ircc_dma_xmit_complete(self, iobase);
1427
1428                 smsc_ircc_dma_receive(self, iobase);
1429         }
1430
1431         if (iir & IRCC_IIR_ACTIVE_FRAME) {
1432                 /*printk(KERN_WARNING "%s(): Active Frame\n", __FUNCTION__);*/
1433         }
1434
1435         /* Enable interrupts again */
1436
1437         register_bank(iobase, 0);
1438         outb(IRCC_IER_ACTIVE_FRAME|IRCC_IER_EOM, iobase+IRCC_IER);
1439
1440  irq_ret_unlock:
1441         spin_unlock(&self->lock);
1442  irq_ret:
1443         return ret;
1444 }
1445
1446 /*
1447  * Function irport_interrupt_sir (irq, dev_id, regs)
1448  *
1449  *    Interrupt handler for SIR modes
1450  */
1451 static irqreturn_t smsc_ircc_interrupt_sir(struct net_device *dev)
1452 {
1453         struct smsc_ircc_cb *self = dev->priv;
1454         int boguscount = 0;
1455         int iobase;
1456         int iir, lsr;
1457
1458         /* Already locked comming here in smsc_ircc_interrupt() */
1459         /*spin_lock(&self->lock);*/
1460
1461         iobase = self->io.sir_base;
1462
1463         iir = inb(iobase+UART_IIR) & UART_IIR_ID;
1464         if (iir == 0)
1465                 return IRQ_NONE;
1466         while (iir) {
1467                 /* Clear interrupt */
1468                 lsr = inb(iobase+UART_LSR);
1469
1470                 IRDA_DEBUG(4, "%s(), iir=%02x, lsr=%02x, iobase=%#x\n",
1471                             __FUNCTION__, iir, lsr, iobase);
1472
1473                 switch (iir) {
1474                 case UART_IIR_RLSI:
1475                         IRDA_DEBUG(2, "%s(), RLSI\n", __FUNCTION__);
1476                         break;
1477                 case UART_IIR_RDI:
1478                         /* Receive interrupt */
1479                         smsc_ircc_sir_receive(self);
1480                         break;
1481                 case UART_IIR_THRI:
1482                         if (lsr & UART_LSR_THRE)
1483                                 /* Transmitter ready for data */
1484                                 smsc_ircc_sir_write_wakeup(self);
1485                         break;
1486                 default:
1487                         IRDA_DEBUG(0, "%s(), unhandled IIR=%#x\n",
1488                                    __FUNCTION__, iir);
1489                         break;
1490                 }
1491
1492                 /* Make sure we don't stay here to long */
1493                 if (boguscount++ > 100)
1494                         break;
1495
1496                 iir = inb(iobase + UART_IIR) & UART_IIR_ID;
1497         }
1498         /*spin_unlock(&self->lock);*/
1499         return IRQ_HANDLED;
1500 }
1501
1502
1503 #if 0 /* unused */
1504 /*
1505  * Function ircc_is_receiving (self)
1506  *
1507  *    Return TRUE is we are currently receiving a frame
1508  *
1509  */
1510 static int ircc_is_receiving(struct smsc_ircc_cb *self)
1511 {
1512         int status = FALSE;
1513         /* int iobase; */
1514
1515         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1516
1517         ASSERT(self != NULL, return FALSE;);
1518
1519         IRDA_DEBUG(0, "%s: dma count = %d\n", __FUNCTION__,
1520                    get_dma_residue(self->io.dma));
1521
1522         status = (self->rx_buff.state != OUTSIDE_FRAME);
1523
1524         return status;
1525 }
1526 #endif /* unused */
1527
1528
1529 /*
1530  * Function smsc_ircc_net_open (dev)
1531  *
1532  *    Start the device
1533  *
1534  */
1535 static int smsc_ircc_net_open(struct net_device *dev)
1536 {
1537         struct smsc_ircc_cb *self;
1538         int iobase;
1539         char hwname[16];
1540         unsigned long flags;
1541
1542         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1543
1544         ASSERT(dev != NULL, return -1;);
1545         self = (struct smsc_ircc_cb *) dev->priv;
1546         ASSERT(self != NULL, return 0;);
1547
1548         iobase = self->io.fir_base;
1549
1550         if (request_irq(self->io.irq, smsc_ircc_interrupt, 0, dev->name,
1551                         (void *) dev)) {
1552                 IRDA_DEBUG(0, "%s(), unable to allocate irq=%d\n",
1553                            __FUNCTION__, self->io.irq);
1554                 return -EAGAIN;
1555         }
1556
1557         spin_lock_irqsave(&self->lock, flags);
1558         /*smsc_ircc_sir_start(self);*/
1559         self->io.speed = 0;
1560         smsc_ircc_change_speed(self, SMSC_IRCC2_C_IRDA_FALLBACK_SPEED);
1561         spin_unlock_irqrestore(&self->lock, flags);
1562
1563         /* Give self a hardware name */
1564         /* It would be cool to offer the chip revision here - Jean II */
1565         sprintf(hwname, "SMSC @ 0x%03x", self->io.fir_base);
1566
1567         /*
1568          * Open new IrLAP layer instance, now that everything should be
1569          * initialized properly
1570          */
1571         self->irlap = irlap_open(dev, &self->qos, hwname);
1572
1573         /*
1574          * Always allocate the DMA channel after the IRQ,
1575          * and clean up on failure.
1576          */
1577         if (request_dma(self->io.dma, dev->name)) {
1578                 smsc_ircc_net_close(dev);
1579
1580                 WARNING("%s(), unable to allocate DMA=%d\n",
1581                         __FUNCTION__, self->io.dma);
1582                 return -EAGAIN;
1583         }
1584
1585         netif_start_queue(dev);
1586
1587         return 0;
1588 }
1589
1590 /*
1591  * Function smsc_ircc_net_close (dev)
1592  *
1593  *    Stop the device
1594  *
1595  */
1596 static int smsc_ircc_net_close(struct net_device *dev)
1597 {
1598         struct smsc_ircc_cb *self;
1599         int iobase;
1600
1601         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1602
1603         ASSERT(dev != NULL, return -1;);
1604         self = (struct smsc_ircc_cb *) dev->priv;
1605         ASSERT(self != NULL, return 0;);
1606
1607         iobase = self->io.fir_base;
1608
1609         /* Stop device */
1610         netif_stop_queue(dev);
1611
1612         /* Stop and remove instance of IrLAP */
1613         if (self->irlap)
1614                 irlap_close(self->irlap);
1615         self->irlap = NULL;
1616
1617         free_irq(self->io.irq, dev);
1618
1619         disable_dma(self->io.dma);
1620
1621         free_dma(self->io.dma);
1622
1623         return 0;
1624 }
1625
1626
1627 static void smsc_ircc_suspend(struct smsc_ircc_cb *self)
1628 {
1629         MESSAGE("%s, Suspending\n", driver_name);
1630
1631         if (self->io.suspended)
1632                 return;
1633
1634         smsc_ircc_net_close(self->netdev);
1635
1636         self->io.suspended = 1;
1637 }
1638
1639 static void smsc_ircc_wakeup(struct smsc_ircc_cb *self)
1640 {
1641         if (!self->io.suspended)
1642                 return;
1643
1644         /* The code was doing a "cli()" here, but this can't be right.
1645          * If you need protection, do it in net_open with a spinlock
1646          * or give a good reason. - Jean II */
1647
1648         smsc_ircc_net_open(self->netdev);
1649
1650         MESSAGE("%s, Waking up\n", driver_name);
1651 }
1652
1653 static int smsc_ircc_pmproc(struct pm_dev *dev, pm_request_t rqst, void *data)
1654 {
1655         struct smsc_ircc_cb *self = (struct smsc_ircc_cb*) dev->data;
1656         if (self) {
1657                 switch (rqst) {
1658                 case PM_SUSPEND:
1659                         smsc_ircc_suspend(self);
1660                         break;
1661                 case PM_RESUME:
1662                         smsc_ircc_wakeup(self);
1663                         break;
1664                 }
1665         }
1666         return 0;
1667 }
1668
1669 /*
1670  * Function smsc_ircc_close (self)
1671  *
1672  *    Close driver instance
1673  *
1674  */
1675 static int __exit smsc_ircc_close(struct smsc_ircc_cb *self)
1676 {
1677         int iobase;
1678         unsigned long flags;
1679
1680         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1681
1682         ASSERT(self != NULL, return -1;);
1683
1684         iobase = self->io.fir_base;
1685
1686         if (self->pmdev)
1687                 pm_unregister(self->pmdev);
1688
1689         /* Remove netdevice */
1690         unregister_netdev(self->netdev);
1691
1692         /* Make sure the irq handler is not exectuting */
1693         spin_lock_irqsave(&self->lock, flags);
1694
1695         /* Stop interrupts */
1696         register_bank(iobase, 0);
1697         outb(0, iobase+IRCC_IER);
1698         outb(IRCC_MASTER_RESET, iobase+IRCC_MASTER);
1699         outb(0x00, iobase+IRCC_MASTER);
1700 #if 0
1701         /* Reset to SIR mode */
1702         register_bank(iobase, 1);
1703         outb(IRCC_CFGA_IRDA_SIR_A|IRCC_CFGA_TX_POLARITY, iobase+IRCC_SCE_CFGA);
1704         outb(IRCC_CFGB_IR, iobase+IRCC_SCE_CFGB);
1705 #endif
1706         spin_unlock_irqrestore(&self->lock, flags);
1707
1708         /* Release the PORTS that this driver is using */
1709         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n",  __FUNCTION__,
1710                    self->io.fir_base);
1711
1712         release_region(self->io.fir_base, self->io.fir_ext);
1713
1714         IRDA_DEBUG(0, "%s(), releasing 0x%03x\n", __FUNCTION__,
1715                    self->io.sir_base);
1716
1717         release_region(self->io.sir_base, self->io.sir_ext);
1718
1719         if (self->tx_buff.head)
1720                 kfree(self->tx_buff.head);
1721
1722         if (self->rx_buff.head)
1723                 kfree(self->rx_buff.head);
1724
1725         free_netdev(self->netdev);
1726
1727         return 0;
1728 }
1729
1730 static void __exit smsc_ircc_cleanup(void)
1731 {
1732         int i;
1733
1734         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
1735
1736         for (i=0; i < 2; i++) {
1737                 if (dev_self[i])
1738                         smsc_ircc_close(dev_self[i]);
1739         }
1740 }
1741
1742 /*
1743  *      Start SIR operations
1744  *
1745  * This function *must* be called with spinlock held, because it may
1746  * be called from the irq handler (via smsc_ircc_change_speed()). - Jean II
1747  */
1748 void smsc_ircc_sir_start(struct smsc_ircc_cb *self)
1749 {
1750         struct net_device *dev;
1751         int fir_base, sir_base;
1752
1753         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1754
1755         ASSERT(self != NULL, return;);
1756         dev= self->netdev;
1757         ASSERT(dev != NULL, return;);
1758         dev->hard_start_xmit = &smsc_ircc_hard_xmit_sir;
1759
1760         fir_base = self->io.fir_base;
1761         sir_base = self->io.sir_base;
1762
1763         /* Reset everything */
1764         outb(IRCC_MASTER_RESET, fir_base+IRCC_MASTER);
1765
1766         #if SMSC_IRCC2_C_SIR_STOP
1767         /*smsc_ircc_sir_stop(self);*/
1768         #endif
1769
1770         register_bank(fir_base, 1);
1771         outb(((inb(fir_base+IRCC_SCE_CFGA) & IRCC_SCE_CFGA_BLOCK_CTRL_BITS_MASK) | IRCC_CFGA_IRDA_SIR_A), fir_base+IRCC_SCE_CFGA);
1772
1773         /* Initialize UART */
1774         outb(UART_LCR_WLEN8, sir_base+UART_LCR);  /* Reset DLAB */
1775         outb((UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2), sir_base+UART_MCR);
1776
1777         /* Turn on interrups */
1778         outb(UART_IER_RLSI | UART_IER_RDI |UART_IER_THRI, sir_base+UART_IER);
1779
1780         IRDA_DEBUG(3, "%s() - exit\n", __FUNCTION__);
1781
1782         outb(0x00, fir_base+IRCC_MASTER);
1783 }
1784
1785 #if SMSC_IRCC2_C_SIR_STOP
1786 void smsc_ircc_sir_stop(struct smsc_ircc_cb *self)
1787 {
1788         int iobase;
1789
1790         IRDA_DEBUG(3, "%s\n", __FUNCTION__);
1791         iobase = self->io.sir_base;
1792
1793         /* Reset UART */
1794         outb(0, iobase+UART_MCR);
1795
1796         /* Turn off interrupts */
1797         outb(0, iobase+UART_IER);
1798 }
1799 #endif
1800
1801 /*
1802  * Function smsc_sir_write_wakeup (self)
1803  *
1804  *    Called by the SIR interrupt handler when there's room for more data.
1805  *    If we have more packets to send, we send them here.
1806  *
1807  */
1808 static void smsc_ircc_sir_write_wakeup(struct smsc_ircc_cb *self)
1809 {
1810         int actual = 0;
1811         int iobase;
1812         int fcr;
1813
1814         ASSERT(self != NULL, return;);
1815
1816         IRDA_DEBUG(4, "%s\n", __FUNCTION__);
1817
1818         iobase = self->io.sir_base;
1819
1820         /* Finished with frame?  */
1821         if (self->tx_buff.len > 0)  {
1822                 /* Write data left in transmit buffer */
1823                 actual = smsc_ircc_sir_write(iobase, self->io.fifo_size,
1824                                       self->tx_buff.data, self->tx_buff.len);
1825                 self->tx_buff.data += actual;
1826                 self->tx_buff.len  -= actual;
1827         } else {
1828
1829         /*if (self->tx_buff.len ==0)  {*/
1830
1831                 /*
1832                  *  Now serial buffer is almost free & we can start
1833                  *  transmission of another packet. But first we must check
1834                  *  if we need to change the speed of the hardware
1835                  */
1836                 if (self->new_speed) {
1837                         IRDA_DEBUG(5, "%s(), Changing speed to %d.\n",
1838                                    __FUNCTION__, self->new_speed);
1839                         smsc_ircc_sir_wait_hw_transmitter_finish(self);
1840                         smsc_ircc_change_speed(self, self->new_speed);
1841                         self->new_speed = 0;
1842                 } else {
1843                         /* Tell network layer that we want more frames */
1844                         netif_wake_queue(self->netdev);
1845                 }
1846                 self->stats.tx_packets++;
1847
1848                 if(self->io.speed <= 115200) {
1849                 /*
1850                  * Reset Rx FIFO to make sure that all reflected transmit data
1851                  * is discarded. This is needed for half duplex operation
1852                  */
1853                 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR;
1854                 if (self->io.speed < 38400)
1855                         fcr |= UART_FCR_TRIGGER_1;
1856                 else
1857                         fcr |= UART_FCR_TRIGGER_14;
1858
1859                 outb(fcr, iobase+UART_FCR);
1860
1861                 /* Turn on receive interrupts */
1862                 outb(UART_IER_RDI, iobase+UART_IER);
1863                 }
1864         }
1865 }
1866
1867 /*
1868  * Function smsc_ircc_sir_write (iobase, fifo_size, buf, len)
1869  *
1870  *    Fill Tx FIFO with transmit data
1871  *
1872  */
1873 static int smsc_ircc_sir_write(int iobase, int fifo_size, __u8 *buf, int len)
1874 {
1875         int actual = 0;
1876
1877         /* Tx FIFO should be empty! */
1878         if (!(inb(iobase+UART_LSR) & UART_LSR_THRE)) {
1879                 WARNING("%s(), failed, fifo not empty!\n", __FUNCTION__);
1880                 return 0;
1881         }
1882
1883         /* Fill FIFO with current frame */
1884         while ((fifo_size-- > 0) && (actual < len)) {
1885                 /* Transmit next byte */
1886                 outb(buf[actual], iobase+UART_TX);
1887                 actual++;
1888         }
1889         return actual;
1890 }
1891
1892 /*
1893  * Function smsc_ircc_is_receiving (self)
1894  *
1895  *    Returns true is we are currently receiving data
1896  *
1897  */
1898 static int smsc_ircc_is_receiving(struct smsc_ircc_cb *self)
1899 {
1900         return (self->rx_buff.state != OUTSIDE_FRAME);
1901 }
1902
1903
1904 /*
1905  * Function smsc_ircc_probe_transceiver(self)
1906  *
1907  *    Tries to find the used Transceiver
1908  *
1909  */
1910 static void smsc_ircc_probe_transceiver(struct smsc_ircc_cb *self)
1911 {
1912         unsigned int    i;
1913
1914         ASSERT(self != NULL, return;);
1915
1916         for(i=0; smsc_transceivers[i].name!=NULL; i++)
1917                 if((*smsc_transceivers[i].probe)(self->io.fir_base)) {
1918                         MESSAGE(" %s transceiver found\n", smsc_transceivers[i].name);
1919                         self->transceiver= i+1;
1920                         return;
1921                 }
1922         MESSAGE("No transceiver found. Defaulting to %s\n", smsc_transceivers[SMSC_IRCC2_C_DEFAULT_TRANSCEIVER].name);
1923
1924         self->transceiver= SMSC_IRCC2_C_DEFAULT_TRANSCEIVER;
1925 }
1926
1927
1928 /*
1929  * Function smsc_ircc_set_transceiver_for_speed(self, speed)
1930  *
1931  *    Set the transceiver according to the speed
1932  *
1933  */
1934 static void smsc_ircc_set_transceiver_for_speed(struct smsc_ircc_cb *self, u32 speed)
1935 {
1936         unsigned int trx;
1937
1938         trx = self->transceiver;
1939         if(trx>0) (*smsc_transceivers[trx-1].set_for_speed)(self->io.fir_base, speed);
1940 }
1941
1942 /*
1943  * Function smsc_ircc_wait_hw_transmitter_finish ()
1944  *
1945  *    Wait for the real end of HW transmission
1946  *
1947  * The UART is a strict FIFO, and we get called only when we have finished
1948  * pushing data to the FIFO, so the maximum amount of time we must wait
1949  * is only for the FIFO to drain out.
1950  *
1951  * We use a simple calibrated loop. We may need to adjust the loop
1952  * delay (udelay) to balance I/O traffic and latency. And we also need to
1953  * adjust the maximum timeout.
1954  * It would probably be better to wait for the proper interrupt,
1955  * but it doesn't seem to be available.
1956  *
1957  * We can't use jiffies or kernel timers because :
1958  * 1) We are called from the interrupt handler, which disable softirqs,
1959  * so jiffies won't be increased
1960  * 2) Jiffies granularity is usually very coarse (10ms), and we don't
1961  * want to wait that long to detect stuck hardware.
1962  * Jean II
1963  */
1964
1965 static void smsc_ircc_sir_wait_hw_transmitter_finish(struct smsc_ircc_cb *self)
1966 {
1967         int iobase;
1968         int count = SMSC_IRCC2_HW_TRANSMITTER_TIMEOUT_US;
1969
1970         iobase = self->io.sir_base;
1971
1972         /* Calibrated busy loop */
1973         while((count-- > 0) && !(inb(iobase+UART_LSR) & UART_LSR_TEMT))
1974                 udelay(1);
1975
1976         if(count == 0)
1977                 IRDA_DEBUG(0, "%s(): stuck transmitter\n", __FUNCTION__);
1978 }
1979
1980
1981 /* PROBING
1982  *
1983  *
1984  */
1985
1986 static int __init smsc_ircc_look_for_chips(void)
1987 {
1988         smsc_chip_address_t *address;
1989         char    *type;
1990         unsigned int cfg_base, found;
1991
1992         found = 0;
1993         address = possible_addresses;
1994
1995         while(address->cfg_base){
1996                 cfg_base = address->cfg_base;
1997
1998                 /*printk(KERN_WARNING "%s(): probing: 0x%02x for: 0x%02x\n", __FUNCTION__, cfg_base, address->type);*/
1999
2000                 if( address->type & SMSCSIO_TYPE_FDC){
2001                         type = "FDC";
2002                         if((address->type) & SMSCSIO_TYPE_FLAT) {
2003                                 if(!smsc_superio_flat(fdc_chips_flat,cfg_base, type)) found++;
2004                         }
2005                         if((address->type) & SMSCSIO_TYPE_PAGED) {
2006                                 if(!smsc_superio_paged(fdc_chips_paged,cfg_base, type)) found++;
2007                         }
2008                 }
2009                 if( address->type & SMSCSIO_TYPE_LPC){
2010                         type = "LPC";
2011                         if((address->type) & SMSCSIO_TYPE_FLAT) {
2012                                 if(!smsc_superio_flat(lpc_chips_flat,cfg_base,type)) found++;
2013                         }
2014                         if((address->type) & SMSCSIO_TYPE_PAGED) {
2015                                 if(!smsc_superio_paged(lpc_chips_paged,cfg_base,"LPC")) found++;
2016                         }
2017                 }
2018                 address++;
2019         }
2020         return found;
2021 }
2022
2023 /*
2024  * Function smsc_superio_flat (chip, base, type)
2025  *
2026  *    Try to get configuration of a smc SuperIO chip with flat register model
2027  *
2028  */
2029 static int __init smsc_superio_flat(const smsc_chip_t *chips, unsigned short cfgbase, char *type)
2030 {
2031         unsigned short firbase, sirbase;
2032         u8 mode, dma, irq;
2033         int ret = -ENODEV;
2034
2035         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2036
2037         if (smsc_ircc_probe(cfgbase, SMSCSIOFLAT_DEVICEID_REG, chips, type)==NULL)
2038                 return ret;
2039
2040         outb(SMSCSIOFLAT_UARTMODE0C_REG, cfgbase);
2041         mode = inb(cfgbase+1);
2042
2043         /*printk(KERN_WARNING "%s(): mode: 0x%02x\n", __FUNCTION__, mode);*/
2044
2045         if(!(mode & SMSCSIOFLAT_UART2MODE_VAL_IRDA))
2046                 WARNING("%s(): IrDA not enabled\n", __FUNCTION__);
2047
2048         outb(SMSCSIOFLAT_UART2BASEADDR_REG, cfgbase);
2049         sirbase = inb(cfgbase+1) << 2;
2050
2051         /* FIR iobase */
2052         outb(SMSCSIOFLAT_FIRBASEADDR_REG, cfgbase);
2053         firbase = inb(cfgbase+1) << 3;
2054
2055         /* DMA */
2056         outb(SMSCSIOFLAT_FIRDMASELECT_REG, cfgbase);
2057         dma = inb(cfgbase+1) & SMSCSIOFLAT_FIRDMASELECT_MASK;
2058
2059         /* IRQ */
2060         outb(SMSCSIOFLAT_UARTIRQSELECT_REG, cfgbase);
2061         irq = inb(cfgbase+1) & SMSCSIOFLAT_UART2IRQSELECT_MASK;
2062
2063         MESSAGE("%s(): fir: 0x%02x, sir: 0x%02x, dma: %02d, irq: %d, mode: 0x%02x\n", __FUNCTION__, firbase, sirbase, dma, irq, mode);
2064
2065         if (firbase) {
2066                 if (smsc_ircc_open(firbase, sirbase, dma, irq) == 0)
2067                         ret=0;
2068         }
2069
2070         /* Exit configuration */
2071         outb(SMSCSIO_CFGEXITKEY, cfgbase);
2072
2073         return ret;
2074 }
2075
2076 /*
2077  * Function smsc_superio_paged (chip, base, type)
2078  *
2079  *    Try  to get configuration of a smc SuperIO chip with paged register model
2080  *
2081  */
2082 static int __init smsc_superio_paged(const smsc_chip_t *chips, unsigned short cfg_base, char *type)
2083 {
2084         unsigned short fir_io, sir_io;
2085         int ret = -ENODEV;
2086
2087         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2088
2089         if (smsc_ircc_probe(cfg_base,0x20,chips,type)==NULL)
2090                 return ret;
2091
2092         /* Select logical device (UART2) */
2093         outb(0x07, cfg_base);
2094         outb(0x05, cfg_base + 1);
2095
2096         /* SIR iobase */
2097         outb(0x60, cfg_base);
2098         sir_io  = inb(cfg_base + 1) << 8;
2099         outb(0x61, cfg_base);
2100         sir_io |= inb(cfg_base + 1);
2101
2102         /* Read FIR base */
2103         outb(0x62, cfg_base);
2104         fir_io = inb(cfg_base + 1) << 8;
2105         outb(0x63, cfg_base);
2106         fir_io |= inb(cfg_base + 1);
2107         outb(0x2b, cfg_base); /* ??? */
2108
2109         if (fir_io) {
2110                 if (smsc_ircc_open(fir_io, sir_io, ircc_dma, ircc_irq) == 0)
2111                         ret=0;
2112         }
2113
2114         /* Exit configuration */
2115         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2116
2117         return ret;
2118 }
2119
2120
2121 static int __init smsc_access(unsigned short cfg_base,unsigned char reg)
2122 {
2123         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2124
2125         outb(reg, cfg_base);
2126
2127         if (inb(cfg_base)!=reg)
2128                 return -1;
2129
2130         return 0;
2131 }
2132
2133 static const smsc_chip_t * __init smsc_ircc_probe(unsigned short cfg_base,u8 reg,const smsc_chip_t *chip,char *type)
2134 {
2135         u8 devid,xdevid,rev;
2136
2137         IRDA_DEBUG(1, "%s\n", __FUNCTION__);
2138
2139         /* Leave configuration */
2140
2141         outb(SMSCSIO_CFGEXITKEY, cfg_base);
2142
2143         if (inb(cfg_base) == SMSCSIO_CFGEXITKEY)        /* not a smc superio chip */
2144                 return NULL;
2145
2146         outb(reg, cfg_base);
2147
2148         xdevid=inb(cfg_base+1);
2149
2150         /* Enter configuration */
2151
2152         outb(SMSCSIO_CFGACCESSKEY, cfg_base);
2153
2154         #if 0
2155         if (smsc_access(cfg_base,0x55)) /* send second key and check */
2156                 return NULL;
2157         #endif
2158
2159         /* probe device ID */
2160
2161         if (smsc_access(cfg_base,reg))
2162                 return NULL;
2163
2164         devid=inb(cfg_base+1);
2165
2166         if (devid==0)                   /* typical value for unused port */
2167                 return NULL;
2168
2169         if (devid==0xff)                /* typical value for unused port */
2170                 return NULL;
2171
2172         /* probe revision ID */
2173
2174         if (smsc_access(cfg_base,reg+1))
2175                 return NULL;
2176
2177         rev=inb(cfg_base+1);
2178
2179         if (rev>=128)                   /* i think this will make no sense */
2180                 return NULL;
2181
2182         if (devid==xdevid)              /* protection against false positives */
2183                 return NULL;
2184
2185         /* Check for expected device ID; are there others? */
2186
2187         while(chip->devid!=devid) {
2188
2189                 chip++;
2190
2191                 if (chip->name==NULL)
2192                         return NULL;
2193         }
2194
2195         MESSAGE("found SMC SuperIO Chip (devid=0x%02x rev=%02X base=0x%04x): %s%s\n",devid,rev,cfg_base,type,chip->name);
2196
2197         if (chip->rev>rev){
2198                 MESSAGE("Revision higher than expected\n");
2199                 return NULL;
2200         }
2201
2202         if (chip->flags&NoIRDA)
2203                 MESSAGE("chipset does not support IRDA\n");
2204
2205         return chip;
2206 }
2207
2208 static int __init smsc_superio_fdc(unsigned short cfg_base)
2209 {
2210         int ret = -1;
2211
2212         if (!request_region(cfg_base, 2, driver_name)) {
2213                 WARNING("%s: can't get cfg_base of 0x%03x\n",
2214                         __FUNCTION__, cfg_base);
2215         } else {
2216                 if (!smsc_superio_flat(fdc_chips_flat,cfg_base,"FDC")
2217                     ||!smsc_superio_paged(fdc_chips_paged,cfg_base,"FDC"))
2218                         ret =  0;
2219
2220                 release_region(cfg_base, 2);
2221         }
2222
2223         return ret;
2224 }
2225
2226 static int __init smsc_superio_lpc(unsigned short cfg_base)
2227 {
2228         int ret = -1;
2229
2230         if (!request_region(cfg_base, 2, driver_name)) {
2231                 WARNING("%s: can't get cfg_base of 0x%03x\n",
2232                         __FUNCTION__, cfg_base);
2233         } else {
2234                 if (!smsc_superio_flat(lpc_chips_flat,cfg_base,"LPC")
2235                     ||!smsc_superio_paged(lpc_chips_paged,cfg_base,"LPC"))
2236                         ret = 0;
2237                 release_region(cfg_base, 2);
2238         }
2239         return ret;
2240 }
2241
2242 /************************************************
2243  *
2244  * Transceivers specific functions
2245  *
2246  ************************************************/
2247
2248
2249 /*
2250  * Function smsc_ircc_set_transceiver_smsc_ircc_atc(fir_base, speed)
2251  *
2252  *    Program transceiver through smsc-ircc ATC circuitry
2253  *
2254  */
2255
2256 static void smsc_ircc_set_transceiver_smsc_ircc_atc(int fir_base, u32 speed)
2257 {
2258         unsigned long jiffies_now, jiffies_timeout;
2259         u8      val;
2260
2261         jiffies_now= jiffies;
2262         jiffies_timeout= jiffies+SMSC_IRCC2_ATC_PROGRAMMING_TIMEOUT_JIFFIES;
2263
2264         /* ATC */
2265         register_bank(fir_base, 4);
2266         outb((inb(fir_base+IRCC_ATC) & IRCC_ATC_MASK) |IRCC_ATC_nPROGREADY|IRCC_ATC_ENABLE, fir_base+IRCC_ATC);
2267         while((val=(inb(fir_base+IRCC_ATC) & IRCC_ATC_nPROGREADY)) && !time_after(jiffies, jiffies_timeout));
2268         if(val)
2269                 WARNING("%s(): ATC: 0x%02x\n", __FUNCTION__,
2270                         inb(fir_base+IRCC_ATC));
2271 }
2272
2273 /*
2274  * Function smsc_ircc_probe_transceiver_smsc_ircc_atc(fir_base)
2275  *
2276  *    Probe transceiver smsc-ircc ATC circuitry
2277  *
2278  */
2279
2280 static int smsc_ircc_probe_transceiver_smsc_ircc_atc(int fir_base)
2281 {
2282         return 0;
2283 }
2284
2285 /*
2286  * Function smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(self, speed)
2287  *
2288  *    Set transceiver
2289  *
2290  */
2291
2292 static void smsc_ircc_set_transceiver_smsc_ircc_fast_pin_select(int fir_base, u32 speed)
2293 {
2294         u8      fast_mode;
2295
2296         switch(speed)
2297         {
2298                 default:
2299                 case 576000 :
2300                 fast_mode = 0;
2301                 break;
2302                 case 1152000 :
2303                 case 4000000 :
2304                 fast_mode = IRCC_LCR_A_FAST;
2305                 break;
2306
2307         }
2308         register_bank(fir_base, 0);
2309         outb((inb(fir_base+IRCC_LCR_A) &  0xbf) | fast_mode, fir_base+IRCC_LCR_A);
2310 }
2311
2312 /*
2313  * Function smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(fir_base)
2314  *
2315  *    Probe transceiver
2316  *
2317  */
2318
2319 static int smsc_ircc_probe_transceiver_smsc_ircc_fast_pin_select(int fir_base)
2320 {
2321         return 0;
2322 }
2323
2324 /*
2325  * Function smsc_ircc_set_transceiver_toshiba_sat1800(fir_base, speed)
2326  *
2327  *    Set transceiver
2328  *
2329  */
2330
2331 static void smsc_ircc_set_transceiver_toshiba_sat1800(int fir_base, u32 speed)
2332 {
2333         u8      fast_mode;
2334
2335         switch(speed)
2336         {
2337                 default:
2338                 case 576000 :
2339                 fast_mode = 0;
2340                 break;
2341                 case 1152000 :
2342                 case 4000000 :
2343                 fast_mode = /*IRCC_LCR_A_FAST |*/ IRCC_LCR_A_GP_DATA;
2344                 break;
2345
2346         }
2347         /* This causes an interrupt */
2348         register_bank(fir_base, 0);
2349         outb((inb(fir_base+IRCC_LCR_A) &  0xbf) | fast_mode, fir_base+IRCC_LCR_A);
2350 }
2351
2352 /*
2353  * Function smsc_ircc_probe_transceiver_toshiba_sat1800(fir_base)
2354  *
2355  *    Probe transceiver
2356  *
2357  */
2358
2359 static int smsc_ircc_probe_transceiver_toshiba_sat1800(int fir_base)
2360 {
2361         return 0;
2362 }
2363
2364
2365 module_init(smsc_ircc_init);
2366 module_exit(smsc_ircc_cleanup);
2367
2368 MODULE_AUTHOR("Daniele Peri <peri@csai.unipa.it>");
2369 MODULE_DESCRIPTION("SMC IrCC SIR/FIR controller driver");
2370 MODULE_LICENSE("GPL");
2371
2372 MODULE_PARM(ircc_dma, "1i");
2373 MODULE_PARM_DESC(ircc_dma, "DMA channel");
2374 MODULE_PARM(ircc_irq, "1i");
2375 MODULE_PARM_DESC(ircc_irq, "IRQ line");
2376 MODULE_PARM(ircc_fir, "1-4i");
2377 MODULE_PARM_DESC(ircc_fir, "FIR Base Address");
2378 MODULE_PARM(ircc_sir, "1-4i");
2379 MODULE_PARM_DESC(ircc_sir, "SIR Base Address");
2380 MODULE_PARM(ircc_cfg, "1-4i");
2381 MODULE_PARM_DESC(ircc_cfg, "Configuration register base address");
2382 MODULE_PARM(ircc_transceiver, "1i");
2383 MODULE_PARM_DESC(ircc_transceiver, "Transceiver type");