drivers/net/irda/via-ircc.c

   1 /********************************************************************
   2  Filename:      via-ircc.c
   3  Version:       1.0
   4  Description:   Driver for the VIA VT8231/VT8233 IrDA chipsets
   5  Author:        VIA Technologies,inc
   6  Date  :        08/06/2003
   7
   8 Copyright (c) 1998-2003 VIA Technologies, Inc.
   9
  10 This program is free software; you can redistribute it and/or modify it under
  11 the terms of the GNU General Public License as published by the Free Software
  12 Foundation; either version 2, or (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful, but WITHOUT
  15 ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17 See the GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along with
  20 this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 F01 Oct/02/02: Modify code for V0.11(move out back to back transfer)
  24 F02 Oct/28/02: Add SB device ID for 3147 and 3177.
  25  Comment :
  26        jul/09/2002 : only implement two kind of dongle currently.
  27        Oct/02/2002 : work on VT8231 and VT8233 .
  28        Aug/06/2003 : change driver format to pci driver .
  29
  30  ********************************************************************/
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/types.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/ioport.h>
  37 #include <linux/delay.h>
  38 #include <linux/slab.h>
  39 #include <linux/init.h>
  40 #include <linux/rtnetlink.h>
  41 #include <linux/pci.h>
  42 #include <linux/dma-mapping.h>
  43
  44 #include <asm/io.h>
  45 #include <asm/dma.h>
  46 #include <asm/byteorder.h>
  47
  48 #include <linux/pm.h>
  49
  50 #include <net/irda/wrapper.h>
  51 #include <net/irda/irda.h>
  52 #include <net/irda/irda_device.h>
  53
  54 #include "via-ircc.h"
  55
  56 //#define DBG_IO        1
  57 //#define   DBGMSG 1
  58 //#define   DBGMSG_96 1
  59 //#define   DBGMSG_76 1
  60 //static int debug=0;
  61
  62
  63 #define DBG(x) {if (debug) x;}
  64
  65 #define   VIA_MODULE_NAME "via-ircc"
  66 #define CHIP_IO_EXTENT 8
  67 #define BROKEN_DONGLE_ID
  68
  69 static char *driver_name = "via-ircc";
  70
  71 /* Module parameters */
  72 static int qos_mtt_bits = 0x07; /* 1 ms or more */
  73 static int dongle_id = 9;       //defalut IBM type
  74
  75 /* Resource is allocate by BIOS user only need to supply dongle_id*/
  76 MODULE_PARM(dongle_id, "i");
  77
  78 /* Max 4 instances for now */
  79 static struct via_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  80
  81 /* Some prototypes */
  82 static int via_ircc_open(int i, chipio_t * info, unsigned int id);
  83 static int __exit via_ircc_close(struct via_ircc_cb *self);
  84 static int via_ircc_setup(chipio_t * info, unsigned int id);
  85 static int via_ircc_dma_receive(struct via_ircc_cb *self);
  86 static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  87                                          int iobase);
  88 static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  89                                   struct net_device *dev);
  90 static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  91                                   struct net_device *dev);
  92 static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 baud);
  93 static irqreturn_t via_ircc_interrupt(int irq, void *dev_id,
  94                                       struct pt_regs *regs);
  95 static int via_ircc_is_receiving(struct via_ircc_cb *self);
  96 static int via_ircc_read_dongle_id(int iobase);
  97
  98 static int via_ircc_net_open(struct net_device *dev);
  99 static int via_ircc_net_close(struct net_device *dev);
 100 static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
 101                               int cmd);
 102 static struct net_device_stats *via_ircc_net_get_stats(struct net_device
 103                                                        *dev);
 104 static void via_ircc_change_dongle_speed(int iobase, int speed,
 105                                          int dongle_id);
 106 static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
 107 static void hwreset(struct via_ircc_cb *self);
 108 static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
 109 static int upload_rxdata(struct via_ircc_cb *self, int iobase);
 110 static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id);
 111 static void __exit via_remove_one (struct pci_dev *pdev);
 112
 113 /* Should use udelay() instead, even if we are x86 only - Jean II */
 114 static void iodelay(int udelay)
 115 {
 116         u8 data;
 117         int i;
 118
 119         for (i = 0; i < udelay; i++) {
 120                 data = inb(0x80);
 121         }
 122 }
 123
 124 static struct pci_device_id via_pci_tbl[] = {
 125         { PCI_VENDOR_ID_VIA, DeviceID1, PCI_ANY_ID, PCI_ANY_ID,0,0,0 },
 126         { PCI_VENDOR_ID_VIA, DeviceID2, PCI_ANY_ID, PCI_ANY_ID,0,0,1 },
 127         { PCI_VENDOR_ID_VIA, DeviceID3, PCI_ANY_ID, PCI_ANY_ID,0,0,2 },
 128         { PCI_VENDOR_ID_VIA, DeviceID4, PCI_ANY_ID, PCI_ANY_ID,0,0,3 },
 129         { PCI_VENDOR_ID_VIA, DeviceID5, PCI_ANY_ID, PCI_ANY_ID,0,0,4 },
 130         { 0, }
 131 };
 132
 133 MODULE_DEVICE_TABLE(pci,via_pci_tbl);
 134
 135
 136 static struct pci_driver via_driver = {
 137         .name           = VIA_MODULE_NAME,
 138         .id_table       = via_pci_tbl,
 139         .probe          = via_init_one,
 140         .remove         = via_remove_one,
 141 };
 142
 143
 144 /*
 145  * Function via_ircc_init ()
 146  *
 147  *    Initialize chip. Just find out chip type and resource.
 148  */
 149 static int __init via_ircc_init(void)
 150 {
 151         int rc;
 152
 153 #ifdef  HEADMSG
 154         DBG(printk(KERN_INFO "via_ircc_init ......\n"));
 155 #endif
 156         rc = pci_register_driver (&via_driver);
 157 #ifdef  HEADMSG
 158         DBG(printk(KERN_INFO "via_ircc_init :rc = %d......\n",rc));
 159 #endif
 160         if (rc < 1) {
 161 #ifdef  HEADMSG
 162         DBG(printk(KERN_INFO "via_ircc_init return -ENODEV......\n"));
 163 #endif
 164                 if (rc == 0)    pci_unregister_driver (&via_driver);
 165                 return -ENODEV;
 166         }
 167         return 0;
 168
 169 }
 170
 171 static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id)
 172 {
 173         int rc;
 174         u8 temp,oldPCI_40,oldPCI_44,bTmp,bTmp1;
 175         u16 Chipset,FirDRQ1,FirDRQ0,FirIRQ,FirIOBase;
 176         chipio_t info;
 177
 178 #ifdef  HEADMSG
 179         DBG(printk(KERN_INFO "via_init_one : Device ID=(0X%X)\n",id->device));
 180 #endif
 181         if(id->device != DeviceID1 && id->device != DeviceID2 &&
 182            id->device != DeviceID3 && id->device != DeviceID4 &&
 183            id->device != DeviceID5  ){
 184 #ifdef  HEADMSG
 185                 DBG(printk(KERN_INFO "via_init_one : Device ID(0X%X) not Supported\n",id->device));
 186 #endif
 187               return -ENODEV; //South not exist !!!!!
 188         }
 189         rc = pci_enable_device (pcidev);
 190 #ifdef  HEADMSG
 191         DBG(printk(KERN_INFO "via_init_one : rc=%d\n",rc));
 192 #endif
 193         if (rc)
 194                 return -ENODEV;
 195         //South Bridge exist
 196         if ( ReadLPCReg(0x20) != 0x3C )
 197                 Chipset=0x3096;
 198         else
 199                 Chipset=0x3076;
 200         if (Chipset==0x3076) {
 201 #ifdef  HEADMSG
 202                 DBG(printk(KERN_INFO "via_init_one : 3076 ......\n"));
 203 #endif
 204                 WriteLPCReg(7,0x0c );
 205                 temp=ReadLPCReg(0x30);//check if BIOS Enable Fir
 206                 if((temp&0x01)==1) {   // BIOS close or no FIR
 207                         WriteLPCReg(0x1d, 0x82 );
 208                         WriteLPCReg(0x23,0x18);
 209                         temp=ReadLPCReg(0xF0);
 210                         if((temp&0x01)==0) {
 211                                 temp=(ReadLPCReg(0x74)&0x03);    //DMA
 212                                 FirDRQ0=temp + 4;
 213                                 temp=(ReadLPCReg(0x74)&0x0C) >> 2;
 214                                 FirDRQ1=temp + 4;
 215                         } else {
 216                                 temp=(ReadLPCReg(0x74)&0x0C) >> 2;    //DMA
 217                                 FirDRQ0=temp + 4;
 218                                 FirDRQ1=FirDRQ0;
 219                         }
 220                         FirIRQ=(ReadLPCReg(0x70)&0x0f);         //IRQ
 221                         FirIOBase=ReadLPCReg(0x60 ) << 8;       //IO Space :high byte
 222                         FirIOBase=FirIOBase| ReadLPCReg(0x61) ; //low byte
 223                         FirIOBase=FirIOBase  ;
 224                         info.fir_base=FirIOBase;
 225                         info.irq=FirIRQ;
 226                         info.dma=FirDRQ1;
 227                         info.dma2=FirDRQ0;
 228                         pci_read_config_byte(pcidev,0x40,&bTmp);
 229                         pci_write_config_byte(pcidev,0x40,((bTmp | 0x08) & 0xfe));
 230                         pci_read_config_byte(pcidev,0x42,&bTmp);
 231                         pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
 232                         pci_write_config_byte(pcidev,0x5a,0xc0);
 233                         WriteLPCReg(0x28, 0x70 );
 234                         if (via_ircc_open(0, &info,0x3076) == 0)
 235                                 rc=0;
 236                 } else
 237                         rc = -ENODEV; //IR not turn on
 238         } else { //Not VT1211
 239 #ifdef  HEADMSG
 240                 DBG(printk(KERN_INFO "via_init_one : 3096 ......\n"));
 241 #endif
 242                 pci_read_config_byte(pcidev,0x67,&bTmp);//check if BIOS Enable Fir
 243                 if((bTmp&0x01)==1) {  // BIOS enable FIR
 244                         //Enable Double DMA clock
 245                         pci_read_config_byte(pcidev,0x42,&oldPCI_40);
 246                         pci_write_config_byte(pcidev,0x42,oldPCI_40 | 0x80);
 247                         pci_read_config_byte(pcidev,0x40,&oldPCI_40);
 248                         pci_write_config_byte(pcidev,0x40,oldPCI_40 & 0xf7);
 249                         pci_read_config_byte(pcidev,0x44,&oldPCI_44);
 250                         pci_write_config_byte(pcidev,0x44,0x4e);
 251   //---------- read configuration from Function0 of south bridge
 252                         if((bTmp&0x02)==0) {
 253                                 pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
 254                                 FirDRQ0 = (bTmp1 & 0x30) >> 4;
 255                                 pci_read_config_byte(pcidev,0x44,&bTmp1);
 256                                 FirDRQ1 = (bTmp1 & 0xc0) >> 6;
 257                         } else  {
 258                                 pci_read_config_byte(pcidev,0x44,&bTmp1);    //DMA
 259                                 FirDRQ0 = (bTmp1 & 0x30) >> 4 ;
 260                                 FirDRQ1=0;
 261                         }
 262                         pci_read_config_byte(pcidev,0x47,&bTmp1);  //IRQ
 263                         FirIRQ = bTmp1 & 0x0f;
 264
 265                         pci_read_config_byte(pcidev,0x69,&bTmp);
 266                         FirIOBase = bTmp << 8;//hight byte
 267                         pci_read_config_byte(pcidev,0x68,&bTmp);
 268                         FirIOBase = (FirIOBase | bTmp ) & 0xfff0;
 269   //-------------------------
 270                         info.fir_base=FirIOBase;
 271                         info.irq=FirIRQ;
 272                         info.dma=FirDRQ1;
 273                         info.dma2=FirDRQ0;
 274                         if (via_ircc_open(0, &info,0x3096) == 0)
 275                                 rc=0;
 276                 } else
 277                         rc = -ENODEV; //IR not turn on !!!!!
 278         }//Not VT1211
 279 #ifdef  HEADMSG
 280         DBG(printk(KERN_INFO "via_init_one End : rc=%d\n",rc));
 281 #endif
 282         return rc;
 283 }
 284
 285 /*
 286  * Function via_ircc_clean ()
 287  *
 288  *    Close all configured chips
 289  *
 290  */
 291 static void __exit via_ircc_clean(void)
 292 {
 293         int i;
 294
 295 #ifdef  HEADMSG
 296         DBG(printk(KERN_INFO "via_ircc_clean\n"));
 297 #endif
 298         for (i=0; i < 4; i++) {
 299                 if (dev_self[i])
 300                         via_ircc_close(dev_self[i]);
 301         }
 302 }
 303
 304 static void __exit via_remove_one (struct pci_dev *pdev)
 305 {
 306 #ifdef  HEADMSG
 307         DBG(printk(KERN_INFO "via_remove_one :  ......\n"));
 308 #endif
 309         via_ircc_clean();
 310
 311 }
 312
 313 static void __exit via_ircc_cleanup(void)
 314 {
 315
 316 #ifdef  HEADMSG
 317         DBG(printk(KERN_INFO "via_ircc_cleanup ......\n"));
 318 #endif
 319         via_ircc_clean();
 320         pci_unregister_driver (&via_driver);
 321 }
 322
 323 /*
 324  * Function via_ircc_open (iobase, irq)
 325  *
 326  *    Open driver instance
 327  *
 328  */
 329 static __devinit int via_ircc_open(int i, chipio_t * info, unsigned int id)
 330 {
 331         struct net_device *dev;
 332         struct via_ircc_cb *self;
 333         int err;
 334
 335         if ((via_ircc_setup(info, id)) == -1)
 336                 return -1;
 337
 338         /* Allocate new instance of the driver */
 339         dev = alloc_irdadev(sizeof(struct via_ircc_cb));
 340         if (dev == NULL)
 341                 return -ENOMEM;
 342
 343         self = dev->priv;
 344         self->netdev = dev;
 345         spin_lock_init(&self->lock);
 346
 347         /* Need to store self somewhere */
 348         dev_self[i] = self;
 349         self->index = i;
 350         /* Initialize Resource */
 351         self->io.cfg_base = info->cfg_base;
 352         self->io.fir_base = info->fir_base;
 353         self->io.irq = info->irq;
 354         self->io.fir_ext = CHIP_IO_EXTENT;
 355         self->io.dma = info->dma;
 356         self->io.dma2 = info->dma2;
 357         self->io.fifo_size = 32;
 358         self->chip_id = id;
 359         self->st_fifo.len = 0;
 360         self->RxDataReady = 0;
 361
 362         /* Reserve the ioports that we need */
 363         if (!request_region(self->io.fir_base, self->io.fir_ext, driver_name)) {
 364 //              WARNING("%s(), can't get iobase of 0x%03x\n", __FUNCTION__, self->io.fir_base);
 365                 err = -ENODEV;
 366                 goto err_out1;
 367         }
 368
 369         /* Initialize QoS for this device */
 370         irda_init_max_qos_capabilies(&self->qos);
 371         /* The only value we must override it the baudrate */
 372 //      self->qos.baud_rate.bits = IR_9600;// May use this for testing
 373
 374         self->qos.baud_rate.bits =
 375             IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200 |
 376             IR_576000 | IR_1152000 | (IR_4000000 << 8);
 377
 378         self->qos.min_turn_time.bits = qos_mtt_bits;
 379         irda_qos_bits_to_value(&self->qos);
 380
 381         /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
 382         self->rx_buff.truesize = 14384 + 2048;
 383         self->tx_buff.truesize = 14384 + 2048;
 384
 385         /* Allocate memory if needed */
 386         self->rx_buff.head =
 387                 dma_alloc_coherent(NULL, self->rx_buff.truesize,
 388                                    &self->rx_buff_dma, GFP_KERNEL);
 389         if (self->rx_buff.head == NULL) {
 390                 err = -ENOMEM;
 391                 goto err_out2;
 392         }
 393         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 394
 395         self->tx_buff.head =
 396                 dma_alloc_coherent(NULL, self->tx_buff.truesize,
 397                                    &self->tx_buff_dma, GFP_KERNEL);
 398         if (self->tx_buff.head == NULL) {
 399                 err = -ENOMEM;
 400                 goto err_out3;
 401         }
 402         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 403
 404         self->rx_buff.in_frame = FALSE;
 405         self->rx_buff.state = OUTSIDE_FRAME;
 406         self->tx_buff.data = self->tx_buff.head;
 407         self->rx_buff.data = self->rx_buff.head;
 408
 409         /* Reset Tx queue info */
 410         self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
 411         self->tx_fifo.tail = self->tx_buff.head;
 412
 413         /* Keep track of module usage */
 414         SET_MODULE_OWNER(dev);
 415
 416         /* Override the network functions we need to use */
 417         dev->hard_start_xmit = via_ircc_hard_xmit_sir;
 418         dev->open = via_ircc_net_open;
 419         dev->stop = via_ircc_net_close;
 420         dev->do_ioctl = via_ircc_net_ioctl;
 421         dev->get_stats = via_ircc_net_get_stats;
 422
 423         err = register_netdev(dev);
 424         if (err)
 425                 goto err_out4;
 426
 427         MESSAGE("IrDA: Registered device %s\n", dev->name);
 428
 429         /* Check if user has supplied the dongle id or not */
 430         if (!dongle_id)
 431                 dongle_id = via_ircc_read_dongle_id(self->io.fir_base);
 432         self->io.dongle_id = dongle_id;
 433         via_ircc_change_dongle_speed(self->io.fir_base, 9600,
 434                                      self->io.dongle_id);
 435
 436         return 0;
 437  err_out4:
 438         dma_free_coherent(NULL, self->tx_buff.truesize,
 439                           self->tx_buff.head, self->tx_buff_dma);
 440  err_out3:
 441         dma_free_coherent(NULL, self->rx_buff.truesize,
 442                           self->rx_buff.head, self->rx_buff_dma);
 443  err_out2:
 444         release_region(self->io.fir_base, self->io.fir_ext);
 445  err_out1:
 446         free_netdev(dev);
 447         dev_self[i] = NULL;
 448         return err;
 449 }
 450
 451 /*
 452  * Function via_ircc_close (self)
 453  *
 454  *    Close driver instance
 455  *
 456  */
 457 static int __exit via_ircc_close(struct via_ircc_cb *self)
 458 {
 459         int iobase;
 460
 461         IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
 462
 463         ASSERT(self != NULL, return -1;);
 464
 465         iobase = self->io.fir_base;
 466
 467         ResetChip(iobase, 5);   //hardware reset.
 468         /* Remove netdevice */
 469         unregister_netdev(self->netdev);
 470
 471         /* Release the PORT that this driver is using */
 472         IRDA_DEBUG(4, "%s(), Releasing Region %03x\n",
 473                    __FUNCTION__, self->io.fir_base);
 474         release_region(self->io.fir_base, self->io.fir_ext);
 475         if (self->tx_buff.head)
 476                 dma_free_coherent(NULL, self->tx_buff.truesize,
 477                                   self->tx_buff.head, self->tx_buff_dma);
 478         if (self->rx_buff.head)
 479                 dma_free_coherent(NULL, self->rx_buff.truesize,
 480                                   self->rx_buff.head, self->rx_buff_dma);
 481         dev_self[self->index] = NULL;
 482
 483         free_netdev(self->netdev);
 484
 485         return 0;
 486 }
 487
 488 /*
 489  * Function via_ircc_setup (info)
 490  *
 491  *    Returns non-negative on success.
 492  *
 493  */
 494 static int via_ircc_setup(chipio_t * info, unsigned int chip_id)
 495 {
 496         int iobase = info->fir_base;
 497
 498         SetMaxRxPacketSize(iobase, 0x0fff);     //set to max:4095
 499         // FIFO Init
 500         EnRXFIFOReadyInt(iobase, OFF);
 501         EnRXFIFOHalfLevelInt(iobase, OFF);
 502         EnTXFIFOHalfLevelInt(iobase, OFF);
 503         EnTXFIFOUnderrunEOMInt(iobase, ON);
 504         EnTXFIFOReadyInt(iobase, OFF);
 505         InvertTX(iobase, OFF);
 506         InvertRX(iobase, OFF);
 507         if (ReadLPCReg(0x20) == 0x3c)
 508                 WriteLPCReg(0xF0, 0);   // for VT1211
 509         if (IsSIROn(iobase)) {
 510                 SIRFilter(iobase, ON);
 511                 SIRRecvAny(iobase, ON);
 512         } else {
 513                 SIRFilter(iobase, OFF);
 514                 SIRRecvAny(iobase, OFF);
 515         }
 516         //Int Init
 517         EnRXSpecInt(iobase, ON);
 518         //DMA Init Later....
 519         WriteReg(iobase, I_ST_CT_0, 0x80);
 520         EnableDMA(iobase, ON);
 521
 522         return 0;
 523 }
 524
 525 /*
 526  * Function via_ircc_read_dongle_id (void)
 527  *
 528  */
 529 static int via_ircc_read_dongle_id(int iobase)
 530 {
 531         int dongle_id = 9;
 532
 533         return dongle_id;
 534 }
 535
 536 /*
 537  * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
 538  *    Change speed of the attach dongle
 539  *    only implement two type of dongle currently.
 540  */
 541 static void via_ircc_change_dongle_speed(int iobase, int speed,
 542                                          int dongle_id)
 543 {
 544         u8 mode = 0;
 545
 546         WriteReg(iobase, I_ST_CT_0, 0x0);
 547         switch (dongle_id) {    //HP1100
 548         case 0x00:              /* same as */
 549         case 0x01:              /* Differential serial interface */
 550                 break;
 551         case 0x02:              /* same as */
 552         case 0x03:              /* Reserved */
 553                 break;
 554         case 0x04:              /* Sharp RY5HD01 */
 555                 break;
 556         case 0x05:              /* Reserved, but this is what the Thinkpad reports */
 557                 break;
 558         case 0x06:              /* Single-ended serial interface */
 559                 break;
 560         case 0x07:              /* Consumer-IR only */
 561                 break;
 562
 563         case 0x08:              /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
 564                 UseOneRX(iobase, ON);   // use one RX pin   RX1,RX2
 565                 InvertTX(iobase, OFF);
 566                 InvertRX(iobase, OFF);
 567
 568                 EnRX2(iobase, ON);      //sir to rx2
 569                 EnGPIOtoRX2(iobase, OFF);
 570
 571                 if (IsSIROn(iobase)) {  //sir
 572                         // Mode select Off
 573                         SlowIRRXLowActive(iobase, ON);
 574                         udelay(1000);
 575                         SlowIRRXLowActive(iobase, OFF);
 576                 } else {
 577                         if (IsMIROn(iobase)) {  //mir
 578                                 // Mode select On
 579                                 SlowIRRXLowActive(iobase, OFF);
 580                                 udelay(20);
 581                         } else {        // fir
 582                                 if (IsFIROn(iobase)) {  //fir
 583                                         // Mode select On
 584                                         SlowIRRXLowActive(iobase, OFF);
 585                                         udelay(20);
 586                                 }
 587                         }
 588                 }
 589                 break;
 590         case 0x09:              /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
 591                 UseOneRX(iobase, ON);   //use ONE RX....RX1
 592                 InvertTX(iobase, OFF);
 593                 InvertRX(iobase, OFF);  // invert RX pin
 594                 EnRX2(iobase, ON);
 595                 EnGPIOtoRX2(iobase, OFF);
 596                 if (IsSIROn(iobase)) {  //sir
 597                         // Mode select On
 598                         SlowIRRXLowActive(iobase, ON);
 599                         udelay(20);
 600                         // Mode select Off
 601                         SlowIRRXLowActive(iobase, OFF);
 602                 }
 603                 if (IsMIROn(iobase)) {  //mir
 604                         // Mode select On
 605                         SlowIRRXLowActive(iobase, OFF);
 606                         udelay(20);
 607                         // Mode select Off
 608                         SlowIRRXLowActive(iobase, ON);
 609                 } else {        // fir
 610                         if (IsFIROn(iobase)) {  //fir
 611                                 // Mode select On
 612                                 SlowIRRXLowActive(iobase, OFF);
 613                                 // TX On
 614                                 WriteTX(iobase, ON);
 615                                 udelay(20);
 616                                 // Mode select OFF
 617                                 SlowIRRXLowActive(iobase, ON);
 618                                 udelay(20);
 619                                 // TX Off
 620                                 WriteTX(iobase, OFF);
 621                         }
 622                 }
 623                 break;
 624         case 0x0d:
 625                 UseOneRX(iobase, OFF);  // use two RX pin   RX1,RX2
 626                 InvertTX(iobase, OFF);
 627                 InvertRX(iobase, OFF);
 628                 SlowIRRXLowActive(iobase, OFF);
 629                 if (IsSIROn(iobase)) {  //sir
 630                         EnGPIOtoRX2(iobase, OFF);
 631                         WriteGIO(iobase, OFF);
 632                         EnRX2(iobase, OFF);     //sir to rx2
 633                 } else {        // fir mir
 634                         EnGPIOtoRX2(iobase, OFF);
 635                         WriteGIO(iobase, OFF);
 636                         EnRX2(iobase, OFF);     //fir to rx
 637                 }
 638                 break;
 639         case 0x0ff:             /* Vishay */
 640                 if (IsSIROn(iobase))
 641                         mode = 0;
 642                 else if (IsMIROn(iobase))
 643                         mode = 1;
 644                 else if (IsFIROn(iobase))
 645                         mode = 2;
 646                 else if (IsVFIROn(iobase))
 647                         mode = 5;       //VFIR-16
 648                 SI_SetMode(iobase, mode);
 649         }
 650         WriteReg(iobase, I_ST_CT_0, 0x80);
 651
 652 }
 653
 654 /*
 655  * Function via_ircc_change_speed (self, baud)
 656  *
 657  *    Change the speed of the device
 658  *
 659  */
 660 static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 speed)
 661 {
 662         struct net_device *dev = self->netdev;
 663         u16 iobase;
 664         u8 value = 0, bTmp;
 665
 666         iobase = self->io.fir_base;
 667         /* Update accounting for new speed */
 668         self->io.speed = speed;
 669 #ifdef  DBGMSG
 670         DBG(printk(KERN_INFO "change_speed =%x......\n", speed));
 671 #endif
 672
 673 #ifdef  DBG_IO
 674         if (self->io.speed > 0x2580)
 675                 outb(0xaa, 0x90);
 676         else
 677                 outb(0xbb, 0x90);
 678 #endif
 679
 680
 681         /* Controller mode sellection */
 682         switch (speed) {
 683         case 9600:
 684                 value = 11;
 685                 SetSIR(iobase, ON);
 686                 CRC16(iobase, ON);
 687                 break;
 688         case 19200:
 689                 value = 5;
 690                 SetSIR(iobase, ON);
 691                 CRC16(iobase, ON);
 692                 break;
 693         case 38400:
 694                 value = 2;
 695                 SetSIR(iobase, ON);
 696                 CRC16(iobase, ON);
 697                 break;
 698         case 57600:
 699                 value = 1;
 700                 SetSIR(iobase, ON);
 701                 CRC16(iobase, ON);
 702                 break;
 703         case 115200:
 704                 value = 0;
 705                 SetSIR(iobase, ON);
 706                 CRC16(iobase, ON);
 707                 break;
 708         case 576000:
 709                 value = 0;
 710                 SetSIR(iobase, ON);
 711                 CRC16(iobase, ON);
 712                 break;
 713         case 1152000:
 714                 value = 0;
 715                 SetMIR(iobase, ON);
 716                 break;
 717         case 4000000:
 718                 value = 0;
 719                 SetFIR(iobase, ON);
 720                 SetPulseWidth(iobase, 0);
 721                 SetSendPreambleCount(iobase, 14);
 722                 CRC16(iobase, OFF);
 723                 EnTXCRC(iobase, ON);
 724                 break;
 725         case 16000000:
 726                 value = 0;
 727                 SetVFIR(iobase, ON);
 728                 break;
 729         default:
 730                 value = 0;
 731                 break;
 732         }
 733         /* Set baudrate to 0x19[2..7] */
 734         bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
 735         bTmp = bTmp | (value << 2);
 736         WriteReg(iobase, I_CF_H_1, bTmp);
 737         via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
 738 // EnTXFIFOHalfLevelInt(iobase,ON);
 739         /* Set FIFO size to 64 */
 740         SetFIFO(iobase, 64);
 741         /* Enable some interrupts so we can receive frames */
 742         //EnAllInt(iobase,ON);
 743
 744         if (IsSIROn(iobase)) {
 745                 SIRFilter(iobase, ON);
 746                 SIRRecvAny(iobase, ON);
 747         } else {
 748                 SIRFilter(iobase, OFF);
 749                 SIRRecvAny(iobase, OFF);
 750         }
 751         if (speed > 115200) {
 752                 /* Install FIR xmit handler */
 753                 dev->hard_start_xmit = via_ircc_hard_xmit_fir;
 754                 via_ircc_dma_receive(self);
 755         } else {
 756                 /* Install SIR xmit handler */
 757                 dev->hard_start_xmit = via_ircc_hard_xmit_sir;
 758         }
 759         netif_wake_queue(dev);
 760 }
 761
 762 /*
 763  * Function via_ircc_hard_xmit (skb, dev)
 764  *
 765  *    Transmit the frame!
 766  *
 767  */
 768 static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
 769                                   struct net_device *dev)
 770 {
 771         struct via_ircc_cb *self;
 772         unsigned long flags;
 773         u16 iobase;
 774         __u32 speed;
 775
 776         self = (struct via_ircc_cb *) dev->priv;
 777         ASSERT(self != NULL, return 0;);
 778         iobase = self->io.fir_base;
 779
 780         netif_stop_queue(dev);
 781         /* Check if we need to change the speed */
 782         speed = irda_get_next_speed(skb);
 783         if ((speed != self->io.speed) && (speed != -1)) {
 784                 /* Check for empty frame */
 785                 if (!skb->len) {
 786                         via_ircc_change_speed(self, speed);
 787                         dev->trans_start = jiffies;
 788                         dev_kfree_skb(skb);
 789                         return 0;
 790                 } else
 791                         self->new_speed = speed;
 792         }
 793         InitCard(iobase);
 794         CommonInit(iobase);
 795         SIRFilter(iobase, ON);
 796         SetSIR(iobase, ON);
 797         CRC16(iobase, ON);
 798         EnTXCRC(iobase, 0);
 799         WriteReg(iobase, I_ST_CT_0, 0x00);
 800
 801         spin_lock_irqsave(&self->lock, flags);
 802         self->tx_buff.data = self->tx_buff.head;
 803         self->tx_buff.len =
 804             async_wrap_skb(skb, self->tx_buff.data,
 805                            self->tx_buff.truesize);
 806
 807         self->stats.tx_bytes += self->tx_buff.len;
 808         SetBaudRate(iobase, speed);
 809         SetPulseWidth(iobase, 12);
 810         SetSendPreambleCount(iobase, 0);
 811         WriteReg(iobase, I_ST_CT_0, 0x80);
 812
 813         EnableTX(iobase, ON);
 814         EnableRX(iobase, OFF);
 815
 816         ResetChip(iobase, 0);
 817         ResetChip(iobase, 1);
 818         ResetChip(iobase, 2);
 819         ResetChip(iobase, 3);
 820         ResetChip(iobase, 4);
 821
 822         EnAllInt(iobase, ON);
 823         EnTXDMA(iobase, ON);
 824         EnRXDMA(iobase, OFF);
 825
 826         irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
 827                        DMA_TX_MODE);
 828
 829         SetSendByte(iobase, self->tx_buff.len);
 830         RXStart(iobase, OFF);
 831         TXStart(iobase, ON);
 832
 833         dev->trans_start = jiffies;
 834         spin_unlock_irqrestore(&self->lock, flags);
 835         dev_kfree_skb(skb);
 836         return 0;
 837 }
 838
 839 static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
 840                                   struct net_device *dev)
 841 {
 842         struct via_ircc_cb *self;
 843         u16 iobase;
 844         __u32 speed;
 845         unsigned long flags;
 846
 847         self = (struct via_ircc_cb *) dev->priv;
 848         iobase = self->io.fir_base;
 849
 850         if (self->st_fifo.len)
 851                 return 0;
 852         if (self->chip_id == 0x3076)
 853                 iodelay(1500);
 854         else
 855                 udelay(1500);
 856         netif_stop_queue(dev);
 857         speed = irda_get_next_speed(skb);
 858         if ((speed != self->io.speed) && (speed != -1)) {
 859                 if (!skb->len) {
 860                         via_ircc_change_speed(self, speed);
 861                         dev->trans_start = jiffies;
 862                         dev_kfree_skb(skb);
 863                         return 0;
 864                 } else
 865                         self->new_speed = speed;
 866         }
 867         spin_lock_irqsave(&self->lock, flags);
 868         self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
 869         self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
 870
 871         self->tx_fifo.tail += skb->len;
 872         self->stats.tx_bytes += skb->len;
 873         memcpy(self->tx_fifo.queue[self->tx_fifo.free].start, skb->data,
 874                skb->len);
 875         self->tx_fifo.len++;
 876         self->tx_fifo.free++;
 877 //F01   if (self->tx_fifo.len == 1) {
 878         via_ircc_dma_xmit(self, iobase);
 879 //F01   }
 880 //F01   if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) netif_wake_queue(self->netdev);
 881         dev->trans_start = jiffies;
 882         dev_kfree_skb(skb);
 883         spin_unlock_irqrestore(&self->lock, flags);
 884         return 0;
 885
 886 }
 887
 888 static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
 889 {
 890 //      int i;
 891 //      u8 *ch;
 892
 893         EnTXDMA(iobase, OFF);
 894         self->io.direction = IO_XMIT;
 895         EnPhys(iobase, ON);
 896         EnableTX(iobase, ON);
 897         EnableRX(iobase, OFF);
 898         ResetChip(iobase, 0);
 899         ResetChip(iobase, 1);
 900         ResetChip(iobase, 2);
 901         ResetChip(iobase, 3);
 902         ResetChip(iobase, 4);
 903         EnAllInt(iobase, ON);
 904         EnTXDMA(iobase, ON);
 905         EnRXDMA(iobase, OFF);
 906         irda_setup_dma(self->io.dma,
 907                        ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
 908                         self->tx_buff.head) + self->tx_buff_dma,
 909                        self->tx_fifo.queue[self->tx_fifo.ptr].len, DMA_TX_MODE);
 910 #ifdef  DBGMSG
 911         DBG(printk
 912             (KERN_INFO "dma_xmit:tx_fifo.ptr=%x,len=%x,tx_fifo.len=%x..\n",
 913              self->tx_fifo.ptr, self->tx_fifo.queue[self->tx_fifo.ptr].len,
 914              self->tx_fifo.len));
 915 /*
 916         ch = self->tx_fifo.queue[self->tx_fifo.ptr].start;
 917         for(i=0 ; i < self->tx_fifo.queue[self->tx_fifo.ptr].len ; i++) {
 918             DBG(printk(KERN_INFO "%x..\n",ch[i]));
 919         }
 920 */
 921 #endif
 922
 923         SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
 924         RXStart(iobase, OFF);
 925         TXStart(iobase, ON);
 926         return 0;
 927
 928 }
 929
 930 /*
 931  * Function via_ircc_dma_xmit_complete (self)
 932  *
 933  *    The transfer of a frame in finished. This function will only be called
 934  *    by the interrupt handler
 935  *
 936  */
 937 static int via_ircc_dma_xmit_complete(struct via_ircc_cb *self)
 938 {
 939         int iobase;
 940         int ret = TRUE;
 941         u8 Tx_status;
 942
 943         IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
 944         iobase = self->io.fir_base;
 945         /* Disable DMA */
 946 //      DisableDmaChannel(self->io.dma);
 947         /* Check for underrrun! */
 948         /* Clear bit, by writing 1 into it */
 949         Tx_status = GetTXStatus(iobase);
 950         if (Tx_status & 0x08) {
 951                 self->stats.tx_errors++;
 952                 self->stats.tx_fifo_errors++;
 953                 hwreset(self);
 954 // how to clear underrrun ?
 955         } else {
 956                 self->stats.tx_packets++;
 957                 ResetChip(iobase, 3);
 958                 ResetChip(iobase, 4);
 959         }
 960         /* Check if we need to change the speed */
 961         if (self->new_speed) {
 962                 via_ircc_change_speed(self, self->new_speed);
 963                 self->new_speed = 0;
 964         }
 965
 966         /* Finished with this frame, so prepare for next */
 967         if (IsFIROn(iobase)) {
 968                 if (self->tx_fifo.len) {
 969                         self->tx_fifo.len--;
 970                         self->tx_fifo.ptr++;
 971                 }
 972         }
 973 #ifdef  DBGMSG
 974         DBG(printk
 975             (KERN_INFO
 976              "via_ircc_dma_xmit_complete:tx_fifo.len=%x ,tx_fifo.ptr=%x,tx_fifo.free=%x...\n",
 977              self->tx_fifo.len, self->tx_fifo.ptr, self->tx_fifo.free));
 978 #endif
 979 /* F01_S
 980         // Any frames to be sent back-to-back?
 981         if (self->tx_fifo.len) {
 982                 // Not finished yet!
 983                 via_ircc_dma_xmit(self, iobase);
 984                 ret = FALSE;
 985         } else {
 986 F01_E*/
 987         // Reset Tx FIFO info
 988         self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
 989         self->tx_fifo.tail = self->tx_buff.head;
 990 //F01   }
 991
 992         // Make sure we have room for more frames
 993 //F01   if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) {
 994         // Not busy transmitting anymore
 995         // Tell the network layer, that we can accept more frames
 996         netif_wake_queue(self->netdev);
 997 //F01   }
 998         return ret;
 999 }
1000
1001 /*
1002  * Function via_ircc_dma_receive (self)
1003  *
1004  *    Set configuration for receive a frame.
1005  *
1006  */
1007 static int via_ircc_dma_receive(struct via_ircc_cb *self)
1008 {
1009         int iobase;
1010
1011         iobase = self->io.fir_base;
1012
1013         self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1014         self->tx_fifo.tail = self->tx_buff.head;
1015         self->RxDataReady = 0;
1016         self->io.direction = IO_RECV;
1017         self->rx_buff.data = self->rx_buff.head;
1018         self->st_fifo.len = self->st_fifo.pending_bytes = 0;
1019         self->st_fifo.tail = self->st_fifo.head = 0;
1020         EnPhys(iobase, ON);
1021         EnableTX(iobase, OFF);
1022         EnableRX(iobase, ON);
1023
1024         ResetChip(iobase, 0);
1025         ResetChip(iobase, 1);
1026         ResetChip(iobase, 2);
1027         ResetChip(iobase, 3);
1028         ResetChip(iobase, 4);
1029
1030         EnAllInt(iobase, ON);
1031         EnTXDMA(iobase, OFF);
1032         EnRXDMA(iobase, ON);
1033         irda_setup_dma(self->io.dma2, self->rx_buff_dma,
1034                   self->rx_buff.truesize, DMA_RX_MODE);
1035         TXStart(iobase, OFF);
1036         RXStart(iobase, ON);
1037
1038         return 0;
1039 }
1040
1041 /*
1042  * Function via_ircc_dma_receive_complete (self)
1043  *
1044  *    Controller Finished with receiving frames,
1045  *    and this routine is call by ISR
1046  *
1047  */
1048 static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
1049                                          int iobase)
1050 {
1051         struct st_fifo *st_fifo;
1052         struct sk_buff *skb;
1053         int len, i;
1054         u8 status = 0;
1055
1056         iobase = self->io.fir_base;
1057         st_fifo = &self->st_fifo;
1058
1059         if (self->io.speed < 4000000) { //Speed below FIR
1060                 len = GetRecvByte(iobase, self);
1061                 skb = dev_alloc_skb(len + 1);
1062                 if (skb == NULL)
1063                         return FALSE;
1064                 // Make sure IP header gets aligned
1065                 skb_reserve(skb, 1);
1066                 skb_put(skb, len - 2);
1067                 if (self->chip_id == 0x3076) {
1068                         for (i = 0; i < len - 2; i++)
1069                                 skb->data[i] = self->rx_buff.data[i * 2];
1070                 } else {
1071                         if (self->chip_id == 0x3096) {
1072                                 for (i = 0; i < len - 2; i++)
1073                                         skb->data[i] =
1074                                             self->rx_buff.data[i];
1075                         }
1076                 }
1077                 // Move to next frame
1078                 self->rx_buff.data += len;
1079                 self->stats.rx_bytes += len;
1080                 self->stats.rx_packets++;
1081                 skb->dev = self->netdev;
1082                 skb->mac.raw = skb->data;
1083                 skb->protocol = htons(ETH_P_IRDA);
1084                 netif_rx(skb);
1085                 return TRUE;
1086         }
1087
1088         else {                  //FIR mode
1089                 len = GetRecvByte(iobase, self);
1090                 if (len == 0)
1091                         return TRUE;    //interrupt only, data maybe move by RxT
1092                 if (((len - 4) < 2) || ((len - 4) > 2048)) {
1093 #ifdef  DBGMSG
1094                         DBG(printk
1095                             (KERN_INFO
1096                              "receive_comple:Trouble:len=%x,CurCount=%x,LastCount=%x..\n",
1097                              len, RxCurCount(iobase, self),
1098                              self->RxLastCount));
1099 #endif
1100                         hwreset(self);
1101                         return FALSE;
1102                 }
1103 #ifdef  DBGMSG
1104                 DBG(printk
1105                     (KERN_INFO
1106                      "recv_comple:fifo.len=%x,len=%x,CurCount=%x..\n",
1107                      st_fifo->len, len - 4, RxCurCount(iobase, self)));
1108 #endif
1109                 st_fifo->entries[st_fifo->tail].status = status;
1110                 st_fifo->entries[st_fifo->tail].len = len;
1111                 st_fifo->pending_bytes += len;
1112                 st_fifo->tail++;
1113                 st_fifo->len++;
1114                 if (st_fifo->tail > MAX_RX_WINDOW)
1115                         st_fifo->tail = 0;
1116                 self->RxDataReady = 0;
1117
1118                 // It maybe have MAX_RX_WINDOW package receive by
1119                 // receive_complete before Timer IRQ
1120 /* F01_S
1121           if (st_fifo->len < (MAX_RX_WINDOW+2 )) {
1122                   RXStart(iobase,ON);
1123                   SetTimer(iobase,4);
1124           }
1125           else    {
1126 F01_E */
1127                 EnableRX(iobase, OFF);
1128                 EnRXDMA(iobase, OFF);
1129                 RXStart(iobase, OFF);
1130 //F01_S
1131                 // Put this entry back in fifo
1132                 if (st_fifo->head > MAX_RX_WINDOW)
1133                         st_fifo->head = 0;
1134                 status = st_fifo->entries[st_fifo->head].status;
1135                 len = st_fifo->entries[st_fifo->head].len;
1136                 st_fifo->head++;
1137                 st_fifo->len--;
1138
1139                 skb = dev_alloc_skb(len + 1 - 4);
1140                 /*
1141                  * if frame size,data ptr,or skb ptr are wrong ,the get next
1142                  * entry.
1143                  */
1144                 if ((skb == NULL) || (skb->data == NULL)
1145                     || (self->rx_buff.data == NULL) || (len < 6)) {
1146                         self->stats.rx_dropped++;
1147                         return TRUE;
1148                 }
1149                 skb_reserve(skb, 1);
1150                 skb_put(skb, len - 4);
1151                 memcpy(skb->data, self->rx_buff.data, len - 4);
1152 #ifdef  DBGMSG
1153                 DBG(printk
1154                     (KERN_INFO "RxT:len=%x.rx_buff=%x\n", len - 4,
1155                      self->rx_buff.data));
1156 /*              for(i=0 ; i < (len-4) ; i++) {
1157                     DBG(printk(KERN_INFO "%x..\n",self->rx_buff.data[i]));
1158                 }
1159 */
1160 #endif
1161                 // Move to next frame
1162                 self->rx_buff.data += len;
1163                 self->stats.rx_bytes += len;
1164                 self->stats.rx_packets++;
1165                 skb->dev = self->netdev;
1166                 skb->mac.raw = skb->data;
1167                 skb->protocol = htons(ETH_P_IRDA);
1168                 netif_rx(skb);
1169
1170 //F01_E
1171         }                       //FIR
1172         return TRUE;
1173
1174 }
1175
1176 /*
1177  * if frame is received , but no INT ,then use this routine to upload frame.
1178  */
1179 static int upload_rxdata(struct via_ircc_cb *self, int iobase)
1180 {
1181         struct sk_buff *skb;
1182         int len;
1183         struct st_fifo *st_fifo;
1184         st_fifo = &self->st_fifo;
1185
1186         len = GetRecvByte(iobase, self);
1187
1188 #ifdef  DBGMSG
1189         DBG(printk(KERN_INFO "upload_rxdata: len=%x\n", len));
1190 #endif
1191         skb = dev_alloc_skb(len + 1);
1192         if ((skb == NULL) || ((len - 4) < 2)) {
1193                 self->stats.rx_dropped++;
1194                 return FALSE;
1195         }
1196         skb_reserve(skb, 1);
1197         skb_put(skb, len - 4 + 1);
1198         memcpy(skb->data, self->rx_buff.data, len - 4 + 1);
1199         st_fifo->tail++;
1200         st_fifo->len++;
1201         if (st_fifo->tail > MAX_RX_WINDOW)
1202                 st_fifo->tail = 0;
1203         // Move to next frame
1204         self->rx_buff.data += len;
1205         self->stats.rx_bytes += len;
1206         self->stats.rx_packets++;
1207         skb->dev = self->netdev;
1208         skb->mac.raw = skb->data;
1209         skb->protocol = htons(ETH_P_IRDA);
1210         netif_rx(skb);
1211         if (st_fifo->len < (MAX_RX_WINDOW + 2)) {
1212                 RXStart(iobase, ON);
1213         } else {
1214                 EnableRX(iobase, OFF);
1215                 EnRXDMA(iobase, OFF);
1216                 RXStart(iobase, OFF);
1217         }
1218         return TRUE;
1219 }
1220
1221 /*
1222  * Implement back to back receive , use this routine to upload data.
1223  */
1224
1225 static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
1226 {
1227         struct st_fifo *st_fifo;
1228         struct sk_buff *skb;
1229         int len;
1230         u8 status;
1231
1232         st_fifo = &self->st_fifo;
1233
1234         if (CkRxRecv(iobase, self)) {
1235                 // if still receiving ,then return ,don't upload frame
1236                 self->RetryCount = 0;
1237                 SetTimer(iobase, 20);
1238                 self->RxDataReady++;
1239                 return FALSE;
1240         } else
1241                 self->RetryCount++;
1242
1243         if ((self->RetryCount >= 1) ||
1244             ((st_fifo->pending_bytes + 2048) > self->rx_buff.truesize)
1245             || (st_fifo->len >= (MAX_RX_WINDOW))) {
1246                 while (st_fifo->len > 0) {      //upload frame
1247                         // Put this entry back in fifo
1248                         if (st_fifo->head > MAX_RX_WINDOW)
1249                                 st_fifo->head = 0;
1250                         status = st_fifo->entries[st_fifo->head].status;
1251                         len = st_fifo->entries[st_fifo->head].len;
1252                         st_fifo->head++;
1253                         st_fifo->len--;
1254
1255                         skb = dev_alloc_skb(len + 1 - 4);
1256                         /*
1257                          * if frame size, data ptr, or skb ptr are wrong,
1258                          * then get next entry.
1259                          */
1260                         if ((skb == NULL) || (skb->data == NULL)
1261                             || (self->rx_buff.data == NULL) || (len < 6)) {
1262                                 self->stats.rx_dropped++;
1263                                 continue;
1264                         }
1265                         skb_reserve(skb, 1);
1266                         skb_put(skb, len - 4);
1267                         memcpy(skb->data, self->rx_buff.data, len - 4);
1268 #ifdef  DBGMSG
1269                         DBG(printk
1270                             (KERN_INFO "RxT:len=%x.head=%x\n", len - 4,
1271                              st_fifo->head));
1272 #endif
1273                         // Move to next frame
1274                         self->rx_buff.data += len;
1275                         self->stats.rx_bytes += len;
1276                         self->stats.rx_packets++;
1277                         skb->dev = self->netdev;
1278                         skb->mac.raw = skb->data;
1279                         skb->protocol = htons(ETH_P_IRDA);
1280                         netif_rx(skb);
1281                 }               //while
1282                 self->RetryCount = 0;
1283 #ifdef  DBGMSG
1284                 DBG(printk
1285                     (KERN_INFO
1286                      "RxT:End of upload HostStatus=%x,RxStatus=%x\n",
1287                      GetHostStatus(iobase), GetRXStatus(iobase)));
1288 #endif
1289                 /*
1290                  * if frame is receive complete at this routine ,then upload
1291                  * frame.
1292                  */
1293                 if ((GetRXStatus(iobase) & 0x10)
1294                     && (RxCurCount(iobase, self) != self->RxLastCount)) {
1295                         upload_rxdata(self, iobase);
1296                         if (irda_device_txqueue_empty(self->netdev))
1297                                 via_ircc_dma_receive(self);
1298                 }
1299         }                       // timer detect complete
1300         else
1301                 SetTimer(iobase, 4);
1302         return TRUE;
1303
1304 }
1305
1306
1307
1308 /*
1309  * Function via_ircc_interrupt (irq, dev_id, regs)
1310  *
1311  *    An interrupt from the chip has arrived. Time to do some work
1312  *
1313  */
1314 static irqreturn_t via_ircc_interrupt(int irq, void *dev_id,
1315                                       struct pt_regs *regs)
1316 {
1317         struct net_device *dev = (struct net_device *) dev_id;
1318         struct via_ircc_cb *self;
1319         int iobase;
1320         u8 iHostIntType, iRxIntType, iTxIntType;
1321
1322         if (!dev) {
1323                 WARNING("%s: irq %d for unknown device.\n", driver_name,
1324                         irq);
1325                 return IRQ_NONE;
1326         }
1327         self = (struct via_ircc_cb *) dev->priv;
1328         iobase = self->io.fir_base;
1329         spin_lock(&self->lock);
1330         iHostIntType = GetHostStatus(iobase);
1331         if ((iHostIntType & 0x40) != 0) {       //Timer Event
1332                 self->EventFlag.TimeOut++;
1333                 ClearTimerInt(iobase, 1);
1334                 if (self->io.direction == IO_XMIT) {
1335                         via_ircc_dma_xmit(self, iobase);
1336                 }
1337                 if (self->io.direction == IO_RECV) {
1338                         /*
1339                          * frame ready hold too long, must reset.
1340                          */
1341                         if (self->RxDataReady > 30) {
1342                                 hwreset(self);
1343                                 if (irda_device_txqueue_empty
1344                                     (self->netdev)) {
1345                                         via_ircc_dma_receive(self);
1346                                 }
1347                         } else {        // call this to upload frame.
1348                                 RxTimerHandler(self, iobase);
1349                         }
1350                 }               //RECV
1351         }                       //Timer Event
1352         if ((iHostIntType & 0x20) != 0) {       //Tx Event
1353                 iTxIntType = GetTXStatus(iobase);
1354                 if (iTxIntType & 0x4) {
1355                         self->EventFlag.EOMessage++;    // read and will auto clean
1356                         if (via_ircc_dma_xmit_complete(self)) {
1357                                 if (irda_device_txqueue_empty
1358                                     (self->netdev)) {
1359                                         via_ircc_dma_receive(self);
1360                                 }
1361                         } else {
1362                                 self->EventFlag.Unknown++;
1363                         }
1364                 }               //EOP
1365         }                       //Tx Event
1366         //----------------------------------------
1367         if ((iHostIntType & 0x10) != 0) {       //Rx Event
1368                 /* Check if DMA has finished */
1369                 iRxIntType = GetRXStatus(iobase);
1370 #ifdef  DBGMSG
1371                 if (!iRxIntType)
1372                         DBG(printk(KERN_INFO " RxIRQ =0\n"));
1373 #endif
1374                 if (iRxIntType & 0x10) {
1375                         if (via_ircc_dma_receive_complete(self, iobase)) {
1376 //F01       if(!(IsFIROn(iobase)))  via_ircc_dma_receive(self);
1377                                 via_ircc_dma_receive(self);
1378                         }
1379                 }               // No ERR
1380                 else {          //ERR
1381 #ifdef  DBGMSG
1382                         DBG(printk
1383                             (KERN_INFO
1384                              " RxIRQ ERR:iRxIntType=%x,HostIntType=%x,CurCount=%x,RxLastCount=%x_____\n",
1385                              iRxIntType, iHostIntType, RxCurCount(iobase,
1386                                                                   self),
1387                              self->RxLastCount));
1388 #endif
1389                         if (iRxIntType & 0x20) {        //FIFO OverRun ERR
1390                                 ResetChip(iobase, 0);
1391                                 ResetChip(iobase, 1);
1392                         } else {        //PHY,CRC ERR
1393
1394                                 if (iRxIntType != 0x08)
1395                                         hwreset(self);  //F01
1396                         }
1397                         via_ircc_dma_receive(self);
1398                 }               //ERR
1399
1400         }                       //Rx Event
1401         spin_unlock(&self->lock);
1402         return IRQ_RETVAL(iHostIntType);
1403 }
1404
1405 static void hwreset(struct via_ircc_cb *self)
1406 {
1407         int iobase;
1408         iobase = self->io.fir_base;
1409 #ifdef  DBGMSG
1410         DBG(printk(KERN_INFO "hwreset  ....\n"));
1411 #endif
1412         ResetChip(iobase, 5);
1413         EnableDMA(iobase, OFF);
1414         EnableTX(iobase, OFF);
1415         EnableRX(iobase, OFF);
1416         EnRXDMA(iobase, OFF);
1417         EnTXDMA(iobase, OFF);
1418         RXStart(iobase, OFF);
1419         TXStart(iobase, OFF);
1420         InitCard(iobase);
1421         CommonInit(iobase);
1422         SIRFilter(iobase, ON);
1423         SetSIR(iobase, ON);
1424         CRC16(iobase, ON);
1425         EnTXCRC(iobase, 0);
1426         WriteReg(iobase, I_ST_CT_0, 0x00);
1427         SetBaudRate(iobase, 9600);
1428         SetPulseWidth(iobase, 12);
1429         SetSendPreambleCount(iobase, 0);
1430         WriteReg(iobase, I_ST_CT_0, 0x80);
1431         via_ircc_change_speed(self, self->io.speed);
1432         self->st_fifo.len = 0;
1433 }
1434
1435 /*
1436  * Function via_ircc_is_receiving (self)
1437  *
1438  *    Return TRUE is we are currently receiving a frame
1439  *
1440  */
1441 static int via_ircc_is_receiving(struct via_ircc_cb *self)
1442 {
1443         int status = FALSE;
1444         int iobase;
1445
1446         ASSERT(self != NULL, return FALSE;);
1447
1448         iobase = self->io.fir_base;
1449         if (CkRxRecv(iobase, self))
1450                 status = TRUE;
1451 #ifdef  DBGMSG
1452         DBG(printk(KERN_INFO "is_receiving  status=%x....\n", status));
1453 #endif
1454         return status;
1455 }
1456
1457
1458 /*
1459  * Function via_ircc_net_open (dev)
1460  *
1461  *    Start the device
1462  *
1463  */
1464 static int via_ircc_net_open(struct net_device *dev)
1465 {
1466         struct via_ircc_cb *self;
1467         int iobase;
1468         char hwname[32];
1469
1470         IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
1471
1472         ASSERT(dev != NULL, return -1;);
1473         self = (struct via_ircc_cb *) dev->priv;
1474         self->stats.rx_packets = 0;
1475         ASSERT(self != NULL, return 0;);
1476         iobase = self->io.fir_base;
1477         if (request_irq
1478             (self->io.irq, via_ircc_interrupt, 0, dev->name, dev)) {
1479                 WARNING("%s, unable to allocate irq=%d\n", driver_name,
1480                         self->io.irq);
1481                 return -EAGAIN;
1482         }
1483         /*
1484          * Always allocate the DMA channel after the IRQ, and clean up on
1485          * failure.
1486          */
1487         if (request_dma(self->io.dma, dev->name)) {
1488                 WARNING("%s, unable to allocate dma=%d\n", driver_name,
1489                         self->io.dma);
1490                 free_irq(self->io.irq, self);
1491                 return -EAGAIN;
1492         }
1493         if (self->io.dma2 != self->io.dma) {
1494                 if (request_dma(self->io.dma2, dev->name)) {
1495                         WARNING("%s, unable to allocate dma2=%d\n",
1496                                 driver_name, self->io.dma2);
1497                         free_irq(self->io.irq, self);
1498                         return -EAGAIN;
1499                 }
1500         }
1501
1502
1503         /* turn on interrupts */
1504         EnAllInt(iobase, ON);
1505         EnInternalLoop(iobase, OFF);
1506         EnExternalLoop(iobase, OFF);
1507         /* Ready to play! */
1508         netif_start_queue(dev);
1509
1510         /*
1511          * Open new IrLAP layer instance, now that everything should be
1512          * initialized properly
1513          */
1514         sprintf(hwname, "VIA");
1515         /*
1516          * for different kernel ,irlap_open have different parameter.
1517          */
1518         self->irlap = irlap_open(dev, &self->qos, hwname);
1519 //      self->irlap = irlap_open(dev, &self->qos);
1520
1521         self->RxLastCount = 0;
1522
1523         return 0;
1524 }
1525
1526 /*
1527  * Function via_ircc_net_close (dev)
1528  *
1529  *    Stop the device
1530  *
1531  */
1532 static int via_ircc_net_close(struct net_device *dev)
1533 {
1534         struct via_ircc_cb *self;
1535         int iobase;
1536
1537         IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
1538
1539         ASSERT(dev != NULL, return -1;);
1540         self = (struct via_ircc_cb *) dev->priv;
1541         ASSERT(self != NULL, return 0;);
1542
1543 #ifdef  DBG_IO
1544         outb(0xff, 0x90);
1545         outb(0xff, 0x94);
1546 #endif
1547         /* Stop device */
1548         netif_stop_queue(dev);
1549         /* Stop and remove instance of IrLAP */
1550         if (self->irlap)
1551                 irlap_close(self->irlap);
1552         self->irlap = NULL;
1553         iobase = self->io.fir_base;
1554         EnTXDMA(iobase, OFF);
1555         EnRXDMA(iobase, OFF);
1556         DisableDmaChannel(self->io.dma);
1557
1558         /* Disable interrupts */
1559         EnAllInt(iobase, OFF);
1560         free_irq(self->io.irq, dev);
1561         free_dma(self->io.dma);
1562
1563         return 0;
1564 }
1565
1566 /*
1567  * Function via_ircc_net_ioctl (dev, rq, cmd)
1568  *
1569  *    Process IOCTL commands for this device
1570  *
1571  */
1572 static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
1573                               int cmd)
1574 {
1575         struct if_irda_req *irq = (struct if_irda_req *) rq;
1576         struct via_ircc_cb *self;
1577         unsigned long flags;
1578         int ret = 0;
1579
1580         ASSERT(dev != NULL, return -1;);
1581         self = dev->priv;
1582         ASSERT(self != NULL, return -1;);
1583         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name,
1584                    cmd);
1585         /* Disable interrupts & save flags */
1586         spin_lock_irqsave(&self->lock, flags);
1587         switch (cmd) {
1588         case SIOCSBANDWIDTH:    /* Set bandwidth */
1589                 if (!capable(CAP_NET_ADMIN)) {
1590                         ret = -EPERM;
1591                         goto out;
1592                 }
1593                 via_ircc_change_speed(self, irq->ifr_baudrate);
1594                 break;
1595         case SIOCSMEDIABUSY:    /* Set media busy */
1596                 if (!capable(CAP_NET_ADMIN)) {
1597                         ret = -EPERM;
1598                         goto out;
1599                 }
1600                 irda_device_set_media_busy(self->netdev, TRUE);
1601                 break;
1602         case SIOCGRECEIVING:    /* Check if we are receiving right now */
1603                 irq->ifr_receiving = via_ircc_is_receiving(self);
1604                 break;
1605         default:
1606                 ret = -EOPNOTSUPP;
1607         }
1608       out:
1609         spin_unlock_irqrestore(&self->lock, flags);
1610         return ret;
1611 }
1612
1613 static struct net_device_stats *via_ircc_net_get_stats(struct net_device
1614                                                        *dev)
1615 {
1616         struct via_ircc_cb *self = (struct via_ircc_cb *) dev->priv;
1617
1618         return &self->stats;
1619 }
1620
1621 MODULE_AUTHOR("VIA Technologies,inc");
1622 MODULE_DESCRIPTION("VIA IrDA Device Driver");
1623 MODULE_LICENSE("GPL");
1624
1625 module_init(via_ircc_init);
1626 module_exit(via_ircc_cleanup);