drivers/net/irda/via-ircc.c

   1 /********************************************************************
   2  Filename:      via-ircc.c
   3  Version:       1.0
   4  Description:   Driver for the VIA VT8231/VT8233 IrDA chipsets
   5  Author:        VIA Technologies,inc
   6  Date  :        08/06/2003
   7
   8 Copyright (c) 1998-2003 VIA Technologies, Inc.
   9
  10 This program is free software; you can redistribute it and/or modify it under
  11 the terms of the GNU General Public License as published by the Free Software
  12 Foundation; either version 2, or (at your option) any later version.
  13
  14 This program is distributed in the hope that it will be useful, but WITHOUT
  15 ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17 See the GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along with
  20 this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 F01 Oct/02/02: Modify code for V0.11(move out back to back transfer)
  24 F02 Oct/28/02: Add SB device ID for 3147 and 3177.
  25  Comment :
  26        jul/09/2002 : only implement two kind of dongle currently.
  27        Oct/02/2002 : work on VT8231 and VT8233 .
  28        Aug/06/2003 : change driver format to pci driver .
  29
  30  ********************************************************************/
  31 #include <linux/module.h>
  32 #include <linux/kernel.h>
  33 #include <linux/types.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/ioport.h>
  37 #include <linux/delay.h>
  38 #include <linux/slab.h>
  39 #include <linux/init.h>
  40 #include <linux/rtnetlink.h>
  41 #include <linux/pci.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/dma.h>
  45 #include <asm/byteorder.h>
  46
  47 #include <linux/pm.h>
  48
  49 #include <net/irda/wrapper.h>
  50 #include <net/irda/irda.h>
  51 #include <net/irda/irda_device.h>
  52
  53 #include "via-ircc.h"
  54
  55 //#define DBG_IO        1
  56 //#define   DBGMSG 1
  57 //#define   DBGMSG_96 1
  58 //#define   DBGMSG_76 1
  59 //static int debug=0;
  60
  61
  62 #define DBG(x) {if (debug) x;}
  63
  64 #define   VIA_MODULE_NAME "via-ircc"
  65 #define CHIP_IO_EXTENT 8
  66 #define BROKEN_DONGLE_ID
  67
  68 static char *driver_name = "via-ircc";
  69
  70 /* Module parameters */
  71 static int qos_mtt_bits = 0x07; /* 1 ms or more */
  72 static int dongle_id = 9;       //defalut IBM type
  73
  74 /* Resource is allocate by BIOS user only need to supply dongle_id*/
  75 MODULE_PARM(dongle_id, "i");
  76
  77 /* Max 4 instances for now */
  78 static struct via_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  79
  80 /* Some prototypes */
  81 static int via_ircc_open(int i, chipio_t * info, unsigned int id);
  82 static int __exit via_ircc_close(struct via_ircc_cb *self);
  83 static int via_ircc_setup(chipio_t * info, unsigned int id);
  84 static int via_ircc_dma_receive(struct via_ircc_cb *self);
  85 static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  86                                          int iobase);
  87 static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  88                                   struct net_device *dev);
  89 static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  90                                   struct net_device *dev);
  91 static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 baud);
  92 static irqreturn_t via_ircc_interrupt(int irq, void *dev_id,
  93                                       struct pt_regs *regs);
  94 static int via_ircc_is_receiving(struct via_ircc_cb *self);
  95 static int via_ircc_read_dongle_id(int iobase);
  96
  97 static int via_ircc_net_open(struct net_device *dev);
  98 static int via_ircc_net_close(struct net_device *dev);
  99 static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
 100                               int cmd);
 101 static struct net_device_stats *via_ircc_net_get_stats(struct net_device
 102                                                        *dev);
 103 static void via_ircc_change_dongle_speed(int iobase, int speed,
 104                                          int dongle_id);
 105 static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
 106 static void hwreset(struct via_ircc_cb *self);
 107 static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
 108 static int upload_rxdata(struct via_ircc_cb *self, int iobase);
 109 static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id);
 110 static void __exit via_remove_one (struct pci_dev *pdev);
 111
 112 /* Should use udelay() instead, even if we are x86 only - Jean II */
 113 static void iodelay(int udelay)
 114 {
 115         u8 data;
 116         int i;
 117
 118         for (i = 0; i < udelay; i++) {
 119                 data = inb(0x80);
 120         }
 121 }
 122
 123 static struct pci_device_id via_pci_tbl[] = {
 124         { PCI_VENDOR_ID_VIA, DeviceID1, PCI_ANY_ID, PCI_ANY_ID,0,0,0 },
 125         { PCI_VENDOR_ID_VIA, DeviceID2, PCI_ANY_ID, PCI_ANY_ID,0,0,1 },
 126         { PCI_VENDOR_ID_VIA, DeviceID3, PCI_ANY_ID, PCI_ANY_ID,0,0,2 },
 127         { PCI_VENDOR_ID_VIA, DeviceID4, PCI_ANY_ID, PCI_ANY_ID,0,0,3 },
 128         { PCI_VENDOR_ID_VIA, DeviceID5, PCI_ANY_ID, PCI_ANY_ID,0,0,4 },
 129         { 0, }
 130 };
 131
 132 MODULE_DEVICE_TABLE(pci,via_pci_tbl);
 133
 134
 135 static struct pci_driver via_driver = {
 136         .name           = VIA_MODULE_NAME,
 137         .id_table       = via_pci_tbl,
 138         .probe          = via_init_one,
 139         .remove         = via_remove_one,
 140 };
 141
 142
 143 /*
 144  * Function via_ircc_init ()
 145  *
 146  *    Initialize chip. Just find out chip type and resource.
 147  */
 148 static int __init via_ircc_init(void)
 149 {
 150         int rc;
 151
 152 #ifdef  HEADMSG
 153         DBG(printk(KERN_INFO "via_ircc_init ......\n"));
 154 #endif
 155         rc = pci_register_driver (&via_driver);
 156 #ifdef  HEADMSG
 157         DBG(printk(KERN_INFO "via_ircc_init :rc = %d......\n",rc));
 158 #endif
 159         if (rc < 1) {
 160 #ifdef  HEADMSG
 161         DBG(printk(KERN_INFO "via_ircc_init return -ENODEV......\n"));
 162 #endif
 163                 if (rc == 0)    pci_unregister_driver (&via_driver);
 164                 return -ENODEV;
 165         }
 166         return 0;
 167
 168 }
 169
 170 static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id)
 171 {
 172         int rc;
 173         u8 temp,oldPCI_40,oldPCI_44,bTmp,bTmp1;
 174         u16 Chipset,FirDRQ1,FirDRQ0,FirIRQ,FirIOBase;
 175         chipio_t info;
 176
 177 #ifdef  HEADMSG
 178         DBG(printk(KERN_INFO "via_init_one : Device ID=(0X%X)\n",id->device));
 179 #endif
 180         if(id->device != DeviceID1 && id->device != DeviceID2 &&
 181            id->device != DeviceID3 && id->device != DeviceID4 &&
 182            id->device != DeviceID5  ){
 183 #ifdef  HEADMSG
 184                 DBG(printk(KERN_INFO "via_init_one : Device ID(0X%X) not Supported\n",id->device));
 185 #endif
 186               return -ENODEV; //South not exist !!!!!
 187         }
 188         rc = pci_enable_device (pcidev);
 189 #ifdef  HEADMSG
 190         DBG(printk(KERN_INFO "via_init_one : rc=%d\n",rc));
 191 #endif
 192         if (rc)
 193                 return -ENODEV;
 194         //South Bridge exist
 195         if ( ReadLPCReg(0x20) != 0x3C )
 196                 Chipset=0x3096;
 197         else
 198                 Chipset=0x3076;
 199         if (Chipset==0x3076) {
 200 #ifdef  HEADMSG
 201                 DBG(printk(KERN_INFO "via_init_one : 3076 ......\n"));
 202 #endif
 203                 WriteLPCReg(7,0x0c );
 204                 temp=ReadLPCReg(0x30);//check if BIOS Enable Fir
 205                 if((temp&0x01)==1) {   // BIOS close or no FIR
 206                         WriteLPCReg(0x1d, 0x82 );
 207                         WriteLPCReg(0x23,0x18);
 208                         temp=ReadLPCReg(0xF0);
 209                         if((temp&0x01)==0) {
 210                                 temp=(ReadLPCReg(0x74)&0x03);    //DMA
 211                                 FirDRQ0=temp + 4;
 212                                 temp=(ReadLPCReg(0x74)&0x0C) >> 2;
 213                                 FirDRQ1=temp + 4;
 214                         } else {
 215                                 temp=(ReadLPCReg(0x74)&0x0C) >> 2;    //DMA
 216                                 FirDRQ0=temp + 4;
 217                                 FirDRQ1=FirDRQ0;
 218                         }
 219                         FirIRQ=(ReadLPCReg(0x70)&0x0f);         //IRQ
 220                         FirIOBase=ReadLPCReg(0x60 ) << 8;       //IO Space :high byte
 221                         FirIOBase=FirIOBase| ReadLPCReg(0x61) ; //low byte
 222                         FirIOBase=FirIOBase  ;
 223                         info.fir_base=FirIOBase;
 224                         info.irq=FirIRQ;
 225                         info.dma=FirDRQ1;
 226                         info.dma2=FirDRQ0;
 227                         pci_read_config_byte(pcidev,0x40,&bTmp);
 228                         pci_write_config_byte(pcidev,0x40,((bTmp | 0x08) & 0xfe));
 229                         pci_read_config_byte(pcidev,0x42,&bTmp);
 230                         pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
 231                         pci_write_config_byte(pcidev,0x5a,0xc0);
 232                         WriteLPCReg(0x28, 0x70 );
 233                         if (via_ircc_open(0, &info,0x3076) == 0)
 234                                 rc=0;
 235                 } else
 236                         rc = -ENODEV; //IR not turn on
 237         } else { //Not VT1211
 238 #ifdef  HEADMSG
 239                 DBG(printk(KERN_INFO "via_init_one : 3096 ......\n"));
 240 #endif
 241                 pci_read_config_byte(pcidev,0x67,&bTmp);//check if BIOS Enable Fir
 242                 if((bTmp&0x01)==1) {  // BIOS enable FIR
 243                         //Enable Double DMA clock
 244                         pci_read_config_byte(pcidev,0x42,&oldPCI_40);
 245                         pci_write_config_byte(pcidev,0x42,oldPCI_40 | 0x80);
 246                         pci_read_config_byte(pcidev,0x40,&oldPCI_40);
 247                         pci_write_config_byte(pcidev,0x40,oldPCI_40 & 0xf7);
 248                         pci_read_config_byte(pcidev,0x44,&oldPCI_44);
 249                         pci_write_config_byte(pcidev,0x44,0x4e);
 250   //---------- read configuration from Function0 of south bridge
 251                         if((bTmp&0x02)==0) {
 252                                 pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
 253                                 FirDRQ0 = (bTmp1 & 0x30) >> 4;
 254                                 pci_read_config_byte(pcidev,0x44,&bTmp1);
 255                                 FirDRQ1 = (bTmp1 & 0xc0) >> 6;
 256                         } else  {
 257                                 pci_read_config_byte(pcidev,0x44,&bTmp1);    //DMA
 258                                 FirDRQ0 = (bTmp1 & 0x30) >> 4 ;
 259                                 FirDRQ1=0;
 260                         }
 261                         pci_read_config_byte(pcidev,0x47,&bTmp1);  //IRQ
 262                         FirIRQ = bTmp1 & 0x0f;
 263
 264                         pci_read_config_byte(pcidev,0x69,&bTmp);
 265                         FirIOBase = bTmp << 8;//hight byte
 266                         pci_read_config_byte(pcidev,0x68,&bTmp);
 267                         FirIOBase = (FirIOBase | bTmp ) & 0xfff0;
 268   //-------------------------
 269                         info.fir_base=FirIOBase;
 270                         info.irq=FirIRQ;
 271                         info.dma=FirDRQ1;
 272                         info.dma2=FirDRQ0;
 273                         if (via_ircc_open(0, &info,0x3096) == 0)
 274                                 rc=0;
 275                 } else
 276                         rc = -ENODEV; //IR not turn on !!!!!
 277         }//Not VT1211
 278 #ifdef  HEADMSG
 279         DBG(printk(KERN_INFO "via_init_one End : rc=%d\n",rc));
 280 #endif
 281         return rc;
 282 }
 283
 284 /*
 285  * Function via_ircc_clean ()
 286  *
 287  *    Close all configured chips
 288  *
 289  */
 290 static void __exit via_ircc_clean(void)
 291 {
 292         int i;
 293
 294 #ifdef  HEADMSG
 295         DBG(printk(KERN_INFO "via_ircc_clean\n"));
 296 #endif
 297         for (i=0; i < 4; i++) {
 298                 if (dev_self[i])
 299                         via_ircc_close(dev_self[i]);
 300         }
 301 }
 302
 303 static void __exit via_remove_one (struct pci_dev *pdev)
 304 {
 305 #ifdef  HEADMSG
 306         DBG(printk(KERN_INFO "via_remove_one :  ......\n"));
 307 #endif
 308         via_ircc_clean();
 309
 310 }
 311
 312 static void __exit via_ircc_cleanup(void)
 313 {
 314
 315 #ifdef  HEADMSG
 316         DBG(printk(KERN_INFO "via_ircc_cleanup ......\n"));
 317 #endif
 318         via_ircc_clean();
 319         pci_unregister_driver (&via_driver);
 320 }
 321
 322 /*
 323  * Function via_ircc_open (iobase, irq)
 324  *
 325  *    Open driver instance
 326  *
 327  */
 328 static __devinit int via_ircc_open(int i, chipio_t * info, unsigned int id)
 329 {
 330         struct net_device *dev;
 331         struct via_ircc_cb *self;
 332         int err;
 333
 334         if ((via_ircc_setup(info, id)) == -1)
 335                 return -1;
 336
 337         /* Allocate new instance of the driver */
 338         dev = alloc_irdadev(sizeof(struct via_ircc_cb));
 339         if (dev == NULL)
 340                 return -ENOMEM;
 341
 342         self = dev->priv;
 343         self->netdev = dev;
 344         spin_lock_init(&self->lock);
 345
 346         /* Need to store self somewhere */
 347         dev_self[i] = self;
 348         self->index = i;
 349         /* Initialize Resource */
 350         self->io.cfg_base = info->cfg_base;
 351         self->io.fir_base = info->fir_base;
 352         self->io.irq = info->irq;
 353         self->io.fir_ext = CHIP_IO_EXTENT;
 354         self->io.dma = info->dma;
 355         self->io.dma2 = info->dma2;
 356         self->io.fifo_size = 32;
 357         self->chip_id = id;
 358         self->st_fifo.len = 0;
 359         self->RxDataReady = 0;
 360
 361         /* Reserve the ioports that we need */
 362         if (!request_region(self->io.fir_base, self->io.fir_ext, driver_name)) {
 363 //              WARNING("%s(), can't get iobase of 0x%03x\n", __FUNCTION__, self->io.fir_base);
 364                 err = -ENODEV;
 365                 goto err_out1;
 366         }
 367
 368         /* Initialize QoS for this device */
 369         irda_init_max_qos_capabilies(&self->qos);
 370         /* The only value we must override it the baudrate */
 371 //      self->qos.baud_rate.bits = IR_9600;// May use this for testing
 372
 373         self->qos.baud_rate.bits =
 374             IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200 |
 375             IR_576000 | IR_1152000 | (IR_4000000 << 8);
 376
 377         self->qos.min_turn_time.bits = qos_mtt_bits;
 378         irda_qos_bits_to_value(&self->qos);
 379
 380         /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
 381         self->rx_buff.truesize = 14384 + 2048;
 382         self->tx_buff.truesize = 14384 + 2048;
 383
 384         /* Allocate memory if needed */
 385         self->rx_buff.head =
 386             (__u8 *) kmalloc(self->rx_buff.truesize, GFP_KERNEL | GFP_DMA);
 387         if (self->rx_buff.head == NULL) {
 388                 err = -ENOMEM;
 389                 goto err_out2;
 390         }
 391         memset(self->rx_buff.head, 0, self->rx_buff.truesize);
 392
 393         self->tx_buff.head =
 394             (__u8 *) kmalloc(self->tx_buff.truesize, GFP_KERNEL | GFP_DMA);
 395         if (self->tx_buff.head == NULL) {
 396                 err = -ENOMEM;
 397                 goto err_out3;
 398         }
 399         memset(self->tx_buff.head, 0, self->tx_buff.truesize);
 400
 401         self->rx_buff.in_frame = FALSE;
 402         self->rx_buff.state = OUTSIDE_FRAME;
 403         self->tx_buff.data = self->tx_buff.head;
 404         self->rx_buff.data = self->rx_buff.head;
 405
 406         /* Reset Tx queue info */
 407         self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
 408         self->tx_fifo.tail = self->tx_buff.head;
 409
 410         /* Keep track of module usage */
 411         SET_MODULE_OWNER(dev);
 412
 413         /* Override the network functions we need to use */
 414         dev->hard_start_xmit = via_ircc_hard_xmit_sir;
 415         dev->open = via_ircc_net_open;
 416         dev->stop = via_ircc_net_close;
 417         dev->do_ioctl = via_ircc_net_ioctl;
 418         dev->get_stats = via_ircc_net_get_stats;
 419
 420         err = register_netdev(dev);
 421         if (err)
 422                 goto err_out4;
 423
 424         MESSAGE("IrDA: Registered device %s\n", dev->name);
 425
 426         /* Check if user has supplied the dongle id or not */
 427         if (!dongle_id)
 428                 dongle_id = via_ircc_read_dongle_id(self->io.fir_base);
 429         self->io.dongle_id = dongle_id;
 430         via_ircc_change_dongle_speed(self->io.fir_base, 9600,
 431                                      self->io.dongle_id);
 432
 433         return 0;
 434  err_out4:
 435         kfree(self->tx_buff.head);
 436  err_out3:
 437         kfree(self->rx_buff.head);
 438  err_out2:
 439         release_region(self->io.fir_base, self->io.fir_ext);
 440  err_out1:
 441         free_netdev(dev);
 442         dev_self[i] = NULL;
 443         return err;
 444 }
 445
 446 /*
 447  * Function via_ircc_close (self)
 448  *
 449  *    Close driver instance
 450  *
 451  */
 452 static int __exit via_ircc_close(struct via_ircc_cb *self)
 453 {
 454         int iobase;
 455
 456         IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
 457
 458         ASSERT(self != NULL, return -1;);
 459
 460         iobase = self->io.fir_base;
 461
 462         ResetChip(iobase, 5);   //hardware reset.
 463         /* Remove netdevice */
 464         unregister_netdev(self->netdev);
 465
 466         /* Release the PORT that this driver is using */
 467         IRDA_DEBUG(4, "%s(), Releasing Region %03x\n",
 468                    __FUNCTION__, self->io.fir_base);
 469         release_region(self->io.fir_base, self->io.fir_ext);
 470         if (self->tx_buff.head)
 471                 kfree(self->tx_buff.head);
 472         if (self->rx_buff.head)
 473                 kfree(self->rx_buff.head);
 474         dev_self[self->index] = NULL;
 475
 476         free_netdev(self->netdev);
 477
 478         return 0;
 479 }
 480
 481 /*
 482  * Function via_ircc_setup (info)
 483  *
 484  *    Returns non-negative on success.
 485  *
 486  */
 487 static int via_ircc_setup(chipio_t * info, unsigned int chip_id)
 488 {
 489         int iobase = info->fir_base;
 490
 491         SetMaxRxPacketSize(iobase, 0x0fff);     //set to max:4095
 492         // FIFO Init
 493         EnRXFIFOReadyInt(iobase, OFF);
 494         EnRXFIFOHalfLevelInt(iobase, OFF);
 495         EnTXFIFOHalfLevelInt(iobase, OFF);
 496         EnTXFIFOUnderrunEOMInt(iobase, ON);
 497         EnTXFIFOReadyInt(iobase, OFF);
 498         InvertTX(iobase, OFF);
 499         InvertRX(iobase, OFF);
 500         if (ReadLPCReg(0x20) == 0x3c)
 501                 WriteLPCReg(0xF0, 0);   // for VT1211
 502         if (IsSIROn(iobase)) {
 503                 SIRFilter(iobase, ON);
 504                 SIRRecvAny(iobase, ON);
 505         } else {
 506                 SIRFilter(iobase, OFF);
 507                 SIRRecvAny(iobase, OFF);
 508         }
 509         //Int Init
 510         EnRXSpecInt(iobase, ON);
 511         //DMA Init Later....
 512         WriteReg(iobase, I_ST_CT_0, 0x80);
 513         EnableDMA(iobase, ON);
 514
 515         return 0;
 516 }
 517
 518 /*
 519  * Function via_ircc_read_dongle_id (void)
 520  *
 521  */
 522 static int via_ircc_read_dongle_id(int iobase)
 523 {
 524         int dongle_id = 9;
 525
 526         return dongle_id;
 527 }
 528
 529 /*
 530  * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
 531  *    Change speed of the attach dongle
 532  *    only implement two type of dongle currently.
 533  */
 534 static void via_ircc_change_dongle_speed(int iobase, int speed,
 535                                          int dongle_id)
 536 {
 537         u8 mode = 0;
 538
 539         WriteReg(iobase, I_ST_CT_0, 0x0);
 540         switch (dongle_id) {    //HP1100
 541         case 0x00:              /* same as */
 542         case 0x01:              /* Differential serial interface */
 543                 break;
 544         case 0x02:              /* same as */
 545         case 0x03:              /* Reserved */
 546                 break;
 547         case 0x04:              /* Sharp RY5HD01 */
 548                 break;
 549         case 0x05:              /* Reserved, but this is what the Thinkpad reports */
 550                 break;
 551         case 0x06:              /* Single-ended serial interface */
 552                 break;
 553         case 0x07:              /* Consumer-IR only */
 554                 break;
 555
 556         case 0x08:              /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
 557                 UseOneRX(iobase, ON);   // use one RX pin   RX1,RX2
 558                 InvertTX(iobase, OFF);
 559                 InvertRX(iobase, OFF);
 560
 561                 EnRX2(iobase, ON);      //sir to rx2
 562                 EnGPIOtoRX2(iobase, OFF);
 563
 564                 if (IsSIROn(iobase)) {  //sir
 565                         // Mode select Off
 566                         SlowIRRXLowActive(iobase, ON);
 567                         udelay(1000);
 568                         SlowIRRXLowActive(iobase, OFF);
 569                 } else {
 570                         if (IsMIROn(iobase)) {  //mir
 571                                 // Mode select On
 572                                 SlowIRRXLowActive(iobase, OFF);
 573                                 udelay(20);
 574                         } else {        // fir
 575                                 if (IsFIROn(iobase)) {  //fir
 576                                         // Mode select On
 577                                         SlowIRRXLowActive(iobase, OFF);
 578                                         udelay(20);
 579                                 }
 580                         }
 581                 }
 582                 break;
 583         case 0x09:              /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
 584                 UseOneRX(iobase, ON);   //use ONE RX....RX1
 585                 InvertTX(iobase, OFF);
 586                 InvertRX(iobase, OFF);  // invert RX pin
 587                 EnRX2(iobase, ON);
 588                 EnGPIOtoRX2(iobase, OFF);
 589                 if (IsSIROn(iobase)) {  //sir
 590                         // Mode select On
 591                         SlowIRRXLowActive(iobase, ON);
 592                         udelay(20);
 593                         // Mode select Off
 594                         SlowIRRXLowActive(iobase, OFF);
 595                 }
 596                 if (IsMIROn(iobase)) {  //mir
 597                         // Mode select On
 598                         SlowIRRXLowActive(iobase, OFF);
 599                         udelay(20);
 600                         // Mode select Off
 601                         SlowIRRXLowActive(iobase, ON);
 602                 } else {        // fir
 603                         if (IsFIROn(iobase)) {  //fir
 604                                 // Mode select On
 605                                 SlowIRRXLowActive(iobase, OFF);
 606                                 // TX On
 607                                 WriteTX(iobase, ON);
 608                                 udelay(20);
 609                                 // Mode select OFF
 610                                 SlowIRRXLowActive(iobase, ON);
 611                                 udelay(20);
 612                                 // TX Off
 613                                 WriteTX(iobase, OFF);
 614                         }
 615                 }
 616                 break;
 617         case 0x0d:
 618                 UseOneRX(iobase, OFF);  // use two RX pin   RX1,RX2
 619                 InvertTX(iobase, OFF);
 620                 InvertRX(iobase, OFF);
 621                 SlowIRRXLowActive(iobase, OFF);
 622                 if (IsSIROn(iobase)) {  //sir
 623                         EnGPIOtoRX2(iobase, OFF);
 624                         WriteGIO(iobase, OFF);
 625                         EnRX2(iobase, OFF);     //sir to rx2
 626                 } else {        // fir mir
 627                         EnGPIOtoRX2(iobase, OFF);
 628                         WriteGIO(iobase, OFF);
 629                         EnRX2(iobase, OFF);     //fir to rx
 630                 }
 631                 break;
 632         case 0x0ff:             /* Vishay */
 633                 if (IsSIROn(iobase))
 634                         mode = 0;
 635                 else if (IsMIROn(iobase))
 636                         mode = 1;
 637                 else if (IsFIROn(iobase))
 638                         mode = 2;
 639                 else if (IsVFIROn(iobase))
 640                         mode = 5;       //VFIR-16
 641                 SI_SetMode(iobase, mode);
 642         }
 643         WriteReg(iobase, I_ST_CT_0, 0x80);
 644
 645 }
 646
 647 /*
 648  * Function via_ircc_change_speed (self, baud)
 649  *
 650  *    Change the speed of the device
 651  *
 652  */
 653 static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 speed)
 654 {
 655         struct net_device *dev = self->netdev;
 656         u16 iobase;
 657         u8 value = 0, bTmp;
 658
 659         iobase = self->io.fir_base;
 660         /* Update accounting for new speed */
 661         self->io.speed = speed;
 662 #ifdef  DBGMSG
 663         DBG(printk(KERN_INFO "change_speed =%x......\n", speed));
 664 #endif
 665
 666 #ifdef  DBG_IO
 667         if (self->io.speed > 0x2580)
 668                 outb(0xaa, 0x90);
 669         else
 670                 outb(0xbb, 0x90);
 671 #endif
 672
 673
 674         /* Controller mode sellection */
 675         switch (speed) {
 676         case 9600:
 677                 value = 11;
 678                 SetSIR(iobase, ON);
 679                 CRC16(iobase, ON);
 680                 break;
 681         case 19200:
 682                 value = 5;
 683                 SetSIR(iobase, ON);
 684                 CRC16(iobase, ON);
 685                 break;
 686         case 38400:
 687                 value = 2;
 688                 SetSIR(iobase, ON);
 689                 CRC16(iobase, ON);
 690                 break;
 691         case 57600:
 692                 value = 1;
 693                 SetSIR(iobase, ON);
 694                 CRC16(iobase, ON);
 695                 break;
 696         case 115200:
 697                 value = 0;
 698                 SetSIR(iobase, ON);
 699                 CRC16(iobase, ON);
 700                 break;
 701         case 576000:
 702                 value = 0;
 703                 SetSIR(iobase, ON);
 704                 CRC16(iobase, ON);
 705                 break;
 706         case 1152000:
 707                 value = 0;
 708                 SetMIR(iobase, ON);
 709                 break;
 710         case 4000000:
 711                 value = 0;
 712                 SetFIR(iobase, ON);
 713                 SetPulseWidth(iobase, 0);
 714                 SetSendPreambleCount(iobase, 14);
 715                 CRC16(iobase, OFF);
 716                 EnTXCRC(iobase, ON);
 717                 break;
 718         case 16000000:
 719                 value = 0;
 720                 SetVFIR(iobase, ON);
 721                 break;
 722         default:
 723                 value = 0;
 724                 break;
 725         }
 726         /* Set baudrate to 0x19[2..7] */
 727         bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
 728         bTmp = bTmp | (value << 2);
 729         WriteReg(iobase, I_CF_H_1, bTmp);
 730         via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
 731 // EnTXFIFOHalfLevelInt(iobase,ON);
 732         /* Set FIFO size to 64 */
 733         SetFIFO(iobase, 64);
 734         /* Enable some interrupts so we can receive frames */
 735         //EnAllInt(iobase,ON);
 736
 737         if (IsSIROn(iobase)) {
 738                 SIRFilter(iobase, ON);
 739                 SIRRecvAny(iobase, ON);
 740         } else {
 741                 SIRFilter(iobase, OFF);
 742                 SIRRecvAny(iobase, OFF);
 743         }
 744         if (speed > 115200) {
 745                 /* Install FIR xmit handler */
 746                 dev->hard_start_xmit = via_ircc_hard_xmit_fir;
 747                 via_ircc_dma_receive(self);
 748         } else {
 749                 /* Install SIR xmit handler */
 750                 dev->hard_start_xmit = via_ircc_hard_xmit_sir;
 751         }
 752         netif_wake_queue(dev);
 753 }
 754
 755 /*
 756  * Function via_ircc_hard_xmit (skb, dev)
 757  *
 758  *    Transmit the frame!
 759  *
 760  */
 761 static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
 762                                   struct net_device *dev)
 763 {
 764         struct via_ircc_cb *self;
 765         unsigned long flags;
 766         u16 iobase;
 767         __u32 speed;
 768
 769         self = (struct via_ircc_cb *) dev->priv;
 770         ASSERT(self != NULL, return 0;);
 771         iobase = self->io.fir_base;
 772
 773         netif_stop_queue(dev);
 774         /* Check if we need to change the speed */
 775         speed = irda_get_next_speed(skb);
 776         if ((speed != self->io.speed) && (speed != -1)) {
 777                 /* Check for empty frame */
 778                 if (!skb->len) {
 779                         via_ircc_change_speed(self, speed);
 780                         dev->trans_start = jiffies;
 781                         dev_kfree_skb(skb);
 782                         return 0;
 783                 } else
 784                         self->new_speed = speed;
 785         }
 786         InitCard(iobase);
 787         CommonInit(iobase);
 788         SIRFilter(iobase, ON);
 789         SetSIR(iobase, ON);
 790         CRC16(iobase, ON);
 791         EnTXCRC(iobase, 0);
 792         WriteReg(iobase, I_ST_CT_0, 0x00);
 793
 794         spin_lock_irqsave(&self->lock, flags);
 795         self->tx_buff.data = self->tx_buff.head;
 796         self->tx_buff.len =
 797             async_wrap_skb(skb, self->tx_buff.data,
 798                            self->tx_buff.truesize);
 799
 800         self->stats.tx_bytes += self->tx_buff.len;
 801         SetBaudRate(iobase, speed);
 802         SetPulseWidth(iobase, 12);
 803         SetSendPreambleCount(iobase, 0);
 804         WriteReg(iobase, I_ST_CT_0, 0x80);
 805
 806         EnableTX(iobase, ON);
 807         EnableRX(iobase, OFF);
 808
 809         ResetChip(iobase, 0);
 810         ResetChip(iobase, 1);
 811         ResetChip(iobase, 2);
 812         ResetChip(iobase, 3);
 813         ResetChip(iobase, 4);
 814
 815         EnAllInt(iobase, ON);
 816         EnTXDMA(iobase, ON);
 817         EnRXDMA(iobase, OFF);
 818
 819         irda_setup_dma(self->io.dma, self->tx_buff.data, self->tx_buff.len,
 820                        DMA_TX_MODE);
 821
 822         SetSendByte(iobase, self->tx_buff.len);
 823         RXStart(iobase, OFF);
 824         TXStart(iobase, ON);
 825
 826         dev->trans_start = jiffies;
 827         spin_unlock_irqrestore(&self->lock, flags);
 828         dev_kfree_skb(skb);
 829         return 0;
 830 }
 831
 832 static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
 833                                   struct net_device *dev)
 834 {
 835         struct via_ircc_cb *self;
 836         u16 iobase;
 837         __u32 speed;
 838         unsigned long flags;
 839
 840         self = (struct via_ircc_cb *) dev->priv;
 841         iobase = self->io.fir_base;
 842
 843         if (self->st_fifo.len)
 844                 return 0;
 845         if (self->chip_id == 0x3076)
 846                 iodelay(1500);
 847         else
 848                 udelay(1500);
 849         netif_stop_queue(dev);
 850         speed = irda_get_next_speed(skb);
 851         if ((speed != self->io.speed) && (speed != -1)) {
 852                 if (!skb->len) {
 853                         via_ircc_change_speed(self, speed);
 854                         dev->trans_start = jiffies;
 855                         dev_kfree_skb(skb);
 856                         return 0;
 857                 } else
 858                         self->new_speed = speed;
 859         }
 860         spin_lock_irqsave(&self->lock, flags);
 861         self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
 862         self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
 863
 864         self->tx_fifo.tail += skb->len;
 865         self->stats.tx_bytes += skb->len;
 866         memcpy(self->tx_fifo.queue[self->tx_fifo.free].start, skb->data,
 867                skb->len);
 868         self->tx_fifo.len++;
 869         self->tx_fifo.free++;
 870 //F01   if (self->tx_fifo.len == 1) {
 871         via_ircc_dma_xmit(self, iobase);
 872 //F01   }
 873 //F01   if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) netif_wake_queue(self->netdev);
 874         dev->trans_start = jiffies;
 875         dev_kfree_skb(skb);
 876         spin_unlock_irqrestore(&self->lock, flags);
 877         return 0;
 878
 879 }
 880
 881 static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
 882 {
 883 //      int i;
 884 //      u8 *ch;
 885
 886         EnTXDMA(iobase, OFF);
 887         self->io.direction = IO_XMIT;
 888         EnPhys(iobase, ON);
 889         EnableTX(iobase, ON);
 890         EnableRX(iobase, OFF);
 891         ResetChip(iobase, 0);
 892         ResetChip(iobase, 1);
 893         ResetChip(iobase, 2);
 894         ResetChip(iobase, 3);
 895         ResetChip(iobase, 4);
 896         EnAllInt(iobase, ON);
 897         EnTXDMA(iobase, ON);
 898         EnRXDMA(iobase, OFF);
 899         irda_setup_dma(self->io.dma,
 900                        self->tx_fifo.queue[self->tx_fifo.ptr].start,
 901                        self->tx_fifo.queue[self->tx_fifo.ptr].len, DMA_TX_MODE);
 902 #ifdef  DBGMSG
 903         DBG(printk
 904             (KERN_INFO "dma_xmit:tx_fifo.ptr=%x,len=%x,tx_fifo.len=%x..\n",
 905              self->tx_fifo.ptr, self->tx_fifo.queue[self->tx_fifo.ptr].len,
 906              self->tx_fifo.len));
 907 /*
 908         ch = self->tx_fifo.queue[self->tx_fifo.ptr].start;
 909         for(i=0 ; i < self->tx_fifo.queue[self->tx_fifo.ptr].len ; i++) {
 910             DBG(printk(KERN_INFO "%x..\n",ch[i]));
 911         }
 912 */
 913 #endif
 914
 915         SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
 916         RXStart(iobase, OFF);
 917         TXStart(iobase, ON);
 918         return 0;
 919
 920 }
 921
 922 /*
 923  * Function via_ircc_dma_xmit_complete (self)
 924  *
 925  *    The transfer of a frame in finished. This function will only be called
 926  *    by the interrupt handler
 927  *
 928  */
 929 static int via_ircc_dma_xmit_complete(struct via_ircc_cb *self)
 930 {
 931         int iobase;
 932         int ret = TRUE;
 933         u8 Tx_status;
 934
 935         IRDA_DEBUG(2, "%s()\n", __FUNCTION__);
 936         iobase = self->io.fir_base;
 937         /* Disable DMA */
 938 //      DisableDmaChannel(self->io.dma);
 939         /* Check for underrrun! */
 940         /* Clear bit, by writing 1 into it */
 941         Tx_status = GetTXStatus(iobase);
 942         if (Tx_status & 0x08) {
 943                 self->stats.tx_errors++;
 944                 self->stats.tx_fifo_errors++;
 945                 hwreset(self);
 946 // how to clear underrrun ?
 947         } else {
 948                 self->stats.tx_packets++;
 949                 ResetChip(iobase, 3);
 950                 ResetChip(iobase, 4);
 951         }
 952         /* Check if we need to change the speed */
 953         if (self->new_speed) {
 954                 via_ircc_change_speed(self, self->new_speed);
 955                 self->new_speed = 0;
 956         }
 957
 958         /* Finished with this frame, so prepare for next */
 959         if (IsFIROn(iobase)) {
 960                 if (self->tx_fifo.len) {
 961                         self->tx_fifo.len--;
 962                         self->tx_fifo.ptr++;
 963                 }
 964         }
 965 #ifdef  DBGMSG
 966         DBG(printk
 967             (KERN_INFO
 968              "via_ircc_dma_xmit_complete:tx_fifo.len=%x ,tx_fifo.ptr=%x,tx_fifo.free=%x...\n",
 969              self->tx_fifo.len, self->tx_fifo.ptr, self->tx_fifo.free));
 970 #endif
 971 /* F01_S
 972         // Any frames to be sent back-to-back?
 973         if (self->tx_fifo.len) {
 974                 // Not finished yet!
 975                 via_ircc_dma_xmit(self, iobase);
 976                 ret = FALSE;
 977         } else {
 978 F01_E*/
 979         // Reset Tx FIFO info
 980         self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
 981         self->tx_fifo.tail = self->tx_buff.head;
 982 //F01   }
 983
 984         // Make sure we have room for more frames
 985 //F01   if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) {
 986         // Not busy transmitting anymore
 987         // Tell the network layer, that we can accept more frames
 988         netif_wake_queue(self->netdev);
 989 //F01   }
 990         return ret;
 991 }
 992
 993 /*
 994  * Function via_ircc_dma_receive (self)
 995  *
 996  *    Set configuration for receive a frame.
 997  *
 998  */
 999 static int via_ircc_dma_receive(struct via_ircc_cb *self)
1000 {
1001         int iobase;
1002
1003         iobase = self->io.fir_base;
1004
1005         self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
1006         self->tx_fifo.tail = self->tx_buff.head;
1007         self->RxDataReady = 0;
1008         self->io.direction = IO_RECV;
1009         self->rx_buff.data = self->rx_buff.head;
1010         self->st_fifo.len = self->st_fifo.pending_bytes = 0;
1011         self->st_fifo.tail = self->st_fifo.head = 0;
1012         EnPhys(iobase, ON);
1013         EnableTX(iobase, OFF);
1014         EnableRX(iobase, ON);
1015
1016         ResetChip(iobase, 0);
1017         ResetChip(iobase, 1);
1018         ResetChip(iobase, 2);
1019         ResetChip(iobase, 3);
1020         ResetChip(iobase, 4);
1021
1022         EnAllInt(iobase, ON);
1023         EnTXDMA(iobase, OFF);
1024         EnRXDMA(iobase, ON);
1025         irda_setup_dma(self->io.dma2, self->rx_buff.data,
1026                        self->rx_buff.truesize, DMA_RX_MODE);
1027         TXStart(iobase, OFF);
1028         RXStart(iobase, ON);
1029
1030         return 0;
1031 }
1032
1033 /*
1034  * Function via_ircc_dma_receive_complete (self)
1035  *
1036  *    Controller Finished with receiving frames,
1037  *    and this routine is call by ISR
1038  *
1039  */
1040 static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
1041                                          int iobase)
1042 {
1043         struct st_fifo *st_fifo;
1044         struct sk_buff *skb;
1045         int len, i;
1046         u8 status = 0;
1047
1048         iobase = self->io.fir_base;
1049         st_fifo = &self->st_fifo;
1050
1051         if (self->io.speed < 4000000) { //Speed below FIR
1052                 len = GetRecvByte(iobase, self);
1053                 skb = dev_alloc_skb(len + 1);
1054                 if (skb == NULL)
1055                         return FALSE;
1056                 // Make sure IP header gets aligned
1057                 skb_reserve(skb, 1);
1058                 skb_put(skb, len - 2);
1059                 if (self->chip_id == 0x3076) {
1060                         for (i = 0; i < len - 2; i++)
1061                                 skb->data[i] = self->rx_buff.data[i * 2];
1062                 } else {
1063                         if (self->chip_id == 0x3096) {
1064                                 for (i = 0; i < len - 2; i++)
1065                                         skb->data[i] =
1066                                             self->rx_buff.data[i];
1067                         }
1068                 }
1069                 // Move to next frame
1070                 self->rx_buff.data += len;
1071                 self->stats.rx_bytes += len;
1072                 self->stats.rx_packets++;
1073                 skb->dev = self->netdev;
1074                 skb->mac.raw = skb->data;
1075                 skb->protocol = htons(ETH_P_IRDA);
1076                 netif_rx(skb);
1077                 return TRUE;
1078         }
1079
1080         else {                  //FIR mode
1081                 len = GetRecvByte(iobase, self);
1082                 if (len == 0)
1083                         return TRUE;    //interrupt only, data maybe move by RxT
1084                 if (((len - 4) < 2) || ((len - 4) > 2048)) {
1085 #ifdef  DBGMSG
1086                         DBG(printk
1087                             (KERN_INFO
1088                              "receive_comple:Trouble:len=%x,CurCount=%x,LastCount=%x..\n",
1089                              len, RxCurCount(iobase, self),
1090                              self->RxLastCount));
1091 #endif
1092                         hwreset(self);
1093                         return FALSE;
1094                 }
1095 #ifdef  DBGMSG
1096                 DBG(printk
1097                     (KERN_INFO
1098                      "recv_comple:fifo.len=%x,len=%x,CurCount=%x..\n",
1099                      st_fifo->len, len - 4, RxCurCount(iobase, self)));
1100 #endif
1101                 st_fifo->entries[st_fifo->tail].status = status;
1102                 st_fifo->entries[st_fifo->tail].len = len;
1103                 st_fifo->pending_bytes += len;
1104                 st_fifo->tail++;
1105                 st_fifo->len++;
1106                 if (st_fifo->tail > MAX_RX_WINDOW)
1107                         st_fifo->tail = 0;
1108                 self->RxDataReady = 0;
1109
1110                 // It maybe have MAX_RX_WINDOW package receive by
1111                 // receive_complete before Timer IRQ
1112 /* F01_S
1113           if (st_fifo->len < (MAX_RX_WINDOW+2 )) {
1114                   RXStart(iobase,ON);
1115                   SetTimer(iobase,4);
1116           }
1117           else    {
1118 F01_E */
1119                 EnableRX(iobase, OFF);
1120                 EnRXDMA(iobase, OFF);
1121                 RXStart(iobase, OFF);
1122 //F01_S
1123                 // Put this entry back in fifo
1124                 if (st_fifo->head > MAX_RX_WINDOW)
1125                         st_fifo->head = 0;
1126                 status = st_fifo->entries[st_fifo->head].status;
1127                 len = st_fifo->entries[st_fifo->head].len;
1128                 st_fifo->head++;
1129                 st_fifo->len--;
1130
1131                 skb = dev_alloc_skb(len + 1 - 4);
1132                 /*
1133                  * if frame size,data ptr,or skb ptr are wrong ,the get next
1134                  * entry.
1135                  */
1136                 if ((skb == NULL) || (skb->data == NULL)
1137                     || (self->rx_buff.data == NULL) || (len < 6)) {
1138                         self->stats.rx_dropped++;
1139                         return TRUE;
1140                 }
1141                 skb_reserve(skb, 1);
1142                 skb_put(skb, len - 4);
1143                 memcpy(skb->data, self->rx_buff.data, len - 4);
1144 #ifdef  DBGMSG
1145                 DBG(printk
1146                     (KERN_INFO "RxT:len=%x.rx_buff=%x\n", len - 4,
1147                      self->rx_buff.data));
1148 /*              for(i=0 ; i < (len-4) ; i++) {
1149                     DBG(printk(KERN_INFO "%x..\n",self->rx_buff.data[i]));
1150                 }
1151 */
1152 #endif
1153                 // Move to next frame
1154                 self->rx_buff.data += len;
1155                 self->stats.rx_bytes += len;
1156                 self->stats.rx_packets++;
1157                 skb->dev = self->netdev;
1158                 skb->mac.raw = skb->data;
1159                 skb->protocol = htons(ETH_P_IRDA);
1160                 netif_rx(skb);
1161
1162 //F01_E
1163         }                       //FIR
1164         return TRUE;
1165
1166 }
1167
1168 /*
1169  * if frame is received , but no INT ,then use this routine to upload frame.
1170  */
1171 static int upload_rxdata(struct via_ircc_cb *self, int iobase)
1172 {
1173         struct sk_buff *skb;
1174         int len;
1175         struct st_fifo *st_fifo;
1176         st_fifo = &self->st_fifo;
1177
1178         len = GetRecvByte(iobase, self);
1179
1180 #ifdef  DBGMSG
1181         DBG(printk(KERN_INFO "upload_rxdata: len=%x\n", len));
1182 #endif
1183         skb = dev_alloc_skb(len + 1);
1184         if ((skb == NULL) || ((len - 4) < 2)) {
1185                 self->stats.rx_dropped++;
1186                 return FALSE;
1187         }
1188         skb_reserve(skb, 1);
1189         skb_put(skb, len - 4 + 1);
1190         memcpy(skb->data, self->rx_buff.data, len - 4 + 1);
1191         st_fifo->tail++;
1192         st_fifo->len++;
1193         if (st_fifo->tail > MAX_RX_WINDOW)
1194                 st_fifo->tail = 0;
1195         // Move to next frame
1196         self->rx_buff.data += len;
1197         self->stats.rx_bytes += len;
1198         self->stats.rx_packets++;
1199         skb->dev = self->netdev;
1200         skb->mac.raw = skb->data;
1201         skb->protocol = htons(ETH_P_IRDA);
1202         netif_rx(skb);
1203         if (st_fifo->len < (MAX_RX_WINDOW + 2)) {
1204                 RXStart(iobase, ON);
1205         } else {
1206                 EnableRX(iobase, OFF);
1207                 EnRXDMA(iobase, OFF);
1208                 RXStart(iobase, OFF);
1209         }
1210         return TRUE;
1211 }
1212
1213 /*
1214  * Implement back to back receive , use this routine to upload data.
1215  */
1216
1217 static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
1218 {
1219         struct st_fifo *st_fifo;
1220         struct sk_buff *skb;
1221         int len;
1222         u8 status;
1223
1224         st_fifo = &self->st_fifo;
1225
1226         if (CkRxRecv(iobase, self)) {
1227                 // if still receiving ,then return ,don't upload frame
1228                 self->RetryCount = 0;
1229                 SetTimer(iobase, 20);
1230                 self->RxDataReady++;
1231                 return FALSE;
1232         } else
1233                 self->RetryCount++;
1234
1235         if ((self->RetryCount >= 1) ||
1236             ((st_fifo->pending_bytes + 2048) > self->rx_buff.truesize)
1237             || (st_fifo->len >= (MAX_RX_WINDOW))) {
1238                 while (st_fifo->len > 0) {      //upload frame
1239                         // Put this entry back in fifo
1240                         if (st_fifo->head > MAX_RX_WINDOW)
1241                                 st_fifo->head = 0;
1242                         status = st_fifo->entries[st_fifo->head].status;
1243                         len = st_fifo->entries[st_fifo->head].len;
1244                         st_fifo->head++;
1245                         st_fifo->len--;
1246
1247                         skb = dev_alloc_skb(len + 1 - 4);
1248                         /*
1249                          * if frame size, data ptr, or skb ptr are wrong,
1250                          * then get next entry.
1251                          */
1252                         if ((skb == NULL) || (skb->data == NULL)
1253                             || (self->rx_buff.data == NULL) || (len < 6)) {
1254                                 self->stats.rx_dropped++;
1255                                 continue;
1256                         }
1257                         skb_reserve(skb, 1);
1258                         skb_put(skb, len - 4);
1259                         memcpy(skb->data, self->rx_buff.data, len - 4);
1260 #ifdef  DBGMSG
1261                         DBG(printk
1262                             (KERN_INFO "RxT:len=%x.head=%x\n", len - 4,
1263                              st_fifo->head));
1264 #endif
1265                         // Move to next frame
1266                         self->rx_buff.data += len;
1267                         self->stats.rx_bytes += len;
1268                         self->stats.rx_packets++;
1269                         skb->dev = self->netdev;
1270                         skb->mac.raw = skb->data;
1271                         skb->protocol = htons(ETH_P_IRDA);
1272                         netif_rx(skb);
1273                 }               //while
1274                 self->RetryCount = 0;
1275 #ifdef  DBGMSG
1276                 DBG(printk
1277                     (KERN_INFO
1278                      "RxT:End of upload HostStatus=%x,RxStatus=%x\n",
1279                      GetHostStatus(iobase), GetRXStatus(iobase)));
1280 #endif
1281                 /*
1282                  * if frame is receive complete at this routine ,then upload
1283                  * frame.
1284                  */
1285                 if ((GetRXStatus(iobase) & 0x10)
1286                     && (RxCurCount(iobase, self) != self->RxLastCount)) {
1287                         upload_rxdata(self, iobase);
1288                         if (irda_device_txqueue_empty(self->netdev))
1289                                 via_ircc_dma_receive(self);
1290                 }
1291         }                       // timer detect complete
1292         else
1293                 SetTimer(iobase, 4);
1294         return TRUE;
1295
1296 }
1297
1298
1299
1300 /*
1301  * Function via_ircc_interrupt (irq, dev_id, regs)
1302  *
1303  *    An interrupt from the chip has arrived. Time to do some work
1304  *
1305  */
1306 static irqreturn_t via_ircc_interrupt(int irq, void *dev_id,
1307                                       struct pt_regs *regs)
1308 {
1309         struct net_device *dev = (struct net_device *) dev_id;
1310         struct via_ircc_cb *self;
1311         int iobase;
1312         u8 iHostIntType, iRxIntType, iTxIntType;
1313
1314         if (!dev) {
1315                 WARNING("%s: irq %d for unknown device.\n", driver_name,
1316                         irq);
1317                 return IRQ_NONE;
1318         }
1319         self = (struct via_ircc_cb *) dev->priv;
1320         iobase = self->io.fir_base;
1321         spin_lock(&self->lock);
1322         iHostIntType = GetHostStatus(iobase);
1323         if ((iHostIntType & 0x40) != 0) {       //Timer Event
1324                 self->EventFlag.TimeOut++;
1325                 ClearTimerInt(iobase, 1);
1326                 if (self->io.direction == IO_XMIT) {
1327                         via_ircc_dma_xmit(self, iobase);
1328                 }
1329                 if (self->io.direction == IO_RECV) {
1330                         /*
1331                          * frame ready hold too long, must reset.
1332                          */
1333                         if (self->RxDataReady > 30) {
1334                                 hwreset(self);
1335                                 if (irda_device_txqueue_empty
1336                                     (self->netdev)) {
1337                                         via_ircc_dma_receive(self);
1338                                 }
1339                         } else {        // call this to upload frame.
1340                                 RxTimerHandler(self, iobase);
1341                         }
1342                 }               //RECV
1343         }                       //Timer Event
1344         if ((iHostIntType & 0x20) != 0) {       //Tx Event
1345                 iTxIntType = GetTXStatus(iobase);
1346                 if (iTxIntType & 0x4) {
1347                         self->EventFlag.EOMessage++;    // read and will auto clean
1348                         if (via_ircc_dma_xmit_complete(self)) {
1349                                 if (irda_device_txqueue_empty
1350                                     (self->netdev)) {
1351                                         via_ircc_dma_receive(self);
1352                                 }
1353                         } else {
1354                                 self->EventFlag.Unknown++;
1355                         }
1356                 }               //EOP
1357         }                       //Tx Event
1358         //----------------------------------------
1359         if ((iHostIntType & 0x10) != 0) {       //Rx Event
1360                 /* Check if DMA has finished */
1361                 iRxIntType = GetRXStatus(iobase);
1362 #ifdef  DBGMSG
1363                 if (!iRxIntType)
1364                         DBG(printk(KERN_INFO " RxIRQ =0\n"));
1365 #endif
1366                 if (iRxIntType & 0x10) {
1367                         if (via_ircc_dma_receive_complete(self, iobase)) {
1368 //F01       if(!(IsFIROn(iobase)))  via_ircc_dma_receive(self);
1369                                 via_ircc_dma_receive(self);
1370                         }
1371                 }               // No ERR
1372                 else {          //ERR
1373 #ifdef  DBGMSG
1374                         DBG(printk
1375                             (KERN_INFO
1376                              " RxIRQ ERR:iRxIntType=%x,HostIntType=%x,CurCount=%x,RxLastCount=%x_____\n",
1377                              iRxIntType, iHostIntType, RxCurCount(iobase,
1378                                                                   self),
1379                              self->RxLastCount));
1380 #endif
1381                         if (iRxIntType & 0x20) {        //FIFO OverRun ERR
1382                                 ResetChip(iobase, 0);
1383                                 ResetChip(iobase, 1);
1384                         } else {        //PHY,CRC ERR
1385
1386                                 if (iRxIntType != 0x08)
1387                                         hwreset(self);  //F01
1388                         }
1389                         via_ircc_dma_receive(self);
1390                 }               //ERR
1391
1392         }                       //Rx Event
1393         spin_unlock(&self->lock);
1394         return IRQ_RETVAL(iHostIntType);
1395 }
1396
1397 static void hwreset(struct via_ircc_cb *self)
1398 {
1399         int iobase;
1400         iobase = self->io.fir_base;
1401 #ifdef  DBGMSG
1402         DBG(printk(KERN_INFO "hwreset  ....\n"));
1403 #endif
1404         ResetChip(iobase, 5);
1405         EnableDMA(iobase, OFF);
1406         EnableTX(iobase, OFF);
1407         EnableRX(iobase, OFF);
1408         EnRXDMA(iobase, OFF);
1409         EnTXDMA(iobase, OFF);
1410         RXStart(iobase, OFF);
1411         TXStart(iobase, OFF);
1412         InitCard(iobase);
1413         CommonInit(iobase);
1414         SIRFilter(iobase, ON);
1415         SetSIR(iobase, ON);
1416         CRC16(iobase, ON);
1417         EnTXCRC(iobase, 0);
1418         WriteReg(iobase, I_ST_CT_0, 0x00);
1419         SetBaudRate(iobase, 9600);
1420         SetPulseWidth(iobase, 12);
1421         SetSendPreambleCount(iobase, 0);
1422         WriteReg(iobase, I_ST_CT_0, 0x80);
1423         via_ircc_change_speed(self, self->io.speed);
1424         self->st_fifo.len = 0;
1425 }
1426
1427 /*
1428  * Function via_ircc_is_receiving (self)
1429  *
1430  *    Return TRUE is we are currently receiving a frame
1431  *
1432  */
1433 static int via_ircc_is_receiving(struct via_ircc_cb *self)
1434 {
1435         int status = FALSE;
1436         int iobase;
1437
1438         ASSERT(self != NULL, return FALSE;);
1439
1440         iobase = self->io.fir_base;
1441         if (CkRxRecv(iobase, self))
1442                 status = TRUE;
1443 #ifdef  DBGMSG
1444         DBG(printk(KERN_INFO "is_receiving  status=%x....\n", status));
1445 #endif
1446         return status;
1447 }
1448
1449
1450 /*
1451  * Function via_ircc_net_open (dev)
1452  *
1453  *    Start the device
1454  *
1455  */
1456 static int via_ircc_net_open(struct net_device *dev)
1457 {
1458         struct via_ircc_cb *self;
1459         int iobase;
1460         char hwname[32];
1461
1462         IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
1463
1464         ASSERT(dev != NULL, return -1;);
1465         self = (struct via_ircc_cb *) dev->priv;
1466         self->stats.rx_packets = 0;
1467         ASSERT(self != NULL, return 0;);
1468         iobase = self->io.fir_base;
1469         if (request_irq
1470             (self->io.irq, via_ircc_interrupt, 0, dev->name, dev)) {
1471                 WARNING("%s, unable to allocate irq=%d\n", driver_name,
1472                         self->io.irq);
1473                 return -EAGAIN;
1474         }
1475         /*
1476          * Always allocate the DMA channel after the IRQ, and clean up on
1477          * failure.
1478          */
1479         if (request_dma(self->io.dma, dev->name)) {
1480                 WARNING("%s, unable to allocate dma=%d\n", driver_name,
1481                         self->io.dma);
1482                 free_irq(self->io.irq, self);
1483                 return -EAGAIN;
1484         }
1485         if (self->io.dma2 != self->io.dma) {
1486                 if (request_dma(self->io.dma2, dev->name)) {
1487                         WARNING("%s, unable to allocate dma2=%d\n",
1488                                 driver_name, self->io.dma2);
1489                         free_irq(self->io.irq, self);
1490                         return -EAGAIN;
1491                 }
1492         }
1493
1494
1495         /* turn on interrupts */
1496         EnAllInt(iobase, ON);
1497         EnInternalLoop(iobase, OFF);
1498         EnExternalLoop(iobase, OFF);
1499         /* Ready to play! */
1500         netif_start_queue(dev);
1501
1502         /*
1503          * Open new IrLAP layer instance, now that everything should be
1504          * initialized properly
1505          */
1506         sprintf(hwname, "VIA");
1507         /*
1508          * for different kernel ,irlap_open have different parameter.
1509          */
1510         self->irlap = irlap_open(dev, &self->qos, hwname);
1511 //      self->irlap = irlap_open(dev, &self->qos);
1512
1513         self->RxLastCount = 0;
1514
1515         return 0;
1516 }
1517
1518 /*
1519  * Function via_ircc_net_close (dev)
1520  *
1521  *    Stop the device
1522  *
1523  */
1524 static int via_ircc_net_close(struct net_device *dev)
1525 {
1526         struct via_ircc_cb *self;
1527         int iobase;
1528
1529         IRDA_DEBUG(4, "%s()\n", __FUNCTION__);
1530
1531         ASSERT(dev != NULL, return -1;);
1532         self = (struct via_ircc_cb *) dev->priv;
1533         ASSERT(self != NULL, return 0;);
1534
1535 #ifdef  DBG_IO
1536         outb(0xff, 0x90);
1537         outb(0xff, 0x94);
1538 #endif
1539         /* Stop device */
1540         netif_stop_queue(dev);
1541         /* Stop and remove instance of IrLAP */
1542         if (self->irlap)
1543                 irlap_close(self->irlap);
1544         self->irlap = NULL;
1545         iobase = self->io.fir_base;
1546         EnTXDMA(iobase, OFF);
1547         EnRXDMA(iobase, OFF);
1548         DisableDmaChannel(self->io.dma);
1549
1550         /* Disable interrupts */
1551         EnAllInt(iobase, OFF);
1552         free_irq(self->io.irq, dev);
1553         free_dma(self->io.dma);
1554
1555         return 0;
1556 }
1557
1558 /*
1559  * Function via_ircc_net_ioctl (dev, rq, cmd)
1560  *
1561  *    Process IOCTL commands for this device
1562  *
1563  */
1564 static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
1565                               int cmd)
1566 {
1567         struct if_irda_req *irq = (struct if_irda_req *) rq;
1568         struct via_ircc_cb *self;
1569         unsigned long flags;
1570         int ret = 0;
1571
1572         ASSERT(dev != NULL, return -1;);
1573         self = dev->priv;
1574         ASSERT(self != NULL, return -1;);
1575         IRDA_DEBUG(2, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name,
1576                    cmd);
1577         /* Disable interrupts & save flags */
1578         spin_lock_irqsave(&self->lock, flags);
1579         switch (cmd) {
1580         case SIOCSBANDWIDTH:    /* Set bandwidth */
1581                 if (!capable(CAP_NET_ADMIN)) {
1582                         ret = -EPERM;
1583                         goto out;
1584                 }
1585                 via_ircc_change_speed(self, irq->ifr_baudrate);
1586                 break;
1587         case SIOCSMEDIABUSY:    /* Set media busy */
1588                 if (!capable(CAP_NET_ADMIN)) {
1589                         ret = -EPERM;
1590                         goto out;
1591                 }
1592                 irda_device_set_media_busy(self->netdev, TRUE);
1593                 break;
1594         case SIOCGRECEIVING:    /* Check if we are receiving right now */
1595                 irq->ifr_receiving = via_ircc_is_receiving(self);
1596                 break;
1597         default:
1598                 ret = -EOPNOTSUPP;
1599         }
1600       out:
1601         spin_unlock_irqrestore(&self->lock, flags);
1602         return ret;
1603 }
1604
1605 static struct net_device_stats *via_ircc_net_get_stats(struct net_device
1606                                                        *dev)
1607 {
1608         struct via_ircc_cb *self = (struct via_ircc_cb *) dev->priv;
1609
1610         return &self->stats;
1611 }
1612
1613 MODULE_AUTHOR("VIA Technologies,inc");
1614 MODULE_DESCRIPTION("VIA IrDA Device Driver");
1615 MODULE_LICENSE("GPL");
1616
1617 module_init(via_ircc_init);
1618 module_exit(via_ircc_cleanup);