1 /*******************************************************************************
4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *******************************************************************************/
28 /* glue for the OS independant part of ixgb
29 * includes register access macros
35 #include <linux/types.h>
36 #include <linux/pci.h>
37 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
42 /* FIXME: eliminate me */
43 #define msec_delay(x) do { if(in_interrupt()) { \
46 set_current_state(TASK_UNINTERRUPTIBLE); \
47 schedule_timeout((x * HZ)/1000); \
55 #define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
58 #define ASSERT(x) if(!(x)) BUG()
59 #define DEBUGOUT(S) printk(KERN_ERR S "\n")
60 #define DEBUGOUT1(S, A...) printk(KERN_ERR S "\n", A)
64 #define DEBUGOUT1(S, A...)
67 #define DEBUGOUT2 DEBUGOUT1
68 #define DEBUGOUT3 DEBUGOUT1
69 #define DEBUGOUT7 DEBUGOUT1
70 #define DEBUGFUNC(F) DEBUGOUT(F)
72 #define IXGB_WRITE_REG(a, reg, value) ( \
73 writel((value), ((a)->hw_addr + IXGB_##reg)))
75 #define IXGB_READ_REG(a, reg) ( \
76 readl((a)->hw_addr + IXGB_##reg))
78 #define IXGB_WRITE_REG_ARRAY(a, reg, offset, value) ( \
79 writel((value), ((a)->hw_addr + IXGB_##reg + ((offset) << 2))))
81 #define IXGB_READ_REG_ARRAY(a, reg, offset) ( \
82 readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
84 #endif /* IXGB_OSDEP_H */