drivers/net/meth.c

   1 /*
   2  * meth.c -- O2 Builtin 10/100 Ethernet driver
   3  *
   4  * Copyright (C) 2001-2003 Ilya Volynets
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/module.h>
  12 #include <linux/init.h>
  13
  14 #include <linux/sched.h>
  15 #include <linux/kernel.h> /* printk() */
  16 #include <linux/delay.h>
  17 #include <linux/slab.h>
  18 #include <linux/errno.h>  /* error codes */
  19 #include <linux/types.h>  /* size_t */
  20 #include <linux/interrupt.h> /* mark_bh */
  21
  22 #include <linux/in.h>
  23 #include <linux/in6.h>
  24 #include <linux/device.h> /* struct device, et al */
  25 #include <linux/netdevice.h>   /* struct device, and other headers */
  26 #include <linux/etherdevice.h> /* eth_type_trans */
  27 #include <linux/ip.h>          /* struct iphdr */
  28 #include <linux/tcp.h>         /* struct tcphdr */
  29 #include <linux/skbuff.h>
  30 #include <linux/mii.h> /*MII definitions */
  31
  32 #include <asm/ip32/mace.h>
  33 #include <asm/ip32/ip32_ints.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/checksum.h>
  37 #include <asm/scatterlist.h>
  38 #include <linux/dma-mapping.h>
  39
  40 #include "meth.h"
  41
  42 #ifndef MFE_DEBUG
  43 #define MFE_DEBUG 0
  44 #endif
  45
  46 #if MFE_DEBUG>=1
  47 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __FUNCTION__ , ## args)
  48 #define MFE_RX_DEBUG 2
  49 #else
  50 #define DPRINTK(str,args...)
  51 #define MFE_RX_DEBUG 0
  52 #endif
  53
  54
  55 static const char *meth_str="SGI O2 Fast Ethernet";
  56 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
  57 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
  58
  59 #define HAVE_TX_TIMEOUT
  60 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
  61 #define TX_TIMEOUT (400*HZ/1000)
  62
  63 #ifdef HAVE_TX_TIMEOUT
  64 static int timeout = TX_TIMEOUT;
  65 MODULE_PARM(timeout, "i");
  66 #endif
  67
  68 /*
  69  * This structure is private to each device. It is used to pass
  70  * packets in and out, so there is place for a packet
  71  */
  72 struct meth_private {
  73         struct net_device_stats stats;
  74         /* in-memory copy of MAC Control register */
  75         unsigned long mac_ctrl;
  76         /* in-memory copy of DMA Control register */
  77         unsigned long dma_ctrl;
  78         /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
  79         unsigned long phy_addr;
  80         tx_packet *tx_ring;
  81         dma_addr_t tx_ring_dma;
  82         struct sk_buff *tx_skbs[TX_RING_ENTRIES];
  83         dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
  84         unsigned long tx_read, tx_write, tx_count;
  85
  86         rx_packet *rx_ring[RX_RING_ENTRIES];
  87         dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
  88         struct sk_buff *rx_skbs[RX_RING_ENTRIES];
  89         unsigned long rx_write;
  90
  91         spinlock_t meth_lock;
  92 };
  93
  94 static void meth_tx_timeout(struct net_device *dev);
  95 static irqreturn_t meth_interrupt(int irq, void *dev_id, struct pt_regs *pregs);
  96
  97 /* global, initialized in ip32-setup.c */
  98 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
  99
 100 static inline void load_eaddr(struct net_device *dev)
 101 {
 102         int i;
 103         DPRINTK("Loading MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n",
 104                 (int)o2meth_eaddr[0]&0xFF,(int)o2meth_eaddr[1]&0xFF,(int)o2meth_eaddr[2]&0xFF,
 105                 (int)o2meth_eaddr[3]&0xFF,(int)o2meth_eaddr[4]&0xFF,(int)o2meth_eaddr[5]&0xFF);
 106         for (i = 0; i < 6; i++)
 107                 dev->dev_addr[i] = o2meth_eaddr[i];
 108         mace_eth_write((*(u64*)o2meth_eaddr)>>16, mac_addr);
 109 }
 110
 111 /*
 112  * Waits for BUSY status of mdio bus to clear
 113  */
 114 #define WAIT_FOR_PHY(___rval)                                           \
 115         while ((___rval = mace_eth_read(phy_data)) & MDIO_BUSY) {       \
 116                 udelay(25);                                             \
 117         }
 118 /*read phy register, return value read */
 119 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
 120 {
 121         unsigned long rval;
 122         WAIT_FOR_PHY(rval);
 123         mace_eth_write((priv->phy_addr << 5) | (phyreg & 0x1f), phy_regs);
 124         udelay(25);
 125         mace_eth_write(1, phy_trans_go);
 126         udelay(25);
 127         WAIT_FOR_PHY(rval);
 128         return rval&MDIO_DATA_MASK;
 129 }
 130
 131 static int mdio_probe(struct meth_private *priv)
 132 {
 133         int i;
 134         unsigned long p2, p3;
 135         /* check if phy is detected already */
 136         if(priv->phy_addr>=0&&priv->phy_addr<32)
 137                 return 0;
 138         spin_lock(&priv->meth_lock);
 139         for (i=0;i<32;++i){
 140                 priv->phy_addr=i;
 141                 p2=mdio_read(priv,2);
 142                 p3=mdio_read(priv,3);
 143 #if MFE_DEBUG>=2
 144                 switch ((p2<<12)|(p3>>4)){
 145                 case PHY_QS6612X:
 146                         DPRINTK("PHY is QS6612X\n");
 147                         break;
 148                 case PHY_ICS1889:
 149                         DPRINTK("PHY is ICS1889\n");
 150                         break;
 151                 case PHY_ICS1890:
 152                         DPRINTK("PHY is ICS1890\n");
 153                         break;
 154                 case PHY_DP83840:
 155                         DPRINTK("PHY is DP83840\n");
 156                         break;
 157                 }
 158 #endif
 159                 if(p2!=0xffff&&p2!=0x0000){
 160                         DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
 161                         break;
 162                 }
 163         }
 164         spin_unlock(&priv->meth_lock);
 165         if(priv->phy_addr<32) {
 166                 return 0;
 167         }
 168         DPRINTK("Oopsie! PHY is not known!\n");
 169         priv->phy_addr=-1;
 170         return -ENODEV;
 171 }
 172
 173 static void meth_check_link(struct net_device *dev)
 174 {
 175         struct meth_private *priv = (struct meth_private *) dev->priv;
 176         unsigned long mii_advertising = mdio_read(priv, 4);
 177         unsigned long mii_partner = mdio_read(priv, 5);
 178         unsigned long negotiated = mii_advertising & mii_partner;
 179         unsigned long duplex, speed;
 180
 181         if (mii_partner == 0xffff)
 182                 return;
 183
 184         speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
 185         duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
 186                  METH_PHY_FDX : 0;
 187
 188         if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
 189                 DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
 190                 if (duplex)
 191                         priv->mac_ctrl |= METH_PHY_FDX;
 192                 else
 193                         priv->mac_ctrl &= ~METH_PHY_FDX;
 194                 mace_eth_write(priv->mac_ctrl, mac_ctrl);
 195         }
 196
 197         if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
 198                 DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
 199                 if (duplex)
 200                         priv->mac_ctrl |= METH_100MBIT;
 201                 else
 202                         priv->mac_ctrl &= ~METH_100MBIT;
 203                 mace_eth_write(priv->mac_ctrl, mac_ctrl);
 204         }
 205 }
 206
 207
 208 static int meth_init_tx_ring(struct meth_private *priv)
 209 {
 210         /* Init TX ring */
 211         priv->tx_ring = dma_alloc_coherent(NULL, TX_RING_BUFFER_SIZE,
 212                                            &priv->tx_ring_dma, GFP_ATOMIC);
 213         if (!priv->tx_ring)
 214                 return -ENOMEM;
 215         memset(priv->tx_ring, 0, TX_RING_BUFFER_SIZE);
 216         priv->tx_count = priv->tx_read = priv->tx_write = 0;
 217         mace_eth_write(priv->tx_ring_dma, tx_ring_base);
 218         /* Now init skb save area */
 219         memset(priv->tx_skbs,0,sizeof(priv->tx_skbs));
 220         memset(priv->tx_skb_dmas,0,sizeof(priv->tx_skb_dmas));
 221         return 0;
 222 }
 223
 224 static int meth_init_rx_ring(struct meth_private *priv)
 225 {
 226         int i;
 227         for(i=0;i<RX_RING_ENTRIES;i++){
 228                 priv->rx_skbs[i]=alloc_skb(METH_RX_BUFF_SIZE,0);
 229                 /* 8byte status vector+3quad padding + 2byte padding,
 230                    to put data on 64bit aligned boundary */
 231                 skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
 232                 priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
 233                 /* I'll need to re-sync it after each RX */
 234                 priv->rx_ring_dmas[i]=dma_map_single(NULL,priv->rx_ring[i],
 235                                                      METH_RX_BUFF_SIZE,DMA_FROM_DEVICE);
 236                 mace_eth_write(priv->rx_ring_dmas[i], rx_fifo);
 237         }
 238         priv->rx_write = 0;
 239         return 0;
 240 }
 241 static void meth_free_tx_ring(struct meth_private *priv)
 242 {
 243         int i;
 244
 245         /* Remove any pending skb */
 246         for (i = 0; i < TX_RING_ENTRIES; i++) {
 247                 if (priv->tx_skbs[i])
 248                         dev_kfree_skb(priv->tx_skbs[i]);
 249                 priv->tx_skbs[i] = NULL;
 250         }
 251         dma_free_coherent(NULL, TX_RING_BUFFER_SIZE, priv->tx_ring,
 252                           priv->tx_ring_dma);
 253 }
 254
 255 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
 256 static void meth_free_rx_ring(struct meth_private *priv)
 257 {
 258         int i;
 259
 260         for(i=0;i<RX_RING_ENTRIES;i++) {
 261                 dma_unmap_single(NULL,priv->rx_ring_dmas[i],METH_RX_BUFF_SIZE,DMA_FROM_DEVICE);
 262                 priv->rx_ring[i]=0;
 263                 priv->rx_ring_dmas[i]=0;
 264                 kfree_skb(priv->rx_skbs[i]);
 265         }
 266 }
 267
 268 int meth_reset(struct net_device *dev)
 269 {
 270         struct meth_private *priv = (struct meth_private *) dev->priv;
 271
 272         /* Reset card */
 273         mace_eth_write(SGI_MAC_RESET, mac_ctrl);
 274         mace_eth_write(0, mac_ctrl);
 275         udelay(25);
 276
 277         /* Load ethernet address */
 278         load_eaddr(dev);
 279         /* Should load some "errata", but later */
 280
 281         /* Check for device */
 282         if(mdio_probe(priv) < 0) {
 283                 DPRINTK("Unable to find PHY\n");
 284                 return -ENODEV;
 285         }
 286
 287         /* Initial mode: 10 | Half-duplex | Accept normal packets */
 288         priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
 289         if(dev->flags | IFF_PROMISC)
 290                 priv->mac_ctrl |= METH_PROMISC;
 291         mace_eth_write(priv->mac_ctrl, mac_ctrl);
 292
 293         /* Autonegotiate speed and duplex mode */
 294         meth_check_link(dev);
 295
 296         /* Now set dma control, but don't enable DMA, yet */
 297         priv->dma_ctrl= (4 << METH_RX_OFFSET_SHIFT) |
 298                 (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
 299         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 300
 301         return 0;
 302 }
 303
 304 /*============End Helper Routines=====================*/
 305
 306 /*
 307  * Open and close
 308  */
 309 static int meth_open(struct net_device *dev)
 310 {
 311         struct meth_private *priv = dev->priv;
 312         int ret;
 313
 314         priv->phy_addr = -1;    /* No PHY is known yet... */
 315
 316         /* Initialize the hardware */
 317         ret = meth_reset(dev);
 318         if (ret < 0)
 319                 return ret;
 320
 321         /* Allocate the ring buffers */
 322         ret = meth_init_tx_ring(priv);
 323         if (ret < 0)
 324                 return ret;
 325         ret = meth_init_rx_ring(priv);
 326         if (ret < 0)
 327                 goto out_free_tx_ring;
 328
 329         ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
 330         if (ret) {
 331                 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
 332                 goto out_free_rx_ring;
 333         }
 334
 335         /* Start DMA */
 336         priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
 337                           METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
 338         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 339
 340         DPRINTK("About to start queue\n");
 341         netif_start_queue(dev);
 342
 343         return 0;
 344
 345 out_free_rx_ring:
 346         meth_free_rx_ring(priv);
 347 out_free_tx_ring:
 348         meth_free_tx_ring(priv);
 349
 350         return ret;
 351 }
 352
 353 static int meth_release(struct net_device *dev)
 354 {
 355         struct meth_private *priv = dev->priv;
 356
 357         DPRINTK("Stopping queue\n");
 358         netif_stop_queue(dev); /* can't transmit any more */
 359         /* shut down DMA */
 360         priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
 361                             METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
 362         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 363         free_irq(dev->irq, dev);
 364         meth_free_tx_ring(priv);
 365         meth_free_rx_ring(priv);
 366
 367         return 0;
 368 }
 369
 370 /*
 371  * Receive a packet: retrieve, encapsulate and pass over to upper levels
 372  */
 373 static void meth_rx(struct net_device* dev, unsigned long int_status)
 374 {
 375         struct sk_buff *skb;
 376         struct meth_private *priv = (struct meth_private *) dev->priv;
 377         unsigned long fifo_rptr=(int_status&METH_INT_RX_RPTR_MASK)>>8;
 378         spin_lock(&priv->meth_lock);
 379         priv->dma_ctrl&=~METH_DMA_RX_INT_EN;
 380         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 381         spin_unlock(&priv->meth_lock);
 382
 383         if (int_status & METH_INT_RX_UNDERFLOW){
 384                 fifo_rptr=(fifo_rptr-1)&(0xF);
 385         }
 386         while(priv->rx_write != fifo_rptr) {
 387                 u64 status;
 388                 dma_unmap_single(NULL,priv->rx_ring_dmas[priv->rx_write],
 389                                  METH_RX_BUFF_SIZE,DMA_FROM_DEVICE);
 390                 status=priv->rx_ring[priv->rx_write]->status.raw;
 391 #if MFE_DEBUG
 392                 if(!(status&METH_RX_ST_VALID)) {
 393                         DPRINTK("Not received? status=%016lx\n",status);
 394                 }
 395 #endif
 396                 if((!(status&METH_RX_STATUS_ERRORS))&&(status&METH_RX_ST_VALID)){
 397                         int len=(status&0xFFFF) - 4; /* omit CRC */
 398                         /* length sanity check */
 399                         if(len < 60 || len > 1518) {
 400                                 printk(KERN_DEBUG "%s: bogus packet size: %d, status=%#2lx.\n",
 401                                        dev->name, priv->rx_write,
 402                                        priv->rx_ring[priv->rx_write]->status.raw);
 403                                 priv->stats.rx_errors++;
 404                                 priv->stats.rx_length_errors++;
 405                                 skb=priv->rx_skbs[priv->rx_write];
 406                         } else {
 407                                 skb=alloc_skb(METH_RX_BUFF_SIZE,GFP_ATOMIC|GFP_DMA);
 408                                 if(!skb){
 409                                         /* Ouch! No memory! Drop packet on the floor */
 410                                         DPRINTK("No mem: dropping packet\n");
 411                                         priv->stats.rx_dropped++;
 412                                         skb=priv->rx_skbs[priv->rx_write];
 413                                 } else {
 414                                         struct sk_buff *skb_c=priv->rx_skbs[priv->rx_write];
 415                                         /* 8byte status vector+3quad padding + 2byte padding,
 416                                            to put data on 64bit aligned boundary */
 417                                         skb_reserve(skb,METH_RX_HEAD);
 418                                         /* Write metadata, and then pass to the receive level */
 419                                         skb_put(skb_c,len);
 420                                         priv->rx_skbs[priv->rx_write]=skb;
 421                                         skb_c->dev = dev;
 422                                         skb_c->protocol = eth_type_trans(skb_c, dev);
 423                                         dev->last_rx = jiffies;
 424                                         priv->stats.rx_packets++;
 425                                         priv->stats.rx_bytes+=len;
 426                                         netif_rx(skb_c);
 427                                 }
 428                         }
 429                 } else {
 430                         priv->stats.rx_errors++;
 431                         skb=priv->rx_skbs[priv->rx_write];
 432 #if MFE_DEBUG>0
 433                         printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
 434                         if(status&METH_RX_ST_RCV_CODE_VIOLATION)
 435                                 printk(KERN_WARNING "Receive Code Violation\n");
 436                         if(status&METH_RX_ST_CRC_ERR)
 437                                 printk(KERN_WARNING "CRC error\n");
 438                         if(status&METH_RX_ST_INV_PREAMBLE_CTX)
 439                                 printk(KERN_WARNING "Invalid Preamble Context\n");
 440                         if(status&METH_RX_ST_LONG_EVT_SEEN)
 441                                 printk(KERN_WARNING "Long Event Seen...\n");
 442                         if(status&METH_RX_ST_BAD_PACKET)
 443                                 printk(KERN_WARNING "Bad Packet\n");
 444                         if(status&METH_RX_ST_CARRIER_EVT_SEEN)
 445                                 printk(KERN_WARNING "Carrier Event Seen\n");
 446 #endif
 447                 }
 448                 priv->rx_ring[priv->rx_write]=(rx_packet*)skb->head;
 449                 priv->rx_ring[priv->rx_write]->status.raw=0;
 450                 priv->rx_ring_dmas[priv->rx_write]=dma_map_single(NULL,priv->rx_ring[priv->rx_write],
 451                                                                   METH_RX_BUFF_SIZE,DMA_FROM_DEVICE);
 452                 mace_eth_write(priv->rx_ring_dmas[priv->rx_write], rx_fifo);
 453                 ADVANCE_RX_PTR(priv->rx_write);
 454         }
 455         spin_lock(&priv->meth_lock);
 456         /* In case there was underflow, and Rx DMA was disabled */
 457         priv->dma_ctrl|=METH_DMA_RX_INT_EN|METH_DMA_RX_EN;
 458         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 459         mace_eth_write(METH_INT_RX_THRESHOLD, int_stat);
 460         spin_unlock(&priv->meth_lock);
 461 }
 462
 463 static int meth_tx_full(struct net_device *dev)
 464 {
 465         struct meth_private *priv = (struct meth_private *) dev->priv;
 466
 467         return(priv->tx_count >= TX_RING_ENTRIES-1);
 468 }
 469
 470 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
 471 {
 472         struct meth_private *priv = dev->priv;
 473         u64 status;
 474         struct sk_buff *skb;
 475         unsigned long rptr=(int_status&TX_INFO_RPTR)>>16;
 476
 477         spin_lock(&priv->meth_lock);
 478
 479         /* Stop DMA notification */
 480         priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
 481         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 482
 483         while(priv->tx_read != rptr){
 484                 skb = priv->tx_skbs[priv->tx_read];
 485                 status = priv->tx_ring[priv->tx_read].header.raw;
 486 #if MFE_DEBUG>=1
 487                 if(priv->tx_read==priv->tx_write)
 488                         DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n",priv->tx_read,priv->tx_write,rptr);
 489 #endif
 490                 if(status & METH_TX_ST_DONE) {
 491                         if(status & METH_TX_ST_SUCCESS){
 492                                 priv->stats.tx_packets++;
 493                                 priv->stats.tx_bytes += skb->len;
 494                         } else {
 495                                 priv->stats.tx_errors++;
 496 #if MFE_DEBUG>=1
 497                                 DPRINTK("TX error: status=%016lx <",status);
 498                                 if(status & METH_TX_ST_SUCCESS)
 499                                         printk(" SUCCESS");
 500                                 if(status & METH_TX_ST_TOOLONG)
 501                                         printk(" TOOLONG");
 502                                 if(status & METH_TX_ST_UNDERRUN)
 503                                         printk(" UNDERRUN");
 504                                 if(status & METH_TX_ST_EXCCOLL)
 505                                         printk(" EXCCOLL");
 506                                 if(status & METH_TX_ST_DEFER)
 507                                         printk(" DEFER");
 508                                 if(status & METH_TX_ST_LATECOLL)
 509                                         printk(" LATECOLL");
 510                                 printk(" >\n");
 511 #endif
 512                         }
 513                 } else {
 514                         DPRINTK("RPTR points us here, but packet not done?\n");
 515                         break;
 516                 }
 517                 dev_kfree_skb_irq(skb);
 518                 priv->tx_skbs[priv->tx_read] = NULL;
 519                 priv->tx_ring[priv->tx_read].header.raw = 0;
 520                 priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
 521                 priv->tx_count --;
 522         }
 523
 524         /* wake up queue if it was stopped */
 525         if (netif_queue_stopped(dev) && ! meth_tx_full(dev)) {
 526                 netif_wake_queue(dev);
 527         }
 528
 529         mace_eth_write(METH_INT_TX_EMPTY | METH_INT_TX_PKT, int_stat);
 530         spin_unlock(&priv->meth_lock);
 531 }
 532
 533 static void meth_error(struct net_device* dev, u32 status)
 534 {
 535         struct meth_private *priv = (struct meth_private *) dev->priv;
 536
 537         printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
 538         /* check for errors too... */
 539         if (status & (METH_INT_TX_LINK_FAIL))
 540                 printk(KERN_WARNING "meth: link failure\n");
 541         /* Should I do full reset in this case? */
 542         if (status & (METH_INT_MEM_ERROR))
 543                 printk(KERN_WARNING "meth: memory error\n");
 544         if (status & (METH_INT_TX_ABORT))
 545                 printk(KERN_WARNING "meth: aborted\n");
 546         if (status & (METH_INT_RX_OVERFLOW))
 547                 printk(KERN_WARNING "meth: Rx overflow\n");
 548         if (status & (METH_INT_RX_UNDERFLOW)) {
 549                 printk(KERN_WARNING "meth: Rx underflow\n");
 550                 spin_lock(&priv->meth_lock);
 551                 mace_eth_write(METH_INT_RX_UNDERFLOW, int_stat);
 552                 /* more underflow interrupts will be delivered,
 553                    effectively throwing us into an infinite loop.
 554                    Thus I stop processing Rx in this case.
 555                 */
 556                 priv->dma_ctrl&=~METH_DMA_RX_EN;
 557                 mace_eth_write(priv->dma_ctrl, dma_ctrl);
 558                 DPRINTK("Disabled meth Rx DMA temporarily\n");
 559                 spin_unlock(&priv->meth_lock);
 560         }
 561         mace_eth_write(METH_INT_ERROR, int_stat);
 562 }
 563
 564 /*
 565  * The typical interrupt entry point
 566  */
 567 static irqreturn_t meth_interrupt(int irq, void *dev_id, struct pt_regs *pregs)
 568 {
 569         struct net_device *dev = (struct net_device *)dev_id;
 570         struct meth_private *priv = (struct meth_private *) dev->priv;
 571         unsigned long status;
 572
 573         status = mace_eth_read(int_stat);
 574         while (status & 0xFF) {
 575                 /* First handle errors - if we get Rx underflow,
 576                    Rx DMA will be disabled, and Rx handler will reenable
 577                    it. I don't think it's possible to get Rx underflow,
 578                    without getting Rx interrupt */
 579                 if (status & METH_INT_ERROR) {
 580                         meth_error(dev, status);
 581                 }
 582                 if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
 583                         /* a transmission is over: free the skb */
 584                         meth_tx_cleanup(dev, status);
 585                 }
 586                 if (status & METH_INT_RX_THRESHOLD) {
 587                         if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
 588                                 break;
 589                         /* send it to meth_rx for handling */
 590                         meth_rx(dev, status);
 591                 }
 592                 status = mace_eth_read(int_stat);
 593         }
 594
 595         return IRQ_HANDLED;
 596 }
 597
 598 /*
 599  * Transmits packets that fit into TX descriptor (are <=120B)
 600  */
 601 static void meth_tx_short_prepare(struct meth_private *priv,
 602                                   struct sk_buff *skb)
 603 {
 604         tx_packet *desc=&priv->tx_ring[priv->tx_write];
 605         int len = (skb->len<ETH_ZLEN)?ETH_ZLEN:skb->len;
 606
 607         desc->header.raw=METH_TX_CMD_INT_EN|(len-1)|((128-len)<<16);
 608         /* maybe I should set whole thing to 0 first... */
 609         memcpy(desc->data.dt+(120-len),skb->data,skb->len);
 610         if(skb->len < len)
 611                 memset(desc->data.dt+120-len+skb->len,0,len-skb->len);
 612 }
 613 #define TX_CATBUF1 BIT(25)
 614 static void meth_tx_1page_prepare(struct meth_private *priv,
 615                                   struct sk_buff *skb)
 616 {
 617         tx_packet *desc=&priv->tx_ring[priv->tx_write];
 618         void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
 619         int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
 620         int buffer_len = skb->len - unaligned_len;
 621         dma_addr_t catbuf;
 622
 623         desc->header.raw=METH_TX_CMD_INT_EN|TX_CATBUF1|(skb->len-1);
 624
 625         /* unaligned part */
 626         if(unaligned_len){
 627                 memcpy(desc->data.dt+(120-unaligned_len),
 628                        skb->data, unaligned_len);
 629                 desc->header.raw |= (128-unaligned_len) << 16;
 630         }
 631
 632         /* first page */
 633         catbuf = dma_map_single(NULL, buffer_data, buffer_len,
 634                                 DMA_TO_DEVICE);
 635         desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
 636         desc->data.cat_buf[0].form.len = buffer_len-1;
 637 }
 638 #define TX_CATBUF2 BIT(26)
 639 static void meth_tx_2page_prepare(struct meth_private *priv,
 640                                   struct sk_buff *skb)
 641 {
 642         tx_packet *desc=&priv->tx_ring[priv->tx_write];
 643         void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
 644         void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
 645         int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
 646         int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
 647         int buffer2_len = skb->len - buffer1_len - unaligned_len;
 648         dma_addr_t catbuf1, catbuf2;
 649
 650         desc->header.raw=METH_TX_CMD_INT_EN|TX_CATBUF1|TX_CATBUF2|(skb->len-1);
 651         /* unaligned part */
 652         if(unaligned_len){
 653                 memcpy(desc->data.dt+(120-unaligned_len),
 654                        skb->data, unaligned_len);
 655                 desc->header.raw |= (128-unaligned_len) << 16;
 656         }
 657
 658         /* first page */
 659         catbuf1 = dma_map_single(NULL, buffer1_data, buffer1_len,
 660                                  DMA_TO_DEVICE);
 661         desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
 662         desc->data.cat_buf[0].form.len = buffer1_len-1;
 663         /* second page */
 664         catbuf2 = dma_map_single(NULL, buffer2_data, buffer2_len,
 665                                  DMA_TO_DEVICE);
 666         desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
 667         desc->data.cat_buf[1].form.len = buffer2_len-1;
 668 }
 669
 670 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
 671 {
 672         /* Remember the skb, so we can free it at interrupt time */
 673         priv->tx_skbs[priv->tx_write] = skb;
 674         if(skb->len <= 120) {
 675                 /* Whole packet fits into descriptor */
 676                 meth_tx_short_prepare(priv,skb);
 677         } else if(PAGE_ALIGN((unsigned long)skb->data) !=
 678                   PAGE_ALIGN((unsigned long)skb->data+skb->len-1)) {
 679                 /* Packet crosses page boundary */
 680                 meth_tx_2page_prepare(priv,skb);
 681         } else {
 682                 /* Packet is in one page */
 683                 meth_tx_1page_prepare(priv,skb);
 684         }
 685         priv->tx_write = (priv->tx_write+1) & (TX_RING_ENTRIES-1);
 686         mace_eth_write(priv->tx_write, tx_info);
 687         priv->tx_count ++;
 688 }
 689
 690 /*
 691  * Transmit a packet (called by the kernel)
 692  */
 693 static int meth_tx(struct sk_buff *skb, struct net_device *dev)
 694 {
 695         struct meth_private *priv = (struct meth_private *) dev->priv;
 696         unsigned long flags;
 697
 698         spin_lock_irqsave(&priv->meth_lock,flags);
 699         /* Stop DMA notification */
 700         priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
 701         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 702
 703         meth_add_to_tx_ring(priv, skb);
 704         dev->trans_start = jiffies; /* save the timestamp */
 705
 706         /* If TX ring is full, tell the upper layer to stop sending packets */
 707         if (meth_tx_full(dev)) {
 708                 printk(KERN_DEBUG "TX full: stopping\n");
 709                 netif_stop_queue(dev);
 710         }
 711
 712         /* Restart DMA notification */
 713         priv->dma_ctrl |= METH_DMA_TX_INT_EN;
 714         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 715
 716         spin_unlock_irqrestore(&priv->meth_lock,flags);
 717
 718         return 0;
 719 }
 720
 721 /*
 722  * Deal with a transmit timeout.
 723  */
 724 static void meth_tx_timeout(struct net_device *dev)
 725 {
 726         struct meth_private *priv = (struct meth_private *) dev->priv;
 727         unsigned long flags;
 728
 729         printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
 730
 731         /* Protect against concurrent rx interrupts */
 732         spin_lock_irqsave(&priv->meth_lock,flags);
 733
 734         /* Try to reset the interface. */
 735         meth_reset(dev);
 736
 737         priv->stats.tx_errors++;
 738
 739         /* Clear all rings */
 740         meth_free_tx_ring(priv);
 741         meth_free_rx_ring(priv);
 742         meth_init_tx_ring(priv);
 743         meth_init_rx_ring(priv);
 744
 745         /* Restart dma */
 746         priv->dma_ctrl|=METH_DMA_TX_EN|METH_DMA_RX_EN|METH_DMA_RX_INT_EN;
 747         mace_eth_write(priv->dma_ctrl, dma_ctrl);
 748
 749         /* Enable interrupt */
 750         spin_unlock_irqrestore(&priv->meth_lock,flags);
 751
 752         dev->trans_start = jiffies;
 753         netif_wake_queue(dev);
 754
 755         return;
 756 }
 757
 758 /*
 759  * Ioctl commands
 760  */
 761 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 762 {
 763         DPRINTK("ioctl\n");
 764         return 0;
 765 }
 766
 767 /*
 768  * Return statistics to the caller
 769  */
 770 static struct net_device_stats *meth_stats(struct net_device *dev)
 771 {
 772         struct meth_private *priv = (struct meth_private *) dev->priv;
 773         return &priv->stats;
 774 }
 775
 776 /*
 777  * The init function.
 778  */
 779 static struct net_device *meth_init(void)
 780 {
 781         struct net_device *dev;
 782         struct meth_private *priv;
 783         int ret;
 784
 785         dev = alloc_etherdev(sizeof(struct meth_private));
 786         if (!dev)
 787                 return ERR_PTR(-ENOMEM);
 788
 789         dev->open            = meth_open;
 790         dev->stop            = meth_release;
 791         dev->hard_start_xmit = meth_tx;
 792         dev->do_ioctl        = meth_ioctl;
 793         dev->get_stats       = meth_stats;
 794 #ifdef HAVE_TX_TIMEOUT
 795         dev->tx_timeout      = meth_tx_timeout;
 796         dev->watchdog_timeo  = timeout;
 797 #endif
 798         dev->irq             = MACE_ETHERNET_IRQ;
 799         dev->base_addr       = (unsigned long)&mace->eth;
 800
 801         priv = (struct meth_private *) dev->priv;
 802         spin_lock_init(&priv->meth_lock);
 803
 804         ret = register_netdev(dev);
 805         if (ret) {
 806                 free_netdev(dev);
 807                 return ERR_PTR(ret);
 808         }
 809
 810         printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
 811                dev->name, (unsigned int)mace_eth_read(mac_ctrl) >> 29);
 812         return 0;
 813 }
 814
 815 static struct net_device *meth_dev;
 816
 817 static int __init meth_init_module(void)
 818 {
 819         meth_dev = meth_init();
 820         if (IS_ERR(meth_dev))
 821                 return PTR_ERR(meth_dev);
 822         return 0;
 823 }
 824
 825 static void __exit meth_exit_module(void)
 826 {
 827         unregister_netdev(meth_dev);
 828         free_netdev(meth_dev);
 829 }
 830
 831 module_init(meth_init_module);
 832 module_exit(meth_exit_module);