drivers/net/sb1250-mac.c

   1 /*
   2  * Copyright (C) 2001,2002,2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 /*
  20   This driver is designed for the Broadcom SiByte SOC built-in
  21   Ethernet controllers.
  22
  23   Written by Mitch Lichtenberg at Broadcom Corp.
  24 */
  25
  26
  27
  28 #define CONFIG_SBMAC_COALESCE
  29
  30 /* A few user-configurable values.
  31    These may be modified when a driver module is loaded. */
  32
  33 static int debug = 1;                   /* 1 normal messages, 0 quiet .. 7 verbose. */
  34 static int noisy_mii = 1;               /* mii status msgs */
  35
  36 /* Used to pass the media type, etc.
  37    Both 'options[]' and 'full_duplex[]' should exist for driver
  38    interoperability.
  39    The media type is usually passed in 'options[]'.
  40 */
  41
  42 #define MAX_UNITS 3             /* More are supported, limit only on options */
  43 #ifdef MODULE
  44 static int options[MAX_UNITS] = {-1, -1, -1};
  45 static int full_duplex[MAX_UNITS] = {-1, -1, -1};
  46 #endif
  47
  48 #ifdef CONFIG_SBMAC_COALESCE
  49 static int int_pktcnt = 0;
  50 static int int_timeout = 0;
  51 #endif
  52
  53 /* Operational parameters that usually are not changed. */
  54
  55 /* Time in jiffies before concluding the transmitter is hung. */
  56 #define TX_TIMEOUT  (2*HZ)
  57
  58 #include <linux/module.h>
  59 #include <linux/kernel.h>
  60 #include <linux/string.h>
  61 #include <linux/timer.h>
  62 #include <linux/errno.h>
  63 #include <linux/ioport.h>
  64 #include <linux/slab.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/netdevice.h>
  67 #include <linux/etherdevice.h>
  68 #include <linux/skbuff.h>
  69 #include <linux/init.h>
  70 #include <linux/config.h>
  71 #include <linux/bitops.h>
  72 #include <asm/processor.h>              /* Processor type for cache alignment. */
  73 #include <asm/io.h>
  74 #include <asm/cache.h>
  75
  76 /* This is only here until the firmware is ready.  In that case,
  77    the firmware leaves the ethernet address in the register for us. */
  78 #ifdef CONFIG_SIBYTE_STANDALONE
  79 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
  80 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
  81 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
  82 #endif
  83
  84
  85 /* These identify the driver base version and may not be removed. */
  86 #if 0
  87 static char version1[] __devinitdata =
  88 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
  89 #endif
  90
  91
  92
  93 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
  94 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
  95 MODULE_PARM(debug, "i");
  96 MODULE_PARM(noisy_mii, "i");
  97 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
  98 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
  99
 100 MODULE_PARM(int_pktcnt, "i");
 101 MODULE_PARM(int_timeout, "i");
 102
 103 #include <asm/sibyte/sb1250.h>
 104 #include <asm/sibyte/sb1250_defs.h>
 105 #include <asm/sibyte/sb1250_regs.h>
 106 #include <asm/sibyte/sb1250_mac.h>
 107 #include <asm/sibyte/sb1250_dma.h>
 108 #include <asm/sibyte/sb1250_int.h>
 109 #include <asm/sibyte/sb1250_scd.h>
 110
 111
 112 /**********************************************************************
 113  *  Simple types
 114  ********************************************************************* */
 115
 116
 117 typedef unsigned long sbmac_port_t;
 118
 119 typedef enum { sbmac_speed_auto, sbmac_speed_10,
 120                sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
 121
 122 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
 123                sbmac_duplex_full } sbmac_duplex_t;
 124
 125 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
 126                sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
 127
 128 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
 129                sbmac_state_broken } sbmac_state_t;
 130
 131
 132 /**********************************************************************
 133  *  Macros
 134  ********************************************************************* */
 135
 136
 137 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
 138                           (d)->sbdma_dscrtable : (d)->f+1)
 139
 140
 141 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
 142
 143 #define SBMAC_READCSR(t)        __raw_readq((unsigned long)t)
 144 #define SBMAC_WRITECSR(t,v)     __raw_writeq(v, (unsigned long)t)
 145
 146
 147 #define SBMAC_MAX_TXDESCR       32
 148 #define SBMAC_MAX_RXDESCR       32
 149
 150 #define ETHER_ALIGN     2
 151 #define ETHER_ADDR_LEN  6
 152 #define ENET_PACKET_SIZE        1518
 153 /*#define ENET_PACKET_SIZE      9216 */
 154
 155 /**********************************************************************
 156  *  DMA Descriptor structure
 157  ********************************************************************* */
 158
 159 typedef struct sbdmadscr_s {
 160         uint64_t  dscr_a;
 161         uint64_t  dscr_b;
 162 } sbdmadscr_t;
 163
 164 typedef unsigned long paddr_t;
 165
 166 /**********************************************************************
 167  *  DMA Controller structure
 168  ********************************************************************* */
 169
 170 typedef struct sbmacdma_s {
 171
 172         /*
 173          * This stuff is used to identify the channel and the registers
 174          * associated with it.
 175          */
 176
 177         struct sbmac_softc *sbdma_eth;          /* back pointer to associated MAC */
 178         int              sbdma_channel; /* channel number */
 179         int              sbdma_txdir;       /* direction (1=transmit) */
 180         int              sbdma_maxdescr;        /* total # of descriptors in ring */
 181 #ifdef CONFIG_SBMAC_COALESCE
 182         int              sbdma_int_pktcnt;  /* # descriptors rx/tx before interrupt*/
 183         int              sbdma_int_timeout; /* # usec rx/tx interrupt */
 184 #endif
 185
 186         sbmac_port_t     sbdma_config0; /* DMA config register 0 */
 187         sbmac_port_t     sbdma_config1; /* DMA config register 1 */
 188         sbmac_port_t     sbdma_dscrbase;        /* Descriptor base address */
 189         sbmac_port_t     sbdma_dscrcnt;     /* Descriptor count register */
 190         sbmac_port_t     sbdma_curdscr; /* current descriptor address */
 191
 192         /*
 193          * This stuff is for maintenance of the ring
 194          */
 195
 196         sbdmadscr_t     *sbdma_dscrtable;       /* base of descriptor table */
 197         sbdmadscr_t     *sbdma_dscrtable_end; /* end of descriptor table */
 198
 199         struct sk_buff **sbdma_ctxtable;    /* context table, one per descr */
 200
 201         paddr_t          sbdma_dscrtable_phys; /* and also the phys addr */
 202         sbdmadscr_t     *sbdma_addptr;  /* next dscr for sw to add */
 203         sbdmadscr_t     *sbdma_remptr;  /* next dscr for sw to remove */
 204 } sbmacdma_t;
 205
 206
 207 /**********************************************************************
 208  *  Ethernet softc structure
 209  ********************************************************************* */
 210
 211 struct sbmac_softc {
 212
 213         /*
 214          * Linux-specific things
 215          */
 216
 217         struct net_device *sbm_dev;             /* pointer to linux device */
 218         spinlock_t sbm_lock;            /* spin lock */
 219         struct timer_list sbm_timer;            /* for monitoring MII */
 220         struct net_device_stats sbm_stats;
 221         int sbm_devflags;                       /* current device flags */
 222
 223         int          sbm_phy_oldbmsr;
 224         int          sbm_phy_oldanlpar;
 225         int          sbm_phy_oldk1stsr;
 226         int          sbm_phy_oldlinkstat;
 227         int sbm_buffersize;
 228
 229         unsigned char sbm_phys[2];
 230
 231         /*
 232          * Controller-specific things
 233          */
 234
 235         unsigned long   sbm_base;          /* MAC's base address */
 236         sbmac_state_t    sbm_state;         /* current state */
 237
 238         sbmac_port_t     sbm_macenable; /* MAC Enable Register */
 239         sbmac_port_t     sbm_maccfg;    /* MAC Configuration Register */
 240         sbmac_port_t     sbm_fifocfg;   /* FIFO configuration register */
 241         sbmac_port_t     sbm_framecfg;  /* Frame configuration register */
 242         sbmac_port_t     sbm_rxfilter;  /* receive filter register */
 243         sbmac_port_t     sbm_isr;               /* Interrupt status register */
 244         sbmac_port_t     sbm_imr;               /* Interrupt mask register */
 245         sbmac_port_t     sbm_mdio;              /* MDIO register */
 246
 247         sbmac_speed_t    sbm_speed;             /* current speed */
 248         sbmac_duplex_t   sbm_duplex;    /* current duplex */
 249         sbmac_fc_t       sbm_fc;                /* current flow control setting */
 250
 251         unsigned char    sbm_hwaddr[ETHER_ADDR_LEN];
 252
 253         sbmacdma_t       sbm_txdma;             /* for now, only use channel 0 */
 254         sbmacdma_t       sbm_rxdma;
 255         int              rx_hw_checksum;
 256         int              sbe_idx;
 257 };
 258
 259
 260 /**********************************************************************
 261  *  Externs
 262  ********************************************************************* */
 263
 264 /**********************************************************************
 265  *  Prototypes
 266  ********************************************************************* */
 267
 268 static void sbdma_initctx(sbmacdma_t *d,
 269                           struct sbmac_softc *s,
 270                           int chan,
 271                           int txrx,
 272                           int maxdescr);
 273 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
 274 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
 275 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
 276 static void sbdma_emptyring(sbmacdma_t *d);
 277 static void sbdma_fillring(sbmacdma_t *d);
 278 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 279 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 280 static int sbmac_initctx(struct sbmac_softc *s);
 281 static void sbmac_channel_start(struct sbmac_softc *s);
 282 static void sbmac_channel_stop(struct sbmac_softc *s);
 283 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
 284 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
 285 static uint64_t sbmac_addr2reg(unsigned char *ptr);
 286 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs);
 287 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
 288 static void sbmac_setmulti(struct sbmac_softc *sc);
 289 static int sbmac_init(struct net_device *dev, int idx);
 290 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
 291 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
 292
 293 static int sbmac_open(struct net_device *dev);
 294 static void sbmac_timer(unsigned long data);
 295 static void sbmac_tx_timeout (struct net_device *dev);
 296 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
 297 static void sbmac_set_rx_mode(struct net_device *dev);
 298 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 299 static int sbmac_close(struct net_device *dev);
 300 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
 301
 302 static void sbmac_mii_sync(struct sbmac_softc *s);
 303 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
 304 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
 305 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 306                             unsigned int regval);
 307
 308
 309 /**********************************************************************
 310  *  Globals
 311  ********************************************************************* */
 312
 313 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
 314
 315
 316 /**********************************************************************
 317  *  MDIO constants
 318  ********************************************************************* */
 319
 320 #define MII_COMMAND_START       0x01
 321 #define MII_COMMAND_READ        0x02
 322 #define MII_COMMAND_WRITE       0x01
 323 #define MII_COMMAND_ACK         0x02
 324
 325 #define BMCR_RESET     0x8000
 326 #define BMCR_LOOPBACK  0x4000
 327 #define BMCR_SPEED0    0x2000
 328 #define BMCR_ANENABLE  0x1000
 329 #define BMCR_POWERDOWN 0x0800
 330 #define BMCR_ISOLATE   0x0400
 331 #define BMCR_RESTARTAN 0x0200
 332 #define BMCR_DUPLEX    0x0100
 333 #define BMCR_COLTEST   0x0080
 334 #define BMCR_SPEED1    0x0040
 335 #define BMCR_SPEED1000  BMCR_SPEED1
 336 #define BMCR_SPEED100   BMCR_SPEED0
 337 #define BMCR_SPEED10    0
 338
 339 #define BMSR_100BT4     0x8000
 340 #define BMSR_100BT_FDX  0x4000
 341 #define BMSR_100BT_HDX  0x2000
 342 #define BMSR_10BT_FDX   0x1000
 343 #define BMSR_10BT_HDX   0x0800
 344 #define BMSR_100BT2_FDX 0x0400
 345 #define BMSR_100BT2_HDX 0x0200
 346 #define BMSR_1000BT_XSR 0x0100
 347 #define BMSR_PRESUP     0x0040
 348 #define BMSR_ANCOMPLT   0x0020
 349 #define BMSR_REMFAULT   0x0010
 350 #define BMSR_AUTONEG    0x0008
 351 #define BMSR_LINKSTAT   0x0004
 352 #define BMSR_JABDETECT  0x0002
 353 #define BMSR_EXTCAPAB   0x0001
 354
 355 #define PHYIDR1         0x2000
 356 #define PHYIDR2         0x5C60
 357
 358 #define ANAR_NP         0x8000
 359 #define ANAR_RF         0x2000
 360 #define ANAR_ASYPAUSE   0x0800
 361 #define ANAR_PAUSE      0x0400
 362 #define ANAR_T4         0x0200
 363 #define ANAR_TXFD       0x0100
 364 #define ANAR_TXHD       0x0080
 365 #define ANAR_10FD       0x0040
 366 #define ANAR_10HD       0x0020
 367 #define ANAR_PSB        0x0001
 368
 369 #define ANLPAR_NP       0x8000
 370 #define ANLPAR_ACK      0x4000
 371 #define ANLPAR_RF       0x2000
 372 #define ANLPAR_ASYPAUSE 0x0800
 373 #define ANLPAR_PAUSE    0x0400
 374 #define ANLPAR_T4       0x0200
 375 #define ANLPAR_TXFD     0x0100
 376 #define ANLPAR_TXHD     0x0080
 377 #define ANLPAR_10FD     0x0040
 378 #define ANLPAR_10HD     0x0020
 379 #define ANLPAR_PSB      0x0001  /* 802.3 */
 380
 381 #define ANER_PDF        0x0010
 382 #define ANER_LPNPABLE   0x0008
 383 #define ANER_NPABLE     0x0004
 384 #define ANER_PAGERX     0x0002
 385 #define ANER_LPANABLE   0x0001
 386
 387 #define ANNPTR_NP       0x8000
 388 #define ANNPTR_MP       0x2000
 389 #define ANNPTR_ACK2     0x1000
 390 #define ANNPTR_TOGTX    0x0800
 391 #define ANNPTR_CODE     0x0008
 392
 393 #define ANNPRR_NP       0x8000
 394 #define ANNPRR_MP       0x2000
 395 #define ANNPRR_ACK3     0x1000
 396 #define ANNPRR_TOGTX    0x0800
 397 #define ANNPRR_CODE     0x0008
 398
 399 #define K1TCR_TESTMODE  0x0000
 400 #define K1TCR_MSMCE     0x1000
 401 #define K1TCR_MSCV      0x0800
 402 #define K1TCR_RPTR      0x0400
 403 #define K1TCR_1000BT_FDX 0x200
 404 #define K1TCR_1000BT_HDX 0x100
 405
 406 #define K1STSR_MSMCFLT  0x8000
 407 #define K1STSR_MSCFGRES 0x4000
 408 #define K1STSR_LRSTAT   0x2000
 409 #define K1STSR_RRSTAT   0x1000
 410 #define K1STSR_LP1KFD   0x0800
 411 #define K1STSR_LP1KHD   0x0400
 412 #define K1STSR_LPASMDIR 0x0200
 413
 414 #define K1SCR_1KX_FDX   0x8000
 415 #define K1SCR_1KX_HDX   0x4000
 416 #define K1SCR_1KT_FDX   0x2000
 417 #define K1SCR_1KT_HDX   0x1000
 418
 419 #define STRAP_PHY1      0x0800
 420 #define STRAP_NCMODE    0x0400
 421 #define STRAP_MANMSCFG  0x0200
 422 #define STRAP_ANENABLE  0x0100
 423 #define STRAP_MSVAL     0x0080
 424 #define STRAP_1KHDXADV  0x0010
 425 #define STRAP_1KFDXADV  0x0008
 426 #define STRAP_100ADV    0x0004
 427 #define STRAP_SPEEDSEL  0x0000
 428 #define STRAP_SPEED100  0x0001
 429
 430 #define PHYSUP_SPEED1000 0x10
 431 #define PHYSUP_SPEED100  0x08
 432 #define PHYSUP_SPEED10   0x00
 433 #define PHYSUP_LINKUP    0x04
 434 #define PHYSUP_FDX       0x02
 435
 436 #define MII_BMCR        0x00    /* Basic mode control register (rw) */
 437 #define MII_BMSR        0x01    /* Basic mode status register (ro) */
 438 #define MII_K1STSR      0x0A    /* 1K Status Register (ro) */
 439 #define MII_ANLPAR      0x05    /* Autonegotiation lnk partner abilities (rw) */
 440
 441
 442 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
 443
 444 #define ENABLE          1
 445 #define DISABLE         0
 446
 447 /**********************************************************************
 448  *  SBMAC_MII_SYNC(s)
 449  *
 450  *  Synchronize with the MII - send a pattern of bits to the MII
 451  *  that will guarantee that it is ready to accept a command.
 452  *
 453  *  Input parameters:
 454  *         s - sbmac structure
 455  *
 456  *  Return value:
 457  *         nothing
 458  ********************************************************************* */
 459
 460 static void sbmac_mii_sync(struct sbmac_softc *s)
 461 {
 462         int cnt;
 463         uint64_t bits;
 464         int mac_mdio_genc;
 465
 466         mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
 467
 468         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
 469
 470         SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 471
 472         for (cnt = 0; cnt < 32; cnt++) {
 473                 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
 474                 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 475         }
 476 }
 477
 478 /**********************************************************************
 479  *  SBMAC_MII_SENDDATA(s,data,bitcnt)
 480  *
 481  *  Send some bits to the MII.  The bits to be sent are right-
 482  *  justified in the 'data' parameter.
 483  *
 484  *  Input parameters:
 485  *         s - sbmac structure
 486  *         data - data to send
 487  *         bitcnt - number of bits to send
 488  ********************************************************************* */
 489
 490 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
 491 {
 492         int i;
 493         uint64_t bits;
 494         unsigned int curmask;
 495         int mac_mdio_genc;
 496
 497         mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
 498
 499         bits = M_MAC_MDIO_DIR_OUTPUT;
 500         SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 501
 502         curmask = 1 << (bitcnt - 1);
 503
 504         for (i = 0; i < bitcnt; i++) {
 505                 if (data & curmask)
 506                         bits |= M_MAC_MDIO_OUT;
 507                 else bits &= ~M_MAC_MDIO_OUT;
 508                 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 509                 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC | mac_mdio_genc);
 510                 SBMAC_WRITECSR(s->sbm_mdio,bits | mac_mdio_genc);
 511                 curmask >>= 1;
 512         }
 513 }
 514
 515
 516
 517 /**********************************************************************
 518  *  SBMAC_MII_READ(s,phyaddr,regidx)
 519  *
 520  *  Read a PHY register.
 521  *
 522  *  Input parameters:
 523  *         s - sbmac structure
 524  *         phyaddr - PHY's address
 525  *         regidx = index of register to read
 526  *
 527  *  Return value:
 528  *         value read, or 0 if an error occurred.
 529  ********************************************************************* */
 530
 531 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
 532 {
 533         int idx;
 534         int error;
 535         int regval;
 536         int mac_mdio_genc;
 537
 538         /*
 539          * Synchronize ourselves so that the PHY knows the next
 540          * thing coming down is a command
 541          */
 542
 543         sbmac_mii_sync(s);
 544
 545         /*
 546          * Send the data to the PHY.  The sequence is
 547          * a "start" command (2 bits)
 548          * a "read" command (2 bits)
 549          * the PHY addr (5 bits)
 550          * the register index (5 bits)
 551          */
 552
 553         sbmac_mii_senddata(s,MII_COMMAND_START, 2);
 554         sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
 555         sbmac_mii_senddata(s,phyaddr, 5);
 556         sbmac_mii_senddata(s,regidx, 5);
 557
 558         mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
 559
 560         /*
 561          * Switch the port around without a clock transition.
 562          */
 563         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
 564
 565         /*
 566          * Send out a clock pulse to signal we want the status
 567          */
 568
 569         SBMAC_WRITECSR(s->sbm_mdio,
 570                        M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
 571         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
 572
 573         /*
 574          * If an error occurred, the PHY will signal '1' back
 575          */
 576         error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN;
 577
 578         /*
 579          * Issue an 'idle' clock pulse, but keep the direction
 580          * the same.
 581          */
 582         SBMAC_WRITECSR(s->sbm_mdio,
 583                        M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc);
 584         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
 585
 586         regval = 0;
 587
 588         for (idx = 0; idx < 16; idx++) {
 589                 regval <<= 1;
 590
 591                 if (error == 0) {
 592                         if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN)
 593                                 regval |= 1;
 594                 }
 595
 596                 SBMAC_WRITECSR(s->sbm_mdio,
 597                                M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc);
 598                 SBMAC_WRITECSR(s->sbm_mdio,
 599                                M_MAC_MDIO_DIR_INPUT | mac_mdio_genc);
 600         }
 601
 602         /* Switch back to output */
 603         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
 604
 605         if (error == 0)
 606                 return regval;
 607         return 0;
 608 }
 609
 610
 611 /**********************************************************************
 612  *  SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
 613  *
 614  *  Write a value to a PHY register.
 615  *
 616  *  Input parameters:
 617  *         s - sbmac structure
 618  *         phyaddr - PHY to use
 619  *         regidx - register within the PHY
 620  *         regval - data to write to register
 621  *
 622  *  Return value:
 623  *         nothing
 624  ********************************************************************* */
 625
 626 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 627                             unsigned int regval)
 628 {
 629         int mac_mdio_genc;
 630
 631         sbmac_mii_sync(s);
 632
 633         sbmac_mii_senddata(s,MII_COMMAND_START,2);
 634         sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
 635         sbmac_mii_senddata(s,phyaddr, 5);
 636         sbmac_mii_senddata(s,regidx, 5);
 637         sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
 638         sbmac_mii_senddata(s,regval,16);
 639
 640         mac_mdio_genc = SBMAC_READCSR(s->sbm_mdio) & M_MAC_GENC;
 641
 642         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc);
 643 }
 644
 645
 646
 647 /**********************************************************************
 648  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
 649  *
 650  *  Initialize a DMA channel context.  Since there are potentially
 651  *  eight DMA channels per MAC, it's nice to do this in a standard
 652  *  way.
 653  *
 654  *  Input parameters:
 655  *         d - sbmacdma_t structure (DMA channel context)
 656  *         s - sbmac_softc structure (pointer to a MAC)
 657  *         chan - channel number (0..1 right now)
 658  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
 659  *      maxdescr - number of descriptors
 660  *
 661  *  Return value:
 662  *         nothing
 663  ********************************************************************* */
 664
 665 static void sbdma_initctx(sbmacdma_t *d,
 666                           struct sbmac_softc *s,
 667                           int chan,
 668                           int txrx,
 669                           int maxdescr)
 670 {
 671         /*
 672          * Save away interesting stuff in the structure
 673          */
 674
 675         d->sbdma_eth       = s;
 676         d->sbdma_channel   = chan;
 677         d->sbdma_txdir     = txrx;
 678
 679 #if 0
 680         /* RMON clearing */
 681         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
 682 #endif
 683
 684         SBMAC_WRITECSR(IOADDR(
 685         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0);
 686         SBMAC_WRITECSR(IOADDR(
 687         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0);
 688         SBMAC_WRITECSR(IOADDR(
 689         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0);
 690         SBMAC_WRITECSR(IOADDR(
 691         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0);
 692         SBMAC_WRITECSR(IOADDR(
 693         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0);
 694         SBMAC_WRITECSR(IOADDR(
 695         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0);
 696         SBMAC_WRITECSR(IOADDR(
 697         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0);
 698         SBMAC_WRITECSR(IOADDR(
 699         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0);
 700         SBMAC_WRITECSR(IOADDR(
 701         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0);
 702         SBMAC_WRITECSR(IOADDR(
 703         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0);
 704         SBMAC_WRITECSR(IOADDR(
 705         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0);
 706         SBMAC_WRITECSR(IOADDR(
 707         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0);
 708         SBMAC_WRITECSR(IOADDR(
 709         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0);
 710         SBMAC_WRITECSR(IOADDR(
 711         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
 712         SBMAC_WRITECSR(IOADDR(
 713         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
 714         SBMAC_WRITECSR(IOADDR(
 715         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
 716         SBMAC_WRITECSR(IOADDR(
 717         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
 718         SBMAC_WRITECSR(IOADDR(
 719         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
 720         SBMAC_WRITECSR(IOADDR(
 721         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
 722         SBMAC_WRITECSR(IOADDR(
 723         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
 724         SBMAC_WRITECSR(IOADDR(
 725         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
 726
 727         /*
 728          * initialize register pointers
 729          */
 730
 731         d->sbdma_config0 =
 732                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
 733         d->sbdma_config1 =
 734                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
 735         d->sbdma_dscrbase =
 736                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
 737         d->sbdma_dscrcnt =
 738                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
 739         d->sbdma_curdscr =
 740                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
 741
 742         /*
 743          * Allocate memory for the ring
 744          */
 745
 746         d->sbdma_maxdescr = maxdescr;
 747
 748         d->sbdma_dscrtable = (sbdmadscr_t *)
 749                 kmalloc(d->sbdma_maxdescr*sizeof(sbdmadscr_t), GFP_KERNEL);
 750
 751         memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
 752
 753         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
 754
 755         d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
 756
 757         /*
 758          * And context table
 759          */
 760
 761         d->sbdma_ctxtable = (struct sk_buff **)
 762                 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
 763
 764         memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
 765
 766 #ifdef CONFIG_SBMAC_COALESCE
 767         /*
 768          * Setup Rx/Tx DMA coalescing defaults
 769          */
 770
 771         if ( int_pktcnt ) {
 772                 d->sbdma_int_pktcnt = int_pktcnt;
 773         } else {
 774                 d->sbdma_int_pktcnt = 1;
 775         }
 776
 777         if ( int_timeout ) {
 778                 d->sbdma_int_timeout = int_timeout;
 779         } else {
 780                 d->sbdma_int_timeout = 0;
 781         }
 782 #endif
 783
 784 }
 785
 786 /**********************************************************************
 787  *  SBDMA_CHANNEL_START(d)
 788  *
 789  *  Initialize the hardware registers for a DMA channel.
 790  *
 791  *  Input parameters:
 792  *         d - DMA channel to init (context must be previously init'd
 793  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
 794  *
 795  *  Return value:
 796  *         nothing
 797  ********************************************************************* */
 798
 799 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
 800 {
 801         /*
 802          * Turn on the DMA channel
 803          */
 804
 805 #ifdef CONFIG_SBMAC_COALESCE
 806         SBMAC_WRITECSR(d->sbdma_config1,
 807                        V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
 808                        0);
 809         SBMAC_WRITECSR(d->sbdma_config0,
 810                        M_DMA_EOP_INT_EN |
 811                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 812                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
 813                        0);
 814 #else
 815         SBMAC_WRITECSR(d->sbdma_config1,0);
 816         SBMAC_WRITECSR(d->sbdma_config0,
 817                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 818                        0);
 819 #endif
 820
 821         SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
 822
 823         /*
 824          * Initialize ring pointers
 825          */
 826
 827         d->sbdma_addptr = d->sbdma_dscrtable;
 828         d->sbdma_remptr = d->sbdma_dscrtable;
 829 }
 830
 831 /**********************************************************************
 832  *  SBDMA_CHANNEL_STOP(d)
 833  *
 834  *  Initialize the hardware registers for a DMA channel.
 835  *
 836  *  Input parameters:
 837  *         d - DMA channel to init (context must be previously init'd
 838  *
 839  *  Return value:
 840  *         nothing
 841  ********************************************************************* */
 842
 843 static void sbdma_channel_stop(sbmacdma_t *d)
 844 {
 845         /*
 846          * Turn off the DMA channel
 847          */
 848
 849         SBMAC_WRITECSR(d->sbdma_config1,0);
 850
 851         SBMAC_WRITECSR(d->sbdma_dscrbase,0);
 852
 853         SBMAC_WRITECSR(d->sbdma_config0,0);
 854
 855         /*
 856          * Zero ring pointers
 857          */
 858
 859         d->sbdma_addptr = 0;
 860         d->sbdma_remptr = 0;
 861 }
 862
 863 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
 864 {
 865         unsigned long addr;
 866         unsigned long newaddr;
 867
 868         addr = (unsigned long) skb->data;
 869
 870         newaddr = (addr + power2 - 1) & ~(power2 - 1);
 871
 872         skb_reserve(skb,newaddr-addr+offset);
 873 }
 874
 875
 876 /**********************************************************************
 877  *  SBDMA_ADD_RCVBUFFER(d,sb)
 878  *
 879  *  Add a buffer to the specified DMA channel.   For receive channels,
 880  *  this queues a buffer for inbound packets.
 881  *
 882  *  Input parameters:
 883  *         d - DMA channel descriptor
 884  *         sb - sk_buff to add, or NULL if we should allocate one
 885  *
 886  *  Return value:
 887  *         0 if buffer could not be added (ring is full)
 888  *         1 if buffer added successfully
 889  ********************************************************************* */
 890
 891
 892 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
 893 {
 894         sbdmadscr_t *dsc;
 895         sbdmadscr_t *nextdsc;
 896         struct sk_buff *sb_new = NULL;
 897         int pktsize = ENET_PACKET_SIZE;
 898
 899         /* get pointer to our current place in the ring */
 900
 901         dsc = d->sbdma_addptr;
 902         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
 903
 904         /*
 905          * figure out if the ring is full - if the next descriptor
 906          * is the same as the one that we're going to remove from
 907          * the ring, the ring is full
 908          */
 909
 910         if (nextdsc == d->sbdma_remptr) {
 911                 return -ENOSPC;
 912         }
 913
 914         /*
 915          * Allocate a sk_buff if we don't already have one.
 916          * If we do have an sk_buff, reset it so that it's empty.
 917          *
 918          * Note: sk_buffs don't seem to be guaranteed to have any sort
 919          * of alignment when they are allocated.  Therefore, allocate enough
 920          * extra space to make sure that:
 921          *
 922          *    1. the data does not start in the middle of a cache line.
 923          *    2. The data does not end in the middle of a cache line
 924          *    3. The buffer can be aligned such that the IP addresses are
 925          *       naturally aligned.
 926          *
 927          *  Remember, the SOCs MAC writes whole cache lines at a time,
 928          *  without reading the old contents first.  So, if the sk_buff's
 929          *  data portion starts in the middle of a cache line, the SOC
 930          *  DMA will trash the beginning (and ending) portions.
 931          */
 932
 933         if (sb == NULL) {
 934                 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
 935                 if (sb_new == NULL) {
 936                         printk(KERN_INFO "%s: sk_buff allocation failed\n",
 937                                d->sbdma_eth->sbm_dev->name);
 938                         return -ENOBUFS;
 939                 }
 940
 941                 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
 942
 943                 /* mark skbuff owned by our device */
 944                 sb_new->dev = d->sbdma_eth->sbm_dev;
 945         }
 946         else {
 947                 sb_new = sb;
 948                 /*
 949                  * nothing special to reinit buffer, it's already aligned
 950                  * and sb->data already points to a good place.
 951                  */
 952         }
 953
 954         /*
 955          * fill in the descriptor
 956          */
 957
 958 #ifdef CONFIG_SBMAC_COALESCE
 959         /*
 960          * Do not interrupt per DMA transfer.
 961          */
 962         dsc->dscr_a = virt_to_phys(sb_new->tail) |
 963                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 964                 0;
 965 #else
 966         dsc->dscr_a = virt_to_phys(sb_new->tail) |
 967                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 968                 M_DMA_DSCRA_INTERRUPT;
 969 #endif
 970
 971         /* receiving: no options */
 972         dsc->dscr_b = 0;
 973
 974         /*
 975          * fill in the context
 976          */
 977
 978         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
 979
 980         /*
 981          * point at next packet
 982          */
 983
 984         d->sbdma_addptr = nextdsc;
 985
 986         /*
 987          * Give the buffer to the DMA engine.
 988          */
 989
 990         SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
 991
 992         return 0;                                       /* we did it */
 993 }
 994
 995 /**********************************************************************
 996  *  SBDMA_ADD_TXBUFFER(d,sb)
 997  *
 998  *  Add a transmit buffer to the specified DMA channel, causing a
 999  *  transmit to start.
1000  *
1001  *  Input parameters:
1002  *         d - DMA channel descriptor
1003  *         sb - sk_buff to add
1004  *
1005  *  Return value:
1006  *         0 transmit queued successfully
1007  *         otherwise error code
1008  ********************************************************************* */
1009
1010
1011 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1012 {
1013         sbdmadscr_t *dsc;
1014         sbdmadscr_t *nextdsc;
1015         uint64_t phys;
1016         uint64_t ncb;
1017         int length;
1018
1019         /* get pointer to our current place in the ring */
1020
1021         dsc = d->sbdma_addptr;
1022         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1023
1024         /*
1025          * figure out if the ring is full - if the next descriptor
1026          * is the same as the one that we're going to remove from
1027          * the ring, the ring is full
1028          */
1029
1030         if (nextdsc == d->sbdma_remptr) {
1031                 return -ENOSPC;
1032         }
1033
1034         /*
1035          * Under Linux, it's not necessary to copy/coalesce buffers
1036          * like it is on NetBSD.  We think they're all contiguous,
1037          * but that may not be true for GBE.
1038          */
1039
1040         length = sb->len;
1041
1042         /*
1043          * fill in the descriptor.  Note that the number of cache
1044          * blocks in the descriptor is the number of blocks
1045          * *spanned*, so we need to add in the offset (if any)
1046          * while doing the calculation.
1047          */
1048
1049         phys = virt_to_phys(sb->data);
1050         ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1051
1052         dsc->dscr_a = phys |
1053                 V_DMA_DSCRA_A_SIZE(ncb) |
1054 #ifndef CONFIG_SBMAC_COALESCE
1055                 M_DMA_DSCRA_INTERRUPT |
1056 #endif
1057                 M_DMA_ETHTX_SOP;
1058
1059         /* transmitting: set outbound options and length */
1060
1061         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1062                 V_DMA_DSCRB_PKT_SIZE(length);
1063
1064         /*
1065          * fill in the context
1066          */
1067
1068         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1069
1070         /*
1071          * point at next packet
1072          */
1073
1074         d->sbdma_addptr = nextdsc;
1075
1076         /*
1077          * Give the buffer to the DMA engine.
1078          */
1079
1080         SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
1081
1082         return 0;                                       /* we did it */
1083 }
1084
1085
1086
1087
1088 /**********************************************************************
1089  *  SBDMA_EMPTYRING(d)
1090  *
1091  *  Free all allocated sk_buffs on the specified DMA channel;
1092  *
1093  *  Input parameters:
1094  *         d  - DMA channel
1095  *
1096  *  Return value:
1097  *         nothing
1098  ********************************************************************* */
1099
1100 static void sbdma_emptyring(sbmacdma_t *d)
1101 {
1102         int idx;
1103         struct sk_buff *sb;
1104
1105         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1106                 sb = d->sbdma_ctxtable[idx];
1107                 if (sb) {
1108                         dev_kfree_skb(sb);
1109                         d->sbdma_ctxtable[idx] = NULL;
1110                 }
1111         }
1112 }
1113
1114
1115 /**********************************************************************
1116  *  SBDMA_FILLRING(d)
1117  *
1118  *  Fill the specified DMA channel (must be receive channel)
1119  *  with sk_buffs
1120  *
1121  *  Input parameters:
1122  *         d - DMA channel
1123  *
1124  *  Return value:
1125  *         nothing
1126  ********************************************************************* */
1127
1128 static void sbdma_fillring(sbmacdma_t *d)
1129 {
1130         int idx;
1131
1132         for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1133                 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1134                         break;
1135         }
1136 }
1137
1138
1139 /**********************************************************************
1140  *  SBDMA_RX_PROCESS(sc,d)
1141  *
1142  *  Process "completed" receive buffers on the specified DMA channel.
1143  *  Note that this isn't really ideal for priority channels, since
1144  *  it processes all of the packets on a given channel before
1145  *  returning.
1146  *
1147  *  Input parameters:
1148  *         sc - softc structure
1149  *         d - DMA channel context
1150  *
1151  *  Return value:
1152  *         nothing
1153  ********************************************************************* */
1154
1155 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1156 {
1157         int curidx;
1158         int hwidx;
1159         sbdmadscr_t *dsc;
1160         struct sk_buff *sb;
1161         int len;
1162
1163         for (;;) {
1164                 /*
1165                  * figure out where we are (as an index) and where
1166                  * the hardware is (also as an index)
1167                  *
1168                  * This could be done faster if (for example) the
1169                  * descriptor table was page-aligned and contiguous in
1170                  * both virtual and physical memory -- you could then
1171                  * just compare the low-order bits of the virtual address
1172                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1173                  */
1174
1175                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1176                 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1177                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1178
1179                 /*
1180                  * If they're the same, that means we've processed all
1181                  * of the descriptors up to (but not including) the one that
1182                  * the hardware is working on right now.
1183                  */
1184
1185                 if (curidx == hwidx)
1186                         break;
1187
1188                 /*
1189                  * Otherwise, get the packet's sk_buff ptr back
1190                  */
1191
1192                 dsc = &(d->sbdma_dscrtable[curidx]);
1193                 sb = d->sbdma_ctxtable[curidx];
1194                 d->sbdma_ctxtable[curidx] = NULL;
1195
1196                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1197
1198                 /*
1199                  * Check packet status.  If good, process it.
1200                  * If not, silently drop it and put it back on the
1201                  * receive ring.
1202                  */
1203
1204                 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1205
1206                         /*
1207                          * Add a new buffer to replace the old one.  If we fail
1208                          * to allocate a buffer, we're going to drop this
1209                          * packet and put it right back on the receive ring.
1210                          */
1211
1212                         if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1213                                 sc->sbm_stats.rx_dropped++;
1214                                 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1215                         } else {
1216                                 /*
1217                                  * Set length into the packet
1218                                  */
1219                                 skb_put(sb,len);
1220
1221                                 /*
1222                                  * Buffer has been replaced on the
1223                                  * receive ring.  Pass the buffer to
1224                                  * the kernel
1225                                  */
1226                                 sc->sbm_stats.rx_bytes += len;
1227                                 sc->sbm_stats.rx_packets++;
1228                                 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1229                                 /* Check hw IPv4/TCP checksum if supported */
1230                                 if (sc->rx_hw_checksum == ENABLE) {
1231                                         if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1232                                             !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1233                                                 sb->ip_summed = CHECKSUM_UNNECESSARY;
1234                                                 /* don't need to set sb->csum */
1235                                         } else {
1236                                                 sb->ip_summed = CHECKSUM_NONE;
1237                                         }
1238                                 }
1239
1240                                 netif_rx(sb);
1241                         }
1242                 } else {
1243                         /*
1244                          * Packet was mangled somehow.  Just drop it and
1245                          * put it back on the receive ring.
1246                          */
1247                         sc->sbm_stats.rx_errors++;
1248                         sbdma_add_rcvbuffer(d,sb);
1249                 }
1250
1251
1252                 /*
1253                  * .. and advance to the next buffer.
1254                  */
1255
1256                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1257
1258         }
1259 }
1260
1261
1262
1263 /**********************************************************************
1264  *  SBDMA_TX_PROCESS(sc,d)
1265  *
1266  *  Process "completed" transmit buffers on the specified DMA channel.
1267  *  This is normally called within the interrupt service routine.
1268  *  Note that this isn't really ideal for priority channels, since
1269  *  it processes all of the packets on a given channel before
1270  *  returning.
1271  *
1272  *  Input parameters:
1273  *      sc - softc structure
1274  *         d - DMA channel context
1275  *
1276  *  Return value:
1277  *         nothing
1278  ********************************************************************* */
1279
1280 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1281 {
1282         int curidx;
1283         int hwidx;
1284         sbdmadscr_t *dsc;
1285         struct sk_buff *sb;
1286         unsigned long flags;
1287
1288         spin_lock_irqsave(&(sc->sbm_lock), flags);
1289
1290         for (;;) {
1291                 /*
1292                  * figure out where we are (as an index) and where
1293                  * the hardware is (also as an index)
1294                  *
1295                  * This could be done faster if (for example) the
1296                  * descriptor table was page-aligned and contiguous in
1297                  * both virtual and physical memory -- you could then
1298                  * just compare the low-order bits of the virtual address
1299                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1300                  */
1301
1302                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1303                 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1304                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1305
1306                 /*
1307                  * If they're the same, that means we've processed all
1308                  * of the descriptors up to (but not including) the one that
1309                  * the hardware is working on right now.
1310                  */
1311
1312                 if (curidx == hwidx)
1313                         break;
1314
1315                 /*
1316                  * Otherwise, get the packet's sk_buff ptr back
1317                  */
1318
1319                 dsc = &(d->sbdma_dscrtable[curidx]);
1320                 sb = d->sbdma_ctxtable[curidx];
1321                 d->sbdma_ctxtable[curidx] = NULL;
1322
1323                 /*
1324                  * Stats
1325                  */
1326
1327                 sc->sbm_stats.tx_bytes += sb->len;
1328                 sc->sbm_stats.tx_packets++;
1329
1330                 /*
1331                  * for transmits, we just free buffers.
1332                  */
1333
1334                 dev_kfree_skb_irq(sb);
1335
1336                 /*
1337                  * .. and advance to the next buffer.
1338                  */
1339
1340                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1341
1342         }
1343
1344         /*
1345          * Decide if we should wake up the protocol or not.
1346          * Other drivers seem to do this when we reach a low
1347          * watermark on the transmit queue.
1348          */
1349
1350         netif_wake_queue(d->sbdma_eth->sbm_dev);
1351
1352         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1353
1354 }
1355
1356
1357
1358 /**********************************************************************
1359  *  SBMAC_INITCTX(s)
1360  *
1361  *  Initialize an Ethernet context structure - this is called
1362  *  once per MAC on the 1250.  Memory is allocated here, so don't
1363  *  call it again from inside the ioctl routines that bring the
1364  *  interface up/down
1365  *
1366  *  Input parameters:
1367  *         s - sbmac context structure
1368  *
1369  *  Return value:
1370  *         0
1371  ********************************************************************* */
1372
1373 static int sbmac_initctx(struct sbmac_softc *s)
1374 {
1375
1376         /*
1377          * figure out the addresses of some ports
1378          */
1379
1380         s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1381         s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1382         s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1383         s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1384         s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1385         s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1386         s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1387         s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1388
1389         s->sbm_phys[0]   = 1;
1390         s->sbm_phys[1]   = 0;
1391
1392         s->sbm_phy_oldbmsr = 0;
1393         s->sbm_phy_oldanlpar = 0;
1394         s->sbm_phy_oldk1stsr = 0;
1395         s->sbm_phy_oldlinkstat = 0;
1396
1397         /*
1398          * Initialize the DMA channels.  Right now, only one per MAC is used
1399          * Note: Only do this _once_, as it allocates memory from the kernel!
1400          */
1401
1402         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1403         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1404
1405         /*
1406          * initial state is OFF
1407          */
1408
1409         s->sbm_state = sbmac_state_off;
1410
1411         /*
1412          * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1413          */
1414
1415         s->sbm_speed = sbmac_speed_10;
1416         s->sbm_duplex = sbmac_duplex_half;
1417         s->sbm_fc = sbmac_fc_disabled;
1418
1419         return 0;
1420 }
1421
1422
1423 static void sbdma_uninitctx(struct sbmacdma_s *d)
1424 {
1425         if (d->sbdma_dscrtable) {
1426                 kfree(d->sbdma_dscrtable);
1427                 d->sbdma_dscrtable = NULL;
1428         }
1429
1430         if (d->sbdma_ctxtable) {
1431                 kfree(d->sbdma_ctxtable);
1432                 d->sbdma_ctxtable = NULL;
1433         }
1434 }
1435
1436
1437 static void sbmac_uninitctx(struct sbmac_softc *sc)
1438 {
1439         sbdma_uninitctx(&(sc->sbm_txdma));
1440         sbdma_uninitctx(&(sc->sbm_rxdma));
1441 }
1442
1443
1444 /**********************************************************************
1445  *  SBMAC_CHANNEL_START(s)
1446  *
1447  *  Start packet processing on this MAC.
1448  *
1449  *  Input parameters:
1450  *         s - sbmac structure
1451  *
1452  *  Return value:
1453  *         nothing
1454  ********************************************************************* */
1455
1456 static void sbmac_channel_start(struct sbmac_softc *s)
1457 {
1458         uint64_t reg;
1459         sbmac_port_t port;
1460         uint64_t cfg,fifo,framecfg;
1461         int idx, th_value;
1462
1463         /*
1464          * Don't do this if running
1465          */
1466
1467         if (s->sbm_state == sbmac_state_on)
1468                 return;
1469
1470         /*
1471          * Bring the controller out of reset, but leave it off.
1472          */
1473
1474         SBMAC_WRITECSR(s->sbm_macenable,0);
1475
1476         /*
1477          * Ignore all received packets
1478          */
1479
1480         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1481
1482         /*
1483          * Calculate values for various control registers.
1484          */
1485
1486         cfg = M_MAC_RETRY_EN |
1487                 M_MAC_TX_HOLD_SOP_EN |
1488                 V_MAC_TX_PAUSE_CNT_16K |
1489                 M_MAC_AP_STAT_EN |
1490                 M_MAC_FAST_SYNC |
1491                 M_MAC_SS_EN |
1492                 0;
1493
1494         /*
1495          * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1496          * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1497          * Use a larger RD_THRSH for gigabit
1498          */
1499         if (periph_rev >= 2)
1500                 th_value = 64;
1501         else
1502                 th_value = 28;
1503
1504         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1505                 ((s->sbm_speed == sbmac_speed_1000)
1506                  ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1507                 V_MAC_TX_RL_THRSH(4) |
1508                 V_MAC_RX_PL_THRSH(4) |
1509                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1510                 V_MAC_RX_PL_THRSH(4) |
1511                 V_MAC_RX_RL_THRSH(8) |
1512                 0;
1513
1514         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1515                 V_MAC_MAX_FRAMESZ_DEFAULT |
1516                 V_MAC_BACKOFF_SEL(1);
1517
1518         /*
1519          * Clear out the hash address map
1520          */
1521
1522         port = s->sbm_base + R_MAC_HASH_BASE;
1523         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1524                 SBMAC_WRITECSR(port,0);
1525                 port += sizeof(uint64_t);
1526         }
1527
1528         /*
1529          * Clear out the exact-match table
1530          */
1531
1532         port = s->sbm_base + R_MAC_ADDR_BASE;
1533         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1534                 SBMAC_WRITECSR(port,0);
1535                 port += sizeof(uint64_t);
1536         }
1537
1538         /*
1539          * Clear out the DMA Channel mapping table registers
1540          */
1541
1542         port = s->sbm_base + R_MAC_CHUP0_BASE;
1543         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1544                 SBMAC_WRITECSR(port,0);
1545                 port += sizeof(uint64_t);
1546         }
1547
1548
1549         port = s->sbm_base + R_MAC_CHLO0_BASE;
1550         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1551                 SBMAC_WRITECSR(port,0);
1552                 port += sizeof(uint64_t);
1553         }
1554
1555         /*
1556          * Program the hardware address.  It goes into the hardware-address
1557          * register as well as the first filter register.
1558          */
1559
1560         reg = sbmac_addr2reg(s->sbm_hwaddr);
1561
1562         port = s->sbm_base + R_MAC_ADDR_BASE;
1563         SBMAC_WRITECSR(port,reg);
1564         port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1565
1566 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1567         /*
1568          * Pass1 SOCs do not receive packets addressed to the
1569          * destination address in the R_MAC_ETHERNET_ADDR register.
1570          * Set the value to zero.
1571          */
1572         SBMAC_WRITECSR(port,0);
1573 #else
1574         SBMAC_WRITECSR(port,reg);
1575 #endif
1576
1577         /*
1578          * Set the receive filter for no packets, and write values
1579          * to the various config registers
1580          */
1581
1582         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1583         SBMAC_WRITECSR(s->sbm_imr,0);
1584         SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1585         SBMAC_WRITECSR(s->sbm_fifocfg,fifo);
1586         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1587
1588         /*
1589          * Initialize DMA channels (rings should be ok now)
1590          */
1591
1592         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1593         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1594
1595         /*
1596          * Configure the speed, duplex, and flow control
1597          */
1598
1599         sbmac_set_speed(s,s->sbm_speed);
1600         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1601
1602         /*
1603          * Fill the receive ring
1604          */
1605
1606         sbdma_fillring(&(s->sbm_rxdma));
1607
1608         /*
1609          * Turn on the rest of the bits in the enable register
1610          */
1611
1612         SBMAC_WRITECSR(s->sbm_macenable,
1613                        M_MAC_RXDMA_EN0 |
1614                        M_MAC_TXDMA_EN0 |
1615                        M_MAC_RX_ENABLE |
1616                        M_MAC_TX_ENABLE);
1617
1618
1619
1620
1621 #ifdef CONFIG_SBMAC_COALESCE
1622         /*
1623          * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1624          */
1625         SBMAC_WRITECSR(s->sbm_imr,
1626                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1627                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));
1628 #else
1629         /*
1630          * Accept any kind of interrupt on TX and RX DMA channel 0
1631          */
1632         SBMAC_WRITECSR(s->sbm_imr,
1633                        (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1634                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
1635 #endif
1636
1637         /*
1638          * Enable receiving unicasts and broadcasts
1639          */
1640
1641         SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN);
1642
1643         /*
1644          * we're running now.
1645          */
1646
1647         s->sbm_state = sbmac_state_on;
1648
1649         /*
1650          * Program multicast addresses
1651          */
1652
1653         sbmac_setmulti(s);
1654
1655         /*
1656          * If channel was in promiscuous mode before, turn that on
1657          */
1658
1659         if (s->sbm_devflags & IFF_PROMISC) {
1660                 sbmac_promiscuous_mode(s,1);
1661         }
1662
1663 }
1664
1665
1666 /**********************************************************************
1667  *  SBMAC_CHANNEL_STOP(s)
1668  *
1669  *  Stop packet processing on this MAC.
1670  *
1671  *  Input parameters:
1672  *         s - sbmac structure
1673  *
1674  *  Return value:
1675  *         nothing
1676  ********************************************************************* */
1677
1678 static void sbmac_channel_stop(struct sbmac_softc *s)
1679 {
1680         /* don't do this if already stopped */
1681
1682         if (s->sbm_state == sbmac_state_off)
1683                 return;
1684
1685         /* don't accept any packets, disable all interrupts */
1686
1687         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1688         SBMAC_WRITECSR(s->sbm_imr,0);
1689
1690         /* Turn off ticker */
1691
1692         /* XXX */
1693
1694         /* turn off receiver and transmitter */
1695
1696         SBMAC_WRITECSR(s->sbm_macenable,0);
1697
1698         /* We're stopped now. */
1699
1700         s->sbm_state = sbmac_state_off;
1701
1702         /*
1703          * Stop DMA channels (rings should be ok now)
1704          */
1705
1706         sbdma_channel_stop(&(s->sbm_rxdma));
1707         sbdma_channel_stop(&(s->sbm_txdma));
1708
1709         /* Empty the receive and transmit rings */
1710
1711         sbdma_emptyring(&(s->sbm_rxdma));
1712         sbdma_emptyring(&(s->sbm_txdma));
1713
1714 }
1715
1716 /**********************************************************************
1717  *  SBMAC_SET_CHANNEL_STATE(state)
1718  *
1719  *  Set the channel's state ON or OFF
1720  *
1721  *  Input parameters:
1722  *         state - new state
1723  *
1724  *  Return value:
1725  *         old state
1726  ********************************************************************* */
1727 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1728                                              sbmac_state_t state)
1729 {
1730         sbmac_state_t oldstate = sc->sbm_state;
1731
1732         /*
1733          * If same as previous state, return
1734          */
1735
1736         if (state == oldstate) {
1737                 return oldstate;
1738         }
1739
1740         /*
1741          * If new state is ON, turn channel on
1742          */
1743
1744         if (state == sbmac_state_on) {
1745                 sbmac_channel_start(sc);
1746         }
1747         else {
1748                 sbmac_channel_stop(sc);
1749         }
1750
1751         /*
1752          * Return previous state
1753          */
1754
1755         return oldstate;
1756 }
1757
1758
1759 /**********************************************************************
1760  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1761  *
1762  *  Turn on or off promiscuous mode
1763  *
1764  *  Input parameters:
1765  *         sc - softc
1766  *      onoff - 1 to turn on, 0 to turn off
1767  *
1768  *  Return value:
1769  *         nothing
1770  ********************************************************************* */
1771
1772 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1773 {
1774         uint64_t reg;
1775
1776         if (sc->sbm_state != sbmac_state_on)
1777                 return;
1778
1779         if (onoff) {
1780                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1781                 reg |= M_MAC_ALLPKT_EN;
1782                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1783         }
1784         else {
1785                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1786                 reg &= ~M_MAC_ALLPKT_EN;
1787                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1788         }
1789 }
1790
1791 /**********************************************************************
1792  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1793  *
1794  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1795  *
1796  *  Input parameters:
1797  *         sc - softc
1798  *
1799  *  Return value:
1800  *         nothing
1801  ********************************************************************* */
1802
1803 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1804 {
1805         uint64_t reg;
1806
1807         /* Hard code the off set to 15 for now */
1808         reg = SBMAC_READCSR(sc->sbm_rxfilter);
1809         reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1810         SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1811
1812         /* read system identification to determine revision */
1813         if (periph_rev >= 2) {
1814                 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
1815                        sc->sbm_dev->name);
1816                 sc->rx_hw_checksum = ENABLE;
1817         } else {
1818                 sc->rx_hw_checksum = DISABLE;
1819         }
1820 }
1821
1822
1823 /**********************************************************************
1824  *  SBMAC_ADDR2REG(ptr)
1825  *
1826  *  Convert six bytes into the 64-bit register value that
1827  *  we typically write into the SBMAC's address/mcast registers
1828  *
1829  *  Input parameters:
1830  *         ptr - pointer to 6 bytes
1831  *
1832  *  Return value:
1833  *         register value
1834  ********************************************************************* */
1835
1836 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1837 {
1838         uint64_t reg = 0;
1839
1840         ptr += 6;
1841
1842         reg |= (uint64_t) *(--ptr);
1843         reg <<= 8;
1844         reg |= (uint64_t) *(--ptr);
1845         reg <<= 8;
1846         reg |= (uint64_t) *(--ptr);
1847         reg <<= 8;
1848         reg |= (uint64_t) *(--ptr);
1849         reg <<= 8;
1850         reg |= (uint64_t) *(--ptr);
1851         reg <<= 8;
1852         reg |= (uint64_t) *(--ptr);
1853
1854         return reg;
1855 }
1856
1857
1858 /**********************************************************************
1859  *  SBMAC_SET_SPEED(s,speed)
1860  *
1861  *  Configure LAN speed for the specified MAC.
1862  *  Warning: must be called when MAC is off!
1863  *
1864  *  Input parameters:
1865  *         s - sbmac structure
1866  *         speed - speed to set MAC to (see sbmac_speed_t enum)
1867  *
1868  *  Return value:
1869  *         1 if successful
1870  *      0 indicates invalid parameters
1871  ********************************************************************* */
1872
1873 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1874 {
1875         uint64_t cfg;
1876         uint64_t framecfg;
1877
1878         /*
1879          * Save new current values
1880          */
1881
1882         s->sbm_speed = speed;
1883
1884         if (s->sbm_state == sbmac_state_on)
1885                 return 0;       /* save for next restart */
1886
1887         /*
1888          * Read current register values
1889          */
1890
1891         cfg = SBMAC_READCSR(s->sbm_maccfg);
1892         framecfg = SBMAC_READCSR(s->sbm_framecfg);
1893
1894         /*
1895          * Mask out the stuff we want to change
1896          */
1897
1898         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1899         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1900                       M_MAC_SLOT_SIZE);
1901
1902         /*
1903          * Now add in the new bits
1904          */
1905
1906         switch (speed) {
1907         case sbmac_speed_10:
1908                 framecfg |= V_MAC_IFG_RX_10 |
1909                         V_MAC_IFG_TX_10 |
1910                         K_MAC_IFG_THRSH_10 |
1911                         V_MAC_SLOT_SIZE_10;
1912                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1913                 break;
1914
1915         case sbmac_speed_100:
1916                 framecfg |= V_MAC_IFG_RX_100 |
1917                         V_MAC_IFG_TX_100 |
1918                         V_MAC_IFG_THRSH_100 |
1919                         V_MAC_SLOT_SIZE_100;
1920                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1921                 break;
1922
1923         case sbmac_speed_1000:
1924                 framecfg |= V_MAC_IFG_RX_1000 |
1925                         V_MAC_IFG_TX_1000 |
1926                         V_MAC_IFG_THRSH_1000 |
1927                         V_MAC_SLOT_SIZE_1000;
1928                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1929                 break;
1930
1931         case sbmac_speed_auto:          /* XXX not implemented */
1932                 /* fall through */
1933         default:
1934                 return 0;
1935         }
1936
1937         /*
1938          * Send the bits back to the hardware
1939          */
1940
1941         SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1942         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1943
1944         return 1;
1945 }
1946
1947 /**********************************************************************
1948  *  SBMAC_SET_DUPLEX(s,duplex,fc)
1949  *
1950  *  Set Ethernet duplex and flow control options for this MAC
1951  *  Warning: must be called when MAC is off!
1952  *
1953  *  Input parameters:
1954  *         s - sbmac structure
1955  *         duplex - duplex setting (see sbmac_duplex_t)
1956  *         fc - flow control setting (see sbmac_fc_t)
1957  *
1958  *  Return value:
1959  *         1 if ok
1960  *         0 if an invalid parameter combination was specified
1961  ********************************************************************* */
1962
1963 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1964 {
1965         uint64_t cfg;
1966
1967         /*
1968          * Save new current values
1969          */
1970
1971         s->sbm_duplex = duplex;
1972         s->sbm_fc = fc;
1973
1974         if (s->sbm_state == sbmac_state_on)
1975                 return 0;       /* save for next restart */
1976
1977         /*
1978          * Read current register values
1979          */
1980
1981         cfg = SBMAC_READCSR(s->sbm_maccfg);
1982
1983         /*
1984          * Mask off the stuff we're about to change
1985          */
1986
1987         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1988
1989
1990         switch (duplex) {
1991         case sbmac_duplex_half:
1992                 switch (fc) {
1993                 case sbmac_fc_disabled:
1994                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1995                         break;
1996
1997                 case sbmac_fc_collision:
1998                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1999                         break;
2000
2001                 case sbmac_fc_carrier:
2002                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2003                         break;
2004
2005                 case sbmac_fc_auto:             /* XXX not implemented */
2006                         /* fall through */
2007                 case sbmac_fc_frame:            /* not valid in half duplex */
2008                 default:                        /* invalid selection */
2009                         return 0;
2010                 }
2011                 break;
2012
2013         case sbmac_duplex_full:
2014                 switch (fc) {
2015                 case sbmac_fc_disabled:
2016                         cfg |= V_MAC_FC_CMD_DISABLED;
2017                         break;
2018
2019                 case sbmac_fc_frame:
2020                         cfg |= V_MAC_FC_CMD_ENABLED;
2021                         break;
2022
2023                 case sbmac_fc_collision:        /* not valid in full duplex */
2024                 case sbmac_fc_carrier:          /* not valid in full duplex */
2025                 case sbmac_fc_auto:             /* XXX not implemented */
2026                         /* fall through */
2027                 default:
2028                         return 0;
2029                 }
2030                 break;
2031         case sbmac_duplex_auto:
2032                 /* XXX not implemented */
2033                 break;
2034         }
2035
2036         /*
2037          * Send the bits back to the hardware
2038          */
2039
2040         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
2041
2042         return 1;
2043 }
2044
2045
2046
2047
2048 /**********************************************************************
2049  *  SBMAC_INTR()
2050  *
2051  *  Interrupt handler for MAC interrupts
2052  *
2053  *  Input parameters:
2054  *         MAC structure
2055  *
2056  *  Return value:
2057  *         nothing
2058  ********************************************************************* */
2059 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2060 {
2061         struct net_device *dev = (struct net_device *) dev_instance;
2062         struct sbmac_softc *sc = netdev_priv(dev);
2063         uint64_t isr;
2064         int handled = 0;
2065
2066         for (;;) {
2067
2068                 /*
2069                  * Read the ISR (this clears the bits in the real
2070                  * register, except for counter addr)
2071                  */
2072
2073                 isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2074
2075                 if (isr == 0)
2076                         break;
2077
2078                 handled = 1;
2079
2080                 /*
2081                  * Transmits on channel 0
2082                  */
2083
2084                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2085                         sbdma_tx_process(sc,&(sc->sbm_txdma));
2086                 }
2087
2088                 /*
2089                  * Receives on channel 0
2090                  */
2091
2092                 /*
2093                  * It's important to test all the bits (or at least the
2094                  * EOP_SEEN bit) when deciding to do the RX process
2095                  * particularly when coalescing, to make sure we
2096                  * take care of the following:
2097                  *
2098                  * If you have some packets waiting (have been received
2099                  * but no interrupt) and get a TX interrupt before
2100                  * the RX timer or counter expires, reading the ISR
2101                  * above will clear the timer and counter, and you
2102                  * won't get another interrupt until a packet shows
2103                  * up to start the timer again.  Testing
2104                  * EOP_SEEN here takes care of this case.
2105                  * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2106                  */
2107
2108
2109                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2110                         sbdma_rx_process(sc,&(sc->sbm_rxdma));
2111                 }
2112         }
2113         return IRQ_RETVAL(handled);
2114 }
2115
2116
2117 /**********************************************************************
2118  *  SBMAC_START_TX(skb,dev)
2119  *
2120  *  Start output on the specified interface.  Basically, we
2121  *  queue as many buffers as we can until the ring fills up, or
2122  *  we run off the end of the queue, whichever comes first.
2123  *
2124  *  Input parameters:
2125  *
2126  *
2127  *  Return value:
2128  *         nothing
2129  ********************************************************************* */
2130 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2131 {
2132         struct sbmac_softc *sc = netdev_priv(dev);
2133
2134         /* lock eth irq */
2135         spin_lock_irq (&sc->sbm_lock);
2136
2137         /*
2138          * Put the buffer on the transmit ring.  If we
2139          * don't have room, stop the queue.
2140          */
2141
2142         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2143                 /* XXX save skb that we could not send */
2144                 netif_stop_queue(dev);
2145                 spin_unlock_irq(&sc->sbm_lock);
2146
2147                 return 1;
2148         }
2149
2150         dev->trans_start = jiffies;
2151
2152         spin_unlock_irq (&sc->sbm_lock);
2153
2154         return 0;
2155 }
2156
2157 /**********************************************************************
2158  *  SBMAC_SETMULTI(sc)
2159  *
2160  *  Reprogram the multicast table into the hardware, given
2161  *  the list of multicasts associated with the interface
2162  *  structure.
2163  *
2164  *  Input parameters:
2165  *         sc - softc
2166  *
2167  *  Return value:
2168  *         nothing
2169  ********************************************************************* */
2170
2171 static void sbmac_setmulti(struct sbmac_softc *sc)
2172 {
2173         uint64_t reg;
2174         sbmac_port_t port;
2175         int idx;
2176         struct dev_mc_list *mclist;
2177         struct net_device *dev = sc->sbm_dev;
2178
2179         /*
2180          * Clear out entire multicast table.  We do this by nuking
2181          * the entire hash table and all the direct matches except
2182          * the first one, which is used for our station address
2183          */
2184
2185         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2186                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2187                 SBMAC_WRITECSR(port,0);
2188         }
2189
2190         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2191                 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2192                 SBMAC_WRITECSR(port,0);
2193         }
2194
2195         /*
2196          * Clear the filter to say we don't want any multicasts.
2197          */
2198
2199         reg = SBMAC_READCSR(sc->sbm_rxfilter);
2200         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2201         SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2202
2203         if (dev->flags & IFF_ALLMULTI) {
2204                 /*
2205                  * Enable ALL multicasts.  Do this by inverting the
2206                  * multicast enable bit.
2207                  */
2208                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2209                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2210                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2211                 return;
2212         }
2213
2214
2215         /*
2216          * Progam new multicast entries.  For now, only use the
2217          * perfect filter.  In the future we'll need to use the
2218          * hash filter if the perfect filter overflows
2219          */
2220
2221         /* XXX only using perfect filter for now, need to use hash
2222          * XXX if the table overflows */
2223
2224         idx = 1;                /* skip station address */
2225         mclist = dev->mc_list;
2226         while (mclist && (idx < MAC_ADDR_COUNT)) {
2227                 reg = sbmac_addr2reg(mclist->dmi_addr);
2228                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2229                 SBMAC_WRITECSR(port,reg);
2230                 idx++;
2231                 mclist = mclist->next;
2232         }
2233
2234         /*
2235          * Enable the "accept multicast bits" if we programmed at least one
2236          * multicast.
2237          */
2238
2239         if (idx > 1) {
2240                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2241                 reg |= M_MAC_MCAST_EN;
2242                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2243         }
2244 }
2245
2246
2247
2248 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2249 /**********************************************************************
2250  *  SBMAC_PARSE_XDIGIT(str)
2251  *
2252  *  Parse a hex digit, returning its value
2253  *
2254  *  Input parameters:
2255  *         str - character
2256  *
2257  *  Return value:
2258  *         hex value, or -1 if invalid
2259  ********************************************************************* */
2260
2261 static int sbmac_parse_xdigit(char str)
2262 {
2263         int digit;
2264
2265         if ((str >= '0') && (str <= '9'))
2266                 digit = str - '0';
2267         else if ((str >= 'a') && (str <= 'f'))
2268                 digit = str - 'a' + 10;
2269         else if ((str >= 'A') && (str <= 'F'))
2270                 digit = str - 'A' + 10;
2271         else
2272                 return -1;
2273
2274         return digit;
2275 }
2276
2277 /**********************************************************************
2278  *  SBMAC_PARSE_HWADDR(str,hwaddr)
2279  *
2280  *  Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2281  *  Ethernet address.
2282  *
2283  *  Input parameters:
2284  *         str - string
2285  *         hwaddr - pointer to hardware address
2286  *
2287  *  Return value:
2288  *         0 if ok, else -1
2289  ********************************************************************* */
2290
2291 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2292 {
2293         int digit1,digit2;
2294         int idx = 6;
2295
2296         while (*str && (idx > 0)) {
2297                 digit1 = sbmac_parse_xdigit(*str);
2298                 if (digit1 < 0)
2299                         return -1;
2300                 str++;
2301                 if (!*str)
2302                         return -1;
2303
2304                 if ((*str == ':') || (*str == '-')) {
2305                         digit2 = digit1;
2306                         digit1 = 0;
2307                 }
2308                 else {
2309                         digit2 = sbmac_parse_xdigit(*str);
2310                         if (digit2 < 0)
2311                                 return -1;
2312                         str++;
2313                 }
2314
2315                 *hwaddr++ = (digit1 << 4) | digit2;
2316                 idx--;
2317
2318                 if (*str == '-')
2319                         str++;
2320                 if (*str == ':')
2321                         str++;
2322         }
2323         return 0;
2324 }
2325 #endif
2326
2327 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2328 {
2329         if (new_mtu >  ENET_PACKET_SIZE)
2330                 return -EINVAL;
2331         _dev->mtu = new_mtu;
2332         printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2333         return 0;
2334 }
2335
2336 /**********************************************************************
2337  *  SBMAC_INIT(dev)
2338  *
2339  *  Attach routine - init hardware and hook ourselves into linux
2340  *
2341  *  Input parameters:
2342  *         dev - net_device structure
2343  *
2344  *  Return value:
2345  *         status
2346  ********************************************************************* */
2347
2348 static int sbmac_init(struct net_device *dev, int idx)
2349 {
2350         struct sbmac_softc *sc;
2351         unsigned char *eaddr;
2352         uint64_t ea_reg;
2353         int i;
2354         int err;
2355
2356         sc = netdev_priv(dev);
2357
2358         /* Determine controller base address */
2359
2360         sc->sbm_base = IOADDR(dev->base_addr);
2361         sc->sbm_dev = dev;
2362         sc->sbe_idx = idx;
2363
2364         eaddr = sc->sbm_hwaddr;
2365
2366         /*
2367          * Read the ethernet address.  The firwmare left this programmed
2368          * for us in the ethernet address register for each mac.
2369          */
2370
2371         ea_reg = SBMAC_READCSR(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2372         SBMAC_WRITECSR(sc->sbm_base + R_MAC_ETHERNET_ADDR, 0);
2373         for (i = 0; i < 6; i++) {
2374                 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2375                 ea_reg >>= 8;
2376         }
2377
2378         for (i = 0; i < 6; i++) {
2379                 dev->dev_addr[i] = eaddr[i];
2380         }
2381
2382
2383         /*
2384          * Init packet size
2385          */
2386
2387         sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2388
2389         /*
2390          * Initialize context (get pointers to registers and stuff), then
2391          * allocate the memory for the descriptor tables.
2392          */
2393
2394         sbmac_initctx(sc);
2395
2396         /*
2397          * Set up Linux device callins
2398          */
2399
2400         spin_lock_init(&(sc->sbm_lock));
2401
2402         dev->open               = sbmac_open;
2403         dev->hard_start_xmit    = sbmac_start_tx;
2404         dev->stop               = sbmac_close;
2405         dev->get_stats          = sbmac_get_stats;
2406         dev->set_multicast_list = sbmac_set_rx_mode;
2407         dev->do_ioctl           = sbmac_mii_ioctl;
2408         dev->tx_timeout         = sbmac_tx_timeout;
2409         dev->watchdog_timeo     = TX_TIMEOUT;
2410
2411         dev->change_mtu         = sb1250_change_mtu;
2412
2413         /* This is needed for PASS2 for Rx H/W checksum feature */
2414         sbmac_set_iphdr_offset(sc);
2415
2416         err = register_netdev(dev);
2417         if (err)
2418                 goto out_uninit;
2419
2420         /*
2421          * Display Ethernet address (this is called during the config
2422          * process so we need to finish off the config message that
2423          * was being displayed)
2424          */
2425         printk(KERN_INFO
2426                "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2427                dev->name, dev->base_addr,
2428                eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2429
2430
2431         return 0;
2432
2433 out_uninit:
2434         sbmac_uninitctx(sc);
2435
2436         return err;
2437 }
2438
2439
2440 static int sbmac_open(struct net_device *dev)
2441 {
2442         struct sbmac_softc *sc = netdev_priv(dev);
2443
2444         if (debug > 1) {
2445                 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2446         }
2447
2448         /*
2449          * map/route interrupt (clear status first, in case something
2450          * weird is pending; we haven't initialized the mac registers
2451          * yet)
2452          */
2453
2454         SBMAC_READCSR(sc->sbm_isr);
2455         if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev))
2456                 return -EBUSY;
2457
2458         /*
2459          * Configure default speed
2460          */
2461
2462         sbmac_mii_poll(sc,noisy_mii);
2463
2464         /*
2465          * Turn on the channel
2466          */
2467
2468         sbmac_set_channel_state(sc,sbmac_state_on);
2469
2470         /*
2471          * XXX Station address is in dev->dev_addr
2472          */
2473
2474         if (dev->if_port == 0)
2475                 dev->if_port = 0;
2476
2477         netif_start_queue(dev);
2478
2479         sbmac_set_rx_mode(dev);
2480
2481         /* Set the timer to check for link beat. */
2482         init_timer(&sc->sbm_timer);
2483         sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2484         sc->sbm_timer.data = (unsigned long)dev;
2485         sc->sbm_timer.function = &sbmac_timer;
2486         add_timer(&sc->sbm_timer);
2487
2488         return 0;
2489 }
2490
2491
2492
2493 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2494 {
2495     int bmsr,bmcr,k1stsr,anlpar;
2496     int chg;
2497     char buffer[100];
2498     char *p = buffer;
2499
2500     /* Read the mode status and mode control registers. */
2501     bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2502     bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2503
2504     /* get the link partner status */
2505     anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2506
2507     /* if supported, read the 1000baseT register */
2508     if (bmsr & BMSR_1000BT_XSR) {
2509         k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2510         }
2511     else {
2512         k1stsr = 0;
2513         }
2514
2515     chg = 0;
2516
2517     if ((bmsr & BMSR_LINKSTAT) == 0) {
2518         /*
2519          * If link status is down, clear out old info so that when
2520          * it comes back up it will force us to reconfigure speed
2521          */
2522         s->sbm_phy_oldbmsr = 0;
2523         s->sbm_phy_oldanlpar = 0;
2524         s->sbm_phy_oldk1stsr = 0;
2525         return 0;
2526         }
2527
2528     if ((s->sbm_phy_oldbmsr != bmsr) ||
2529         (s->sbm_phy_oldanlpar != anlpar) ||
2530         (s->sbm_phy_oldk1stsr != k1stsr)) {
2531         if (debug > 1) {
2532             printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x  k1stsr:%x/%x\n",
2533                s->sbm_dev->name,
2534                s->sbm_phy_oldbmsr,bmsr,
2535                s->sbm_phy_oldanlpar,anlpar,
2536                s->sbm_phy_oldk1stsr,k1stsr);
2537             }
2538         s->sbm_phy_oldbmsr = bmsr;
2539         s->sbm_phy_oldanlpar = anlpar;
2540         s->sbm_phy_oldk1stsr = k1stsr;
2541         chg = 1;
2542         }
2543
2544     if (chg == 0)
2545             return 0;
2546
2547     p += sprintf(p,"Link speed: ");
2548
2549     if (k1stsr & K1STSR_LP1KFD) {
2550         s->sbm_speed = sbmac_speed_1000;
2551         s->sbm_duplex = sbmac_duplex_full;
2552         s->sbm_fc = sbmac_fc_frame;
2553         p += sprintf(p,"1000BaseT FDX");
2554         }
2555     else if (k1stsr & K1STSR_LP1KHD) {
2556         s->sbm_speed = sbmac_speed_1000;
2557         s->sbm_duplex = sbmac_duplex_half;
2558         s->sbm_fc = sbmac_fc_disabled;
2559         p += sprintf(p,"1000BaseT HDX");
2560         }
2561     else if (anlpar & ANLPAR_TXFD) {
2562         s->sbm_speed = sbmac_speed_100;
2563         s->sbm_duplex = sbmac_duplex_full;
2564         s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2565         p += sprintf(p,"100BaseT FDX");
2566         }
2567     else if (anlpar & ANLPAR_TXHD) {
2568         s->sbm_speed = sbmac_speed_100;
2569         s->sbm_duplex = sbmac_duplex_half;
2570         s->sbm_fc = sbmac_fc_disabled;
2571         p += sprintf(p,"100BaseT HDX");
2572         }
2573     else if (anlpar & ANLPAR_10FD) {
2574         s->sbm_speed = sbmac_speed_10;
2575         s->sbm_duplex = sbmac_duplex_full;
2576         s->sbm_fc = sbmac_fc_frame;
2577         p += sprintf(p,"10BaseT FDX");
2578         }
2579     else if (anlpar & ANLPAR_10HD) {
2580         s->sbm_speed = sbmac_speed_10;
2581         s->sbm_duplex = sbmac_duplex_half;
2582         s->sbm_fc = sbmac_fc_collision;
2583         p += sprintf(p,"10BaseT HDX");
2584         }
2585     else {
2586         p += sprintf(p,"Unknown");
2587         }
2588
2589     if (noisy) {
2590             printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2591             }
2592
2593     return 1;
2594 }
2595
2596
2597 static void sbmac_timer(unsigned long data)
2598 {
2599         struct net_device *dev = (struct net_device *)data;
2600         struct sbmac_softc *sc = netdev_priv(dev);
2601         int next_tick = HZ;
2602         int mii_status;
2603
2604         spin_lock_irq (&sc->sbm_lock);
2605
2606         /* make IFF_RUNNING follow the MII status bit "Link established" */
2607         mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2608
2609         if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2610                 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2611                 if (mii_status & BMSR_LINKSTAT) {
2612                         netif_carrier_on(dev);
2613                 }
2614                 else {
2615                         netif_carrier_off(dev);
2616                 }
2617         }
2618
2619         /*
2620          * Poll the PHY to see what speed we should be running at
2621          */
2622
2623         if (sbmac_mii_poll(sc,noisy_mii)) {
2624                 if (sc->sbm_state != sbmac_state_off) {
2625                         /*
2626                          * something changed, restart the channel
2627                          */
2628                         if (debug > 1) {
2629                                 printk("%s: restarting channel because speed changed\n",
2630                                        sc->sbm_dev->name);
2631                         }
2632                         sbmac_channel_stop(sc);
2633                         sbmac_channel_start(sc);
2634                 }
2635         }
2636
2637         spin_unlock_irq (&sc->sbm_lock);
2638
2639         sc->sbm_timer.expires = jiffies + next_tick;
2640         add_timer(&sc->sbm_timer);
2641 }
2642
2643
2644 static void sbmac_tx_timeout (struct net_device *dev)
2645 {
2646         struct sbmac_softc *sc = netdev_priv(dev);
2647
2648         spin_lock_irq (&sc->sbm_lock);
2649
2650
2651         dev->trans_start = jiffies;
2652         sc->sbm_stats.tx_errors++;
2653
2654         spin_unlock_irq (&sc->sbm_lock);
2655
2656         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2657 }
2658
2659
2660
2661
2662 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2663 {
2664         struct sbmac_softc *sc = netdev_priv(dev);
2665         unsigned long flags;
2666
2667         spin_lock_irqsave(&sc->sbm_lock, flags);
2668
2669         /* XXX update other stats here */
2670
2671         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2672
2673         return &sc->sbm_stats;
2674 }
2675
2676
2677
2678 static void sbmac_set_rx_mode(struct net_device *dev)
2679 {
2680         unsigned long flags;
2681         int msg_flag = 0;
2682         struct sbmac_softc *sc = netdev_priv(dev);
2683
2684         spin_lock_irqsave(&sc->sbm_lock, flags);
2685         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2686                 /*
2687                  * Promiscuous changed.
2688                  */
2689
2690                 if (dev->flags & IFF_PROMISC) {
2691                         /* Unconditionally log net taps. */
2692                         msg_flag = 1;
2693                         sbmac_promiscuous_mode(sc,1);
2694                 }
2695                 else {
2696                         msg_flag = 2;
2697                         sbmac_promiscuous_mode(sc,0);
2698                 }
2699         }
2700         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2701
2702         if (msg_flag) {
2703                 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n",
2704                        dev->name,(msg_flag==1)?"en":"dis");
2705         }
2706
2707         /*
2708          * Program the multicasts.  Do this every time.
2709          */
2710
2711         sbmac_setmulti(sc);
2712
2713 }
2714
2715 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2716 {
2717         struct sbmac_softc *sc = netdev_priv(dev);
2718         u16 *data = (u16 *)&rq->ifr_ifru;
2719         unsigned long flags;
2720         int retval;
2721
2722         spin_lock_irqsave(&sc->sbm_lock, flags);
2723         retval = 0;
2724
2725         switch(cmd) {
2726         case SIOCDEVPRIVATE:            /* Get the address of the PHY in use. */
2727                 data[0] = sc->sbm_phys[0] & 0x1f;
2728                 /* Fall Through */
2729         case SIOCDEVPRIVATE+1:          /* Read the specified MII register. */
2730                 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2731                 break;
2732         case SIOCDEVPRIVATE+2:          /* Write the specified MII register */
2733                 if (!capable(CAP_NET_ADMIN)) {
2734                         retval = -EPERM;
2735                         break;
2736                 }
2737                 if (debug > 1) {
2738                     printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2739                        data[0],data[1],data[2]);
2740                     }
2741                 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2742                 break;
2743         default:
2744                 retval = -EOPNOTSUPP;
2745         }
2746
2747         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2748         return retval;
2749 }
2750
2751 static int sbmac_close(struct net_device *dev)
2752 {
2753         struct sbmac_softc *sc = netdev_priv(dev);
2754         unsigned long flags;
2755         int irq;
2756
2757         sbmac_set_channel_state(sc,sbmac_state_off);
2758
2759         del_timer_sync(&sc->sbm_timer);
2760
2761         spin_lock_irqsave(&sc->sbm_lock, flags);
2762
2763         netif_stop_queue(dev);
2764
2765         if (debug > 1) {
2766                 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2767         }
2768
2769         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2770
2771         irq = dev->irq;
2772         synchronize_irq(irq);
2773         free_irq(irq, dev);
2774
2775         sbdma_emptyring(&(sc->sbm_txdma));
2776         sbdma_emptyring(&(sc->sbm_rxdma));
2777
2778         return 0;
2779 }
2780
2781
2782
2783 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2784 static void
2785 sbmac_setup_hwaddr(int chan,char *addr)
2786 {
2787         uint8_t eaddr[6];
2788         uint64_t val;
2789         sbmac_port_t port;
2790
2791         port = A_MAC_CHANNEL_BASE(chan);
2792         sbmac_parse_hwaddr(addr,eaddr);
2793         val = sbmac_addr2reg(eaddr);
2794         SBMAC_WRITECSR(IOADDR(port+R_MAC_ETHERNET_ADDR),val);
2795         val = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR));
2796 }
2797 #endif
2798
2799 static struct net_device *dev_sbmac[MAX_UNITS];
2800
2801 static int __init
2802 sbmac_init_module(void)
2803 {
2804         int idx;
2805         struct net_device *dev;
2806         sbmac_port_t port;
2807         int chip_max_units;
2808
2809         /*
2810          * For bringup when not using the firmware, we can pre-fill
2811          * the MAC addresses using the environment variables
2812          * specified in this file (or maybe from the config file?)
2813          */
2814 #ifdef SBMAC_ETH0_HWADDR
2815         sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2816 #endif
2817 #ifdef SBMAC_ETH1_HWADDR
2818         sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2819 #endif
2820 #ifdef SBMAC_ETH2_HWADDR
2821         sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2822 #endif
2823
2824         /*
2825          * Walk through the Ethernet controllers and find
2826          * those who have their MAC addresses set.
2827          */
2828         switch (soc_type) {
2829         case K_SYS_SOC_TYPE_BCM1250:
2830         case K_SYS_SOC_TYPE_BCM1250_ALT:
2831                 chip_max_units = 3;
2832                 break;
2833         case K_SYS_SOC_TYPE_BCM1120:
2834         case K_SYS_SOC_TYPE_BCM1125:
2835         case K_SYS_SOC_TYPE_BCM1125H:
2836         case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2837                 chip_max_units = 2;
2838                 break;
2839         default:
2840                 chip_max_units = 0;
2841                 break;
2842         }
2843         if (chip_max_units > MAX_UNITS)
2844                 chip_max_units = MAX_UNITS;
2845
2846         for (idx = 0; idx < chip_max_units; idx++) {
2847
2848                 /*
2849                  * This is the base address of the MAC.
2850                  */
2851
2852                 port = A_MAC_CHANNEL_BASE(idx);
2853
2854                 /*
2855                  * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2856                  * value for us by the firmware if we're going to use this MAC.
2857                  * If we find a zero, skip this MAC.
2858                  */
2859
2860                 sbmac_orig_hwaddr[idx] = SBMAC_READCSR(IOADDR(port+R_MAC_ETHERNET_ADDR));
2861                 if (sbmac_orig_hwaddr[idx] == 0) {
2862                         printk(KERN_DEBUG "sbmac: not configuring MAC at "
2863                                "%lx\n", port);
2864                     continue;
2865                 }
2866
2867                 /*
2868                  * Okay, cool.  Initialize this MAC.
2869                  */
2870
2871                 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2872                 if (!dev)
2873                         return -ENOMEM; /* return ENOMEM */
2874
2875                 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2876
2877                 dev->irq = K_INT_MAC_0 + idx;
2878                 dev->base_addr = port;
2879                 dev->mem_end = 0;
2880                 if (sbmac_init(dev, idx)) {
2881                         port = A_MAC_CHANNEL_BASE(idx);
2882                         SBMAC_WRITECSR(KSEG1ADDR(port+R_MAC_ETHERNET_ADDR),
2883                                         sbmac_orig_hwaddr[idx] );
2884                         free_netdev(dev);
2885                         continue;
2886                 }
2887                 dev_sbmac[idx++] = dev;
2888         }
2889         return 0;
2890 }
2891
2892
2893 static void __exit
2894 sbmac_cleanup_module(void)
2895 {
2896         struct net_device *dev;
2897         int idx;
2898
2899         for (idx = 0; idx < MAX_UNITS; idx++) {
2900                 struct sbmac_softc *sc;
2901                 dev = dev_sbmac[idx];
2902                 if (!dev)
2903                         continue;
2904
2905                 sc = netdev_priv(dev);
2906                 unregister_netdev(dev);
2907                 sbmac_uninitctx(sc);
2908                 free_netdev(dev);
2909         }
2910 }
2911
2912 module_init(sbmac_init_module);
2913 module_exit(sbmac_cleanup_module);