drivers/net/sb1250-mac.c

   1 /*
   2  * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  *
  18  *
  19  * This driver is designed for the Broadcom SiByte SOC built-in
  20  * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp.
  21  */
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/string.h>
  25 #include <linux/timer.h>
  26 #include <linux/errno.h>
  27 #include <linux/ioport.h>
  28 #include <linux/slab.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/init.h>
  34 #include <linux/config.h>
  35 #include <linux/bitops.h>
  36 #include <asm/processor.h>              /* Processor type for cache alignment. */
  37 #include <asm/io.h>
  38 #include <asm/cache.h>
  39
  40 /* This is only here until the firmware is ready.  In that case,
  41    the firmware leaves the ethernet address in the register for us. */
  42 #ifdef CONFIG_SIBYTE_STANDALONE
  43 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
  44 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
  45 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
  46 #define SBMAC_ETH3_HWADDR "40:00:00:00:01:03"
  47 #endif
  48
  49
  50 /* These identify the driver base version and may not be removed. */
  51 #if 0
  52 static char version1[] __devinitdata =
  53 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg\n";
  54 #endif
  55
  56
  57 /* Operational parameters that usually are not changed. */
  58
  59 #define CONFIG_SBMAC_COALESCE
  60
  61 #define MAX_UNITS 4             /* More are supported, limit only on options */
  62
  63 /* Time in jiffies before concluding the transmitter is hung. */
  64 #define TX_TIMEOUT  (2*HZ)
  65
  66
  67 MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)");
  68 MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver");
  69
  70 /* A few user-configurable values which may be modified when a driver
  71    module is loaded. */
  72
  73 /* 1 normal messages, 0 quiet .. 7 verbose. */
  74 static int debug = 1;
  75 module_param(debug, int, S_IRUGO);
  76 MODULE_PARM_DESC(debug, "Debug messages");
  77
  78 /* mii status msgs */
  79 static int noisy_mii = 1;
  80 module_param(noisy_mii, int, S_IRUGO);
  81 MODULE_PARM_DESC(noisy_mii, "MII status messages");
  82
  83 /* Used to pass the media type, etc.
  84    Both 'options[]' and 'full_duplex[]' should exist for driver
  85    interoperability.
  86    The media type is usually passed in 'options[]'.
  87 */
  88 #ifdef MODULE
  89 static int options[MAX_UNITS] = {-1, -1, -1, -1};
  90 module_param_array(options, int, NULL, S_IRUGO);
  91 MODULE_PARM_DESC(options, "1-" __MODULE_STRING(MAX_UNITS));
  92
  93 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1};
  94 module_param_array(full_duplex, int, NULL, S_IRUGO);
  95 MODULE_PARM_DESC(full_duplex, "1-" __MODULE_STRING(MAX_UNITS));
  96 #endif
  97
  98 #ifdef CONFIG_SBMAC_COALESCE
  99 static int int_pktcnt = 0;
 100 module_param(int_pktcnt, int, S_IRUGO);
 101 MODULE_PARM_DESC(int_pktcnt, "Packet count");
 102
 103 static int int_timeout = 0;
 104 module_param(int_timeout, int, S_IRUGO);
 105 MODULE_PARM_DESC(int_timeout, "Timeout value");
 106 #endif
 107
 108 #include <asm/sibyte/sb1250.h>
 109 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 110 #include <asm/sibyte/bcm1480_regs.h>
 111 #include <asm/sibyte/bcm1480_int.h>
 112 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
 113 #include <asm/sibyte/sb1250_regs.h>
 114 #include <asm/sibyte/sb1250_int.h>
 115 #else
 116 #error invalid SiByte MAC configuation
 117 #endif
 118 #include <asm/sibyte/sb1250_scd.h>
 119 #include <asm/sibyte/sb1250_mac.h>
 120 #include <asm/sibyte/sb1250_dma.h>
 121
 122 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
 123 #define UNIT_INT(n)             (K_BCM1480_INT_MAC_0 + ((n) * 2))
 124 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
 125 #define UNIT_INT(n)             (K_INT_MAC_0 + (n))
 126 #else
 127 #error invalid SiByte MAC configuation
 128 #endif
 129
 130 /**********************************************************************
 131  *  Simple types
 132  ********************************************************************* */
 133
 134
 135 typedef enum { sbmac_speed_auto, sbmac_speed_10,
 136                sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
 137
 138 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
 139                sbmac_duplex_full } sbmac_duplex_t;
 140
 141 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
 142                sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
 143
 144 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
 145                sbmac_state_broken } sbmac_state_t;
 146
 147
 148 /**********************************************************************
 149  *  Macros
 150  ********************************************************************* */
 151
 152
 153 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
 154                           (d)->sbdma_dscrtable : (d)->f+1)
 155
 156
 157 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
 158
 159 #define SBMAC_MAX_TXDESCR       32
 160 #define SBMAC_MAX_RXDESCR       32
 161
 162 #define ETHER_ALIGN     2
 163 #define ETHER_ADDR_LEN  6
 164 #define ENET_PACKET_SIZE        1518
 165 /*#define ENET_PACKET_SIZE      9216 */
 166
 167 /**********************************************************************
 168  *  DMA Descriptor structure
 169  ********************************************************************* */
 170
 171 typedef struct sbdmadscr_s {
 172         uint64_t  dscr_a;
 173         uint64_t  dscr_b;
 174 } sbdmadscr_t;
 175
 176 typedef unsigned long paddr_t;
 177
 178 /**********************************************************************
 179  *  DMA Controller structure
 180  ********************************************************************* */
 181
 182 typedef struct sbmacdma_s {
 183
 184         /*
 185          * This stuff is used to identify the channel and the registers
 186          * associated with it.
 187          */
 188
 189         struct sbmac_softc *sbdma_eth;          /* back pointer to associated MAC */
 190         int              sbdma_channel; /* channel number */
 191         int              sbdma_txdir;       /* direction (1=transmit) */
 192         int              sbdma_maxdescr;        /* total # of descriptors in ring */
 193 #ifdef CONFIG_SBMAC_COALESCE
 194         int              sbdma_int_pktcnt;  /* # descriptors rx/tx before interrupt*/
 195         int              sbdma_int_timeout; /* # usec rx/tx interrupt */
 196 #endif
 197
 198         volatile void __iomem *sbdma_config0;   /* DMA config register 0 */
 199         volatile void __iomem *sbdma_config1;   /* DMA config register 1 */
 200         volatile void __iomem *sbdma_dscrbase;  /* Descriptor base address */
 201         volatile void __iomem *sbdma_dscrcnt;     /* Descriptor count register */
 202         volatile void __iomem *sbdma_curdscr;   /* current descriptor address */
 203
 204         /*
 205          * This stuff is for maintenance of the ring
 206          */
 207
 208         sbdmadscr_t     *sbdma_dscrtable;       /* base of descriptor table */
 209         sbdmadscr_t     *sbdma_dscrtable_end; /* end of descriptor table */
 210
 211         struct sk_buff **sbdma_ctxtable;    /* context table, one per descr */
 212
 213         paddr_t          sbdma_dscrtable_phys; /* and also the phys addr */
 214         sbdmadscr_t     *sbdma_addptr;  /* next dscr for sw to add */
 215         sbdmadscr_t     *sbdma_remptr;  /* next dscr for sw to remove */
 216 } sbmacdma_t;
 217
 218
 219 /**********************************************************************
 220  *  Ethernet softc structure
 221  ********************************************************************* */
 222
 223 struct sbmac_softc {
 224
 225         /*
 226          * Linux-specific things
 227          */
 228
 229         struct net_device *sbm_dev;             /* pointer to linux device */
 230         spinlock_t sbm_lock;            /* spin lock */
 231         struct timer_list sbm_timer;            /* for monitoring MII */
 232         struct net_device_stats sbm_stats;
 233         int sbm_devflags;                       /* current device flags */
 234
 235         int          sbm_phy_oldbmsr;
 236         int          sbm_phy_oldanlpar;
 237         int          sbm_phy_oldk1stsr;
 238         int          sbm_phy_oldlinkstat;
 239         int sbm_buffersize;
 240
 241         unsigned char sbm_phys[2];
 242
 243         /*
 244          * Controller-specific things
 245          */
 246
 247         volatile void __iomem *sbm_base;          /* MAC's base address */
 248         sbmac_state_t    sbm_state;         /* current state */
 249
 250         volatile void __iomem   *sbm_macenable; /* MAC Enable Register */
 251         volatile void __iomem   *sbm_maccfg;    /* MAC Configuration Register */
 252         volatile void __iomem   *sbm_fifocfg;   /* FIFO configuration register */
 253         volatile void __iomem   *sbm_framecfg;  /* Frame configuration register */
 254         volatile void __iomem   *sbm_rxfilter;  /* receive filter register */
 255         volatile void __iomem   *sbm_isr;       /* Interrupt status register */
 256         volatile void __iomem   *sbm_imr;       /* Interrupt mask register */
 257         volatile void __iomem   *sbm_mdio;      /* MDIO register */
 258
 259         sbmac_speed_t    sbm_speed;             /* current speed */
 260         sbmac_duplex_t   sbm_duplex;    /* current duplex */
 261         sbmac_fc_t       sbm_fc;                /* current flow control setting */
 262
 263         unsigned char    sbm_hwaddr[ETHER_ADDR_LEN];
 264
 265         sbmacdma_t       sbm_txdma;             /* for now, only use channel 0 */
 266         sbmacdma_t       sbm_rxdma;
 267         int              rx_hw_checksum;
 268         int              sbe_idx;
 269 };
 270
 271
 272 /**********************************************************************
 273  *  Externs
 274  ********************************************************************* */
 275
 276 /**********************************************************************
 277  *  Prototypes
 278  ********************************************************************* */
 279
 280 static void sbdma_initctx(sbmacdma_t *d,
 281                           struct sbmac_softc *s,
 282                           int chan,
 283                           int txrx,
 284                           int maxdescr);
 285 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
 286 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
 287 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
 288 static void sbdma_emptyring(sbmacdma_t *d);
 289 static void sbdma_fillring(sbmacdma_t *d);
 290 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 291 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 292 static int sbmac_initctx(struct sbmac_softc *s);
 293 static void sbmac_channel_start(struct sbmac_softc *s);
 294 static void sbmac_channel_stop(struct sbmac_softc *s);
 295 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
 296 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
 297 static uint64_t sbmac_addr2reg(unsigned char *ptr);
 298 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs);
 299 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
 300 static void sbmac_setmulti(struct sbmac_softc *sc);
 301 static int sbmac_init(struct net_device *dev, int idx);
 302 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
 303 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
 304
 305 static int sbmac_open(struct net_device *dev);
 306 static void sbmac_timer(unsigned long data);
 307 static void sbmac_tx_timeout (struct net_device *dev);
 308 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
 309 static void sbmac_set_rx_mode(struct net_device *dev);
 310 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 311 static int sbmac_close(struct net_device *dev);
 312 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
 313 static int sbmac_mii_probe(struct net_device *dev);
 314
 315 static void sbmac_mii_sync(struct sbmac_softc *s);
 316 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
 317 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
 318 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 319                             unsigned int regval);
 320
 321
 322 /**********************************************************************
 323  *  Globals
 324  ********************************************************************* */
 325
 326 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
 327
 328
 329 /**********************************************************************
 330  *  MDIO constants
 331  ********************************************************************* */
 332
 333 #define MII_COMMAND_START       0x01
 334 #define MII_COMMAND_READ        0x02
 335 #define MII_COMMAND_WRITE       0x01
 336 #define MII_COMMAND_ACK         0x02
 337
 338 #define BMCR_RESET     0x8000
 339 #define BMCR_LOOPBACK  0x4000
 340 #define BMCR_SPEED0    0x2000
 341 #define BMCR_ANENABLE  0x1000
 342 #define BMCR_POWERDOWN 0x0800
 343 #define BMCR_ISOLATE   0x0400
 344 #define BMCR_RESTARTAN 0x0200
 345 #define BMCR_DUPLEX    0x0100
 346 #define BMCR_COLTEST   0x0080
 347 #define BMCR_SPEED1    0x0040
 348 #define BMCR_SPEED1000  BMCR_SPEED1
 349 #define BMCR_SPEED100   BMCR_SPEED0
 350 #define BMCR_SPEED10    0
 351
 352 #define BMSR_100BT4     0x8000
 353 #define BMSR_100BT_FDX  0x4000
 354 #define BMSR_100BT_HDX  0x2000
 355 #define BMSR_10BT_FDX   0x1000
 356 #define BMSR_10BT_HDX   0x0800
 357 #define BMSR_100BT2_FDX 0x0400
 358 #define BMSR_100BT2_HDX 0x0200
 359 #define BMSR_1000BT_XSR 0x0100
 360 #define BMSR_PRESUP     0x0040
 361 #define BMSR_ANCOMPLT   0x0020
 362 #define BMSR_REMFAULT   0x0010
 363 #define BMSR_AUTONEG    0x0008
 364 #define BMSR_LINKSTAT   0x0004
 365 #define BMSR_JABDETECT  0x0002
 366 #define BMSR_EXTCAPAB   0x0001
 367
 368 #define PHYIDR1         0x2000
 369 #define PHYIDR2         0x5C60
 370
 371 #define ANAR_NP         0x8000
 372 #define ANAR_RF         0x2000
 373 #define ANAR_ASYPAUSE   0x0800
 374 #define ANAR_PAUSE      0x0400
 375 #define ANAR_T4         0x0200
 376 #define ANAR_TXFD       0x0100
 377 #define ANAR_TXHD       0x0080
 378 #define ANAR_10FD       0x0040
 379 #define ANAR_10HD       0x0020
 380 #define ANAR_PSB        0x0001
 381
 382 #define ANLPAR_NP       0x8000
 383 #define ANLPAR_ACK      0x4000
 384 #define ANLPAR_RF       0x2000
 385 #define ANLPAR_ASYPAUSE 0x0800
 386 #define ANLPAR_PAUSE    0x0400
 387 #define ANLPAR_T4       0x0200
 388 #define ANLPAR_TXFD     0x0100
 389 #define ANLPAR_TXHD     0x0080
 390 #define ANLPAR_10FD     0x0040
 391 #define ANLPAR_10HD     0x0020
 392 #define ANLPAR_PSB      0x0001  /* 802.3 */
 393
 394 #define ANER_PDF        0x0010
 395 #define ANER_LPNPABLE   0x0008
 396 #define ANER_NPABLE     0x0004
 397 #define ANER_PAGERX     0x0002
 398 #define ANER_LPANABLE   0x0001
 399
 400 #define ANNPTR_NP       0x8000
 401 #define ANNPTR_MP       0x2000
 402 #define ANNPTR_ACK2     0x1000
 403 #define ANNPTR_TOGTX    0x0800
 404 #define ANNPTR_CODE     0x0008
 405
 406 #define ANNPRR_NP       0x8000
 407 #define ANNPRR_MP       0x2000
 408 #define ANNPRR_ACK3     0x1000
 409 #define ANNPRR_TOGTX    0x0800
 410 #define ANNPRR_CODE     0x0008
 411
 412 #define K1TCR_TESTMODE  0x0000
 413 #define K1TCR_MSMCE     0x1000
 414 #define K1TCR_MSCV      0x0800
 415 #define K1TCR_RPTR      0x0400
 416 #define K1TCR_1000BT_FDX 0x200
 417 #define K1TCR_1000BT_HDX 0x100
 418
 419 #define K1STSR_MSMCFLT  0x8000
 420 #define K1STSR_MSCFGRES 0x4000
 421 #define K1STSR_LRSTAT   0x2000
 422 #define K1STSR_RRSTAT   0x1000
 423 #define K1STSR_LP1KFD   0x0800
 424 #define K1STSR_LP1KHD   0x0400
 425 #define K1STSR_LPASMDIR 0x0200
 426
 427 #define K1SCR_1KX_FDX   0x8000
 428 #define K1SCR_1KX_HDX   0x4000
 429 #define K1SCR_1KT_FDX   0x2000
 430 #define K1SCR_1KT_HDX   0x1000
 431
 432 #define STRAP_PHY1      0x0800
 433 #define STRAP_NCMODE    0x0400
 434 #define STRAP_MANMSCFG  0x0200
 435 #define STRAP_ANENABLE  0x0100
 436 #define STRAP_MSVAL     0x0080
 437 #define STRAP_1KHDXADV  0x0010
 438 #define STRAP_1KFDXADV  0x0008
 439 #define STRAP_100ADV    0x0004
 440 #define STRAP_SPEEDSEL  0x0000
 441 #define STRAP_SPEED100  0x0001
 442
 443 #define PHYSUP_SPEED1000 0x10
 444 #define PHYSUP_SPEED100  0x08
 445 #define PHYSUP_SPEED10   0x00
 446 #define PHYSUP_LINKUP    0x04
 447 #define PHYSUP_FDX       0x02
 448
 449 #define MII_BMCR        0x00    /* Basic mode control register (rw) */
 450 #define MII_BMSR        0x01    /* Basic mode status register (ro) */
 451 #define MII_PHYIDR1     0x02
 452 #define MII_PHYIDR2     0x03
 453
 454 #define MII_K1STSR      0x0A    /* 1K Status Register (ro) */
 455 #define MII_ANLPAR      0x05    /* Autonegotiation lnk partner abilities (rw) */
 456
 457
 458 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
 459
 460 #define ENABLE          1
 461 #define DISABLE         0
 462
 463 /**********************************************************************
 464  *  SBMAC_MII_SYNC(s)
 465  *
 466  *  Synchronize with the MII - send a pattern of bits to the MII
 467  *  that will guarantee that it is ready to accept a command.
 468  *
 469  *  Input parameters:
 470  *         s - sbmac structure
 471  *
 472  *  Return value:
 473  *         nothing
 474  ********************************************************************* */
 475
 476 static void sbmac_mii_sync(struct sbmac_softc *s)
 477 {
 478         int cnt;
 479         uint64_t bits;
 480         int mac_mdio_genc;
 481
 482         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 483
 484         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
 485
 486         __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 487
 488         for (cnt = 0; cnt < 32; cnt++) {
 489                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 490                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 491         }
 492 }
 493
 494 /**********************************************************************
 495  *  SBMAC_MII_SENDDATA(s,data,bitcnt)
 496  *
 497  *  Send some bits to the MII.  The bits to be sent are right-
 498  *  justified in the 'data' parameter.
 499  *
 500  *  Input parameters:
 501  *         s - sbmac structure
 502  *         data - data to send
 503  *         bitcnt - number of bits to send
 504  ********************************************************************* */
 505
 506 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
 507 {
 508         int i;
 509         uint64_t bits;
 510         unsigned int curmask;
 511         int mac_mdio_genc;
 512
 513         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 514
 515         bits = M_MAC_MDIO_DIR_OUTPUT;
 516         __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 517
 518         curmask = 1 << (bitcnt - 1);
 519
 520         for (i = 0; i < bitcnt; i++) {
 521                 if (data & curmask)
 522                         bits |= M_MAC_MDIO_OUT;
 523                 else bits &= ~M_MAC_MDIO_OUT;
 524                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 525                 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 526                 __raw_writeq(bits | mac_mdio_genc, s->sbm_mdio);
 527                 curmask >>= 1;
 528         }
 529 }
 530
 531
 532
 533 /**********************************************************************
 534  *  SBMAC_MII_READ(s,phyaddr,regidx)
 535  *
 536  *  Read a PHY register.
 537  *
 538  *  Input parameters:
 539  *         s - sbmac structure
 540  *         phyaddr - PHY's address
 541  *         regidx = index of register to read
 542  *
 543  *  Return value:
 544  *         value read, or 0 if an error occurred.
 545  ********************************************************************* */
 546
 547 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
 548 {
 549         int idx;
 550         int error;
 551         int regval;
 552         int mac_mdio_genc;
 553
 554         /*
 555          * Synchronize ourselves so that the PHY knows the next
 556          * thing coming down is a command
 557          */
 558
 559         sbmac_mii_sync(s);
 560
 561         /*
 562          * Send the data to the PHY.  The sequence is
 563          * a "start" command (2 bits)
 564          * a "read" command (2 bits)
 565          * the PHY addr (5 bits)
 566          * the register index (5 bits)
 567          */
 568
 569         sbmac_mii_senddata(s,MII_COMMAND_START, 2);
 570         sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
 571         sbmac_mii_senddata(s,phyaddr, 5);
 572         sbmac_mii_senddata(s,regidx, 5);
 573
 574         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 575
 576         /*
 577          * Switch the port around without a clock transition.
 578          */
 579         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 580
 581         /*
 582          * Send out a clock pulse to signal we want the status
 583          */
 584
 585         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 586         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 587
 588         /*
 589          * If an error occurred, the PHY will signal '1' back
 590          */
 591         error = __raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN;
 592
 593         /*
 594          * Issue an 'idle' clock pulse, but keep the direction
 595          * the same.
 596          */
 597         __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 598         __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 599
 600         regval = 0;
 601
 602         for (idx = 0; idx < 16; idx++) {
 603                 regval <<= 1;
 604
 605                 if (error == 0) {
 606                         if (__raw_readq(s->sbm_mdio) & M_MAC_MDIO_IN)
 607                                 regval |= 1;
 608                 }
 609
 610                 __raw_writeq(M_MAC_MDIO_DIR_INPUT|M_MAC_MDC | mac_mdio_genc, s->sbm_mdio);
 611                 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, s->sbm_mdio);
 612         }
 613
 614         /* Switch back to output */
 615         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
 616
 617         if (error == 0)
 618                 return regval;
 619         return 0;
 620 }
 621
 622
 623 /**********************************************************************
 624  *  SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
 625  *
 626  *  Write a value to a PHY register.
 627  *
 628  *  Input parameters:
 629  *         s - sbmac structure
 630  *         phyaddr - PHY to use
 631  *         regidx - register within the PHY
 632  *         regval - data to write to register
 633  *
 634  *  Return value:
 635  *         nothing
 636  ********************************************************************* */
 637
 638 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 639                             unsigned int regval)
 640 {
 641         int mac_mdio_genc;
 642
 643         sbmac_mii_sync(s);
 644
 645         sbmac_mii_senddata(s,MII_COMMAND_START,2);
 646         sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
 647         sbmac_mii_senddata(s,phyaddr, 5);
 648         sbmac_mii_senddata(s,regidx, 5);
 649         sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
 650         sbmac_mii_senddata(s,regval,16);
 651
 652         mac_mdio_genc = __raw_readq(s->sbm_mdio) & M_MAC_GENC;
 653
 654         __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, s->sbm_mdio);
 655 }
 656
 657
 658
 659 /**********************************************************************
 660  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
 661  *
 662  *  Initialize a DMA channel context.  Since there are potentially
 663  *  eight DMA channels per MAC, it's nice to do this in a standard
 664  *  way.
 665  *
 666  *  Input parameters:
 667  *         d - sbmacdma_t structure (DMA channel context)
 668  *         s - sbmac_softc structure (pointer to a MAC)
 669  *         chan - channel number (0..1 right now)
 670  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
 671  *      maxdescr - number of descriptors
 672  *
 673  *  Return value:
 674  *         nothing
 675  ********************************************************************* */
 676
 677 static void sbdma_initctx(sbmacdma_t *d,
 678                           struct sbmac_softc *s,
 679                           int chan,
 680                           int txrx,
 681                           int maxdescr)
 682 {
 683         /*
 684          * Save away interesting stuff in the structure
 685          */
 686
 687         d->sbdma_eth       = s;
 688         d->sbdma_channel   = chan;
 689         d->sbdma_txdir     = txrx;
 690
 691 #if 0
 692         /* RMON clearing */
 693         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
 694 #endif
 695
 696         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)));
 697         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)));
 698         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)));
 699         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)));
 700         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)));
 701         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)));
 702         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)));
 703         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)));
 704         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)));
 705         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)));
 706         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)));
 707         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)));
 708         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)));
 709         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)));
 710         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)));
 711         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)));
 712         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)));
 713         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)));
 714         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)));
 715         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)));
 716         __raw_writeq(0, IOADDR(A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)));
 717
 718         /*
 719          * initialize register pointers
 720          */
 721
 722         d->sbdma_config0 =
 723                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0);
 724         d->sbdma_config1 =
 725                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1);
 726         d->sbdma_dscrbase =
 727                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE);
 728         d->sbdma_dscrcnt =
 729                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT);
 730         d->sbdma_curdscr =
 731                 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR);
 732
 733         /*
 734          * Allocate memory for the ring
 735          */
 736
 737         d->sbdma_maxdescr = maxdescr;
 738
 739         d->sbdma_dscrtable = (sbdmadscr_t *)
 740                 kmalloc((d->sbdma_maxdescr+1)*sizeof(sbdmadscr_t), GFP_KERNEL);
 741
 742         /*
 743          * The descriptor table must be aligned to at least 16 bytes or the
 744          * MAC will corrupt it.
 745          */
 746         d->sbdma_dscrtable = (sbdmadscr_t *)
 747                 ALIGN((unsigned long)d->sbdma_dscrtable, sizeof(sbdmadscr_t));
 748
 749         memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
 750
 751         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
 752
 753         d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable);
 754
 755         /*
 756          * And context table
 757          */
 758
 759         d->sbdma_ctxtable = (struct sk_buff **)
 760                 kmalloc(d->sbdma_maxdescr*sizeof(struct sk_buff *), GFP_KERNEL);
 761
 762         memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
 763
 764 #ifdef CONFIG_SBMAC_COALESCE
 765         /*
 766          * Setup Rx/Tx DMA coalescing defaults
 767          */
 768
 769         if ( int_pktcnt ) {
 770                 d->sbdma_int_pktcnt = int_pktcnt;
 771         } else {
 772                 d->sbdma_int_pktcnt = 1;
 773         }
 774
 775         if ( int_timeout ) {
 776                 d->sbdma_int_timeout = int_timeout;
 777         } else {
 778                 d->sbdma_int_timeout = 0;
 779         }
 780 #endif
 781
 782 }
 783
 784 /**********************************************************************
 785  *  SBDMA_CHANNEL_START(d)
 786  *
 787  *  Initialize the hardware registers for a DMA channel.
 788  *
 789  *  Input parameters:
 790  *         d - DMA channel to init (context must be previously init'd
 791  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
 792  *
 793  *  Return value:
 794  *         nothing
 795  ********************************************************************* */
 796
 797 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
 798 {
 799         /*
 800          * Turn on the DMA channel
 801          */
 802
 803 #ifdef CONFIG_SBMAC_COALESCE
 804         __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
 805                        0, d->sbdma_config1);
 806         __raw_writeq(M_DMA_EOP_INT_EN |
 807                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 808                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
 809                        0, d->sbdma_config0);
 810 #else
 811         __raw_writeq(0, d->sbdma_config1);
 812         __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) |
 813                        0, d->sbdma_config0);
 814 #endif
 815
 816         __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase);
 817
 818         /*
 819          * Initialize ring pointers
 820          */
 821
 822         d->sbdma_addptr = d->sbdma_dscrtable;
 823         d->sbdma_remptr = d->sbdma_dscrtable;
 824 }
 825
 826 /**********************************************************************
 827  *  SBDMA_CHANNEL_STOP(d)
 828  *
 829  *  Initialize the hardware registers for a DMA channel.
 830  *
 831  *  Input parameters:
 832  *         d - DMA channel to init (context must be previously init'd
 833  *
 834  *  Return value:
 835  *         nothing
 836  ********************************************************************* */
 837
 838 static void sbdma_channel_stop(sbmacdma_t *d)
 839 {
 840         /*
 841          * Turn off the DMA channel
 842          */
 843
 844         __raw_writeq(0, d->sbdma_config1);
 845
 846         __raw_writeq(0, d->sbdma_dscrbase);
 847
 848         __raw_writeq(0, d->sbdma_config0);
 849
 850         /*
 851          * Zero ring pointers
 852          */
 853
 854         d->sbdma_addptr = NULL;
 855         d->sbdma_remptr = NULL;
 856 }
 857
 858 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
 859 {
 860         unsigned long addr;
 861         unsigned long newaddr;
 862
 863         addr = (unsigned long) skb->data;
 864
 865         newaddr = (addr + power2 - 1) & ~(power2 - 1);
 866
 867         skb_reserve(skb,newaddr-addr+offset);
 868 }
 869
 870
 871 /**********************************************************************
 872  *  SBDMA_ADD_RCVBUFFER(d,sb)
 873  *
 874  *  Add a buffer to the specified DMA channel.   For receive channels,
 875  *  this queues a buffer for inbound packets.
 876  *
 877  *  Input parameters:
 878  *         d - DMA channel descriptor
 879  *         sb - sk_buff to add, or NULL if we should allocate one
 880  *
 881  *  Return value:
 882  *         0 if buffer could not be added (ring is full)
 883  *         1 if buffer added successfully
 884  ********************************************************************* */
 885
 886
 887 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
 888 {
 889         sbdmadscr_t *dsc;
 890         sbdmadscr_t *nextdsc;
 891         struct sk_buff *sb_new = NULL;
 892         int pktsize = ENET_PACKET_SIZE;
 893
 894         /* get pointer to our current place in the ring */
 895
 896         dsc = d->sbdma_addptr;
 897         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
 898
 899         /*
 900          * figure out if the ring is full - if the next descriptor
 901          * is the same as the one that we're going to remove from
 902          * the ring, the ring is full
 903          */
 904
 905         if (nextdsc == d->sbdma_remptr) {
 906                 return -ENOSPC;
 907         }
 908
 909         /*
 910          * Allocate a sk_buff if we don't already have one.
 911          * If we do have an sk_buff, reset it so that it's empty.
 912          *
 913          * Note: sk_buffs don't seem to be guaranteed to have any sort
 914          * of alignment when they are allocated.  Therefore, allocate enough
 915          * extra space to make sure that:
 916          *
 917          *    1. the data does not start in the middle of a cache line.
 918          *    2. The data does not end in the middle of a cache line
 919          *    3. The buffer can be aligned such that the IP addresses are
 920          *       naturally aligned.
 921          *
 922          *  Remember, the SOCs MAC writes whole cache lines at a time,
 923          *  without reading the old contents first.  So, if the sk_buff's
 924          *  data portion starts in the middle of a cache line, the SOC
 925          *  DMA will trash the beginning (and ending) portions.
 926          */
 927
 928         if (sb == NULL) {
 929                 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN);
 930                 if (sb_new == NULL) {
 931                         printk(KERN_INFO "%s: sk_buff allocation failed\n",
 932                                d->sbdma_eth->sbm_dev->name);
 933                         return -ENOBUFS;
 934                 }
 935
 936                 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN);
 937
 938                 /* mark skbuff owned by our device */
 939                 sb_new->dev = d->sbdma_eth->sbm_dev;
 940         }
 941         else {
 942                 sb_new = sb;
 943                 /*
 944                  * nothing special to reinit buffer, it's already aligned
 945                  * and sb->data already points to a good place.
 946                  */
 947         }
 948
 949         /*
 950          * fill in the descriptor
 951          */
 952
 953 #ifdef CONFIG_SBMAC_COALESCE
 954         /*
 955          * Do not interrupt per DMA transfer.
 956          */
 957         dsc->dscr_a = virt_to_phys(sb_new->data) |
 958                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) | 0;
 959 #else
 960         dsc->dscr_a = virt_to_phys(sb_new->data) |
 961                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 962                 M_DMA_DSCRA_INTERRUPT;
 963 #endif
 964
 965         /* receiving: no options */
 966         dsc->dscr_b = 0;
 967
 968         /*
 969          * fill in the context
 970          */
 971
 972         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
 973
 974         /*
 975          * point at next packet
 976          */
 977
 978         d->sbdma_addptr = nextdsc;
 979
 980         /*
 981          * Give the buffer to the DMA engine.
 982          */
 983
 984         __raw_writeq(1, d->sbdma_dscrcnt);
 985
 986         return 0;                                       /* we did it */
 987 }
 988
 989 /**********************************************************************
 990  *  SBDMA_ADD_TXBUFFER(d,sb)
 991  *
 992  *  Add a transmit buffer to the specified DMA channel, causing a
 993  *  transmit to start.
 994  *
 995  *  Input parameters:
 996  *         d - DMA channel descriptor
 997  *         sb - sk_buff to add
 998  *
 999  *  Return value:
1000  *         0 transmit queued successfully
1001  *         otherwise error code
1002  ********************************************************************* */
1003
1004
1005 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1006 {
1007         sbdmadscr_t *dsc;
1008         sbdmadscr_t *nextdsc;
1009         uint64_t phys;
1010         uint64_t ncb;
1011         int length;
1012
1013         /* get pointer to our current place in the ring */
1014
1015         dsc = d->sbdma_addptr;
1016         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1017
1018         /*
1019          * figure out if the ring is full - if the next descriptor
1020          * is the same as the one that we're going to remove from
1021          * the ring, the ring is full
1022          */
1023
1024         if (nextdsc == d->sbdma_remptr) {
1025                 return -ENOSPC;
1026         }
1027
1028         /*
1029          * Under Linux, it's not necessary to copy/coalesce buffers
1030          * like it is on NetBSD.  We think they're all contiguous,
1031          * but that may not be true for GBE.
1032          */
1033
1034         length = sb->len;
1035
1036         /*
1037          * fill in the descriptor.  Note that the number of cache
1038          * blocks in the descriptor is the number of blocks
1039          * *spanned*, so we need to add in the offset (if any)
1040          * while doing the calculation.
1041          */
1042
1043         phys = virt_to_phys(sb->data);
1044         ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1)));
1045
1046         dsc->dscr_a = phys |
1047                 V_DMA_DSCRA_A_SIZE(ncb) |
1048 #ifndef CONFIG_SBMAC_COALESCE
1049                 M_DMA_DSCRA_INTERRUPT |
1050 #endif
1051                 M_DMA_ETHTX_SOP;
1052
1053         /* transmitting: set outbound options and length */
1054
1055         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1056                 V_DMA_DSCRB_PKT_SIZE(length);
1057
1058         /*
1059          * fill in the context
1060          */
1061
1062         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1063
1064         /*
1065          * point at next packet
1066          */
1067
1068         d->sbdma_addptr = nextdsc;
1069
1070         /*
1071          * Give the buffer to the DMA engine.
1072          */
1073
1074         __raw_writeq(1, d->sbdma_dscrcnt);
1075
1076         return 0;                                       /* we did it */
1077 }
1078
1079
1080
1081
1082 /**********************************************************************
1083  *  SBDMA_EMPTYRING(d)
1084  *
1085  *  Free all allocated sk_buffs on the specified DMA channel;
1086  *
1087  *  Input parameters:
1088  *         d  - DMA channel
1089  *
1090  *  Return value:
1091  *         nothing
1092  ********************************************************************* */
1093
1094 static void sbdma_emptyring(sbmacdma_t *d)
1095 {
1096         int idx;
1097         struct sk_buff *sb;
1098
1099         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1100                 sb = d->sbdma_ctxtable[idx];
1101                 if (sb) {
1102                         dev_kfree_skb(sb);
1103                         d->sbdma_ctxtable[idx] = NULL;
1104                 }
1105         }
1106 }
1107
1108
1109 /**********************************************************************
1110  *  SBDMA_FILLRING(d)
1111  *
1112  *  Fill the specified DMA channel (must be receive channel)
1113  *  with sk_buffs
1114  *
1115  *  Input parameters:
1116  *         d - DMA channel
1117  *
1118  *  Return value:
1119  *         nothing
1120  ********************************************************************* */
1121
1122 static void sbdma_fillring(sbmacdma_t *d)
1123 {
1124         int idx;
1125
1126         for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1127                 if (sbdma_add_rcvbuffer(d,NULL) != 0)
1128                         break;
1129         }
1130 }
1131
1132
1133 /**********************************************************************
1134  *  SBDMA_RX_PROCESS(sc,d)
1135  *
1136  *  Process "completed" receive buffers on the specified DMA channel.
1137  *  Note that this isn't really ideal for priority channels, since
1138  *  it processes all of the packets on a given channel before
1139  *  returning.
1140  *
1141  *  Input parameters:
1142  *         sc - softc structure
1143  *         d - DMA channel context
1144  *
1145  *  Return value:
1146  *         nothing
1147  ********************************************************************* */
1148
1149 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1150 {
1151         int curidx;
1152         int hwidx;
1153         sbdmadscr_t *dsc;
1154         struct sk_buff *sb;
1155         int len;
1156
1157         for (;;) {
1158                 /*
1159                  * figure out where we are (as an index) and where
1160                  * the hardware is (also as an index)
1161                  *
1162                  * This could be done faster if (for example) the
1163                  * descriptor table was page-aligned and contiguous in
1164                  * both virtual and physical memory -- you could then
1165                  * just compare the low-order bits of the virtual address
1166                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1167                  */
1168
1169                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1170                 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1171                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1172
1173                 /*
1174                  * If they're the same, that means we've processed all
1175                  * of the descriptors up to (but not including) the one that
1176                  * the hardware is working on right now.
1177                  */
1178
1179                 if (curidx == hwidx)
1180                         break;
1181
1182                 /*
1183                  * Otherwise, get the packet's sk_buff ptr back
1184                  */
1185
1186                 dsc = &(d->sbdma_dscrtable[curidx]);
1187                 sb = d->sbdma_ctxtable[curidx];
1188                 d->sbdma_ctxtable[curidx] = NULL;
1189
1190                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1191
1192                 /*
1193                  * Check packet status.  If good, process it.
1194                  * If not, silently drop it and put it back on the
1195                  * receive ring.
1196                  */
1197
1198                 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1199
1200                         /*
1201                          * Add a new buffer to replace the old one.  If we fail
1202                          * to allocate a buffer, we're going to drop this
1203                          * packet and put it right back on the receive ring.
1204                          */
1205
1206                         if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1207                                 sc->sbm_stats.rx_dropped++;
1208                                 sbdma_add_rcvbuffer(d,sb); /* re-add old buffer */
1209                         } else {
1210                                 /*
1211                                  * Set length into the packet
1212                                  */
1213                                 skb_put(sb,len);
1214
1215                                 /*
1216                                  * Buffer has been replaced on the
1217                                  * receive ring.  Pass the buffer to
1218                                  * the kernel
1219                                  */
1220                                 sc->sbm_stats.rx_bytes += len;
1221                                 sc->sbm_stats.rx_packets++;
1222                                 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1223                                 /* Check hw IPv4/TCP checksum if supported */
1224                                 if (sc->rx_hw_checksum == ENABLE) {
1225                                         if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) &&
1226                                             !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) {
1227                                                 sb->ip_summed = CHECKSUM_UNNECESSARY;
1228                                                 /* don't need to set sb->csum */
1229                                         } else {
1230                                                 sb->ip_summed = CHECKSUM_NONE;
1231                                         }
1232                                 }
1233
1234                                 netif_rx(sb);
1235                         }
1236                 } else {
1237                         /*
1238                          * Packet was mangled somehow.  Just drop it and
1239                          * put it back on the receive ring.
1240                          */
1241                         sc->sbm_stats.rx_errors++;
1242                         sbdma_add_rcvbuffer(d,sb);
1243                 }
1244
1245
1246                 /*
1247                  * .. and advance to the next buffer.
1248                  */
1249
1250                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1251
1252         }
1253 }
1254
1255
1256
1257 /**********************************************************************
1258  *  SBDMA_TX_PROCESS(sc,d)
1259  *
1260  *  Process "completed" transmit buffers on the specified DMA channel.
1261  *  This is normally called within the interrupt service routine.
1262  *  Note that this isn't really ideal for priority channels, since
1263  *  it processes all of the packets on a given channel before
1264  *  returning.
1265  *
1266  *  Input parameters:
1267  *      sc - softc structure
1268  *         d - DMA channel context
1269  *
1270  *  Return value:
1271  *         nothing
1272  ********************************************************************* */
1273
1274 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1275 {
1276         int curidx;
1277         int hwidx;
1278         sbdmadscr_t *dsc;
1279         struct sk_buff *sb;
1280         unsigned long flags;
1281
1282         spin_lock_irqsave(&(sc->sbm_lock), flags);
1283
1284         for (;;) {
1285                 /*
1286                  * figure out where we are (as an index) and where
1287                  * the hardware is (also as an index)
1288                  *
1289                  * This could be done faster if (for example) the
1290                  * descriptor table was page-aligned and contiguous in
1291                  * both virtual and physical memory -- you could then
1292                  * just compare the low-order bits of the virtual address
1293                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1294                  */
1295
1296                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1297                 hwidx = (int) (((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1298                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1299
1300                 /*
1301                  * If they're the same, that means we've processed all
1302                  * of the descriptors up to (but not including) the one that
1303                  * the hardware is working on right now.
1304                  */
1305
1306                 if (curidx == hwidx)
1307                         break;
1308
1309                 /*
1310                  * Otherwise, get the packet's sk_buff ptr back
1311                  */
1312
1313                 dsc = &(d->sbdma_dscrtable[curidx]);
1314                 sb = d->sbdma_ctxtable[curidx];
1315                 d->sbdma_ctxtable[curidx] = NULL;
1316
1317                 /*
1318                  * Stats
1319                  */
1320
1321                 sc->sbm_stats.tx_bytes += sb->len;
1322                 sc->sbm_stats.tx_packets++;
1323
1324                 /*
1325                  * for transmits, we just free buffers.
1326                  */
1327
1328                 dev_kfree_skb_irq(sb);
1329
1330                 /*
1331                  * .. and advance to the next buffer.
1332                  */
1333
1334                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1335
1336         }
1337
1338         /*
1339          * Decide if we should wake up the protocol or not.
1340          * Other drivers seem to do this when we reach a low
1341          * watermark on the transmit queue.
1342          */
1343
1344         netif_wake_queue(d->sbdma_eth->sbm_dev);
1345
1346         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1347
1348 }
1349
1350
1351
1352 /**********************************************************************
1353  *  SBMAC_INITCTX(s)
1354  *
1355  *  Initialize an Ethernet context structure - this is called
1356  *  once per MAC on the 1250.  Memory is allocated here, so don't
1357  *  call it again from inside the ioctl routines that bring the
1358  *  interface up/down
1359  *
1360  *  Input parameters:
1361  *         s - sbmac context structure
1362  *
1363  *  Return value:
1364  *         0
1365  ********************************************************************* */
1366
1367 static int sbmac_initctx(struct sbmac_softc *s)
1368 {
1369
1370         /*
1371          * figure out the addresses of some ports
1372          */
1373
1374         s->sbm_macenable = s->sbm_base + R_MAC_ENABLE;
1375         s->sbm_maccfg    = s->sbm_base + R_MAC_CFG;
1376         s->sbm_fifocfg   = s->sbm_base + R_MAC_THRSH_CFG;
1377         s->sbm_framecfg  = s->sbm_base + R_MAC_FRAMECFG;
1378         s->sbm_rxfilter  = s->sbm_base + R_MAC_ADFILTER_CFG;
1379         s->sbm_isr       = s->sbm_base + R_MAC_STATUS;
1380         s->sbm_imr       = s->sbm_base + R_MAC_INT_MASK;
1381         s->sbm_mdio      = s->sbm_base + R_MAC_MDIO;
1382
1383         s->sbm_phys[0]   = 1;
1384         s->sbm_phys[1]   = 0;
1385
1386         s->sbm_phy_oldbmsr = 0;
1387         s->sbm_phy_oldanlpar = 0;
1388         s->sbm_phy_oldk1stsr = 0;
1389         s->sbm_phy_oldlinkstat = 0;
1390
1391         /*
1392          * Initialize the DMA channels.  Right now, only one per MAC is used
1393          * Note: Only do this _once_, as it allocates memory from the kernel!
1394          */
1395
1396         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1397         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1398
1399         /*
1400          * initial state is OFF
1401          */
1402
1403         s->sbm_state = sbmac_state_off;
1404
1405         /*
1406          * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1407          */
1408
1409         s->sbm_speed = sbmac_speed_10;
1410         s->sbm_duplex = sbmac_duplex_half;
1411         s->sbm_fc = sbmac_fc_disabled;
1412
1413         return 0;
1414 }
1415
1416
1417 static void sbdma_uninitctx(struct sbmacdma_s *d)
1418 {
1419         if (d->sbdma_dscrtable) {
1420                 kfree(d->sbdma_dscrtable);
1421                 d->sbdma_dscrtable = NULL;
1422         }
1423
1424         if (d->sbdma_ctxtable) {
1425                 kfree(d->sbdma_ctxtable);
1426                 d->sbdma_ctxtable = NULL;
1427         }
1428 }
1429
1430
1431 static void sbmac_uninitctx(struct sbmac_softc *sc)
1432 {
1433         sbdma_uninitctx(&(sc->sbm_txdma));
1434         sbdma_uninitctx(&(sc->sbm_rxdma));
1435 }
1436
1437
1438 /**********************************************************************
1439  *  SBMAC_CHANNEL_START(s)
1440  *
1441  *  Start packet processing on this MAC.
1442  *
1443  *  Input parameters:
1444  *         s - sbmac structure
1445  *
1446  *  Return value:
1447  *         nothing
1448  ********************************************************************* */
1449
1450 static void sbmac_channel_start(struct sbmac_softc *s)
1451 {
1452         uint64_t reg;
1453         volatile void __iomem *port;
1454         uint64_t cfg,fifo,framecfg;
1455         int idx, th_value;
1456
1457         /*
1458          * Don't do this if running
1459          */
1460
1461         if (s->sbm_state == sbmac_state_on)
1462                 return;
1463
1464         /*
1465          * Bring the controller out of reset, but leave it off.
1466          */
1467
1468         __raw_writeq(0, s->sbm_macenable);
1469
1470         /*
1471          * Ignore all received packets
1472          */
1473
1474         __raw_writeq(0, s->sbm_rxfilter);
1475
1476         /*
1477          * Calculate values for various control registers.
1478          */
1479
1480         cfg = M_MAC_RETRY_EN |
1481                 M_MAC_TX_HOLD_SOP_EN |
1482                 V_MAC_TX_PAUSE_CNT_16K |
1483                 M_MAC_AP_STAT_EN |
1484                 M_MAC_FAST_SYNC |
1485                 M_MAC_SS_EN |
1486                 0;
1487
1488         /*
1489          * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars
1490          * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above
1491          * Use a larger RD_THRSH for gigabit
1492          */
1493         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2)
1494                 th_value = 28;
1495         else
1496                 th_value = 64;
1497
1498         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1499                 ((s->sbm_speed == sbmac_speed_1000)
1500                  ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) |
1501                 V_MAC_TX_RL_THRSH(4) |
1502                 V_MAC_RX_PL_THRSH(4) |
1503                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1504                 V_MAC_RX_PL_THRSH(4) |
1505                 V_MAC_RX_RL_THRSH(8) |
1506                 0;
1507
1508         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1509                 V_MAC_MAX_FRAMESZ_DEFAULT |
1510                 V_MAC_BACKOFF_SEL(1);
1511
1512         /*
1513          * Clear out the hash address map
1514          */
1515
1516         port = s->sbm_base + R_MAC_HASH_BASE;
1517         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1518                 __raw_writeq(0, port);
1519                 port += sizeof(uint64_t);
1520         }
1521
1522         /*
1523          * Clear out the exact-match table
1524          */
1525
1526         port = s->sbm_base + R_MAC_ADDR_BASE;
1527         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1528                 __raw_writeq(0, port);
1529                 port += sizeof(uint64_t);
1530         }
1531
1532         /*
1533          * Clear out the DMA Channel mapping table registers
1534          */
1535
1536         port = s->sbm_base + R_MAC_CHUP0_BASE;
1537         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1538                 __raw_writeq(0, port);
1539                 port += sizeof(uint64_t);
1540         }
1541
1542
1543         port = s->sbm_base + R_MAC_CHLO0_BASE;
1544         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1545                 __raw_writeq(0, port);
1546                 port += sizeof(uint64_t);
1547         }
1548
1549         /*
1550          * Program the hardware address.  It goes into the hardware-address
1551          * register as well as the first filter register.
1552          */
1553
1554         reg = sbmac_addr2reg(s->sbm_hwaddr);
1555
1556         port = s->sbm_base + R_MAC_ADDR_BASE;
1557         __raw_writeq(reg, port);
1558         port = s->sbm_base + R_MAC_ETHERNET_ADDR;
1559
1560 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1561         /*
1562          * Pass1 SOCs do not receive packets addressed to the
1563          * destination address in the R_MAC_ETHERNET_ADDR register.
1564          * Set the value to zero.
1565          */
1566         __raw_writeq(0, port);
1567 #else
1568         __raw_writeq(reg, port);
1569 #endif
1570
1571         /*
1572          * Set the receive filter for no packets, and write values
1573          * to the various config registers
1574          */
1575
1576         __raw_writeq(0, s->sbm_rxfilter);
1577         __raw_writeq(0, s->sbm_imr);
1578         __raw_writeq(framecfg, s->sbm_framecfg);
1579         __raw_writeq(fifo, s->sbm_fifocfg);
1580         __raw_writeq(cfg, s->sbm_maccfg);
1581
1582         /*
1583          * Initialize DMA channels (rings should be ok now)
1584          */
1585
1586         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1587         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1588
1589         /*
1590          * Configure the speed, duplex, and flow control
1591          */
1592
1593         sbmac_set_speed(s,s->sbm_speed);
1594         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1595
1596         /*
1597          * Fill the receive ring
1598          */
1599
1600         sbdma_fillring(&(s->sbm_rxdma));
1601
1602         /*
1603          * Turn on the rest of the bits in the enable register
1604          */
1605
1606 #if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80)
1607         __raw_writeq(M_MAC_RXDMA_EN0 |
1608                        M_MAC_TXDMA_EN0, s->sbm_macenable);
1609 #elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X)
1610         __raw_writeq(M_MAC_RXDMA_EN0 |
1611                        M_MAC_TXDMA_EN0 |
1612                        M_MAC_RX_ENABLE |
1613                        M_MAC_TX_ENABLE, s->sbm_macenable);
1614 #else
1615 #error invalid SiByte MAC configuation
1616 #endif
1617
1618 #ifdef CONFIG_SBMAC_COALESCE
1619         /*
1620          * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1621          */
1622         __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) |
1623                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr);
1624 #else
1625         /*
1626          * Accept any kind of interrupt on TX and RX DMA channel 0
1627          */
1628         __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1629                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr);
1630 #endif
1631
1632         /*
1633          * Enable receiving unicasts and broadcasts
1634          */
1635
1636         __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter);
1637
1638         /*
1639          * we're running now.
1640          */
1641
1642         s->sbm_state = sbmac_state_on;
1643
1644         /*
1645          * Program multicast addresses
1646          */
1647
1648         sbmac_setmulti(s);
1649
1650         /*
1651          * If channel was in promiscuous mode before, turn that on
1652          */
1653
1654         if (s->sbm_devflags & IFF_PROMISC) {
1655                 sbmac_promiscuous_mode(s,1);
1656         }
1657
1658 }
1659
1660
1661 /**********************************************************************
1662  *  SBMAC_CHANNEL_STOP(s)
1663  *
1664  *  Stop packet processing on this MAC.
1665  *
1666  *  Input parameters:
1667  *         s - sbmac structure
1668  *
1669  *  Return value:
1670  *         nothing
1671  ********************************************************************* */
1672
1673 static void sbmac_channel_stop(struct sbmac_softc *s)
1674 {
1675         /* don't do this if already stopped */
1676
1677         if (s->sbm_state == sbmac_state_off)
1678                 return;
1679
1680         /* don't accept any packets, disable all interrupts */
1681
1682         __raw_writeq(0, s->sbm_rxfilter);
1683         __raw_writeq(0, s->sbm_imr);
1684
1685         /* Turn off ticker */
1686
1687         /* XXX */
1688
1689         /* turn off receiver and transmitter */
1690
1691         __raw_writeq(0, s->sbm_macenable);
1692
1693         /* We're stopped now. */
1694
1695         s->sbm_state = sbmac_state_off;
1696
1697         /*
1698          * Stop DMA channels (rings should be ok now)
1699          */
1700
1701         sbdma_channel_stop(&(s->sbm_rxdma));
1702         sbdma_channel_stop(&(s->sbm_txdma));
1703
1704         /* Empty the receive and transmit rings */
1705
1706         sbdma_emptyring(&(s->sbm_rxdma));
1707         sbdma_emptyring(&(s->sbm_txdma));
1708
1709 }
1710
1711 /**********************************************************************
1712  *  SBMAC_SET_CHANNEL_STATE(state)
1713  *
1714  *  Set the channel's state ON or OFF
1715  *
1716  *  Input parameters:
1717  *         state - new state
1718  *
1719  *  Return value:
1720  *         old state
1721  ********************************************************************* */
1722 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1723                                              sbmac_state_t state)
1724 {
1725         sbmac_state_t oldstate = sc->sbm_state;
1726
1727         /*
1728          * If same as previous state, return
1729          */
1730
1731         if (state == oldstate) {
1732                 return oldstate;
1733         }
1734
1735         /*
1736          * If new state is ON, turn channel on
1737          */
1738
1739         if (state == sbmac_state_on) {
1740                 sbmac_channel_start(sc);
1741         }
1742         else {
1743                 sbmac_channel_stop(sc);
1744         }
1745
1746         /*
1747          * Return previous state
1748          */
1749
1750         return oldstate;
1751 }
1752
1753
1754 /**********************************************************************
1755  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1756  *
1757  *  Turn on or off promiscuous mode
1758  *
1759  *  Input parameters:
1760  *         sc - softc
1761  *      onoff - 1 to turn on, 0 to turn off
1762  *
1763  *  Return value:
1764  *         nothing
1765  ********************************************************************* */
1766
1767 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1768 {
1769         uint64_t reg;
1770
1771         if (sc->sbm_state != sbmac_state_on)
1772                 return;
1773
1774         if (onoff) {
1775                 reg = __raw_readq(sc->sbm_rxfilter);
1776                 reg |= M_MAC_ALLPKT_EN;
1777                 __raw_writeq(reg, sc->sbm_rxfilter);
1778         }
1779         else {
1780                 reg = __raw_readq(sc->sbm_rxfilter);
1781                 reg &= ~M_MAC_ALLPKT_EN;
1782                 __raw_writeq(reg, sc->sbm_rxfilter);
1783         }
1784 }
1785
1786 /**********************************************************************
1787  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1788  *
1789  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1790  *
1791  *  Input parameters:
1792  *         sc - softc
1793  *
1794  *  Return value:
1795  *         nothing
1796  ********************************************************************* */
1797
1798 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1799 {
1800         uint64_t reg;
1801
1802         /* Hard code the off set to 15 for now */
1803         reg = __raw_readq(sc->sbm_rxfilter);
1804         reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15);
1805         __raw_writeq(reg, sc->sbm_rxfilter);
1806
1807         /* BCM1250 pass1 didn't have hardware checksum.  Everything
1808            later does.  */
1809         if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) {
1810                 sc->rx_hw_checksum = DISABLE;
1811         } else {
1812                 sc->rx_hw_checksum = ENABLE;
1813         }
1814 }
1815
1816
1817 /**********************************************************************
1818  *  SBMAC_ADDR2REG(ptr)
1819  *
1820  *  Convert six bytes into the 64-bit register value that
1821  *  we typically write into the SBMAC's address/mcast registers
1822  *
1823  *  Input parameters:
1824  *         ptr - pointer to 6 bytes
1825  *
1826  *  Return value:
1827  *         register value
1828  ********************************************************************* */
1829
1830 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1831 {
1832         uint64_t reg = 0;
1833
1834         ptr += 6;
1835
1836         reg |= (uint64_t) *(--ptr);
1837         reg <<= 8;
1838         reg |= (uint64_t) *(--ptr);
1839         reg <<= 8;
1840         reg |= (uint64_t) *(--ptr);
1841         reg <<= 8;
1842         reg |= (uint64_t) *(--ptr);
1843         reg <<= 8;
1844         reg |= (uint64_t) *(--ptr);
1845         reg <<= 8;
1846         reg |= (uint64_t) *(--ptr);
1847
1848         return reg;
1849 }
1850
1851
1852 /**********************************************************************
1853  *  SBMAC_SET_SPEED(s,speed)
1854  *
1855  *  Configure LAN speed for the specified MAC.
1856  *  Warning: must be called when MAC is off!
1857  *
1858  *  Input parameters:
1859  *         s - sbmac structure
1860  *         speed - speed to set MAC to (see sbmac_speed_t enum)
1861  *
1862  *  Return value:
1863  *         1 if successful
1864  *      0 indicates invalid parameters
1865  ********************************************************************* */
1866
1867 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1868 {
1869         uint64_t cfg;
1870         uint64_t framecfg;
1871
1872         /*
1873          * Save new current values
1874          */
1875
1876         s->sbm_speed = speed;
1877
1878         if (s->sbm_state == sbmac_state_on)
1879                 return 0;       /* save for next restart */
1880
1881         /*
1882          * Read current register values
1883          */
1884
1885         cfg = __raw_readq(s->sbm_maccfg);
1886         framecfg = __raw_readq(s->sbm_framecfg);
1887
1888         /*
1889          * Mask out the stuff we want to change
1890          */
1891
1892         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1893         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1894                       M_MAC_SLOT_SIZE);
1895
1896         /*
1897          * Now add in the new bits
1898          */
1899
1900         switch (speed) {
1901         case sbmac_speed_10:
1902                 framecfg |= V_MAC_IFG_RX_10 |
1903                         V_MAC_IFG_TX_10 |
1904                         K_MAC_IFG_THRSH_10 |
1905                         V_MAC_SLOT_SIZE_10;
1906                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1907                 break;
1908
1909         case sbmac_speed_100:
1910                 framecfg |= V_MAC_IFG_RX_100 |
1911                         V_MAC_IFG_TX_100 |
1912                         V_MAC_IFG_THRSH_100 |
1913                         V_MAC_SLOT_SIZE_100;
1914                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1915                 break;
1916
1917         case sbmac_speed_1000:
1918                 framecfg |= V_MAC_IFG_RX_1000 |
1919                         V_MAC_IFG_TX_1000 |
1920                         V_MAC_IFG_THRSH_1000 |
1921                         V_MAC_SLOT_SIZE_1000;
1922                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1923                 break;
1924
1925         case sbmac_speed_auto:          /* XXX not implemented */
1926                 /* fall through */
1927         default:
1928                 return 0;
1929         }
1930
1931         /*
1932          * Send the bits back to the hardware
1933          */
1934
1935         __raw_writeq(framecfg, s->sbm_framecfg);
1936         __raw_writeq(cfg, s->sbm_maccfg);
1937
1938         return 1;
1939 }
1940
1941 /**********************************************************************
1942  *  SBMAC_SET_DUPLEX(s,duplex,fc)
1943  *
1944  *  Set Ethernet duplex and flow control options for this MAC
1945  *  Warning: must be called when MAC is off!
1946  *
1947  *  Input parameters:
1948  *         s - sbmac structure
1949  *         duplex - duplex setting (see sbmac_duplex_t)
1950  *         fc - flow control setting (see sbmac_fc_t)
1951  *
1952  *  Return value:
1953  *         1 if ok
1954  *         0 if an invalid parameter combination was specified
1955  ********************************************************************* */
1956
1957 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
1958 {
1959         uint64_t cfg;
1960
1961         /*
1962          * Save new current values
1963          */
1964
1965         s->sbm_duplex = duplex;
1966         s->sbm_fc = fc;
1967
1968         if (s->sbm_state == sbmac_state_on)
1969                 return 0;       /* save for next restart */
1970
1971         /*
1972          * Read current register values
1973          */
1974
1975         cfg = __raw_readq(s->sbm_maccfg);
1976
1977         /*
1978          * Mask off the stuff we're about to change
1979          */
1980
1981         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
1982
1983
1984         switch (duplex) {
1985         case sbmac_duplex_half:
1986                 switch (fc) {
1987                 case sbmac_fc_disabled:
1988                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
1989                         break;
1990
1991                 case sbmac_fc_collision:
1992                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
1993                         break;
1994
1995                 case sbmac_fc_carrier:
1996                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
1997                         break;
1998
1999                 case sbmac_fc_auto:             /* XXX not implemented */
2000                         /* fall through */
2001                 case sbmac_fc_frame:            /* not valid in half duplex */
2002                 default:                        /* invalid selection */
2003                         return 0;
2004                 }
2005                 break;
2006
2007         case sbmac_duplex_full:
2008                 switch (fc) {
2009                 case sbmac_fc_disabled:
2010                         cfg |= V_MAC_FC_CMD_DISABLED;
2011                         break;
2012
2013                 case sbmac_fc_frame:
2014                         cfg |= V_MAC_FC_CMD_ENABLED;
2015                         break;
2016
2017                 case sbmac_fc_collision:        /* not valid in full duplex */
2018                 case sbmac_fc_carrier:          /* not valid in full duplex */
2019                 case sbmac_fc_auto:             /* XXX not implemented */
2020                         /* fall through */
2021                 default:
2022                         return 0;
2023                 }
2024                 break;
2025         case sbmac_duplex_auto:
2026                 /* XXX not implemented */
2027                 break;
2028         }
2029
2030         /*
2031          * Send the bits back to the hardware
2032          */
2033
2034         __raw_writeq(cfg, s->sbm_maccfg);
2035
2036         return 1;
2037 }
2038
2039
2040
2041
2042 /**********************************************************************
2043  *  SBMAC_INTR()
2044  *
2045  *  Interrupt handler for MAC interrupts
2046  *
2047  *  Input parameters:
2048  *         MAC structure
2049  *
2050  *  Return value:
2051  *         nothing
2052  ********************************************************************* */
2053 static irqreturn_t sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2054 {
2055         struct net_device *dev = (struct net_device *) dev_instance;
2056         struct sbmac_softc *sc = netdev_priv(dev);
2057         uint64_t isr;
2058         int handled = 0;
2059
2060         for (;;) {
2061
2062                 /*
2063                  * Read the ISR (this clears the bits in the real
2064                  * register, except for counter addr)
2065                  */
2066
2067                 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2068
2069                 if (isr == 0)
2070                         break;
2071
2072                 handled = 1;
2073
2074                 /*
2075                  * Transmits on channel 0
2076                  */
2077
2078                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2079                         sbdma_tx_process(sc,&(sc->sbm_txdma));
2080                 }
2081
2082                 /*
2083                  * Receives on channel 0
2084                  */
2085
2086                 /*
2087                  * It's important to test all the bits (or at least the
2088                  * EOP_SEEN bit) when deciding to do the RX process
2089                  * particularly when coalescing, to make sure we
2090                  * take care of the following:
2091                  *
2092                  * If you have some packets waiting (have been received
2093                  * but no interrupt) and get a TX interrupt before
2094                  * the RX timer or counter expires, reading the ISR
2095                  * above will clear the timer and counter, and you
2096                  * won't get another interrupt until a packet shows
2097                  * up to start the timer again.  Testing
2098                  * EOP_SEEN here takes care of this case.
2099                  * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2100                  */
2101
2102
2103                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2104                         sbdma_rx_process(sc,&(sc->sbm_rxdma));
2105                 }
2106         }
2107         return IRQ_RETVAL(handled);
2108 }
2109
2110
2111 /**********************************************************************
2112  *  SBMAC_START_TX(skb,dev)
2113  *
2114  *  Start output on the specified interface.  Basically, we
2115  *  queue as many buffers as we can until the ring fills up, or
2116  *  we run off the end of the queue, whichever comes first.
2117  *
2118  *  Input parameters:
2119  *
2120  *
2121  *  Return value:
2122  *         nothing
2123  ********************************************************************* */
2124 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2125 {
2126         struct sbmac_softc *sc = netdev_priv(dev);
2127
2128         /* lock eth irq */
2129         spin_lock_irq (&sc->sbm_lock);
2130
2131         /*
2132          * Put the buffer on the transmit ring.  If we
2133          * don't have room, stop the queue.
2134          */
2135
2136         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2137                 /* XXX save skb that we could not send */
2138                 netif_stop_queue(dev);
2139                 spin_unlock_irq(&sc->sbm_lock);
2140
2141                 return 1;
2142         }
2143
2144         dev->trans_start = jiffies;
2145
2146         spin_unlock_irq (&sc->sbm_lock);
2147
2148         return 0;
2149 }
2150
2151 /**********************************************************************
2152  *  SBMAC_SETMULTI(sc)
2153  *
2154  *  Reprogram the multicast table into the hardware, given
2155  *  the list of multicasts associated with the interface
2156  *  structure.
2157  *
2158  *  Input parameters:
2159  *         sc - softc
2160  *
2161  *  Return value:
2162  *         nothing
2163  ********************************************************************* */
2164
2165 static void sbmac_setmulti(struct sbmac_softc *sc)
2166 {
2167         uint64_t reg;
2168         volatile void __iomem *port;
2169         int idx;
2170         struct dev_mc_list *mclist;
2171         struct net_device *dev = sc->sbm_dev;
2172
2173         /*
2174          * Clear out entire multicast table.  We do this by nuking
2175          * the entire hash table and all the direct matches except
2176          * the first one, which is used for our station address
2177          */
2178
2179         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2180                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t));
2181                 __raw_writeq(0, port);
2182         }
2183
2184         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2185                 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t));
2186                 __raw_writeq(0, port);
2187         }
2188
2189         /*
2190          * Clear the filter to say we don't want any multicasts.
2191          */
2192
2193         reg = __raw_readq(sc->sbm_rxfilter);
2194         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2195         __raw_writeq(reg, sc->sbm_rxfilter);
2196
2197         if (dev->flags & IFF_ALLMULTI) {
2198                 /*
2199                  * Enable ALL multicasts.  Do this by inverting the
2200                  * multicast enable bit.
2201                  */
2202                 reg = __raw_readq(sc->sbm_rxfilter);
2203                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2204                 __raw_writeq(reg, sc->sbm_rxfilter);
2205                 return;
2206         }
2207
2208
2209         /*
2210          * Progam new multicast entries.  For now, only use the
2211          * perfect filter.  In the future we'll need to use the
2212          * hash filter if the perfect filter overflows
2213          */
2214
2215         /* XXX only using perfect filter for now, need to use hash
2216          * XXX if the table overflows */
2217
2218         idx = 1;                /* skip station address */
2219         mclist = dev->mc_list;
2220         while (mclist && (idx < MAC_ADDR_COUNT)) {
2221                 reg = sbmac_addr2reg(mclist->dmi_addr);
2222                 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t));
2223                 __raw_writeq(reg, port);
2224                 idx++;
2225                 mclist = mclist->next;
2226         }
2227
2228         /*
2229          * Enable the "accept multicast bits" if we programmed at least one
2230          * multicast.
2231          */
2232
2233         if (idx > 1) {
2234                 reg = __raw_readq(sc->sbm_rxfilter);
2235                 reg |= M_MAC_MCAST_EN;
2236                 __raw_writeq(reg, sc->sbm_rxfilter);
2237         }
2238 }
2239
2240
2241
2242 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2243 /**********************************************************************
2244  *  SBMAC_PARSE_XDIGIT(str)
2245  *
2246  *  Parse a hex digit, returning its value
2247  *
2248  *  Input parameters:
2249  *         str - character
2250  *
2251  *  Return value:
2252  *         hex value, or -1 if invalid
2253  ********************************************************************* */
2254
2255 static int sbmac_parse_xdigit(char str)
2256 {
2257         int digit;
2258
2259         if ((str >= '0') && (str <= '9'))
2260                 digit = str - '0';
2261         else if ((str >= 'a') && (str <= 'f'))
2262                 digit = str - 'a' + 10;
2263         else if ((str >= 'A') && (str <= 'F'))
2264                 digit = str - 'A' + 10;
2265         else
2266                 return -1;
2267
2268         return digit;
2269 }
2270
2271 /**********************************************************************
2272  *  SBMAC_PARSE_HWADDR(str,hwaddr)
2273  *
2274  *  Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2275  *  Ethernet address.
2276  *
2277  *  Input parameters:
2278  *         str - string
2279  *         hwaddr - pointer to hardware address
2280  *
2281  *  Return value:
2282  *         0 if ok, else -1
2283  ********************************************************************* */
2284
2285 static int sbmac_parse_hwaddr(char *str, unsigned char *hwaddr)
2286 {
2287         int digit1,digit2;
2288         int idx = 6;
2289
2290         while (*str && (idx > 0)) {
2291                 digit1 = sbmac_parse_xdigit(*str);
2292                 if (digit1 < 0)
2293                         return -1;
2294                 str++;
2295                 if (!*str)
2296                         return -1;
2297
2298                 if ((*str == ':') || (*str == '-')) {
2299                         digit2 = digit1;
2300                         digit1 = 0;
2301                 }
2302                 else {
2303                         digit2 = sbmac_parse_xdigit(*str);
2304                         if (digit2 < 0)
2305                                 return -1;
2306                         str++;
2307                 }
2308
2309                 *hwaddr++ = (digit1 << 4) | digit2;
2310                 idx--;
2311
2312                 if (*str == '-')
2313                         str++;
2314                 if (*str == ':')
2315                         str++;
2316         }
2317         return 0;
2318 }
2319 #endif
2320
2321 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2322 {
2323         if (new_mtu >  ENET_PACKET_SIZE)
2324                 return -EINVAL;
2325         _dev->mtu = new_mtu;
2326         printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2327         return 0;
2328 }
2329
2330 /**********************************************************************
2331  *  SBMAC_INIT(dev)
2332  *
2333  *  Attach routine - init hardware and hook ourselves into linux
2334  *
2335  *  Input parameters:
2336  *         dev - net_device structure
2337  *
2338  *  Return value:
2339  *         status
2340  ********************************************************************* */
2341
2342 static int sbmac_init(struct net_device *dev, int idx)
2343 {
2344         struct sbmac_softc *sc;
2345         unsigned char *eaddr;
2346         uint64_t ea_reg;
2347         int i;
2348         int err;
2349
2350         sc = netdev_priv(dev);
2351
2352         /* Determine controller base address */
2353
2354         sc->sbm_base = IOADDR(dev->base_addr);
2355         sc->sbm_dev = dev;
2356         sc->sbe_idx = idx;
2357
2358         eaddr = sc->sbm_hwaddr;
2359
2360         /*
2361          * Read the ethernet address.  The firwmare left this programmed
2362          * for us in the ethernet address register for each mac.
2363          */
2364
2365         ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR);
2366         __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR);
2367         for (i = 0; i < 6; i++) {
2368                 eaddr[i] = (uint8_t) (ea_reg & 0xFF);
2369                 ea_reg >>= 8;
2370         }
2371
2372         for (i = 0; i < 6; i++) {
2373                 dev->dev_addr[i] = eaddr[i];
2374         }
2375
2376
2377         /*
2378          * Init packet size
2379          */
2380
2381         sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN;
2382
2383         /*
2384          * Initialize context (get pointers to registers and stuff), then
2385          * allocate the memory for the descriptor tables.
2386          */
2387
2388         sbmac_initctx(sc);
2389
2390         /*
2391          * Set up Linux device callins
2392          */
2393
2394         spin_lock_init(&(sc->sbm_lock));
2395
2396         dev->open               = sbmac_open;
2397         dev->hard_start_xmit    = sbmac_start_tx;
2398         dev->stop               = sbmac_close;
2399         dev->get_stats          = sbmac_get_stats;
2400         dev->set_multicast_list = sbmac_set_rx_mode;
2401         dev->do_ioctl           = sbmac_mii_ioctl;
2402         dev->tx_timeout         = sbmac_tx_timeout;
2403         dev->watchdog_timeo     = TX_TIMEOUT;
2404
2405         dev->change_mtu         = sb1250_change_mtu;
2406
2407         /* This is needed for PASS2 for Rx H/W checksum feature */
2408         sbmac_set_iphdr_offset(sc);
2409
2410         err = register_netdev(dev);
2411         if (err)
2412                 goto out_uninit;
2413
2414         if (sc->rx_hw_checksum == ENABLE) {
2415                 printk(KERN_INFO "%s: enabling TCP rcv checksum\n",
2416                         sc->sbm_dev->name);
2417         }
2418
2419         /*
2420          * Display Ethernet address (this is called during the config
2421          * process so we need to finish off the config message that
2422          * was being displayed)
2423          */
2424         printk(KERN_INFO
2425                "%s: SiByte Ethernet at 0x%08lX, address: %02X:%02X:%02X:%02X:%02X:%02X\n",
2426                dev->name, dev->base_addr,
2427                eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2428
2429
2430         return 0;
2431
2432 out_uninit:
2433         sbmac_uninitctx(sc);
2434
2435         return err;
2436 }
2437
2438
2439 static int sbmac_open(struct net_device *dev)
2440 {
2441         struct sbmac_softc *sc = netdev_priv(dev);
2442
2443         if (debug > 1) {
2444                 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2445         }
2446
2447         /*
2448          * map/route interrupt (clear status first, in case something
2449          * weird is pending; we haven't initialized the mac registers
2450          * yet)
2451          */
2452
2453         __raw_readq(sc->sbm_isr);
2454         if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev))
2455                 return -EBUSY;
2456
2457         /*
2458          * Probe phy address
2459          */
2460
2461         if(sbmac_mii_probe(dev) == -1) {
2462                 printk("%s: failed to probe PHY.\n", dev->name);
2463                 return -EINVAL;
2464         }
2465
2466         /*
2467          * Configure default speed
2468          */
2469
2470         sbmac_mii_poll(sc,noisy_mii);
2471
2472         /*
2473          * Turn on the channel
2474          */
2475
2476         sbmac_set_channel_state(sc,sbmac_state_on);
2477
2478         /*
2479          * XXX Station address is in dev->dev_addr
2480          */
2481
2482         if (dev->if_port == 0)
2483                 dev->if_port = 0;
2484
2485         netif_start_queue(dev);
2486
2487         sbmac_set_rx_mode(dev);
2488
2489         /* Set the timer to check for link beat. */
2490         init_timer(&sc->sbm_timer);
2491         sc->sbm_timer.expires = jiffies + 2 * HZ/100;
2492         sc->sbm_timer.data = (unsigned long)dev;
2493         sc->sbm_timer.function = &sbmac_timer;
2494         add_timer(&sc->sbm_timer);
2495
2496         return 0;
2497 }
2498
2499 static int sbmac_mii_probe(struct net_device *dev)
2500 {
2501         int i;
2502         struct sbmac_softc *s = netdev_priv(dev);
2503         u16 bmsr, id1, id2;
2504         u32 vendor, device;
2505
2506         for (i=1; i<31; i++) {
2507         bmsr = sbmac_mii_read(s, i, MII_BMSR);
2508                 if (bmsr != 0) {
2509                         s->sbm_phys[0] = i;
2510                         id1 = sbmac_mii_read(s, i, MII_PHYIDR1);
2511                         id2 = sbmac_mii_read(s, i, MII_PHYIDR2);
2512                         vendor = ((u32)id1 << 6) | ((id2 >> 10) & 0x3f);
2513                         device = (id2 >> 4) & 0x3f;
2514
2515                         printk(KERN_INFO "%s: found phy %d, vendor %06x part %02x\n",
2516                                 dev->name, i, vendor, device);
2517                         return i;
2518                 }
2519         }
2520         return -1;
2521 }
2522
2523
2524 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2525 {
2526     int bmsr,bmcr,k1stsr,anlpar;
2527     int chg;
2528     char buffer[100];
2529     char *p = buffer;
2530
2531     /* Read the mode status and mode control registers. */
2532     bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2533     bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2534
2535     /* get the link partner status */
2536     anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2537
2538     /* if supported, read the 1000baseT register */
2539     if (bmsr & BMSR_1000BT_XSR) {
2540         k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2541         }
2542     else {
2543         k1stsr = 0;
2544         }
2545
2546     chg = 0;
2547
2548     if ((bmsr & BMSR_LINKSTAT) == 0) {
2549         /*
2550          * If link status is down, clear out old info so that when
2551          * it comes back up it will force us to reconfigure speed
2552          */
2553         s->sbm_phy_oldbmsr = 0;
2554         s->sbm_phy_oldanlpar = 0;
2555         s->sbm_phy_oldk1stsr = 0;
2556         return 0;
2557         }
2558
2559     if ((s->sbm_phy_oldbmsr != bmsr) ||
2560         (s->sbm_phy_oldanlpar != anlpar) ||
2561         (s->sbm_phy_oldk1stsr != k1stsr)) {
2562         if (debug > 1) {
2563             printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x  k1stsr:%x/%x\n",
2564                s->sbm_dev->name,
2565                s->sbm_phy_oldbmsr,bmsr,
2566                s->sbm_phy_oldanlpar,anlpar,
2567                s->sbm_phy_oldk1stsr,k1stsr);
2568             }
2569         s->sbm_phy_oldbmsr = bmsr;
2570         s->sbm_phy_oldanlpar = anlpar;
2571         s->sbm_phy_oldk1stsr = k1stsr;
2572         chg = 1;
2573         }
2574
2575     if (chg == 0)
2576             return 0;
2577
2578     p += sprintf(p,"Link speed: ");
2579
2580     if (k1stsr & K1STSR_LP1KFD) {
2581         s->sbm_speed = sbmac_speed_1000;
2582         s->sbm_duplex = sbmac_duplex_full;
2583         s->sbm_fc = sbmac_fc_frame;
2584         p += sprintf(p,"1000BaseT FDX");
2585         }
2586     else if (k1stsr & K1STSR_LP1KHD) {
2587         s->sbm_speed = sbmac_speed_1000;
2588         s->sbm_duplex = sbmac_duplex_half;
2589         s->sbm_fc = sbmac_fc_disabled;
2590         p += sprintf(p,"1000BaseT HDX");
2591         }
2592     else if (anlpar & ANLPAR_TXFD) {
2593         s->sbm_speed = sbmac_speed_100;
2594         s->sbm_duplex = sbmac_duplex_full;
2595         s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2596         p += sprintf(p,"100BaseT FDX");
2597         }
2598     else if (anlpar & ANLPAR_TXHD) {
2599         s->sbm_speed = sbmac_speed_100;
2600         s->sbm_duplex = sbmac_duplex_half;
2601         s->sbm_fc = sbmac_fc_disabled;
2602         p += sprintf(p,"100BaseT HDX");
2603         }
2604     else if (anlpar & ANLPAR_10FD) {
2605         s->sbm_speed = sbmac_speed_10;
2606         s->sbm_duplex = sbmac_duplex_full;
2607         s->sbm_fc = sbmac_fc_frame;
2608         p += sprintf(p,"10BaseT FDX");
2609         }
2610     else if (anlpar & ANLPAR_10HD) {
2611         s->sbm_speed = sbmac_speed_10;
2612         s->sbm_duplex = sbmac_duplex_half;
2613         s->sbm_fc = sbmac_fc_collision;
2614         p += sprintf(p,"10BaseT HDX");
2615         }
2616     else {
2617         p += sprintf(p,"Unknown");
2618         }
2619
2620     if (noisy) {
2621             printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2622             }
2623
2624     return 1;
2625 }
2626
2627
2628 static void sbmac_timer(unsigned long data)
2629 {
2630         struct net_device *dev = (struct net_device *)data;
2631         struct sbmac_softc *sc = netdev_priv(dev);
2632         int next_tick = HZ;
2633         int mii_status;
2634
2635         spin_lock_irq (&sc->sbm_lock);
2636
2637         /* make IFF_RUNNING follow the MII status bit "Link established" */
2638         mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2639
2640         if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2641                 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2642                 if (mii_status & BMSR_LINKSTAT) {
2643                         netif_carrier_on(dev);
2644                 }
2645                 else {
2646                         netif_carrier_off(dev);
2647                 }
2648         }
2649
2650         /*
2651          * Poll the PHY to see what speed we should be running at
2652          */
2653
2654         if (sbmac_mii_poll(sc,noisy_mii)) {
2655                 if (sc->sbm_state != sbmac_state_off) {
2656                         /*
2657                          * something changed, restart the channel
2658                          */
2659                         if (debug > 1) {
2660                                 printk("%s: restarting channel because speed changed\n",
2661                                        sc->sbm_dev->name);
2662                         }
2663                         sbmac_channel_stop(sc);
2664                         sbmac_channel_start(sc);
2665                 }
2666         }
2667
2668         spin_unlock_irq (&sc->sbm_lock);
2669
2670         sc->sbm_timer.expires = jiffies + next_tick;
2671         add_timer(&sc->sbm_timer);
2672 }
2673
2674
2675 static void sbmac_tx_timeout (struct net_device *dev)
2676 {
2677         struct sbmac_softc *sc = netdev_priv(dev);
2678
2679         spin_lock_irq (&sc->sbm_lock);
2680
2681
2682         dev->trans_start = jiffies;
2683         sc->sbm_stats.tx_errors++;
2684
2685         spin_unlock_irq (&sc->sbm_lock);
2686
2687         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2688 }
2689
2690
2691
2692
2693 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2694 {
2695         struct sbmac_softc *sc = netdev_priv(dev);
2696         unsigned long flags;
2697
2698         spin_lock_irqsave(&sc->sbm_lock, flags);
2699
2700         /* XXX update other stats here */
2701
2702         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2703
2704         return &sc->sbm_stats;
2705 }
2706
2707
2708
2709 static void sbmac_set_rx_mode(struct net_device *dev)
2710 {
2711         unsigned long flags;
2712         int msg_flag = 0;
2713         struct sbmac_softc *sc = netdev_priv(dev);
2714
2715         spin_lock_irqsave(&sc->sbm_lock, flags);
2716         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2717                 /*
2718                  * Promiscuous changed.
2719                  */
2720
2721                 if (dev->flags & IFF_PROMISC) {
2722                         /* Unconditionally log net taps. */
2723                         msg_flag = 1;
2724                         sbmac_promiscuous_mode(sc,1);
2725                 }
2726                 else {
2727                         msg_flag = 2;
2728                         sbmac_promiscuous_mode(sc,0);
2729                 }
2730         }
2731         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2732
2733         if (msg_flag) {
2734                 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n",
2735                        dev->name,(msg_flag==1)?"en":"dis");
2736         }
2737
2738         /*
2739          * Program the multicasts.  Do this every time.
2740          */
2741
2742         sbmac_setmulti(sc);
2743
2744 }
2745
2746 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2747 {
2748         struct sbmac_softc *sc = netdev_priv(dev);
2749         u16 *data = (u16 *)&rq->ifr_ifru;
2750         unsigned long flags;
2751         int retval;
2752
2753         spin_lock_irqsave(&sc->sbm_lock, flags);
2754         retval = 0;
2755
2756         switch(cmd) {
2757         case SIOCDEVPRIVATE:            /* Get the address of the PHY in use. */
2758                 data[0] = sc->sbm_phys[0] & 0x1f;
2759                 /* Fall Through */
2760         case SIOCDEVPRIVATE+1:          /* Read the specified MII register. */
2761                 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2762                 break;
2763         case SIOCDEVPRIVATE+2:          /* Write the specified MII register */
2764                 if (!capable(CAP_NET_ADMIN)) {
2765                         retval = -EPERM;
2766                         break;
2767                 }
2768                 if (debug > 1) {
2769                     printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2770                        data[0],data[1],data[2]);
2771                     }
2772                 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2773                 break;
2774         default:
2775                 retval = -EOPNOTSUPP;
2776         }
2777
2778         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2779         return retval;
2780 }
2781
2782 static int sbmac_close(struct net_device *dev)
2783 {
2784         struct sbmac_softc *sc = netdev_priv(dev);
2785         unsigned long flags;
2786         int irq;
2787
2788         sbmac_set_channel_state(sc,sbmac_state_off);
2789
2790         del_timer_sync(&sc->sbm_timer);
2791
2792         spin_lock_irqsave(&sc->sbm_lock, flags);
2793
2794         netif_stop_queue(dev);
2795
2796         if (debug > 1) {
2797                 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2798         }
2799
2800         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2801
2802         irq = dev->irq;
2803         synchronize_irq(irq);
2804         free_irq(irq, dev);
2805
2806         sbdma_emptyring(&(sc->sbm_txdma));
2807         sbdma_emptyring(&(sc->sbm_rxdma));
2808
2809         return 0;
2810 }
2811
2812
2813
2814 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR) || defined(SBMAC_ETH3_HWADDR)
2815 static void
2816 sbmac_setup_hwaddr(int chan,char *addr)
2817 {
2818         uint8_t eaddr[6];
2819         uint64_t val;
2820         unsigned long port;
2821
2822         port = A_MAC_CHANNEL_BASE(chan);
2823         sbmac_parse_hwaddr(addr,eaddr);
2824         val = sbmac_addr2reg(eaddr);
2825         __raw_writeq(val, IOADDR(port+R_MAC_ETHERNET_ADDR));
2826         val = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2827 }
2828 #endif
2829
2830 static struct net_device *dev_sbmac[MAX_UNITS];
2831
2832 static int __init
2833 sbmac_init_module(void)
2834 {
2835         int idx;
2836         struct net_device *dev;
2837         unsigned long port;
2838         int chip_max_units;
2839
2840         /* Set the number of available units based on the SOC type.  */
2841         switch (soc_type) {
2842         case K_SYS_SOC_TYPE_BCM1250:
2843         case K_SYS_SOC_TYPE_BCM1250_ALT:
2844                 chip_max_units = 3;
2845                 break;
2846         case K_SYS_SOC_TYPE_BCM1120:
2847         case K_SYS_SOC_TYPE_BCM1125:
2848         case K_SYS_SOC_TYPE_BCM1125H:
2849         case K_SYS_SOC_TYPE_BCM1250_ALT2: /* Hybrid */
2850                 chip_max_units = 2;
2851                 break;
2852         case K_SYS_SOC_TYPE_BCM1x55:
2853         case K_SYS_SOC_TYPE_BCM1x80:
2854                 chip_max_units = 4;
2855                 break;
2856         default:
2857                 chip_max_units = 0;
2858                 break;
2859         }
2860         if (chip_max_units > MAX_UNITS)
2861                 chip_max_units = MAX_UNITS;
2862
2863         /*
2864          * For bringup when not using the firmware, we can pre-fill
2865          * the MAC addresses using the environment variables
2866          * specified in this file (or maybe from the config file?)
2867          */
2868 #ifdef SBMAC_ETH0_HWADDR
2869         if (chip_max_units > 0)
2870           sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2871 #endif
2872 #ifdef SBMAC_ETH1_HWADDR
2873         if (chip_max_units > 1)
2874           sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2875 #endif
2876 #ifdef SBMAC_ETH2_HWADDR
2877         if (chip_max_units > 2)
2878           sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2879 #endif
2880 #ifdef SBMAC_ETH3_HWADDR
2881         if (chip_max_units > 3)
2882           sbmac_setup_hwaddr(3,SBMAC_ETH3_HWADDR);
2883 #endif
2884
2885         /*
2886          * Walk through the Ethernet controllers and find
2887          * those who have their MAC addresses set.
2888          */
2889         for (idx = 0; idx < chip_max_units; idx++) {
2890
2891                 /*
2892                  * This is the base address of the MAC.
2893                  */
2894
2895                 port = A_MAC_CHANNEL_BASE(idx);
2896
2897                 /*
2898                  * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2899                  * value for us by the firmware if we're going to use this MAC.
2900                  * If we find a zero, skip this MAC.
2901                  */
2902
2903                 sbmac_orig_hwaddr[idx] = __raw_readq(IOADDR(port+R_MAC_ETHERNET_ADDR));
2904                 if (sbmac_orig_hwaddr[idx] == 0) {
2905                         printk(KERN_DEBUG "sbmac: not configuring MAC at "
2906                                "%lx\n", port);
2907                     continue;
2908                 }
2909
2910                 /*
2911                  * Okay, cool.  Initialize this MAC.
2912                  */
2913
2914                 dev = alloc_etherdev(sizeof(struct sbmac_softc));
2915                 if (!dev)
2916                         return -ENOMEM; /* return ENOMEM */
2917
2918                 printk(KERN_DEBUG "sbmac: configuring MAC at %lx\n", port);
2919
2920                 dev->irq = UNIT_INT(idx);
2921                 dev->base_addr = port;
2922                 dev->mem_end = 0;
2923                 if (sbmac_init(dev, idx)) {
2924                         port = A_MAC_CHANNEL_BASE(idx);
2925                         __raw_writeq(sbmac_orig_hwaddr[idx], IOADDR(port+R_MAC_ETHERNET_ADDR));
2926                         free_netdev(dev);
2927                         continue;
2928                 }
2929                 dev_sbmac[idx] = dev;
2930         }
2931         return 0;
2932 }
2933
2934
2935 static void __exit
2936 sbmac_cleanup_module(void)
2937 {
2938         struct net_device *dev;
2939         int idx;
2940
2941         for (idx = 0; idx < MAX_UNITS; idx++) {
2942                 struct sbmac_softc *sc;
2943                 dev = dev_sbmac[idx];
2944                 if (!dev)
2945                         continue;
2946
2947                 sc = netdev_priv(dev);
2948                 unregister_netdev(dev);
2949                 sbmac_uninitctx(sc);
2950                 free_netdev(dev);
2951         }
2952 }
2953
2954 module_init(sbmac_init_module);
2955 module_exit(sbmac_cleanup_module);