1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
11 #define TG3_64BIT_REG_HIGH 0x00UL
12 #define TG3_64BIT_REG_LOW 0x04UL
14 /* Descriptor block info. */
15 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
16 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
17 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
18 #define BDINFO_FLAGS_DISABLED 0x00000002
19 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
20 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
21 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
22 #define TG3_BDINFO_SIZE 0x10UL
24 #define RX_COPY_THRESHOLD 256
26 #define RX_STD_MAX_SIZE 1536
27 #define RX_STD_MAX_SIZE_5705 512
28 #define RX_JUMBO_MAX_SIZE 0xdeadbeef /* XXX */
30 /* First 256 bytes are a mirror of PCI config space. */
31 #define TG3PCI_VENDOR 0x00000000
32 #define TG3PCI_VENDOR_BROADCOM 0x14e4
33 #define TG3PCI_DEVICE 0x00000002
34 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
35 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
36 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
37 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
38 #define TG3PCI_COMMAND 0x00000004
39 #define TG3PCI_STATUS 0x00000006
40 #define TG3PCI_CCREVID 0x00000008
41 #define TG3PCI_CACHELINESZ 0x0000000c
42 #define TG3PCI_LATTIMER 0x0000000d
43 #define TG3PCI_HEADERTYPE 0x0000000e
44 #define TG3PCI_BIST 0x0000000f
45 #define TG3PCI_BASE0_LOW 0x00000010
46 #define TG3PCI_BASE0_HIGH 0x00000014
47 /* 0x18 --> 0x2c unused */
48 #define TG3PCI_SUBSYSVENID 0x0000002c
49 #define TG3PCI_SUBSYSID 0x0000002e
50 #define TG3PCI_ROMADDR 0x00000030
51 #define TG3PCI_CAPLIST 0x00000034
52 /* 0x35 --> 0x3c unused */
53 #define TG3PCI_IRQ_LINE 0x0000003c
54 #define TG3PCI_IRQ_PIN 0x0000003d
55 #define TG3PCI_MIN_GNT 0x0000003e
56 #define TG3PCI_MAX_LAT 0x0000003f
57 #define TG3PCI_X_CAPS 0x00000040
58 #define PCIX_CAPS_RELAXED_ORDERING 0x00020000
59 #define PCIX_CAPS_SPLIT_MASK 0x00700000
60 #define PCIX_CAPS_SPLIT_SHIFT 20
61 #define PCIX_CAPS_BURST_MASK 0x000c0000
62 #define PCIX_CAPS_BURST_SHIFT 18
63 #define PCIX_CAPS_MAX_BURST_CPIOB 2
64 #define TG3PCI_PM_CAP_PTR 0x00000041
65 #define TG3PCI_X_COMMAND 0x00000042
66 #define TG3PCI_X_STATUS 0x00000044
67 #define TG3PCI_PM_CAP_ID 0x00000048
68 #define TG3PCI_VPD_CAP_PTR 0x00000049
69 #define TG3PCI_PM_CAPS 0x0000004a
70 #define TG3PCI_PM_CTRL_STAT 0x0000004c
71 #define TG3PCI_BR_SUPP_EXT 0x0000004e
72 #define TG3PCI_PM_DATA 0x0000004f
73 #define TG3PCI_VPD_CAP_ID 0x00000050
74 #define TG3PCI_MSI_CAP_PTR 0x00000051
75 #define TG3PCI_VPD_ADDR_FLAG 0x00000052
76 #define VPD_ADDR_FLAG_WRITE 0x00008000
77 #define TG3PCI_VPD_DATA 0x00000054
78 #define TG3PCI_MSI_CAP_ID 0x00000058
79 #define TG3PCI_NXT_CAP_PTR 0x00000059
80 #define TG3PCI_MSI_CTRL 0x0000005a
81 #define TG3PCI_MSI_ADDR_LOW 0x0000005c
82 #define TG3PCI_MSI_ADDR_HIGH 0x00000060
83 #define TG3PCI_MSI_DATA 0x00000064
84 /* 0x66 --> 0x68 unused */
85 #define TG3PCI_MISC_HOST_CTRL 0x00000068
86 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
87 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
88 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
89 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
90 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
91 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
92 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
93 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
94 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
95 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
96 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
97 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
98 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
99 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
100 MISC_HOST_CTRL_CHIPREV_SHIFT)
101 #define CHIPREV_ID_5700_A0 0x7000
102 #define CHIPREV_ID_5700_A1 0x7001
103 #define CHIPREV_ID_5700_B0 0x7100
104 #define CHIPREV_ID_5700_B1 0x7101
105 #define CHIPREV_ID_5700_B3 0x7102
106 #define CHIPREV_ID_5700_ALTIMA 0x7104
107 #define CHIPREV_ID_5700_C0 0x7200
108 #define CHIPREV_ID_5701_A0 0x0000
109 #define CHIPREV_ID_5701_B0 0x0100
110 #define CHIPREV_ID_5701_B2 0x0102
111 #define CHIPREV_ID_5701_B5 0x0105
112 #define CHIPREV_ID_5703_A0 0x1000
113 #define CHIPREV_ID_5703_A1 0x1001
114 #define CHIPREV_ID_5703_A2 0x1002
115 #define CHIPREV_ID_5703_A3 0x1003
116 #define CHIPREV_ID_5704_A0 0x2000
117 #define CHIPREV_ID_5704_A1 0x2001
118 #define CHIPREV_ID_5704_A2 0x2002
119 #define CHIPREV_ID_5705_A0 0x3000
120 #define CHIPREV_ID_5705_A1 0x3001
121 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
122 #define ASIC_REV_5700 0x07
123 #define ASIC_REV_5701 0x00
124 #define ASIC_REV_5703 0x01
125 #define ASIC_REV_5704 0x02
126 #define ASIC_REV_5705 0x03
127 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
128 #define CHIPREV_5700_AX 0x70
129 #define CHIPREV_5700_BX 0x71
130 #define CHIPREV_5700_CX 0x72
131 #define CHIPREV_5701_AX 0x00
132 #define CHIPREV_5703_AX 0x10
133 #define CHIPREV_5704_AX 0x20
134 #define CHIPREV_5704_BX 0x21
135 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
136 #define METAL_REV_A0 0x00
137 #define METAL_REV_A1 0x01
138 #define METAL_REV_B0 0x00
139 #define METAL_REV_B1 0x01
140 #define METAL_REV_B2 0x02
141 #define TG3PCI_DMA_RW_CTRL 0x0000006c
142 #define DMA_RWCTRL_MIN_DMA 0x000000ff
143 #define DMA_RWCTRL_MIN_DMA_SHIFT 0
144 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
145 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
146 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
147 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
148 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
149 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
150 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
151 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
152 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
153 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
154 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
155 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
156 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
157 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
158 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
159 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
160 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
161 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
162 #define DMA_RWCTRL_ONE_DMA 0x00004000
163 #define DMA_RWCTRL_READ_WATER 0x00070000
164 #define DMA_RWCTRL_READ_WATER_SHIFT 16
165 #define DMA_RWCTRL_WRITE_WATER 0x00380000
166 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
167 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
168 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
169 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
170 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
171 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
172 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
173 #define TG3PCI_PCISTATE 0x00000070
174 #define PCISTATE_FORCE_RESET 0x00000001
175 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
176 #define PCISTATE_CONV_PCI_MODE 0x00000004
177 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
178 #define PCISTATE_BUS_32BIT 0x00000010
179 #define PCISTATE_ROM_ENABLE 0x00000020
180 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
181 #define PCISTATE_FLAT_VIEW 0x00000100
182 #define PCISTATE_RETRY_SAME_DMA 0x00002000
183 #define TG3PCI_CLOCK_CTRL 0x00000074
184 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
185 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
186 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
187 #define CLOCK_CTRL_ALTCLK 0x00001000
188 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
189 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
190 #define CLOCK_CTRL_625_CORE 0x00100000
191 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
192 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
193 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
194 #define TG3PCI_REG_BASE_ADDR 0x00000078
195 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
196 #define TG3PCI_REG_DATA 0x00000080
197 #define TG3PCI_MEM_WIN_DATA 0x00000084
198 #define TG3PCI_MODE_CTRL 0x00000088
199 #define TG3PCI_MISC_CFG 0x0000008c
200 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
201 /* 0x94 --> 0x98 unused */
202 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
203 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
204 #define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
205 /* 0xb0 --> 0x100 unused */
207 /* 0x100 --> 0x200 unused */
209 /* Mailbox registers */
210 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
211 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
212 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
213 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
214 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
215 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
216 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
217 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
218 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
219 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
220 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
221 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
222 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
223 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
224 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
225 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
226 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
227 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
228 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
229 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
230 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
231 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
232 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
233 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
234 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
235 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
236 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
237 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
238 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
239 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
240 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
241 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
242 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
243 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
244 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
245 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
246 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
247 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
248 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
249 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
250 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
251 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
252 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
253 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
254 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
255 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
256 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
257 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
258 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
259 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
260 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
261 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
262 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
263 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
264 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
265 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
266 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
267 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
268 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
269 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
270 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
271 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
272 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
273 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
275 /* MAC control registers */
276 #define MAC_MODE 0x00000400
277 #define MAC_MODE_RESET 0x00000001
278 #define MAC_MODE_HALF_DUPLEX 0x00000002
279 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
280 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
281 #define MAC_MODE_PORT_MODE_GMII 0x00000008
282 #define MAC_MODE_PORT_MODE_MII 0x00000004
283 #define MAC_MODE_PORT_MODE_NONE 0x00000000
284 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
285 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
286 #define MAC_MODE_TX_BURSTING 0x00000100
287 #define MAC_MODE_MAX_DEFER 0x00000200
288 #define MAC_MODE_LINK_POLARITY 0x00000400
289 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
290 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
291 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
292 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
293 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
294 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
295 #define MAC_MODE_SEND_CONFIGS 0x00020000
296 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
297 #define MAC_MODE_ACPI_ENABLE 0x00080000
298 #define MAC_MODE_MIP_ENABLE 0x00100000
299 #define MAC_MODE_TDE_ENABLE 0x00200000
300 #define MAC_MODE_RDE_ENABLE 0x00400000
301 #define MAC_MODE_FHDE_ENABLE 0x00800000
302 #define MAC_STATUS 0x00000404
303 #define MAC_STATUS_PCS_SYNCED 0x00000001
304 #define MAC_STATUS_SIGNAL_DET 0x00000002
305 #define MAC_STATUS_RCVD_CFG 0x00000004
306 #define MAC_STATUS_CFG_CHANGED 0x00000008
307 #define MAC_STATUS_SYNC_CHANGED 0x00000010
308 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
309 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
310 #define MAC_STATUS_MI_COMPLETION 0x00400000
311 #define MAC_STATUS_MI_INTERRUPT 0x00800000
312 #define MAC_STATUS_AP_ERROR 0x01000000
313 #define MAC_STATUS_ODI_ERROR 0x02000000
314 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
315 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
316 #define MAC_EVENT 0x00000408
317 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
318 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
319 #define MAC_EVENT_MI_COMPLETION 0x00400000
320 #define MAC_EVENT_MI_INTERRUPT 0x00800000
321 #define MAC_EVENT_AP_ERROR 0x01000000
322 #define MAC_EVENT_ODI_ERROR 0x02000000
323 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
324 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
325 #define MAC_LED_CTRL 0x0000040c
326 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
327 #define LED_CTRL_1000MBPS_ON 0x00000002
328 #define LED_CTRL_100MBPS_ON 0x00000004
329 #define LED_CTRL_10MBPS_ON 0x00000008
330 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
331 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
332 #define LED_CTRL_TRAFFIC_LED 0x00000040
333 #define LED_CTRL_1000MBPS_STATUS 0x00000080
334 #define LED_CTRL_100MBPS_STATUS 0x00000100
335 #define LED_CTRL_10MBPS_STATUS 0x00000200
336 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
337 #define LED_CTRL_MAC_MODE 0x00000000
338 #define LED_CTRL_PHY_MODE_1 0x00000800
339 #define LED_CTRL_PHY_MODE_2 0x00001000
340 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
341 #define LED_CTRL_BLINK_RATE_SHIFT 19
342 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
343 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
344 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
345 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
346 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
347 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
348 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
349 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
350 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
351 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
352 #define MAC_ACPI_MBUF_PTR 0x00000430
353 #define MAC_ACPI_LEN_OFFSET 0x00000434
354 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
355 #define ACPI_LENOFF_LEN_SHIFT 0
356 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
357 #define ACPI_LENOFF_OFF_SHIFT 16
358 #define MAC_TX_BACKOFF_SEED 0x00000438
359 #define TX_BACKOFF_SEED_MASK 0x000003ff
360 #define MAC_RX_MTU_SIZE 0x0000043c
361 #define RX_MTU_SIZE_MASK 0x0000ffff
362 #define MAC_PCS_TEST 0x00000440
363 #define PCS_TEST_PATTERN_MASK 0x000fffff
364 #define PCS_TEST_PATTERN_SHIFT 0
365 #define PCS_TEST_ENABLE 0x00100000
366 #define MAC_TX_AUTO_NEG 0x00000444
367 #define TX_AUTO_NEG_MASK 0x0000ffff
368 #define TX_AUTO_NEG_SHIFT 0
369 #define MAC_RX_AUTO_NEG 0x00000448
370 #define RX_AUTO_NEG_MASK 0x0000ffff
371 #define RX_AUTO_NEG_SHIFT 0
372 #define MAC_MI_COM 0x0000044c
373 #define MI_COM_CMD_MASK 0x0c000000
374 #define MI_COM_CMD_WRITE 0x04000000
375 #define MI_COM_CMD_READ 0x08000000
376 #define MI_COM_READ_FAILED 0x10000000
377 #define MI_COM_START 0x20000000
378 #define MI_COM_BUSY 0x20000000
379 #define MI_COM_PHY_ADDR_MASK 0x03e00000
380 #define MI_COM_PHY_ADDR_SHIFT 21
381 #define MI_COM_REG_ADDR_MASK 0x001f0000
382 #define MI_COM_REG_ADDR_SHIFT 16
383 #define MI_COM_DATA_MASK 0x0000ffff
384 #define MAC_MI_STAT 0x00000450
385 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
386 #define MAC_MI_MODE 0x00000454
387 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
388 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
389 #define MAC_MI_MODE_AUTO_POLL 0x00000010
390 #define MAC_MI_MODE_CORE_CLK_62MHZ 0x00008000
391 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
392 #define MAC_AUTO_POLL_STATUS 0x00000458
393 #define MAC_AUTO_POLL_ERROR 0x00000001
394 #define MAC_TX_MODE 0x0000045c
395 #define TX_MODE_RESET 0x00000001
396 #define TX_MODE_ENABLE 0x00000002
397 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
398 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
399 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
400 #define MAC_TX_STATUS 0x00000460
401 #define TX_STATUS_XOFFED 0x00000001
402 #define TX_STATUS_SENT_XOFF 0x00000002
403 #define TX_STATUS_SENT_XON 0x00000004
404 #define TX_STATUS_LINK_UP 0x00000008
405 #define TX_STATUS_ODI_UNDERRUN 0x00000010
406 #define TX_STATUS_ODI_OVERRUN 0x00000020
407 #define MAC_TX_LENGTHS 0x00000464
408 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
409 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
410 #define TX_LENGTHS_IPG_MASK 0x00000f00
411 #define TX_LENGTHS_IPG_SHIFT 8
412 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
413 #define TX_LENGTHS_IPG_CRS_SHIFT 12
414 #define MAC_RX_MODE 0x00000468
415 #define RX_MODE_RESET 0x00000001
416 #define RX_MODE_ENABLE 0x00000002
417 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
418 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
419 #define RX_MODE_KEEP_PAUSE 0x00000010
420 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
421 #define RX_MODE_ACCEPT_RUNTS 0x00000040
422 #define RX_MODE_LEN_CHECK 0x00000080
423 #define RX_MODE_PROMISC 0x00000100
424 #define RX_MODE_NO_CRC_CHECK 0x00000200
425 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
426 #define MAC_RX_STATUS 0x0000046c
427 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
428 #define RX_STATUS_XOFF_RCVD 0x00000002
429 #define RX_STATUS_XON_RCVD 0x00000004
430 #define MAC_HASH_REG_0 0x00000470
431 #define MAC_HASH_REG_1 0x00000474
432 #define MAC_HASH_REG_2 0x00000478
433 #define MAC_HASH_REG_3 0x0000047c
434 #define MAC_RCV_RULE_0 0x00000480
435 #define MAC_RCV_VALUE_0 0x00000484
436 #define MAC_RCV_RULE_1 0x00000488
437 #define MAC_RCV_VALUE_1 0x0000048c
438 #define MAC_RCV_RULE_2 0x00000490
439 #define MAC_RCV_VALUE_2 0x00000494
440 #define MAC_RCV_RULE_3 0x00000498
441 #define MAC_RCV_VALUE_3 0x0000049c
442 #define MAC_RCV_RULE_4 0x000004a0
443 #define MAC_RCV_VALUE_4 0x000004a4
444 #define MAC_RCV_RULE_5 0x000004a8
445 #define MAC_RCV_VALUE_5 0x000004ac
446 #define MAC_RCV_RULE_6 0x000004b0
447 #define MAC_RCV_VALUE_6 0x000004b4
448 #define MAC_RCV_RULE_7 0x000004b8
449 #define MAC_RCV_VALUE_7 0x000004bc
450 #define MAC_RCV_RULE_8 0x000004c0
451 #define MAC_RCV_VALUE_8 0x000004c4
452 #define MAC_RCV_RULE_9 0x000004c8
453 #define MAC_RCV_VALUE_9 0x000004cc
454 #define MAC_RCV_RULE_10 0x000004d0
455 #define MAC_RCV_VALUE_10 0x000004d4
456 #define MAC_RCV_RULE_11 0x000004d8
457 #define MAC_RCV_VALUE_11 0x000004dc
458 #define MAC_RCV_RULE_12 0x000004e0
459 #define MAC_RCV_VALUE_12 0x000004e4
460 #define MAC_RCV_RULE_13 0x000004e8
461 #define MAC_RCV_VALUE_13 0x000004ec
462 #define MAC_RCV_RULE_14 0x000004f0
463 #define MAC_RCV_VALUE_14 0x000004f4
464 #define MAC_RCV_RULE_15 0x000004f8
465 #define MAC_RCV_VALUE_15 0x000004fc
466 #define RCV_RULE_DISABLE_MASK 0x7fffffff
467 #define MAC_RCV_RULE_CFG 0x00000500
468 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
469 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
470 /* 0x508 --> 0x520 unused */
471 #define MAC_HASHREGU_0 0x00000520
472 #define MAC_HASHREGU_1 0x00000524
473 #define MAC_HASHREGU_2 0x00000528
474 #define MAC_HASHREGU_3 0x0000052c
475 #define MAC_EXTADDR_0_HIGH 0x00000530
476 #define MAC_EXTADDR_0_LOW 0x00000534
477 #define MAC_EXTADDR_1_HIGH 0x00000538
478 #define MAC_EXTADDR_1_LOW 0x0000053c
479 #define MAC_EXTADDR_2_HIGH 0x00000540
480 #define MAC_EXTADDR_2_LOW 0x00000544
481 #define MAC_EXTADDR_3_HIGH 0x00000548
482 #define MAC_EXTADDR_3_LOW 0x0000054c
483 #define MAC_EXTADDR_4_HIGH 0x00000550
484 #define MAC_EXTADDR_4_LOW 0x00000554
485 #define MAC_EXTADDR_5_HIGH 0x00000558
486 #define MAC_EXTADDR_5_LOW 0x0000055c
487 #define MAC_EXTADDR_6_HIGH 0x00000560
488 #define MAC_EXTADDR_6_LOW 0x00000564
489 #define MAC_EXTADDR_7_HIGH 0x00000568
490 #define MAC_EXTADDR_7_LOW 0x0000056c
491 #define MAC_EXTADDR_8_HIGH 0x00000570
492 #define MAC_EXTADDR_8_LOW 0x00000574
493 #define MAC_EXTADDR_9_HIGH 0x00000578
494 #define MAC_EXTADDR_9_LOW 0x0000057c
495 #define MAC_EXTADDR_10_HIGH 0x00000580
496 #define MAC_EXTADDR_10_LOW 0x00000584
497 #define MAC_EXTADDR_11_HIGH 0x00000588
498 #define MAC_EXTADDR_11_LOW 0x0000058c
499 #define MAC_SERDES_CFG 0x00000590
500 #define MAC_SERDES_STAT 0x00000594
501 /* 0x598 --> 0x600 unused */
502 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
503 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
504 /* 0x624 --> 0x800 unused */
505 #define MAC_TX_STATS_OCTETS 0x00000800
506 #define MAC_TX_STATS_RESV1 0x00000804
507 #define MAC_TX_STATS_COLLISIONS 0x00000808
508 #define MAC_TX_STATS_XON_SENT 0x0000080c
509 #define MAC_TX_STATS_XOFF_SENT 0x00000810
510 #define MAC_TX_STATS_RESV2 0x00000814
511 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
512 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
513 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
514 #define MAC_TX_STATS_DEFERRED 0x00000824
515 #define MAC_TX_STATS_RESV3 0x00000828
516 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
517 #define MAC_TX_STATS_LATE_COL 0x00000830
518 #define MAC_TX_STATS_RESV4_1 0x00000834
519 #define MAC_TX_STATS_RESV4_2 0x00000838
520 #define MAC_TX_STATS_RESV4_3 0x0000083c
521 #define MAC_TX_STATS_RESV4_4 0x00000840
522 #define MAC_TX_STATS_RESV4_5 0x00000844
523 #define MAC_TX_STATS_RESV4_6 0x00000848
524 #define MAC_TX_STATS_RESV4_7 0x0000084c
525 #define MAC_TX_STATS_RESV4_8 0x00000850
526 #define MAC_TX_STATS_RESV4_9 0x00000854
527 #define MAC_TX_STATS_RESV4_10 0x00000858
528 #define MAC_TX_STATS_RESV4_11 0x0000085c
529 #define MAC_TX_STATS_RESV4_12 0x00000860
530 #define MAC_TX_STATS_RESV4_13 0x00000864
531 #define MAC_TX_STATS_RESV4_14 0x00000868
532 #define MAC_TX_STATS_UCAST 0x0000086c
533 #define MAC_TX_STATS_MCAST 0x00000870
534 #define MAC_TX_STATS_BCAST 0x00000874
535 #define MAC_TX_STATS_RESV5_1 0x00000878
536 #define MAC_TX_STATS_RESV5_2 0x0000087c
537 #define MAC_RX_STATS_OCTETS 0x00000880
538 #define MAC_RX_STATS_RESV1 0x00000884
539 #define MAC_RX_STATS_FRAGMENTS 0x00000888
540 #define MAC_RX_STATS_UCAST 0x0000088c
541 #define MAC_RX_STATS_MCAST 0x00000890
542 #define MAC_RX_STATS_BCAST 0x00000894
543 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
544 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
545 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
546 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
547 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
548 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
549 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
550 #define MAC_RX_STATS_JABBERS 0x000008b4
551 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
552 /* 0x8bc --> 0xc00 unused */
554 /* Send data initiator control registers */
555 #define SNDDATAI_MODE 0x00000c00
556 #define SNDDATAI_MODE_RESET 0x00000001
557 #define SNDDATAI_MODE_ENABLE 0x00000002
558 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
559 #define SNDDATAI_STATUS 0x00000c04
560 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
561 #define SNDDATAI_STATSCTRL 0x00000c08
562 #define SNDDATAI_SCTRL_ENABLE 0x00000001
563 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
564 #define SNDDATAI_SCTRL_CLEAR 0x00000004
565 #define SNDDATAI_SCTRL_FLUSH 0x00000008
566 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
567 #define SNDDATAI_STATSENAB 0x00000c0c
568 #define SNDDATAI_STATSINCMASK 0x00000c10
569 /* 0xc14 --> 0xc80 unused */
570 #define SNDDATAI_COS_CNT_0 0x00000c80
571 #define SNDDATAI_COS_CNT_1 0x00000c84
572 #define SNDDATAI_COS_CNT_2 0x00000c88
573 #define SNDDATAI_COS_CNT_3 0x00000c8c
574 #define SNDDATAI_COS_CNT_4 0x00000c90
575 #define SNDDATAI_COS_CNT_5 0x00000c94
576 #define SNDDATAI_COS_CNT_6 0x00000c98
577 #define SNDDATAI_COS_CNT_7 0x00000c9c
578 #define SNDDATAI_COS_CNT_8 0x00000ca0
579 #define SNDDATAI_COS_CNT_9 0x00000ca4
580 #define SNDDATAI_COS_CNT_10 0x00000ca8
581 #define SNDDATAI_COS_CNT_11 0x00000cac
582 #define SNDDATAI_COS_CNT_12 0x00000cb0
583 #define SNDDATAI_COS_CNT_13 0x00000cb4
584 #define SNDDATAI_COS_CNT_14 0x00000cb8
585 #define SNDDATAI_COS_CNT_15 0x00000cbc
586 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
587 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
588 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
589 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
590 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
591 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
592 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
593 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
594 /* 0xce0 --> 0x1000 unused */
596 /* Send data completion control registers */
597 #define SNDDATAC_MODE 0x00001000
598 #define SNDDATAC_MODE_RESET 0x00000001
599 #define SNDDATAC_MODE_ENABLE 0x00000002
600 /* 0x1004 --> 0x1400 unused */
602 /* Send BD ring selector */
603 #define SNDBDS_MODE 0x00001400
604 #define SNDBDS_MODE_RESET 0x00000001
605 #define SNDBDS_MODE_ENABLE 0x00000002
606 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
607 #define SNDBDS_STATUS 0x00001404
608 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
609 #define SNDBDS_HWDIAG 0x00001408
610 /* 0x140c --> 0x1440 */
611 #define SNDBDS_SEL_CON_IDX_0 0x00001440
612 #define SNDBDS_SEL_CON_IDX_1 0x00001444
613 #define SNDBDS_SEL_CON_IDX_2 0x00001448
614 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
615 #define SNDBDS_SEL_CON_IDX_4 0x00001450
616 #define SNDBDS_SEL_CON_IDX_5 0x00001454
617 #define SNDBDS_SEL_CON_IDX_6 0x00001458
618 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
619 #define SNDBDS_SEL_CON_IDX_8 0x00001460
620 #define SNDBDS_SEL_CON_IDX_9 0x00001464
621 #define SNDBDS_SEL_CON_IDX_10 0x00001468
622 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
623 #define SNDBDS_SEL_CON_IDX_12 0x00001470
624 #define SNDBDS_SEL_CON_IDX_13 0x00001474
625 #define SNDBDS_SEL_CON_IDX_14 0x00001478
626 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
627 /* 0x1480 --> 0x1800 unused */
629 /* Send BD initiator control registers */
630 #define SNDBDI_MODE 0x00001800
631 #define SNDBDI_MODE_RESET 0x00000001
632 #define SNDBDI_MODE_ENABLE 0x00000002
633 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
634 #define SNDBDI_STATUS 0x00001804
635 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
636 #define SNDBDI_IN_PROD_IDX_0 0x00001808
637 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
638 #define SNDBDI_IN_PROD_IDX_2 0x00001810
639 #define SNDBDI_IN_PROD_IDX_3 0x00001814
640 #define SNDBDI_IN_PROD_IDX_4 0x00001818
641 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
642 #define SNDBDI_IN_PROD_IDX_6 0x00001820
643 #define SNDBDI_IN_PROD_IDX_7 0x00001824
644 #define SNDBDI_IN_PROD_IDX_8 0x00001828
645 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
646 #define SNDBDI_IN_PROD_IDX_10 0x00001830
647 #define SNDBDI_IN_PROD_IDX_11 0x00001834
648 #define SNDBDI_IN_PROD_IDX_12 0x00001838
649 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
650 #define SNDBDI_IN_PROD_IDX_14 0x00001840
651 #define SNDBDI_IN_PROD_IDX_15 0x00001844
652 /* 0x1848 --> 0x1c00 unused */
654 /* Send BD completion control registers */
655 #define SNDBDC_MODE 0x00001c00
656 #define SNDBDC_MODE_RESET 0x00000001
657 #define SNDBDC_MODE_ENABLE 0x00000002
658 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
659 /* 0x1c04 --> 0x2000 unused */
661 /* Receive list placement control registers */
662 #define RCVLPC_MODE 0x00002000
663 #define RCVLPC_MODE_RESET 0x00000001
664 #define RCVLPC_MODE_ENABLE 0x00000002
665 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
666 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
667 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
668 #define RCVLPC_STATUS 0x00002004
669 #define RCVLPC_STATUS_CLASS0 0x00000004
670 #define RCVLPC_STATUS_MAPOOR 0x00000008
671 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
672 #define RCVLPC_LOCK 0x00002008
673 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
674 #define RCVLPC_LOCK_REQ_SHIFT 0
675 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
676 #define RCVLPC_LOCK_GRANT_SHIFT 16
677 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
678 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
679 #define RCVLPC_CONFIG 0x00002010
680 #define RCVLPC_STATSCTRL 0x00002014
681 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
682 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
683 #define RCVLPC_STATS_ENABLE 0x00002018
684 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
685 #define RCVLPC_STATS_INCMASK 0x0000201c
686 /* 0x2020 --> 0x2100 unused */
687 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
688 #define SELLST_TAIL 0x00000004
689 #define SELLST_CONT 0x00000008
690 #define SELLST_UNUSED 0x0000000c
691 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
692 #define RCVLPC_DROP_FILTER_CNT 0x00002240
693 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
694 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
695 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
696 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
697 #define RCVLPC_IN_ERRORS_CNT 0x00002254
698 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
699 /* 0x225c --> 0x2400 unused */
701 /* Receive Data and Receive BD Initiator Control */
702 #define RCVDBDI_MODE 0x00002400
703 #define RCVDBDI_MODE_RESET 0x00000001
704 #define RCVDBDI_MODE_ENABLE 0x00000002
705 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
706 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
707 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
708 #define RCVDBDI_STATUS 0x00002404
709 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
710 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
711 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
712 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
713 /* 0x240c --> 0x2440 unused */
714 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
715 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
716 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
717 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
718 #define RCVDBDI_STD_CON_IDX 0x00002474
719 #define RCVDBDI_MINI_CON_IDX 0x00002478
720 /* 0x247c --> 0x2480 unused */
721 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
722 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
723 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
724 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
725 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
726 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
727 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
728 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
729 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
730 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
731 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
732 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
733 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
734 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
735 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
736 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
737 #define RCVDBDI_HWDIAG 0x000024c0
738 /* 0x24c4 --> 0x2800 unused */
740 /* Receive Data Completion Control */
741 #define RCVDCC_MODE 0x00002800
742 #define RCVDCC_MODE_RESET 0x00000001
743 #define RCVDCC_MODE_ENABLE 0x00000002
744 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
745 /* 0x2804 --> 0x2c00 unused */
747 /* Receive BD Initiator Control Registers */
748 #define RCVBDI_MODE 0x00002c00
749 #define RCVBDI_MODE_RESET 0x00000001
750 #define RCVBDI_MODE_ENABLE 0x00000002
751 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
752 #define RCVBDI_STATUS 0x00002c04
753 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
754 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
755 #define RCVBDI_STD_PROD_IDX 0x00002c0c
756 #define RCVBDI_MINI_PROD_IDX 0x00002c10
757 #define RCVBDI_MINI_THRESH 0x00002c14
758 #define RCVBDI_STD_THRESH 0x00002c18
759 #define RCVBDI_JUMBO_THRESH 0x00002c1c
760 /* 0x2c20 --> 0x3000 unused */
762 /* Receive BD Completion Control Registers */
763 #define RCVCC_MODE 0x00003000
764 #define RCVCC_MODE_RESET 0x00000001
765 #define RCVCC_MODE_ENABLE 0x00000002
766 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
767 #define RCVCC_STATUS 0x00003004
768 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
769 #define RCVCC_JUMP_PROD_IDX 0x00003008
770 #define RCVCC_STD_PROD_IDX 0x0000300c
771 #define RCVCC_MINI_PROD_IDX 0x00003010
772 /* 0x3014 --> 0x3400 unused */
774 /* Receive list selector control registers */
775 #define RCVLSC_MODE 0x00003400
776 #define RCVLSC_MODE_RESET 0x00000001
777 #define RCVLSC_MODE_ENABLE 0x00000002
778 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
779 #define RCVLSC_STATUS 0x00003404
780 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
781 /* 0x3408 --> 0x3800 unused */
783 /* Mbuf cluster free registers */
784 #define MBFREE_MODE 0x00003800
785 #define MBFREE_MODE_RESET 0x00000001
786 #define MBFREE_MODE_ENABLE 0x00000002
787 #define MBFREE_STATUS 0x00003804
788 /* 0x3808 --> 0x3c00 unused */
790 /* Host coalescing control registers */
791 #define HOSTCC_MODE 0x00003c00
792 #define HOSTCC_MODE_RESET 0x00000001
793 #define HOSTCC_MODE_ENABLE 0x00000002
794 #define HOSTCC_MODE_ATTN 0x00000004
795 #define HOSTCC_MODE_NOW 0x00000008
796 #define HOSTCC_MODE_FULL_STATUS 0x00000000
797 #define HOSTCC_MODE_64BYTE 0x00000080
798 #define HOSTCC_MODE_32BYTE 0x00000100
799 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
800 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
801 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
802 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
803 #define HOSTCC_STATUS 0x00003c04
804 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
805 #define HOSTCC_RXCOL_TICKS 0x00003c08
806 #define LOW_RXCOL_TICKS 0x00000032
807 #define DEFAULT_RXCOL_TICKS 0x00000048
808 #define HIGH_RXCOL_TICKS 0x00000096
809 #define HOSTCC_TXCOL_TICKS 0x00003c0c
810 #define LOW_TXCOL_TICKS 0x00000096
811 #define DEFAULT_TXCOL_TICKS 0x0000012c
812 #define HIGH_TXCOL_TICKS 0x00000145
813 #define HOSTCC_RXMAX_FRAMES 0x00003c10
814 #define LOW_RXMAX_FRAMES 0x00000005
815 #define DEFAULT_RXMAX_FRAMES 0x00000008
816 #define HIGH_RXMAX_FRAMES 0x00000012
817 #define HOSTCC_TXMAX_FRAMES 0x00003c14
818 #define LOW_TXMAX_FRAMES 0x00000035
819 #define DEFAULT_TXMAX_FRAMES 0x0000004b
820 #define HIGH_TXMAX_FRAMES 0x00000052
821 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
822 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
823 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
824 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
825 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
826 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
827 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
828 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
829 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
830 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
831 /* 0x3c2c --> 0x3c30 unused */
832 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
833 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
834 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
835 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
836 #define HOSTCC_FLOW_ATTN 0x00003c48
837 /* 0x3c4c --> 0x3c50 unused */
838 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
839 #define HOSTCC_STD_CON_IDX 0x00003c54
840 #define HOSTCC_MINI_CON_IDX 0x00003c58
841 /* 0x3c5c --> 0x3c80 unused */
842 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
843 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
844 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
845 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
846 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
847 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
848 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
849 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
850 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
851 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
852 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
853 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
854 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
855 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
856 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
857 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
858 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
859 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
860 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
861 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
862 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
863 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
864 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
865 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
866 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
867 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
868 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
869 #define HOSTCC_SND_CON_IDX_11 0x00003cec
870 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
871 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
872 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
873 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
874 /* 0x3d00 --> 0x4000 unused */
876 /* Memory arbiter control registers */
877 #define MEMARB_MODE 0x00004000
878 #define MEMARB_MODE_RESET 0x00000001
879 #define MEMARB_MODE_ENABLE 0x00000002
880 #define MEMARB_STATUS 0x00004004
881 #define MEMARB_TRAP_ADDR_LOW 0x00004008
882 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
883 /* 0x4010 --> 0x4400 unused */
885 /* Buffer manager control registers */
886 #define BUFMGR_MODE 0x00004400
887 #define BUFMGR_MODE_RESET 0x00000001
888 #define BUFMGR_MODE_ENABLE 0x00000002
889 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
890 #define BUFMGR_MODE_BM_TEST 0x00000008
891 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
892 #define BUFMGR_STATUS 0x00004404
893 #define BUFMGR_STATUS_ERROR 0x00000004
894 #define BUFMGR_STATUS_MBLOW 0x00000010
895 #define BUFMGR_MB_POOL_ADDR 0x00004408
896 #define BUFMGR_MB_POOL_SIZE 0x0000440c
897 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
898 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
899 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
900 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
901 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
902 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
903 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
904 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
905 #define BUFMGR_MB_HIGH_WATER 0x00004418
906 #define DEFAULT_MB_HIGH_WATER 0x00000060
907 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
908 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
909 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
910 #define BUFMGR_MB_ALLOC_BIT 0x10000000
911 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
912 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
913 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
914 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
915 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
916 #define BUFMGR_DMA_LOW_WATER 0x00004434
917 #define DEFAULT_DMA_LOW_WATER 0x00000005
918 #define BUFMGR_DMA_HIGH_WATER 0x00004438
919 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
920 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
921 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
922 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
923 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
924 #define BUFMGR_HWDIAG_0 0x0000444c
925 #define BUFMGR_HWDIAG_1 0x00004450
926 #define BUFMGR_HWDIAG_2 0x00004454
927 /* 0x4458 --> 0x4800 unused */
929 /* Read DMA control registers */
930 #define RDMAC_MODE 0x00004800
931 #define RDMAC_MODE_RESET 0x00000001
932 #define RDMAC_MODE_ENABLE 0x00000002
933 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
934 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
935 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
936 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
937 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
938 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
939 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
940 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
941 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
942 #define RDMAC_MODE_SPLIT_RESET 0x00001000
943 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
944 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
945 #define RDMAC_STATUS 0x00004804
946 #define RDMAC_STATUS_TGTABORT 0x00000004
947 #define RDMAC_STATUS_MSTABORT 0x00000008
948 #define RDMAC_STATUS_PARITYERR 0x00000010
949 #define RDMAC_STATUS_ADDROFLOW 0x00000020
950 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
951 #define RDMAC_STATUS_FIFOURUN 0x00000080
952 #define RDMAC_STATUS_FIFOOREAD 0x00000100
953 #define RDMAC_STATUS_LNGREAD 0x00000200
954 /* 0x4808 --> 0x4c00 unused */
956 /* Write DMA control registers */
957 #define WDMAC_MODE 0x00004c00
958 #define WDMAC_MODE_RESET 0x00000001
959 #define WDMAC_MODE_ENABLE 0x00000002
960 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
961 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
962 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
963 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
964 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
965 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
966 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
967 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
968 #define WDMAC_MODE_RX_ACCEL 0x00000400
969 #define WDMAC_STATUS 0x00004c04
970 #define WDMAC_STATUS_TGTABORT 0x00000004
971 #define WDMAC_STATUS_MSTABORT 0x00000008
972 #define WDMAC_STATUS_PARITYERR 0x00000010
973 #define WDMAC_STATUS_ADDROFLOW 0x00000020
974 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
975 #define WDMAC_STATUS_FIFOURUN 0x00000080
976 #define WDMAC_STATUS_FIFOOREAD 0x00000100
977 #define WDMAC_STATUS_LNGREAD 0x00000200
978 /* 0x4c08 --> 0x5000 unused */
980 /* Per-cpu register offsets (arm9) */
981 #define CPU_MODE 0x00000000
982 #define CPU_MODE_RESET 0x00000001
983 #define CPU_MODE_HALT 0x00000400
984 #define CPU_STATE 0x00000004
985 #define CPU_EVTMASK 0x00000008
986 /* 0xc --> 0x1c reserved */
987 #define CPU_PC 0x0000001c
988 #define CPU_INSN 0x00000020
989 #define CPU_SPAD_UFLOW 0x00000024
990 #define CPU_WDOG_CLEAR 0x00000028
991 #define CPU_WDOG_VECTOR 0x0000002c
992 #define CPU_WDOG_PC 0x00000030
993 #define CPU_HW_BP 0x00000034
994 /* 0x38 --> 0x44 unused */
995 #define CPU_WDOG_SAVED_STATE 0x00000044
996 #define CPU_LAST_BRANCH_ADDR 0x00000048
997 #define CPU_SPAD_UFLOW_SET 0x0000004c
998 /* 0x50 --> 0x200 unused */
999 #define CPU_R0 0x00000200
1000 #define CPU_R1 0x00000204
1001 #define CPU_R2 0x00000208
1002 #define CPU_R3 0x0000020c
1003 #define CPU_R4 0x00000210
1004 #define CPU_R5 0x00000214
1005 #define CPU_R6 0x00000218
1006 #define CPU_R7 0x0000021c
1007 #define CPU_R8 0x00000220
1008 #define CPU_R9 0x00000224
1009 #define CPU_R10 0x00000228
1010 #define CPU_R11 0x0000022c
1011 #define CPU_R12 0x00000230
1012 #define CPU_R13 0x00000234
1013 #define CPU_R14 0x00000238
1014 #define CPU_R15 0x0000023c
1015 #define CPU_R16 0x00000240
1016 #define CPU_R17 0x00000244
1017 #define CPU_R18 0x00000248
1018 #define CPU_R19 0x0000024c
1019 #define CPU_R20 0x00000250
1020 #define CPU_R21 0x00000254
1021 #define CPU_R22 0x00000258
1022 #define CPU_R23 0x0000025c
1023 #define CPU_R24 0x00000260
1024 #define CPU_R25 0x00000264
1025 #define CPU_R26 0x00000268
1026 #define CPU_R27 0x0000026c
1027 #define CPU_R28 0x00000270
1028 #define CPU_R29 0x00000274
1029 #define CPU_R30 0x00000278
1030 #define CPU_R31 0x0000027c
1031 /* 0x280 --> 0x400 unused */
1033 #define RX_CPU_BASE 0x00005000
1034 #define TX_CPU_BASE 0x00005400
1037 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1038 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1039 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1040 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1041 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1042 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1043 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1044 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1045 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1046 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1047 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1048 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1049 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1050 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1051 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1052 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1053 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1054 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1055 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1056 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1057 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1058 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1059 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1060 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1061 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1062 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1063 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1064 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1065 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1066 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1067 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1068 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1069 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1070 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1071 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1072 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1073 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1074 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1075 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1076 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1077 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1078 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1079 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1080 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1081 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1082 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1083 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1084 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1085 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1086 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1087 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1088 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1089 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1090 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1091 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1092 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1093 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1094 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1095 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1096 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1097 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1098 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1099 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1100 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1101 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1102 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1103 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1104 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1105 /* 0x5a10 --> 0x5c00 */
1107 /* Flow Through queues */
1108 #define FTQ_RESET 0x00005c00
1109 /* 0x5c04 --> 0x5c10 unused */
1110 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1111 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1112 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1113 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1114 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1115 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1116 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1117 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1118 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1119 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1120 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1121 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1122 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1123 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1124 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1125 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1126 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1127 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1128 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1129 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1130 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1131 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1132 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1133 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1134 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1135 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1136 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1137 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1138 #define FTQ_SWTYPE1_CTL 0x00005c80
1139 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1140 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1141 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1142 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1143 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1144 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1145 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1146 #define FTQ_HOST_COAL_CTL 0x00005ca0
1147 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1148 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1149 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1150 #define FTQ_MAC_TX_CTL 0x00005cb0
1151 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1152 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1153 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1154 #define FTQ_MB_FREE_CTL 0x00005cc0
1155 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1156 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1157 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1158 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1159 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1160 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1161 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1162 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1163 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1164 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1165 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1166 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1167 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1168 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1169 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1170 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1171 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1172 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1173 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1174 #define FTQ_SWTYPE2_CTL 0x00005d10
1175 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1176 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1177 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1178 /* 0x5d20 --> 0x6000 unused */
1180 /* Message signaled interrupt registers */
1181 #define MSGINT_MODE 0x00006000
1182 #define MSGINT_MODE_RESET 0x00000001
1183 #define MSGINT_MODE_ENABLE 0x00000002
1184 #define MSGINT_STATUS 0x00006004
1185 #define MSGINT_FIFO 0x00006008
1186 /* 0x600c --> 0x6400 unused */
1188 /* DMA completion registers */
1189 #define DMAC_MODE 0x00006400
1190 #define DMAC_MODE_RESET 0x00000001
1191 #define DMAC_MODE_ENABLE 0x00000002
1192 /* 0x6404 --> 0x6800 unused */
1195 #define GRC_MODE 0x00006800
1196 #define GRC_MODE_UPD_ON_COAL 0x00000001
1197 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1198 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1199 #define GRC_MODE_BSWAP_DATA 0x00000010
1200 #define GRC_MODE_WSWAP_DATA 0x00000020
1201 #define GRC_MODE_SPLITHDR 0x00000100
1202 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1203 #define GRC_MODE_INCL_CRC 0x00000400
1204 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1205 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1206 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1207 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1208 #define GRC_MODE_HOST_STACKUP 0x00010000
1209 #define GRC_MODE_HOST_SENDBDS 0x00020000
1210 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1211 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1212 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1213 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1214 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1215 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1216 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1217 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1218 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1219 #define GRC_MISC_CFG 0x00006804
1220 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1221 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1222 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1223 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1224 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1225 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1226 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1227 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1228 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1229 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1230 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1231 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1232 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1233 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1234 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1235 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1236 #define GRC_LOCAL_CTRL 0x00006808
1237 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1238 #define GRC_LCLCTRL_CLEARINT 0x00000002
1239 #define GRC_LCLCTRL_SETINT 0x00000004
1240 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1241 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1242 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1243 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1244 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1245 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1246 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1247 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1248 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1249 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1250 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1251 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1252 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1253 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1254 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1255 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1256 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1257 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1258 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1259 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1260 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1261 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1262 #define GRC_TIMER 0x0000680c
1263 #define GRC_RX_CPU_EVENT 0x00006810
1264 #define GRC_RX_TIMER_REF 0x00006814
1265 #define GRC_RX_CPU_SEM 0x00006818
1266 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1267 #define GRC_TX_CPU_EVENT 0x00006820
1268 #define GRC_TX_TIMER_REF 0x00006824
1269 #define GRC_TX_CPU_SEM 0x00006828
1270 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1271 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1272 #define GRC_EEPROM_ADDR 0x00006838
1273 #define EEPROM_ADDR_WRITE 0x00000000
1274 #define EEPROM_ADDR_READ 0x80000000
1275 #define EEPROM_ADDR_COMPLETE 0x40000000
1276 #define EEPROM_ADDR_FSM_RESET 0x20000000
1277 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1278 #define EEPROM_ADDR_DEVID_SHIFT 26
1279 #define EEPROM_ADDR_START 0x02000000
1280 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1281 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1282 #define EEPROM_ADDR_ADDR_SHIFT 0
1283 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1284 #define EEPROM_CHIP_SIZE (64 * 1024)
1285 #define GRC_EEPROM_DATA 0x0000683c
1286 #define GRC_EEPROM_CTRL 0x00006840
1287 #define GRC_MDI_CTRL 0x00006844
1288 #define GRC_SEEPROM_DELAY 0x00006848
1289 /* 0x684c --> 0x6c00 unused */
1291 /* 0x6c00 --> 0x7000 unused */
1293 /* NVRAM Control registers */
1294 #define NVRAM_CMD 0x00007000
1295 #define NVRAM_CMD_RESET 0x00000001
1296 #define NVRAM_CMD_DONE 0x00000008
1297 #define NVRAM_CMD_GO 0x00000010
1298 #define NVRAM_CMD_WR 0x00000020
1299 #define NVRAM_CMD_RD 0x00000000
1300 #define NVRAM_CMD_ERASE 0x00000040
1301 #define NVRAM_CMD_FIRST 0x00000080
1302 #define NVRAM_CMD_LAST 0x00000100
1303 #define NVRAM_STAT 0x00007004
1304 #define NVRAM_WRDATA 0x00007008
1305 #define NVRAM_ADDR 0x0000700c
1306 #define NVRAM_ADDR_MSK 0x00ffffff
1307 #define NVRAM_RDDATA 0x00007010
1308 #define NVRAM_CFG1 0x00007014
1309 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1310 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1311 #define NVRAM_CFG1_PASS_THRU 0x00000004
1312 #define NVRAM_CFG1_BIT_BANG 0x00000008
1313 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1314 #define NVRAM_CFG2 0x00007018
1315 #define NVRAM_CFG3 0x0000701c
1316 #define NVRAM_SWARB 0x00007020
1317 #define SWARB_REQ_SET0 0x00000001
1318 #define SWARB_REQ_SET1 0x00000002
1319 #define SWARB_REQ_SET2 0x00000004
1320 #define SWARB_REQ_SET3 0x00000008
1321 #define SWARB_REQ_CLR0 0x00000010
1322 #define SWARB_REQ_CLR1 0x00000020
1323 #define SWARB_REQ_CLR2 0x00000040
1324 #define SWARB_REQ_CLR3 0x00000080
1325 #define SWARB_GNT0 0x00000100
1326 #define SWARB_GNT1 0x00000200
1327 #define SWARB_GNT2 0x00000400
1328 #define SWARB_GNT3 0x00000800
1329 #define SWARB_REQ0 0x00001000
1330 #define SWARB_REQ1 0x00002000
1331 #define SWARB_REQ2 0x00004000
1332 #define SWARB_REQ3 0x00008000
1333 #define NVRAM_BUFFERED_PAGE_SIZE 264
1334 #define NVRAM_BUFFERED_PAGE_POS 9
1335 /* 0x7024 --> 0x7400 unused */
1337 /* 0x7400 --> 0x8000 unused */
1339 /* 32K Window into NIC internal memory */
1340 #define NIC_SRAM_WIN_BASE 0x00008000
1342 /* Offsets into first 32k of NIC internal memory. */
1343 #define NIC_SRAM_PAGE_ZERO 0x00000000
1344 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
1345 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
1346 #define NIC_SRAM_STATS_BLK 0x00000300
1347 #define NIC_SRAM_STATUS_BLK 0x00000b00
1349 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
1350 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
1351 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
1353 #define NIC_SRAM_DATA_SIG 0x00000b54
1354 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
1356 #define NIC_SRAM_DATA_CFG 0x00000b58
1357 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
1358 #define NIC_SRAM_DATA_CFG_LED_MODE_UNKNOWN 0x00000000
1359 #define NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD 0x00000004
1360 #define NIC_SRAM_DATA_CFG_LED_OPEN_DRAIN 0x00000004
1361 #define NIC_SRAM_DATA_CFG_LED_LINK_SPD 0x00000008
1362 #define NIC_SRAM_DATA_CFG_LED_OUTPUT 0x00000008
1363 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
1364 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
1365 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
1366 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
1367 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
1368 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
1369 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
1370 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
1371 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
1373 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
1374 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
1375 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
1377 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
1378 #define FWCMD_NICDRV_ALIVE 0x00000001
1379 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
1380 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
1381 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
1382 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
1383 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
1384 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
1385 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
1386 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
1387 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
1388 #define DRV_STATE_START 0x00000001
1389 #define DRV_STATE_UNLOAD 0x00000002
1390 #define DRV_STATE_WOL 0x00000003
1391 #define DRV_STATE_SUSPEND 0x00000004
1393 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
1395 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
1396 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
1398 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
1400 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
1401 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
1402 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
1403 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
1404 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
1405 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
1406 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
1407 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
1408 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
1409 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
1411 /* Currently this is fixed. */
1412 #define PHY_ADDR 0x01
1414 /* Tigon3 specific PHY MII registers. */
1415 #define TG3_BMCR_SPEED1000 0x0040
1417 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
1418 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
1419 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
1420 #define MII_TG3_CTRL_AS_MASTER 0x0800
1421 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
1423 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
1424 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
1425 #define MII_TG3_EXT_CTRL_TBI 0x8000
1427 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
1428 #define MII_TG3_EXT_STAT_LPASS 0x0100
1430 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
1432 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
1434 #define MII_TG3_AUX_CTRL 0x18 /* auxilliary control register */
1436 #define MII_TG3_AUX_STAT 0x19 /* auxilliary status register */
1437 #define MII_TG3_AUX_STAT_LPASS 0x0004
1438 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
1439 #define MII_TG3_AUX_STAT_10HALF 0x0100
1440 #define MII_TG3_AUX_STAT_10FULL 0x0200
1441 #define MII_TG3_AUX_STAT_100HALF 0x0300
1442 #define MII_TG3_AUX_STAT_100_4 0x0400
1443 #define MII_TG3_AUX_STAT_100FULL 0x0500
1444 #define MII_TG3_AUX_STAT_1000HALF 0x0600
1445 #define MII_TG3_AUX_STAT_1000FULL 0x0700
1447 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
1448 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
1450 /* ISTAT/IMASK event bits */
1451 #define MII_TG3_INT_LINKCHG 0x0002
1452 #define MII_TG3_INT_SPEEDCHG 0x0004
1453 #define MII_TG3_INT_DUPLEXCHG 0x0008
1454 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
1456 /* XXX Add this to mii.h */
1457 #ifndef ADVERTISE_PAUSE
1458 #define ADVERTISE_PAUSE_CAP 0x0400
1460 #ifndef ADVERTISE_PAUSE_ASYM
1461 #define ADVERTISE_PAUSE_ASYM 0x0800
1464 #define LPA_PAUSE_CAP 0x0400
1466 #ifndef LPA_PAUSE_ASYM
1467 #define LPA_PAUSE_ASYM 0x0800
1470 /* There are two ways to manage the TX descriptors on the tigon3.
1471 * Either the descriptors are in host DMA'able memory, or they
1472 * exist only in the cards on-chip SRAM. All 16 send bds are under
1473 * the same mode, they may not be configured individually.
1475 * The mode we use is controlled by TG3_FLAG_HOST_TXDS in tp->tg3_flags.
1477 * To use host memory TX descriptors:
1478 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
1479 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
1480 * 2) Allocate DMA'able memory.
1481 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1482 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
1483 * obtained in step 2
1484 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
1485 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
1486 * of TX descriptors. Leave flags field clear.
1487 * 4) Access TX descriptors via host memory. The chip
1488 * will refetch into local SRAM as needed when producer
1489 * index mailboxes are updated.
1491 * To use on-chip TX descriptors:
1492 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
1493 * Make sure GRC_MODE_HOST_SENDBDS is clear.
1494 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
1495 * a) Set TG3_BDINFO_HOST_ADDR to zero.
1496 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
1497 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
1498 * 3) Access TX descriptors directly in on-chip SRAM
1499 * using normal {read,write}l(). (and not using
1500 * pointer dereferencing of ioremap()'d memory like
1501 * the broken Broadcom driver does)
1503 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
1504 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
1506 struct tg3_tx_buffer_desc {
1511 #define TXD_FLAG_TCPUDP_CSUM 0x0001
1512 #define TXD_FLAG_IP_CSUM 0x0002
1513 #define TXD_FLAG_END 0x0004
1514 #define TXD_FLAG_IP_FRAG 0x0008
1515 #define TXD_FLAG_IP_FRAG_END 0x0010
1516 #define TXD_FLAG_VLAN 0x0040
1517 #define TXD_FLAG_COAL_NOW 0x0080
1518 #define TXD_FLAG_CPU_PRE_DMA 0x0100
1519 #define TXD_FLAG_CPU_POST_DMA 0x0200
1520 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
1521 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
1522 #define TXD_FLAG_NO_CRC 0x8000
1523 #define TXD_LEN_SHIFT 16
1526 #define TXD_VLAN_TAG_SHIFT 0
1527 #define TXD_MSS_SHIFT 16
1530 #define TXD_ADDR 0x00UL /* 64-bit */
1531 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
1532 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
1533 #define TXD_SIZE 0x10UL
1535 struct tg3_rx_buffer_desc {
1540 #define RXD_IDX_MASK 0xffff0000
1541 #define RXD_IDX_SHIFT 16
1542 #define RXD_LEN_MASK 0x0000ffff
1543 #define RXD_LEN_SHIFT 0
1546 #define RXD_TYPE_SHIFT 16
1547 #define RXD_FLAGS_SHIFT 0
1549 #define RXD_FLAG_END 0x0004
1550 #define RXD_FLAG_MINI 0x0800
1551 #define RXD_FLAG_JUMBO 0x0020
1552 #define RXD_FLAG_VLAN 0x0040
1553 #define RXD_FLAG_ERROR 0x0400
1554 #define RXD_FLAG_IP_CSUM 0x1000
1555 #define RXD_FLAG_TCPUDP_CSUM 0x2000
1556 #define RXD_FLAG_IS_TCP 0x4000
1559 #define RXD_IPCSUM_MASK 0xffff0000
1560 #define RXD_IPCSUM_SHIFT 16
1561 #define RXD_TCPCSUM_MASK 0x0000ffff
1562 #define RXD_TCPCSUM_SHIFT 0
1566 #define RXD_VLAN_MASK 0x0000ffff
1568 #define RXD_ERR_BAD_CRC 0x00010000
1569 #define RXD_ERR_COLLISION 0x00020000
1570 #define RXD_ERR_LINK_LOST 0x00040000
1571 #define RXD_ERR_PHY_DECODE 0x00080000
1572 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
1573 #define RXD_ERR_MAC_ABRT 0x00200000
1574 #define RXD_ERR_TOO_SMALL 0x00400000
1575 #define RXD_ERR_NO_RESOURCES 0x00800000
1576 #define RXD_ERR_HUGE_FRAME 0x01000000
1577 #define RXD_ERR_MASK 0xffff0000
1581 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
1582 #define RXD_OPAQUE_INDEX_SHIFT 0
1583 #define RXD_OPAQUE_RING_STD 0x00010000
1584 #define RXD_OPAQUE_RING_JUMBO 0x00020000
1585 #define RXD_OPAQUE_RING_MINI 0x00040000
1586 #define RXD_OPAQUE_RING_MASK 0x00070000
1589 struct tg3_ext_rx_buffer_desc {
1596 struct tg3_rx_buffer_desc std;
1599 /* We only use this when testing out the DMA engine
1600 * at probe time. This is the internal format of buffer
1601 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
1603 struct tg3_internal_buffer_desc {
1621 #define TG3_HW_STATUS_SIZE 0x50
1622 struct tg3_hw_status {
1624 #define SD_STATUS_UPDATED 0x00000001
1625 #define SD_STATUS_LINK_CHG 0x00000002
1626 #define SD_STATUS_ERROR 0x00000004
1632 u16 rx_jumbo_consumer;
1634 u16 rx_jumbo_consumer;
1640 u16 rx_mini_consumer;
1642 u16 rx_mini_consumer;
1660 struct tg3_hw_stats {
1661 u8 __reserved0[0x400-0x300];
1663 /* Statistics maintained by Receive MAC. */
1664 tg3_stat64_t rx_octets;
1666 tg3_stat64_t rx_fragments;
1667 tg3_stat64_t rx_ucast_packets;
1668 tg3_stat64_t rx_mcast_packets;
1669 tg3_stat64_t rx_bcast_packets;
1670 tg3_stat64_t rx_fcs_errors;
1671 tg3_stat64_t rx_align_errors;
1672 tg3_stat64_t rx_xon_pause_rcvd;
1673 tg3_stat64_t rx_xoff_pause_rcvd;
1674 tg3_stat64_t rx_mac_ctrl_rcvd;
1675 tg3_stat64_t rx_xoff_entered;
1676 tg3_stat64_t rx_frame_too_long_errors;
1677 tg3_stat64_t rx_jabbers;
1678 tg3_stat64_t rx_undersize_packets;
1679 tg3_stat64_t rx_in_length_errors;
1680 tg3_stat64_t rx_out_length_errors;
1681 tg3_stat64_t rx_64_or_less_octet_packets;
1682 tg3_stat64_t rx_65_to_127_octet_packets;
1683 tg3_stat64_t rx_128_to_255_octet_packets;
1684 tg3_stat64_t rx_256_to_511_octet_packets;
1685 tg3_stat64_t rx_512_to_1023_octet_packets;
1686 tg3_stat64_t rx_1024_to_1522_octet_packets;
1687 tg3_stat64_t rx_1523_to_2047_octet_packets;
1688 tg3_stat64_t rx_2048_to_4095_octet_packets;
1689 tg3_stat64_t rx_4096_to_8191_octet_packets;
1690 tg3_stat64_t rx_8192_to_9022_octet_packets;
1694 /* Statistics maintained by Transmit MAC. */
1695 tg3_stat64_t tx_octets;
1697 tg3_stat64_t tx_collisions;
1698 tg3_stat64_t tx_xon_sent;
1699 tg3_stat64_t tx_xoff_sent;
1700 tg3_stat64_t tx_flow_control;
1701 tg3_stat64_t tx_mac_errors;
1702 tg3_stat64_t tx_single_collisions;
1703 tg3_stat64_t tx_mult_collisions;
1704 tg3_stat64_t tx_deferred;
1706 tg3_stat64_t tx_excessive_collisions;
1707 tg3_stat64_t tx_late_collisions;
1708 tg3_stat64_t tx_collide_2times;
1709 tg3_stat64_t tx_collide_3times;
1710 tg3_stat64_t tx_collide_4times;
1711 tg3_stat64_t tx_collide_5times;
1712 tg3_stat64_t tx_collide_6times;
1713 tg3_stat64_t tx_collide_7times;
1714 tg3_stat64_t tx_collide_8times;
1715 tg3_stat64_t tx_collide_9times;
1716 tg3_stat64_t tx_collide_10times;
1717 tg3_stat64_t tx_collide_11times;
1718 tg3_stat64_t tx_collide_12times;
1719 tg3_stat64_t tx_collide_13times;
1720 tg3_stat64_t tx_collide_14times;
1721 tg3_stat64_t tx_collide_15times;
1722 tg3_stat64_t tx_ucast_packets;
1723 tg3_stat64_t tx_mcast_packets;
1724 tg3_stat64_t tx_bcast_packets;
1725 tg3_stat64_t tx_carrier_sense_errors;
1726 tg3_stat64_t tx_discards;
1727 tg3_stat64_t tx_errors;
1731 /* Statistics maintained by Receive List Placement. */
1732 tg3_stat64_t COS_rx_packets[16];
1733 tg3_stat64_t COS_rx_filter_dropped;
1734 tg3_stat64_t dma_writeq_full;
1735 tg3_stat64_t dma_write_prioq_full;
1736 tg3_stat64_t rxbds_empty;
1737 tg3_stat64_t rx_discards;
1738 tg3_stat64_t rx_errors;
1739 tg3_stat64_t rx_threshold_hit;
1743 /* Statistics maintained by Send Data Initiator. */
1744 tg3_stat64_t COS_out_packets[16];
1745 tg3_stat64_t dma_readq_full;
1746 tg3_stat64_t dma_read_prioq_full;
1747 tg3_stat64_t tx_comp_queue_full;
1749 /* Statistics maintained by Host Coalescing. */
1750 tg3_stat64_t ring_set_send_prod_index;
1751 tg3_stat64_t ring_status_update;
1752 tg3_stat64_t nic_irqs;
1753 tg3_stat64_t nic_avoided_irqs;
1754 tg3_stat64_t nic_tx_threshold_hit;
1756 u8 __reserved4[0xb00-0x9c0];
1761 led_mode_three_link,
1765 /* 'mapping' is superfluous as the chip does not write into
1766 * the tx/rx post rings so we could just fetch it from there.
1767 * But the cache behavior is better how we are doing it now.
1770 struct sk_buff *skb;
1771 DECLARE_PCI_UNMAP_ADDR(mapping)
1774 struct tx_ring_info {
1775 struct sk_buff *skb;
1776 DECLARE_PCI_UNMAP_ADDR(mapping)
1780 struct tg3_config_info {
1784 struct tg3_link_config {
1785 /* Describes what we're trying to get. */
1791 /* Describes what we actually have. */
1794 #define SPEED_INVALID 0xffff
1795 #define DUPLEX_INVALID 0xff
1796 #define AUTONEG_INVALID 0xff
1798 /* When we go in and out of low power mode we need
1799 * to swap with this state.
1801 int phy_is_low_power;
1807 struct tg3_bufmgr_config {
1808 u32 mbuf_read_dma_low_water;
1809 u32 mbuf_mac_rx_low_water;
1810 u32 mbuf_high_water;
1812 u32 mbuf_read_dma_low_water_jumbo;
1813 u32 mbuf_mac_rx_low_water_jumbo;
1814 u32 mbuf_high_water_jumbo;
1820 struct tg3_ethtool_stats {
1821 /* Statistics maintained by Receive MAC. */
1823 u64 rx_ucast_packets;
1824 u64 rx_bcast_packets;
1826 u64 rx_xon_pause_rcvd;
1827 u64 rx_xoff_pause_rcvd;
1828 u64 rx_mac_ctrl_rcvd;
1829 u64 rx_xoff_entered;
1830 u64 rx_frame_too_long_errors;
1832 u64 rx_undersize_packets;
1833 u64 rx_in_length_errors;
1834 u64 rx_out_length_errors;
1836 /* Statistics maintained by Transmit MAC. */
1839 u64 tx_flow_control;
1841 u64 tx_single_collisions;
1842 u64 tx_mult_collisions;
1844 u64 tx_excessive_collisions;
1845 u64 tx_late_collisions;
1846 u64 tx_ucast_packets;
1847 u64 tx_mcast_packets;
1848 u64 tx_bcast_packets;
1852 /* begin "general, frequently-used members" cacheline section */
1854 /* SMP locking strategy:
1856 * lock: Held during all operations except TX packet
1859 * tx_lock: Held during tg3_start_xmit{,_4gbug} and tg3_tx
1861 * If you want to shut up all asynchronous processing you must
1862 * acquire both locks, 'lock' taken before 'tx_lock'. IRQs must
1863 * be disabled to take 'lock' but only softirq disabling is
1864 * necessary for acquisition of 'tx_lock'.
1867 spinlock_t indirect_lock;
1870 struct net_device *dev;
1871 struct pci_dev *pdev;
1873 struct tg3_hw_status *hw_status;
1874 dma_addr_t status_mapping;
1878 /* begin "tx thread" cacheline section */
1885 /* TX descs are only used if TG3_FLAG_HOST_TXDS is set. */
1886 struct tg3_tx_buffer_desc *tx_ring;
1887 struct tx_ring_info *tx_buffers;
1888 dma_addr_t tx_desc_mapping;
1890 /* begin "rx thread" cacheline section */
1895 u32 rx_jumbo_pending;
1896 #if TG3_VLAN_TAG_USED
1897 struct vlan_group *vlgrp;
1900 struct tg3_rx_buffer_desc *rx_std;
1901 struct ring_info *rx_std_buffers;
1902 dma_addr_t rx_std_mapping;
1904 struct tg3_rx_buffer_desc *rx_jumbo;
1905 struct ring_info *rx_jumbo_buffers;
1906 dma_addr_t rx_jumbo_mapping;
1908 struct tg3_rx_buffer_desc *rx_rcb;
1909 dma_addr_t rx_rcb_mapping;
1911 /* begin "everything else" cacheline(s) section */
1912 struct net_device_stats net_stats;
1913 struct net_device_stats net_stats_prev;
1914 struct tg3_ethtool_stats estats;
1915 struct tg3_ethtool_stats estats_prev;
1917 unsigned long phy_crc_errors;
1921 #define TG3_FLAG_HOST_TXDS 0x00000001
1922 #define TG3_FLAG_TXD_MBOX_HWBUG 0x00000002
1923 #define TG3_FLAG_RX_CHECKSUMS 0x00000004
1924 #define TG3_FLAG_USE_LINKCHG_REG 0x00000008
1925 #define TG3_FLAG_USE_MI_INTERRUPT 0x00000010
1926 #define TG3_FLAG_ENABLE_ASF 0x00000020
1927 #define TG3_FLAG_5701_REG_WRITE_BUG 0x00000040
1928 #define TG3_FLAG_POLL_SERDES 0x00000080
1929 #if defined(CONFIG_X86)
1930 #define TG3_FLAG_MBOX_WRITE_REORDER 0x00000100
1932 #define TG3_FLAG_MBOX_WRITE_REORDER 0 /* disables code too */
1934 #define TG3_FLAG_PCIX_TARGET_HWBUG 0x00000200
1935 #define TG3_FLAG_WOL_SPEED_100MB 0x00000400
1936 #define TG3_FLAG_WOL_ENABLE 0x00000800
1937 #define TG3_FLAG_EEPROM_WRITE_PROT 0x00001000
1938 #define TG3_FLAG_NVRAM 0x00002000
1939 #define TG3_FLAG_NVRAM_BUFFERED 0x00004000
1940 #define TG3_FLAG_RX_PAUSE 0x00008000
1941 #define TG3_FLAG_TX_PAUSE 0x00010000
1942 #define TG3_FLAG_PCIX_MODE 0x00020000
1943 #define TG3_FLAG_PCI_HIGH_SPEED 0x00040000
1944 #define TG3_FLAG_PCI_32BIT 0x00080000
1945 #define TG3_FLAG_NO_TX_PSEUDO_CSUM 0x00100000
1946 #define TG3_FLAG_NO_RX_PSEUDO_CSUM 0x00200000
1947 #define TG3_FLAG_SERDES_WOL_CAP 0x00400000
1948 #define TG3_FLAG_JUMBO_ENABLE 0x00800000
1949 #define TG3_FLAG_10_100_ONLY 0x01000000
1950 #define TG3_FLAG_PAUSE_AUTONEG 0x02000000
1951 #define TG3_FLAG_PAUSE_RX 0x04000000
1952 #define TG3_FLAG_PAUSE_TX 0x08000000
1953 #define TG3_FLAG_BROKEN_CHECKSUMS 0x10000000
1954 #define TG3_FLAG_GOT_SERDES_FLOWCTL 0x20000000
1955 #define TG3_FLAG_SPLIT_MODE 0x40000000
1956 #define TG3_FLAG_INIT_COMPLETE 0x80000000
1958 #define TG3_FLG2_RESTART_TIMER 0x00000001
1959 #define TG3_FLG2_SUN_5704 0x00000002
1960 #define TG3_FLG2_NO_ETH_WIRE_SPEED 0x00000004
1961 #define TG3_FLG2_IS_5788 0x00000008
1962 #define TG3_FLG2_MAX_RXPEND_64 0x00000010
1963 #define TG3_FLG2_TSO_CAPABLE 0x00000020
1964 #define TG3_FLG2_PHY_ADC_BUG 0x00000040
1965 #define TG3_FLG2_PHY_5704_A0_BUG 0x00000080
1966 #define TG3_FLG2_PHY_BER_BUG 0x00000100
1968 u32 split_mode_max_reqs;
1969 #define SPLIT_MODE_5704_MAX_REQ 3
1971 struct timer_list timer;
1973 u16 timer_multiplier;
1978 struct tg3_link_config link_config;
1979 struct tg3_bufmgr_config bufmgr_config;
1981 /* cache h/w values, often passed straight to h/w */
1993 u16 pci_chip_rev_id;
1994 u8 pci_cacheline_sz;
1998 u32 pci_cfg_state[64 / sizeof(u32)];
2004 #define PHY_ID_MASK 0xfffffff0
2005 #define PHY_ID_BCM5400 0x60008040
2006 #define PHY_ID_BCM5401 0x60008050
2007 #define PHY_ID_BCM5411 0x60008070
2008 #define PHY_ID_BCM5701 0x60008110
2009 #define PHY_ID_BCM5703 0x60008160
2010 #define PHY_ID_BCM5704 0x60008190
2011 #define PHY_ID_BCM5705 0x600081a0
2012 #define PHY_ID_BCM8002 0x60010140
2013 #define PHY_ID_SERDES 0xfeedbee0
2014 #define PHY_ID_INVALID 0xffffffff
2015 #define PHY_ID_REV_MASK 0x0000000f
2016 #define PHY_REV_BCM5401_B0 0x1
2017 #define PHY_REV_BCM5401_B2 0x3
2018 #define PHY_REV_BCM5401_C0 0x6
2019 #define PHY_REV_BCM5411_X0 0x1 /* Found on Netgear GA302T */
2021 enum phy_led_mode led_mode;
2023 char board_part_number[24];
2024 u32 nic_sram_data_cfg;
2026 struct pci_dev *pdev_peer;
2028 /* This macro assumes the passed PHY ID is already masked
2031 #define KNOWN_PHY_ID(X) \
2032 ((X) == PHY_ID_BCM5400 || (X) == PHY_ID_BCM5401 || \
2033 (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
2034 (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
2035 (X) == PHY_ID_BCM5705 || \
2036 (X) == PHY_ID_BCM8002 || (X) == PHY_ID_SERDES)
2038 struct tg3_hw_stats *hw_stats;
2039 dma_addr_t stats_mapping;
2040 struct work_struct reset_task;
2043 #endif /* !(_T3_H) */
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