drivers/net/typhoon.c

   1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
   2 /*
   3         Written 2002-2004 by David Dillow <dave@thedillows.org>
   4         Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
   5         Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
   6
   7         This software may be used and distributed according to the terms of
   8         the GNU General Public License (GPL), incorporated herein by reference.
   9         Drivers based on or derived from this code fall under the GPL and must
  10         retain the authorship, copyright and license notice.  This file is not
  11         a complete program and may only be used when the entire operating
  12         system is licensed under the GPL.
  13
  14         This software is available on a public web site. It may enable
  15         cryptographic capabilities of the 3Com hardware, and may be
  16         exported from the United States under License Exception "TSU"
  17         pursuant to 15 C.F.R. Section 740.13(e).
  18
  19         This work was funded by the National Library of Medicine under
  20         the Department of Energy project number 0274DD06D1 and NLM project
  21         number Y1-LM-2015-01.
  22
  23         This driver is designed for the 3Com 3CR990 Family of cards with the
  24         3XP Processor. It has been tested on x86 and sparc64.
  25
  26         KNOWN ISSUES:
  27         *) The current firmware always strips the VLAN tag off, even if
  28                 we tell it not to. You should filter VLANs at the switch
  29                 as a workaround (good practice in any event) until we can
  30                 get this fixed.
  31         *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  32                 issue. Hopefully 3Com will fix it.
  33         *) Waiting for a command response takes 8ms due to non-preemptable
  34                 polling. Only significant for getting stats and creating
  35                 SAs, but an ugly wart never the less.
  36
  37         TODO:
  38         *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  39         *) Add more support for ethtool (especially for NIC stats)
  40         *) Allow disabling of RX checksum offloading
  41         *) Fix MAC changing to work while the interface is up
  42                 (Need to put commands on the TX ring, which changes
  43                 the locking)
  44         *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  45                 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  46 */
  47
  48 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  49  * Setting to > 1518 effectively disables this feature.
  50  */
  51 static int rx_copybreak = 200;
  52
  53 /* end user-configurable values */
  54
  55 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  56  */
  57 static const int multicast_filter_limit = 32;
  58
  59 /* Operational parameters that are set at compile time. */
  60
  61 /* Keep the ring sizes a power of two for compile efficiency.
  62  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  63  * Making the Tx ring too large decreases the effectiveness of channel
  64  * bonding and packet priority.
  65  * There are no ill effects from too-large receive rings.
  66  *
  67  * We don't currently use the Hi Tx ring so, don't make it very big.
  68  *
  69  * Beware that if we start using the Hi Tx ring, we will need to change
  70  * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  71  */
  72 #define TXHI_ENTRIES            2
  73 #define TXLO_ENTRIES            128
  74 #define RX_ENTRIES              32
  75 #define COMMAND_ENTRIES         16
  76 #define RESPONSE_ENTRIES        32
  77
  78 #define COMMAND_RING_SIZE       (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  79 #define RESPONSE_RING_SIZE      (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  80
  81 /* The 3XP will preload and remove 64 entries from the free buffer
  82  * list, and we need one entry to keep the ring from wrapping, so
  83  * to keep this a power of two, we use 128 entries.
  84  */
  85 #define RXFREE_ENTRIES          128
  86 #define RXENT_ENTRIES           (RXFREE_ENTRIES - 1)
  87
  88 /* Operational parameters that usually are not changed. */
  89
  90 /* Time in jiffies before concluding the transmitter is hung. */
  91 #define TX_TIMEOUT  (2*HZ)
  92
  93 #define PKT_BUF_SZ              1536
  94
  95 #define DRV_MODULE_NAME         "typhoon"
  96 #define DRV_MODULE_VERSION      "1.5.4"
  97 #define DRV_MODULE_RELDATE      "04/09/09"
  98 #define PFX                     DRV_MODULE_NAME ": "
  99 #define ERR_PFX                 KERN_ERR PFX
 100
 101 #include <linux/module.h>
 102 #include <linux/kernel.h>
 103 #include <linux/string.h>
 104 #include <linux/timer.h>
 105 #include <linux/errno.h>
 106 #include <linux/ioport.h>
 107 #include <linux/slab.h>
 108 #include <linux/interrupt.h>
 109 #include <linux/pci.h>
 110 #include <linux/netdevice.h>
 111 #include <linux/etherdevice.h>
 112 #include <linux/skbuff.h>
 113 #include <linux/init.h>
 114 #include <linux/delay.h>
 115 #include <linux/ethtool.h>
 116 #include <linux/if_vlan.h>
 117 #include <linux/crc32.h>
 118 #include <linux/bitops.h>
 119 #include <asm/processor.h>
 120 #include <asm/io.h>
 121 #include <asm/uaccess.h>
 122 #include <linux/in6.h>
 123 #include <asm/checksum.h>
 124 #include <linux/version.h>
 125 #include <linux/dma-mapping.h>
 126
 127 #include "typhoon.h"
 128 #include "typhoon-firmware.h"
 129
 130 static char version[] __devinitdata =
 131     "typhoon.c: version " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 132
 133 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
 134 MODULE_LICENSE("GPL");
 135 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
 136 MODULE_PARM(rx_copybreak, "i");
 137
 138 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
 139 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
 140 #undef NETIF_F_TSO
 141 #endif
 142
 143 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
 144 #error TX ring too small!
 145 #endif
 146
 147 struct typhoon_card_info {
 148         char *name;
 149         int capabilities;
 150 };
 151
 152 #define TYPHOON_CRYPTO_NONE             0x00
 153 #define TYPHOON_CRYPTO_DES              0x01
 154 #define TYPHOON_CRYPTO_3DES             0x02
 155 #define TYPHOON_CRYPTO_VARIABLE         0x04
 156 #define TYPHOON_FIBER                   0x08
 157 #define TYPHOON_WAKEUP_NEEDS_RESET      0x10
 158
 159 enum typhoon_cards {
 160         TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
 161         TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
 162         TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
 163         TYPHOON_FXM,
 164 };
 165
 166 /* directly indexed by enum typhoon_cards, above */
 167 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
 168         { "3Com Typhoon (3C990-TX)",
 169                 TYPHOON_CRYPTO_NONE},
 170         { "3Com Typhoon (3CR990-TX-95)",
 171                 TYPHOON_CRYPTO_DES},
 172         { "3Com Typhoon (3CR990-TX-97)",
 173                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 174         { "3Com Typhoon (3C990SVR)",
 175                 TYPHOON_CRYPTO_NONE},
 176         { "3Com Typhoon (3CR990SVR95)",
 177                 TYPHOON_CRYPTO_DES},
 178         { "3Com Typhoon (3CR990SVR97)",
 179                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 180         { "3Com Typhoon2 (3C990B-TX-M)",
 181                 TYPHOON_CRYPTO_VARIABLE},
 182         { "3Com Typhoon2 (3C990BSVR)",
 183                 TYPHOON_CRYPTO_VARIABLE},
 184         { "3Com Typhoon (3CR990-FX-95)",
 185                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 186         { "3Com Typhoon (3CR990-FX-97)",
 187                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 188         { "3Com Typhoon (3CR990-FX-95 Server)",
 189                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 190         { "3Com Typhoon (3CR990-FX-97 Server)",
 191                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 192         { "3Com Typhoon2 (3C990B-FX-97)",
 193                 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
 194 };
 195
 196 /* Notes on the new subsystem numbering scheme:
 197  * bits 0-1 indicate crypto capabilites: (0) variable, (1) DES, or (2) 3DES
 198  * bit 4 indicates if this card has secured firmware (we don't support it)
 199  * bit 8 indicates if this is a (0) copper or (1) fiber card
 200  * bits 12-16 indicate card type: (0) client and (1) server
 201  */
 202 static struct pci_device_id typhoon_pci_tbl[] = {
 203         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
 204           PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
 205         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
 206           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
 207         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
 208           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
 209         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 210           PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
 211         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 212           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
 213         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 214           PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
 215         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 216           PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
 217         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 218           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
 219         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 220           PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
 221         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 222           PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
 223         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
 224           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
 225         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
 226           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
 227         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
 228           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
 229         { 0, }
 230 };
 231 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
 232
 233 /* Define the shared memory area
 234  * Align everything the 3XP will normally be using.
 235  * We'll need to move/align txHi if we start using that ring.
 236  */
 237 #define __3xp_aligned   ____cacheline_aligned
 238 struct typhoon_shared {
 239         struct typhoon_interface        iface;
 240         struct typhoon_indexes          indexes                 __3xp_aligned;
 241         struct tx_desc                  txLo[TXLO_ENTRIES]      __3xp_aligned;
 242         struct rx_desc                  rxLo[RX_ENTRIES]        __3xp_aligned;
 243         struct rx_desc                  rxHi[RX_ENTRIES]        __3xp_aligned;
 244         struct cmd_desc                 cmd[COMMAND_ENTRIES]    __3xp_aligned;
 245         struct resp_desc                resp[RESPONSE_ENTRIES]  __3xp_aligned;
 246         struct rx_free                  rxBuff[RXFREE_ENTRIES]  __3xp_aligned;
 247         u32                             zeroWord;
 248         struct tx_desc                  txHi[TXHI_ENTRIES];
 249 } __attribute__ ((packed));
 250
 251 struct rxbuff_ent {
 252         struct sk_buff *skb;
 253         dma_addr_t      dma_addr;
 254 };
 255
 256 struct typhoon {
 257         /* Tx cache line section */
 258         struct transmit_ring    txLoRing        ____cacheline_aligned;
 259         struct pci_dev *        tx_pdev;
 260         void __iomem            *tx_ioaddr;
 261         u32                     txlo_dma_addr;
 262
 263         /* Irq/Rx cache line section */
 264         void __iomem            *ioaddr         ____cacheline_aligned;
 265         struct typhoon_indexes *indexes;
 266         u8                      awaiting_resp;
 267         u8                      duplex;
 268         u8                      speed;
 269         u8                      card_state;
 270         struct basic_ring       rxLoRing;
 271         struct pci_dev *        pdev;
 272         struct net_device *     dev;
 273         spinlock_t              state_lock;
 274         struct vlan_group *     vlgrp;
 275         struct basic_ring       rxHiRing;
 276         struct basic_ring       rxBuffRing;
 277         struct rxbuff_ent       rxbuffers[RXENT_ENTRIES];
 278
 279         /* general section */
 280         spinlock_t              command_lock    ____cacheline_aligned;
 281         struct basic_ring       cmdRing;
 282         struct basic_ring       respRing;
 283         struct net_device_stats stats;
 284         struct net_device_stats stats_saved;
 285         const char *            name;
 286         struct typhoon_shared * shared;
 287         dma_addr_t              shared_dma;
 288         u16                     xcvr_select;
 289         u16                     wol_events;
 290         u32                     offload;
 291
 292         /* unused stuff (future use) */
 293         int                     capabilities;
 294         struct transmit_ring    txHiRing;
 295 };
 296
 297 enum completion_wait_values {
 298         NoWait = 0, WaitNoSleep, WaitSleep,
 299 };
 300
 301 /* These are the values for the typhoon.card_state variable.
 302  * These determine where the statistics will come from in get_stats().
 303  * The sleep image does not support the statistics we need.
 304  */
 305 enum state_values {
 306         Sleeping = 0, Running,
 307 };
 308
 309 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
 310  * cannot pass a read, so this forces current writes to post.
 311  */
 312 #define typhoon_post_pci_writes(x) \
 313         do { readl(x + TYPHOON_REG_HEARTBEAT); } while(0)
 314
 315 /* We'll wait up to six seconds for a reset, and half a second normally.
 316  */
 317 #define TYPHOON_UDELAY                  50
 318 #define TYPHOON_RESET_TIMEOUT_SLEEP     (6 * HZ)
 319 #define TYPHOON_RESET_TIMEOUT_NOSLEEP   ((6 * 1000000) / TYPHOON_UDELAY)
 320 #define TYPHOON_WAIT_TIMEOUT            ((1000000 / 2) / TYPHOON_UDELAY)
 321
 322 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 28)
 323 #define typhoon_synchronize_irq(x) synchronize_irq()
 324 #else
 325 #define typhoon_synchronize_irq(x) synchronize_irq(x)
 326 #endif
 327
 328 #if defined(NETIF_F_TSO)
 329 #define skb_tso_size(x)         (skb_shinfo(x)->tso_size)
 330 #define TSO_NUM_DESCRIPTORS     2
 331 #define TSO_OFFLOAD_ON          TYPHOON_OFFLOAD_TCP_SEGMENT
 332 #else
 333 #define NETIF_F_TSO             0
 334 #define skb_tso_size(x)         0
 335 #define TSO_NUM_DESCRIPTORS     0
 336 #define TSO_OFFLOAD_ON          0
 337 #endif
 338
 339 static inline void
 340 typhoon_inc_index(u32 *index, const int count, const int num_entries)
 341 {
 342         /* Increment a ring index -- we can use this for all rings execept
 343          * the Rx rings, as they use different size descriptors
 344          * otherwise, everything is the same size as a cmd_desc
 345          */
 346         *index += count * sizeof(struct cmd_desc);
 347         *index %= num_entries * sizeof(struct cmd_desc);
 348 }
 349
 350 static inline void
 351 typhoon_inc_cmd_index(u32 *index, const int count)
 352 {
 353         typhoon_inc_index(index, count, COMMAND_ENTRIES);
 354 }
 355
 356 static inline void
 357 typhoon_inc_resp_index(u32 *index, const int count)
 358 {
 359         typhoon_inc_index(index, count, RESPONSE_ENTRIES);
 360 }
 361
 362 static inline void
 363 typhoon_inc_rxfree_index(u32 *index, const int count)
 364 {
 365         typhoon_inc_index(index, count, RXFREE_ENTRIES);
 366 }
 367
 368 static inline void
 369 typhoon_inc_tx_index(u32 *index, const int count)
 370 {
 371         /* if we start using the Hi Tx ring, this needs updateing */
 372         typhoon_inc_index(index, count, TXLO_ENTRIES);
 373 }
 374
 375 static inline void
 376 typhoon_inc_rx_index(u32 *index, const int count)
 377 {
 378         /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
 379         *index += count * sizeof(struct rx_desc);
 380         *index %= RX_ENTRIES * sizeof(struct rx_desc);
 381 }
 382
 383 static int
 384 typhoon_reset(void __iomem *ioaddr, int wait_type)
 385 {
 386         int i, err = 0;
 387         int timeout;
 388
 389         if(wait_type == WaitNoSleep)
 390                 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
 391         else
 392                 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
 393
 394         writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 395         writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 396
 397         writel(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
 398         typhoon_post_pci_writes(ioaddr);
 399         udelay(1);
 400         writel(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
 401
 402         if(wait_type != NoWait) {
 403                 for(i = 0; i < timeout; i++) {
 404                         if(readl(ioaddr + TYPHOON_REG_STATUS) ==
 405                            TYPHOON_STATUS_WAITING_FOR_HOST)
 406                                 goto out;
 407
 408                         if(wait_type == WaitSleep) {
 409                                 set_current_state(TASK_UNINTERRUPTIBLE);
 410                                 schedule_timeout(1);
 411                         } else
 412                                 udelay(TYPHOON_UDELAY);
 413                 }
 414
 415                 err = -ETIMEDOUT;
 416         }
 417
 418 out:
 419         writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 420         writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 421
 422         /* The 3XP seems to need a little extra time to complete the load
 423          * of the sleep image before we can reliably boot it. Failure to
 424          * do this occasionally results in a hung adapter after boot in
 425          * typhoon_init_one() while trying to read the MAC address or
 426          * putting the card to sleep. 3Com's driver waits 5ms, but
 427          * that seems to be overkill. However, if we can sleep, we might
 428          * as well give it that much time. Otherwise, we'll give it 500us,
 429          * which should be enough (I've see it work well at 100us, but still
 430          * saw occasional problems.)
 431          */
 432         if(wait_type == WaitSleep)
 433                 msleep(5);
 434         else
 435                 udelay(500);
 436         return err;
 437 }
 438
 439 static int
 440 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
 441 {
 442         int i, err = 0;
 443
 444         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
 445                 if(readl(ioaddr + TYPHOON_REG_STATUS) == wait_value)
 446                         goto out;
 447                 udelay(TYPHOON_UDELAY);
 448         }
 449
 450         err = -ETIMEDOUT;
 451
 452 out:
 453         return err;
 454 }
 455
 456 static inline void
 457 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
 458 {
 459         if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
 460                 netif_carrier_off(dev);
 461         else
 462                 netif_carrier_on(dev);
 463 }
 464
 465 static inline void
 466 typhoon_hello(struct typhoon *tp)
 467 {
 468         struct basic_ring *ring = &tp->cmdRing;
 469         struct cmd_desc *cmd;
 470
 471         /* We only get a hello request if we've not sent anything to the
 472          * card in a long while. If the lock is held, then we're in the
 473          * process of issuing a command, so we don't need to respond.
 474          */
 475         if(spin_trylock(&tp->command_lock)) {
 476                 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
 477                 typhoon_inc_cmd_index(&ring->lastWrite, 1);
 478
 479                 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
 480                 smp_wmb();
 481                 writel(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 482                 spin_unlock(&tp->command_lock);
 483         }
 484 }
 485
 486 static int
 487 typhoon_process_response(struct typhoon *tp, int resp_size,
 488                                 struct resp_desc *resp_save)
 489 {
 490         struct typhoon_indexes *indexes = tp->indexes;
 491         struct resp_desc *resp;
 492         u8 *base = tp->respRing.ringBase;
 493         int count, len, wrap_len;
 494         u32 cleared;
 495         u32 ready;
 496
 497         cleared = le32_to_cpu(indexes->respCleared);
 498         ready = le32_to_cpu(indexes->respReady);
 499         while(cleared != ready) {
 500                 resp = (struct resp_desc *)(base + cleared);
 501                 count = resp->numDesc + 1;
 502                 if(resp_save && resp->seqNo) {
 503                         if(count > resp_size) {
 504                                 resp_save->flags = TYPHOON_RESP_ERROR;
 505                                 goto cleanup;
 506                         }
 507
 508                         wrap_len = 0;
 509                         len = count * sizeof(*resp);
 510                         if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
 511                                 wrap_len = cleared + len - RESPONSE_RING_SIZE;
 512                                 len = RESPONSE_RING_SIZE - cleared;
 513                         }
 514
 515                         memcpy(resp_save, resp, len);
 516                         if(unlikely(wrap_len)) {
 517                                 resp_save += len / sizeof(*resp);
 518                                 memcpy(resp_save, base, wrap_len);
 519                         }
 520
 521                         resp_save = NULL;
 522                 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
 523                         typhoon_media_status(tp->dev, resp);
 524                 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
 525                         typhoon_hello(tp);
 526                 } else {
 527                         printk(KERN_ERR "%s: dumping unexpected response "
 528                                "0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
 529                                tp->name, le16_to_cpu(resp->cmd),
 530                                resp->numDesc, resp->flags,
 531                                le16_to_cpu(resp->parm1),
 532                                le32_to_cpu(resp->parm2),
 533                                le32_to_cpu(resp->parm3));
 534                 }
 535
 536 cleanup:
 537                 typhoon_inc_resp_index(&cleared, count);
 538         }
 539
 540         indexes->respCleared = cpu_to_le32(cleared);
 541         wmb();
 542         return (resp_save == NULL);
 543 }
 544
 545 static inline int
 546 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
 547 {
 548         /* this works for all descriptors but rx_desc, as they are a
 549          * different size than the cmd_desc -- everyone else is the same
 550          */
 551         lastWrite /= sizeof(struct cmd_desc);
 552         lastRead /= sizeof(struct cmd_desc);
 553         return (ringSize + lastRead - lastWrite - 1) % ringSize;
 554 }
 555
 556 static inline int
 557 typhoon_num_free_cmd(struct typhoon *tp)
 558 {
 559         int lastWrite = tp->cmdRing.lastWrite;
 560         int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
 561
 562         return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
 563 }
 564
 565 static inline int
 566 typhoon_num_free_resp(struct typhoon *tp)
 567 {
 568         int respReady = le32_to_cpu(tp->indexes->respReady);
 569         int respCleared = le32_to_cpu(tp->indexes->respCleared);
 570
 571         return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
 572 }
 573
 574 static inline int
 575 typhoon_num_free_tx(struct transmit_ring *ring)
 576 {
 577         /* if we start using the Hi Tx ring, this needs updating */
 578         return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
 579 }
 580
 581 static int
 582 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
 583                       int num_resp, struct resp_desc *resp)
 584 {
 585         struct typhoon_indexes *indexes = tp->indexes;
 586         struct basic_ring *ring = &tp->cmdRing;
 587         struct resp_desc local_resp;
 588         int i, err = 0;
 589         int got_resp;
 590         int freeCmd, freeResp;
 591         int len, wrap_len;
 592
 593         spin_lock(&tp->command_lock);
 594
 595         freeCmd = typhoon_num_free_cmd(tp);
 596         freeResp = typhoon_num_free_resp(tp);
 597
 598         if(freeCmd < num_cmd || freeResp < num_resp) {
 599                 printk("%s: no descs for cmd, had (needed) %d (%d) cmd, "
 600                         "%d (%d) resp\n", tp->name, freeCmd, num_cmd,
 601                         freeResp, num_resp);
 602                 err = -ENOMEM;
 603                 goto out;
 604         }
 605
 606         if(cmd->flags & TYPHOON_CMD_RESPOND) {
 607                 /* If we're expecting a response, but the caller hasn't given
 608                  * us a place to put it, we'll provide one.
 609                  */
 610                 tp->awaiting_resp = 1;
 611                 if(resp == NULL) {
 612                         resp = &local_resp;
 613                         num_resp = 1;
 614                 }
 615         }
 616
 617         wrap_len = 0;
 618         len = num_cmd * sizeof(*cmd);
 619         if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
 620                 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
 621                 len = COMMAND_RING_SIZE - ring->lastWrite;
 622         }
 623
 624         memcpy(ring->ringBase + ring->lastWrite, cmd, len);
 625         if(unlikely(wrap_len)) {
 626                 struct cmd_desc *wrap_ptr = cmd;
 627                 wrap_ptr += len / sizeof(*cmd);
 628                 memcpy(ring->ringBase, wrap_ptr, wrap_len);
 629         }
 630
 631         typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
 632
 633         /* "I feel a presence... another warrior is on the the mesa."
 634          */
 635         wmb();
 636         writel(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 637         typhoon_post_pci_writes(tp->ioaddr);
 638
 639         if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
 640                 goto out;
 641
 642         /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
 643          * preempt or do anything other than take interrupts. So, don't
 644          * wait for a response unless you have to.
 645          *
 646          * I've thought about trying to sleep here, but we're called
 647          * from many contexts that don't allow that. Also, given the way
 648          * 3Com has implemented irq coalescing, we would likely timeout --
 649          * this has been observed in real life!
 650          *
 651          * The big killer is we have to wait to get stats from the card,
 652          * though we could go to a periodic refresh of those if we don't
 653          * mind them getting somewhat stale. The rest of the waiting
 654          * commands occur during open/close/suspend/resume, so they aren't
 655          * time critical. Creating SAs in the future will also have to
 656          * wait here.
 657          */
 658         got_resp = 0;
 659         for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
 660                 if(indexes->respCleared != indexes->respReady)
 661                         got_resp = typhoon_process_response(tp, num_resp,
 662                                                                 resp);
 663                 udelay(TYPHOON_UDELAY);
 664         }
 665
 666         if(!got_resp) {
 667                 err = -ETIMEDOUT;
 668                 goto out;
 669         }
 670
 671         /* Collect the error response even if we don't care about the
 672          * rest of the response
 673          */
 674         if(resp->flags & TYPHOON_RESP_ERROR)
 675                 err = -EIO;
 676
 677 out:
 678         if(tp->awaiting_resp) {
 679                 tp->awaiting_resp = 0;
 680                 smp_wmb();
 681
 682                 /* Ugh. If a response was added to the ring between
 683                  * the call to typhoon_process_response() and the clearing
 684                  * of tp->awaiting_resp, we could have missed the interrupt
 685                  * and it could hang in the ring an indeterminate amount of
 686                  * time. So, check for it, and interrupt ourselves if this
 687                  * is the case.
 688                  */
 689                 if(indexes->respCleared != indexes->respReady)
 690                         writel(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
 691         }
 692
 693         spin_unlock(&tp->command_lock);
 694         return err;
 695 }
 696
 697 static void
 698 typhoon_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
 699 {
 700         struct typhoon *tp = netdev_priv(dev);
 701         struct cmd_desc xp_cmd;
 702         int err;
 703
 704         spin_lock_bh(&tp->state_lock);
 705         if(!tp->vlgrp != !grp) {
 706                 /* We've either been turned on for the first time, or we've
 707                  * been turned off. Update the 3XP.
 708                  */
 709                 if(grp)
 710                         tp->offload |= TYPHOON_OFFLOAD_VLAN;
 711                 else
 712                         tp->offload &= ~TYPHOON_OFFLOAD_VLAN;
 713
 714                 /* If the interface is up, the runtime is running -- and we
 715                  * must be up for the vlan core to call us.
 716                  *
 717                  * Do the command outside of the spin lock, as it is slow.
 718                  */
 719                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd,
 720                                         TYPHOON_CMD_SET_OFFLOAD_TASKS);
 721                 xp_cmd.parm2 = tp->offload;
 722                 xp_cmd.parm3 = tp->offload;
 723                 spin_unlock_bh(&tp->state_lock);
 724                 err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 725                 if(err < 0)
 726                         printk("%s: vlan offload error %d\n", tp->name, -err);
 727                 spin_lock_bh(&tp->state_lock);
 728         }
 729
 730         /* now make the change visible */
 731         tp->vlgrp = grp;
 732         spin_unlock_bh(&tp->state_lock);
 733 }
 734
 735 static void
 736 typhoon_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
 737 {
 738         struct typhoon *tp = netdev_priv(dev);
 739         spin_lock_bh(&tp->state_lock);
 740         if(tp->vlgrp)
 741                 tp->vlgrp->vlan_devices[vid] = NULL;
 742         spin_unlock_bh(&tp->state_lock);
 743 }
 744
 745 static inline void
 746 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
 747                         u32 ring_dma)
 748 {
 749         struct tcpopt_desc *tcpd;
 750         u32 tcpd_offset = ring_dma;
 751
 752         tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
 753         tcpd_offset += txRing->lastWrite;
 754         tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
 755         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 756
 757         tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
 758         tcpd->numDesc = 1;
 759         tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
 760         tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
 761         tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
 762         tcpd->bytesTx = cpu_to_le32(skb->len);
 763         tcpd->status = 0;
 764 }
 765
 766 static int
 767 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
 768 {
 769         struct typhoon *tp = netdev_priv(dev);
 770         struct transmit_ring *txRing;
 771         struct tx_desc *txd, *first_txd;
 772         dma_addr_t skb_dma;
 773         int numDesc;
 774
 775         /* we have two rings to choose from, but we only use txLo for now
 776          * If we start using the Hi ring as well, we'll need to update
 777          * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
 778          * and TXHI_ENTIRES to match, as well as update the TSO code below
 779          * to get the right DMA address
 780          */
 781         txRing = &tp->txLoRing;
 782
 783         /* We need one descriptor for each fragment of the sk_buff, plus the
 784          * one for the ->data area of it.
 785          *
 786          * The docs say a maximum of 16 fragment descriptors per TCP option
 787          * descriptor, then make a new packet descriptor and option descriptor
 788          * for the next 16 fragments. The engineers say just an option
 789          * descriptor is needed. I've tested up to 26 fragments with a single
 790          * packet descriptor/option descriptor combo, so I use that for now.
 791          *
 792          * If problems develop with TSO, check this first.
 793          */
 794         numDesc = skb_shinfo(skb)->nr_frags + 1;
 795         if(skb_tso_size(skb))
 796                 numDesc++;
 797
 798         /* When checking for free space in the ring, we need to also
 799          * account for the initial Tx descriptor, and we always must leave
 800          * at least one descriptor unused in the ring so that it doesn't
 801          * wrap and look empty.
 802          *
 803          * The only time we should loop here is when we hit the race
 804          * between marking the queue awake and updating the cleared index.
 805          * Just loop and it will appear. This comes from the acenic driver.
 806          */
 807         while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
 808                 smp_rmb();
 809
 810         first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 811         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 812
 813         first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
 814         first_txd->numDesc = 0;
 815         first_txd->len = 0;
 816         first_txd->addr = (u64)((unsigned long) skb) & 0xffffffff;
 817         first_txd->addrHi = (u64)((unsigned long) skb) >> 32;
 818         first_txd->processFlags = 0;
 819
 820         if(skb->ip_summed == CHECKSUM_HW) {
 821                 /* The 3XP will figure out if this is UDP/TCP */
 822                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
 823                 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
 824                 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
 825         }
 826
 827         if(vlan_tx_tag_present(skb)) {
 828                 first_txd->processFlags |=
 829                     TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
 830                 first_txd->processFlags |=
 831                     cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
 832                                 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
 833         }
 834
 835         if(skb_tso_size(skb)) {
 836                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
 837                 first_txd->numDesc++;
 838
 839                 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
 840         }
 841
 842         txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 843         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 844
 845         /* No need to worry about padding packet -- the firmware pads
 846          * it with zeros to ETH_ZLEN for us.
 847          */
 848         if(skb_shinfo(skb)->nr_frags == 0) {
 849                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
 850                                        PCI_DMA_TODEVICE);
 851                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 852                 txd->len = cpu_to_le16(skb->len);
 853                 txd->addr = cpu_to_le32(skb_dma);
 854                 txd->addrHi = 0;
 855                 first_txd->numDesc++;
 856         } else {
 857                 int i, len;
 858
 859                 len = skb_headlen(skb);
 860                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
 861                                          PCI_DMA_TODEVICE);
 862                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 863                 txd->len = cpu_to_le16(len);
 864                 txd->addr = cpu_to_le32(skb_dma);
 865                 txd->addrHi = 0;
 866                 first_txd->numDesc++;
 867
 868                 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 869                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 870                         void *frag_addr;
 871
 872                         txd = (struct tx_desc *) (txRing->ringBase +
 873                                                 txRing->lastWrite);
 874                         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 875
 876                         len = frag->size;
 877                         frag_addr = (void *) page_address(frag->page) +
 878                                                 frag->page_offset;
 879                         skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
 880                                          PCI_DMA_TODEVICE);
 881                         txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 882                         txd->len = cpu_to_le16(len);
 883                         txd->addr = cpu_to_le32(skb_dma);
 884                         txd->addrHi = 0;
 885                         first_txd->numDesc++;
 886                 }
 887         }
 888
 889         /* Kick the 3XP
 890          */
 891         wmb();
 892         writel(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
 893
 894         dev->trans_start = jiffies;
 895
 896         /* If we don't have room to put the worst case packet on the
 897          * queue, then we must stop the queue. We need 2 extra
 898          * descriptors -- one to prevent ring wrap, and one for the
 899          * Tx header.
 900          */
 901         numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
 902
 903         if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
 904                 netif_stop_queue(dev);
 905
 906                 /* A Tx complete IRQ could have gotten inbetween, making
 907                  * the ring free again. Only need to recheck here, since
 908                  * Tx is serialized.
 909                  */
 910                 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
 911                         netif_wake_queue(dev);
 912         }
 913
 914         return 0;
 915 }
 916
 917 static void
 918 typhoon_set_rx_mode(struct net_device *dev)
 919 {
 920         struct typhoon *tp = netdev_priv(dev);
 921         struct cmd_desc xp_cmd;
 922         u32 mc_filter[2];
 923         u16 filter;
 924
 925         filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
 926         if(dev->flags & IFF_PROMISC) {
 927                 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
 928                        dev->name);
 929                 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
 930         } else if((dev->mc_count > multicast_filter_limit) ||
 931                   (dev->flags & IFF_ALLMULTI)) {
 932                 /* Too many to match, or accept all multicasts. */
 933                 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
 934         } else if(dev->mc_count) {
 935                 struct dev_mc_list *mclist;
 936                 int i;
 937
 938                 memset(mc_filter, 0, sizeof(mc_filter));
 939                 for(i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
 940                     i++, mclist = mclist->next) {
 941                         int bit = ether_crc(ETH_ALEN, mclist->dmi_addr) & 0x3f;
 942                         mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
 943                 }
 944
 945                 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
 946                                          TYPHOON_CMD_SET_MULTICAST_HASH);
 947                 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
 948                 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
 949                 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
 950                 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 951
 952                 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
 953         }
 954
 955         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
 956         xp_cmd.parm1 = filter;
 957         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 958 }
 959
 960 static int
 961 typhoon_do_get_stats(struct typhoon *tp)
 962 {
 963         struct net_device_stats *stats = &tp->stats;
 964         struct net_device_stats *saved = &tp->stats_saved;
 965         struct cmd_desc xp_cmd;
 966         struct resp_desc xp_resp[7];
 967         struct stats_resp *s = (struct stats_resp *) xp_resp;
 968         int err;
 969
 970         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
 971         err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
 972         if(err < 0)
 973                 return err;
 974
 975         /* 3Com's Linux driver uses txMultipleCollisions as it's
 976          * collisions value, but there is some other collision info as well...
 977          *
 978          * The extra status reported would be a good candidate for
 979          * ethtool_ops->get_{strings,stats}()
 980          */
 981         stats->tx_packets = le32_to_cpu(s->txPackets);
 982         stats->tx_bytes = le32_to_cpu(s->txBytes);
 983         stats->tx_errors = le32_to_cpu(s->txCarrierLost);
 984         stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost);
 985         stats->collisions = le32_to_cpu(s->txMultipleCollisions);
 986         stats->rx_packets = le32_to_cpu(s->rxPacketsGood);
 987         stats->rx_bytes = le32_to_cpu(s->rxBytesGood);
 988         stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns);
 989         stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
 990                         le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors);
 991         stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors);
 992         stats->rx_length_errors = le32_to_cpu(s->rxOversized);
 993         tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
 994                         SPEED_100 : SPEED_10;
 995         tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
 996                         DUPLEX_FULL : DUPLEX_HALF;
 997
 998         /* add in the saved statistics
 999          */
1000         stats->tx_packets += saved->tx_packets;
1001         stats->tx_bytes += saved->tx_bytes;
1002         stats->tx_errors += saved->tx_errors;
1003         stats->collisions += saved->collisions;
1004         stats->rx_packets += saved->rx_packets;
1005         stats->rx_bytes += saved->rx_bytes;
1006         stats->rx_fifo_errors += saved->rx_fifo_errors;
1007         stats->rx_errors += saved->rx_errors;
1008         stats->rx_crc_errors += saved->rx_crc_errors;
1009         stats->rx_length_errors += saved->rx_length_errors;
1010
1011         return 0;
1012 }
1013
1014 static struct net_device_stats *
1015 typhoon_get_stats(struct net_device *dev)
1016 {
1017         struct typhoon *tp = netdev_priv(dev);
1018         struct net_device_stats *stats = &tp->stats;
1019         struct net_device_stats *saved = &tp->stats_saved;
1020
1021         smp_rmb();
1022         if(tp->card_state == Sleeping)
1023                 return saved;
1024
1025         if(typhoon_do_get_stats(tp) < 0) {
1026                 printk(KERN_ERR "%s: error getting stats\n", dev->name);
1027                 return saved;
1028         }
1029
1030         return stats;
1031 }
1032
1033 static int
1034 typhoon_set_mac_address(struct net_device *dev, void *addr)
1035 {
1036         struct sockaddr *saddr = (struct sockaddr *) addr;
1037
1038         if(netif_running(dev))
1039                 return -EBUSY;
1040
1041         memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
1042         return 0;
1043 }
1044
1045 static void
1046 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1047 {
1048         struct typhoon *tp = netdev_priv(dev);
1049         struct pci_dev *pci_dev = tp->pdev;
1050         struct cmd_desc xp_cmd;
1051         struct resp_desc xp_resp[3];
1052
1053         smp_rmb();
1054         if(tp->card_state == Sleeping) {
1055                 strcpy(info->fw_version, "Sleep image");
1056         } else {
1057                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
1058                 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
1059                         strcpy(info->fw_version, "Unknown runtime");
1060                 } else {
1061                         strncpy(info->fw_version, (char *) &xp_resp[1], 32);
1062                         info->fw_version[31] = 0;
1063                 }
1064         }
1065
1066         strcpy(info->driver, DRV_MODULE_NAME);
1067         strcpy(info->version, DRV_MODULE_VERSION);
1068         strcpy(info->bus_info, pci_name(pci_dev));
1069 }
1070
1071 static int
1072 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1073 {
1074         struct typhoon *tp = netdev_priv(dev);
1075
1076         cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1077                                 SUPPORTED_Autoneg;
1078
1079         switch (tp->xcvr_select) {
1080         case TYPHOON_XCVR_10HALF:
1081                 cmd->advertising = ADVERTISED_10baseT_Half;
1082                 break;
1083         case TYPHOON_XCVR_10FULL:
1084                 cmd->advertising = ADVERTISED_10baseT_Full;
1085                 break;
1086         case TYPHOON_XCVR_100HALF:
1087                 cmd->advertising = ADVERTISED_100baseT_Half;
1088                 break;
1089         case TYPHOON_XCVR_100FULL:
1090                 cmd->advertising = ADVERTISED_100baseT_Full;
1091                 break;
1092         case TYPHOON_XCVR_AUTONEG:
1093                 cmd->advertising = ADVERTISED_10baseT_Half |
1094                                             ADVERTISED_10baseT_Full |
1095                                             ADVERTISED_100baseT_Half |
1096                                             ADVERTISED_100baseT_Full |
1097                                             ADVERTISED_Autoneg;
1098                 break;
1099         }
1100
1101         if(tp->capabilities & TYPHOON_FIBER) {
1102                 cmd->supported |= SUPPORTED_FIBRE;
1103                 cmd->advertising |= ADVERTISED_FIBRE;
1104                 cmd->port = PORT_FIBRE;
1105         } else {
1106                 cmd->supported |= SUPPORTED_10baseT_Half |
1107                                         SUPPORTED_10baseT_Full |
1108                                         SUPPORTED_TP;
1109                 cmd->advertising |= ADVERTISED_TP;
1110                 cmd->port = PORT_TP;
1111         }
1112
1113         /* need to get stats to make these link speed/duplex valid */
1114         typhoon_do_get_stats(tp);
1115         cmd->speed = tp->speed;
1116         cmd->duplex = tp->duplex;
1117         cmd->phy_address = 0;
1118         cmd->transceiver = XCVR_INTERNAL;
1119         if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1120                 cmd->autoneg = AUTONEG_ENABLE;
1121         else
1122                 cmd->autoneg = AUTONEG_DISABLE;
1123         cmd->maxtxpkt = 1;
1124         cmd->maxrxpkt = 1;
1125
1126         return 0;
1127 }
1128
1129 static int
1130 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1131 {
1132         struct typhoon *tp = netdev_priv(dev);
1133         struct cmd_desc xp_cmd;
1134         int xcvr;
1135         int err;
1136
1137         err = -EINVAL;
1138         if(cmd->autoneg == AUTONEG_ENABLE) {
1139                 xcvr = TYPHOON_XCVR_AUTONEG;
1140         } else {
1141                 if(cmd->duplex == DUPLEX_HALF) {
1142                         if(cmd->speed == SPEED_10)
1143                                 xcvr = TYPHOON_XCVR_10HALF;
1144                         else if(cmd->speed == SPEED_100)
1145                                 xcvr = TYPHOON_XCVR_100HALF;
1146                         else
1147                                 goto out;
1148                 } else if(cmd->duplex == DUPLEX_FULL) {
1149                         if(cmd->speed == SPEED_10)
1150                                 xcvr = TYPHOON_XCVR_10FULL;
1151                         else if(cmd->speed == SPEED_100)
1152                                 xcvr = TYPHOON_XCVR_100FULL;
1153                         else
1154                                 goto out;
1155                 } else
1156                         goto out;
1157         }
1158
1159         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1160         xp_cmd.parm1 = cpu_to_le16(xcvr);
1161         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1162         if(err < 0)
1163                 goto out;
1164
1165         tp->xcvr_select = xcvr;
1166         if(cmd->autoneg == AUTONEG_ENABLE) {
1167                 tp->speed = 0xff;       /* invalid */
1168                 tp->duplex = 0xff;      /* invalid */
1169         } else {
1170                 tp->speed = cmd->speed;
1171                 tp->duplex = cmd->duplex;
1172         }
1173
1174 out:
1175         return err;
1176 }
1177
1178 static void
1179 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1180 {
1181         struct typhoon *tp = netdev_priv(dev);
1182
1183         wol->supported = WAKE_PHY | WAKE_MAGIC;
1184         wol->wolopts = 0;
1185         if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1186                 wol->wolopts |= WAKE_PHY;
1187         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1188                 wol->wolopts |= WAKE_MAGIC;
1189         memset(&wol->sopass, 0, sizeof(wol->sopass));
1190 }
1191
1192 static int
1193 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1194 {
1195         struct typhoon *tp = netdev_priv(dev);
1196
1197         if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1198                 return -EINVAL;
1199
1200         tp->wol_events = 0;
1201         if(wol->wolopts & WAKE_PHY)
1202                 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1203         if(wol->wolopts & WAKE_MAGIC)
1204                 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1205
1206         return 0;
1207 }
1208
1209 static u32
1210 typhoon_get_rx_csum(struct net_device *dev)
1211 {
1212         /* For now, we don't allow turning off RX checksums.
1213          */
1214         return 1;
1215 }
1216
1217 static void
1218 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1219 {
1220         ering->rx_max_pending = RXENT_ENTRIES;
1221         ering->rx_mini_max_pending = 0;
1222         ering->rx_jumbo_max_pending = 0;
1223         ering->tx_max_pending = TXLO_ENTRIES - 1;
1224
1225         ering->rx_pending = RXENT_ENTRIES;
1226         ering->rx_mini_pending = 0;
1227         ering->rx_jumbo_pending = 0;
1228         ering->tx_pending = TXLO_ENTRIES - 1;
1229 }
1230
1231 static struct ethtool_ops typhoon_ethtool_ops = {
1232         .get_settings           = typhoon_get_settings,
1233         .set_settings           = typhoon_set_settings,
1234         .get_drvinfo            = typhoon_get_drvinfo,
1235         .get_wol                = typhoon_get_wol,
1236         .set_wol                = typhoon_set_wol,
1237         .get_link               = ethtool_op_get_link,
1238         .get_rx_csum            = typhoon_get_rx_csum,
1239         .get_tx_csum            = ethtool_op_get_tx_csum,
1240         .set_tx_csum            = ethtool_op_set_tx_csum,
1241         .get_sg                 = ethtool_op_get_sg,
1242         .set_sg                 = ethtool_op_set_sg,
1243         .get_tso                = ethtool_op_get_tso,
1244         .set_tso                = ethtool_op_set_tso,
1245         .get_ringparam          = typhoon_get_ringparam,
1246 };
1247
1248 static int
1249 typhoon_wait_interrupt(void __iomem *ioaddr)
1250 {
1251         int i, err = 0;
1252
1253         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1254                 if(readl(ioaddr + TYPHOON_REG_INTR_STATUS) &
1255                    TYPHOON_INTR_BOOTCMD)
1256                         goto out;
1257                 udelay(TYPHOON_UDELAY);
1258         }
1259
1260         err = -ETIMEDOUT;
1261
1262 out:
1263         writel(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1264         return err;
1265 }
1266
1267 #define shared_offset(x)        offsetof(struct typhoon_shared, x)
1268
1269 static void
1270 typhoon_init_interface(struct typhoon *tp)
1271 {
1272         struct typhoon_interface *iface = &tp->shared->iface;
1273         dma_addr_t shared_dma;
1274
1275         memset(tp->shared, 0, sizeof(struct typhoon_shared));
1276
1277         /* The *Hi members of iface are all init'd to zero by the memset().
1278          */
1279         shared_dma = tp->shared_dma + shared_offset(indexes);
1280         iface->ringIndex = cpu_to_le32(shared_dma);
1281
1282         shared_dma = tp->shared_dma + shared_offset(txLo);
1283         iface->txLoAddr = cpu_to_le32(shared_dma);
1284         iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1285
1286         shared_dma = tp->shared_dma + shared_offset(txHi);
1287         iface->txHiAddr = cpu_to_le32(shared_dma);
1288         iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1289
1290         shared_dma = tp->shared_dma + shared_offset(rxBuff);
1291         iface->rxBuffAddr = cpu_to_le32(shared_dma);
1292         iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1293                                         sizeof(struct rx_free));
1294
1295         shared_dma = tp->shared_dma + shared_offset(rxLo);
1296         iface->rxLoAddr = cpu_to_le32(shared_dma);
1297         iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1298
1299         shared_dma = tp->shared_dma + shared_offset(rxHi);
1300         iface->rxHiAddr = cpu_to_le32(shared_dma);
1301         iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1302
1303         shared_dma = tp->shared_dma + shared_offset(cmd);
1304         iface->cmdAddr = cpu_to_le32(shared_dma);
1305         iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1306
1307         shared_dma = tp->shared_dma + shared_offset(resp);
1308         iface->respAddr = cpu_to_le32(shared_dma);
1309         iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1310
1311         shared_dma = tp->shared_dma + shared_offset(zeroWord);
1312         iface->zeroAddr = cpu_to_le32(shared_dma);
1313
1314         tp->indexes = &tp->shared->indexes;
1315         tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1316         tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1317         tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1318         tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1319         tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1320         tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1321         tp->respRing.ringBase = (u8 *) tp->shared->resp;
1322
1323         tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1324         tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1325
1326         tp->txlo_dma_addr = iface->txLoAddr;
1327         tp->card_state = Sleeping;
1328         smp_wmb();
1329
1330         tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1331         tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1332
1333         spin_lock_init(&tp->command_lock);
1334         spin_lock_init(&tp->state_lock);
1335 }
1336
1337 static void
1338 typhoon_init_rings(struct typhoon *tp)
1339 {
1340         memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1341
1342         tp->txLoRing.lastWrite = 0;
1343         tp->txHiRing.lastWrite = 0;
1344         tp->rxLoRing.lastWrite = 0;
1345         tp->rxHiRing.lastWrite = 0;
1346         tp->rxBuffRing.lastWrite = 0;
1347         tp->cmdRing.lastWrite = 0;
1348         tp->cmdRing.lastWrite = 0;
1349
1350         tp->txLoRing.lastRead = 0;
1351         tp->txHiRing.lastRead = 0;
1352 }
1353
1354 static int
1355 typhoon_download_firmware(struct typhoon *tp)
1356 {
1357         void __iomem *ioaddr = tp->ioaddr;
1358         struct pci_dev *pdev = tp->pdev;
1359         struct typhoon_file_header *fHdr;
1360         struct typhoon_section_header *sHdr;
1361         u8 *image_data;
1362         void *dpage;
1363         dma_addr_t dpage_dma;
1364         unsigned int csum;
1365         u32 irqEnabled;
1366         u32 irqMasked;
1367         u32 numSections;
1368         u32 section_len;
1369         u32 len;
1370         u32 load_addr;
1371         u32 hmac;
1372         int i;
1373         int err;
1374
1375         err = -EINVAL;
1376         fHdr = (struct typhoon_file_header *) typhoon_firmware_image;
1377         image_data = (u8 *) fHdr;
1378
1379         if(memcmp(fHdr->tag, "TYPHOON", 8)) {
1380                 printk(KERN_ERR "%s: Invalid firmware image!\n", tp->name);
1381                 goto err_out;
1382         }
1383
1384         /* Cannot just map the firmware image using pci_map_single() as
1385          * the firmware is part of the kernel/module image, so we allocate
1386          * some consistent memory to copy the sections into, as it is simpler,
1387          * and short-lived. If we ever split out and require a userland
1388          * firmware loader, then we can revisit this.
1389          */
1390         err = -ENOMEM;
1391         dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1392         if(!dpage) {
1393                 printk(KERN_ERR "%s: no DMA mem for firmware\n", tp->name);
1394                 goto err_out;
1395         }
1396
1397         irqEnabled = readl(ioaddr + TYPHOON_REG_INTR_ENABLE);
1398         writel(irqEnabled | TYPHOON_INTR_BOOTCMD,
1399                ioaddr + TYPHOON_REG_INTR_ENABLE);
1400         irqMasked = readl(ioaddr + TYPHOON_REG_INTR_MASK);
1401         writel(irqMasked | TYPHOON_INTR_BOOTCMD,
1402                ioaddr + TYPHOON_REG_INTR_MASK);
1403
1404         err = -ETIMEDOUT;
1405         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1406                 printk(KERN_ERR "%s: card ready timeout\n", tp->name);
1407                 goto err_out_irq;
1408         }
1409
1410         numSections = le32_to_cpu(fHdr->numSections);
1411         load_addr = le32_to_cpu(fHdr->startAddr);
1412
1413         writel(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1414         writel(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1415         hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1416         writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1417         hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1418         writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1419         hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1420         writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1421         hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1422         writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1423         hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1424         writel(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1425         typhoon_post_pci_writes(ioaddr);
1426         writel(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1427
1428         image_data += sizeof(struct typhoon_file_header);
1429
1430         /* The readl() in typhoon_wait_interrupt() will force the
1431          * last write to the command register to post, so
1432          * we don't need a typhoon_post_pci_writes() after it.
1433          */
1434         for(i = 0; i < numSections; i++) {
1435                 sHdr = (struct typhoon_section_header *) image_data;
1436                 image_data += sizeof(struct typhoon_section_header);
1437                 load_addr = le32_to_cpu(sHdr->startAddr);
1438                 section_len = le32_to_cpu(sHdr->len);
1439
1440                 while(section_len) {
1441                         len = min_t(u32, section_len, PAGE_SIZE);
1442
1443                         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1444                            readl(ioaddr + TYPHOON_REG_STATUS) !=
1445                            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1446                                 printk(KERN_ERR "%s: segment ready timeout\n",
1447                                        tp->name);
1448                                 goto err_out_irq;
1449                         }
1450
1451                         /* Do an pseudo IPv4 checksum on the data -- first
1452                          * need to convert each u16 to cpu order before
1453                          * summing. Fortunately, due to the properties of
1454                          * the checksum, we can do this once, at the end.
1455                          */
1456                         csum = csum_partial_copy_nocheck(image_data, dpage,
1457                                                          len, 0);
1458                         csum = csum_fold(csum);
1459                         csum = le16_to_cpu(csum);
1460
1461                         writel(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1462                         writel(csum, ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1463                         writel(load_addr, ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1464                         writel(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1465                         writel(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1466                         typhoon_post_pci_writes(ioaddr);
1467                         writel(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1468                                ioaddr + TYPHOON_REG_COMMAND);
1469
1470                         image_data += len;
1471                         load_addr += len;
1472                         section_len -= len;
1473                 }
1474         }
1475
1476         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1477            readl(ioaddr + TYPHOON_REG_STATUS) !=
1478            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1479                 printk(KERN_ERR "%s: final segment ready timeout\n", tp->name);
1480                 goto err_out_irq;
1481         }
1482
1483         writel(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1484
1485         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1486                 printk(KERN_ERR "%s: boot ready timeout, status 0x%0x\n",
1487                        tp->name, readl(ioaddr + TYPHOON_REG_STATUS));
1488                 goto err_out_irq;
1489         }
1490
1491         err = 0;
1492
1493 err_out_irq:
1494         writel(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1495         writel(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1496
1497         pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1498
1499 err_out:
1500         return err;
1501 }
1502
1503 static int
1504 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1505 {
1506         void __iomem *ioaddr = tp->ioaddr;
1507
1508         if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1509                 printk(KERN_ERR "%s: boot ready timeout\n", tp->name);
1510                 goto out_timeout;
1511         }
1512
1513         writel(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1514         writel(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1515         typhoon_post_pci_writes(ioaddr);
1516         writel(TYPHOON_BOOTCMD_REG_BOOT_RECORD, ioaddr + TYPHOON_REG_COMMAND);
1517
1518         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1519                 printk(KERN_ERR "%s: boot finish timeout (status 0x%x)\n",
1520                        tp->name, readl(ioaddr + TYPHOON_REG_STATUS));
1521                 goto out_timeout;
1522         }
1523
1524         /* Clear the Transmit and Command ready registers
1525          */
1526         writel(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1527         writel(0, ioaddr + TYPHOON_REG_CMD_READY);
1528         writel(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1529         typhoon_post_pci_writes(ioaddr);
1530         writel(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1531
1532         return 0;
1533
1534 out_timeout:
1535         return -ETIMEDOUT;
1536 }
1537
1538 static u32
1539 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1540                         volatile u32 * index)
1541 {
1542         u32 lastRead = txRing->lastRead;
1543         struct tx_desc *tx;
1544         dma_addr_t skb_dma;
1545         int dma_len;
1546         int type;
1547
1548         while(lastRead != le32_to_cpu(*index)) {
1549                 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1550                 type = tx->flags & TYPHOON_TYPE_MASK;
1551
1552                 if(type == TYPHOON_TX_DESC) {
1553                         /* This tx_desc describes a packet.
1554                          */
1555                         unsigned long ptr = tx->addr | ((u64)tx->addrHi << 32);
1556                         struct sk_buff *skb = (struct sk_buff *) ptr;
1557                         dev_kfree_skb_irq(skb);
1558                 } else if(type == TYPHOON_FRAG_DESC) {
1559                         /* This tx_desc describes a memory mapping. Free it.
1560                          */
1561                         skb_dma = (dma_addr_t) le32_to_cpu(tx->addr);
1562                         dma_len = le16_to_cpu(tx->len);
1563                         pci_unmap_single(tp->pdev, skb_dma, dma_len,
1564                                        PCI_DMA_TODEVICE);
1565                 }
1566
1567                 tx->flags = 0;
1568                 typhoon_inc_tx_index(&lastRead, 1);
1569         }
1570
1571         return lastRead;
1572 }
1573
1574 static void
1575 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1576                         volatile u32 * index)
1577 {
1578         u32 lastRead;
1579         int numDesc = MAX_SKB_FRAGS + 1;
1580
1581         /* This will need changing if we start to use the Hi Tx ring. */
1582         lastRead = typhoon_clean_tx(tp, txRing, index);
1583         if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1584                                 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1585                 netif_wake_queue(tp->dev);
1586
1587         txRing->lastRead = lastRead;
1588         smp_wmb();
1589 }
1590
1591 static void
1592 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1593 {
1594         struct typhoon_indexes *indexes = tp->indexes;
1595         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1596         struct basic_ring *ring = &tp->rxBuffRing;
1597         struct rx_free *r;
1598
1599         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1600                                 indexes->rxBuffCleared) {
1601                 /* no room in ring, just drop the skb
1602                  */
1603                 dev_kfree_skb_any(rxb->skb);
1604                 rxb->skb = NULL;
1605                 return;
1606         }
1607
1608         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1609         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1610         r->virtAddr = idx;
1611         r->physAddr = cpu_to_le32(rxb->dma_addr);
1612
1613         /* Tell the card about it */
1614         wmb();
1615         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1616 }
1617
1618 static int
1619 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1620 {
1621         struct typhoon_indexes *indexes = tp->indexes;
1622         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1623         struct basic_ring *ring = &tp->rxBuffRing;
1624         struct rx_free *r;
1625         struct sk_buff *skb;
1626         dma_addr_t dma_addr;
1627
1628         rxb->skb = NULL;
1629
1630         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1631                                 indexes->rxBuffCleared)
1632                 return -ENOMEM;
1633
1634         skb = dev_alloc_skb(PKT_BUF_SZ);
1635         if(!skb)
1636                 return -ENOMEM;
1637
1638 #if 0
1639         /* Please, 3com, fix the firmware to allow DMA to a unaligned
1640          * address! Pretty please?
1641          */
1642         skb_reserve(skb, 2);
1643 #endif
1644
1645         skb->dev = tp->dev;
1646         dma_addr = pci_map_single(tp->pdev, skb->tail,
1647                                   PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1648
1649         /* Since no card does 64 bit DAC, the high bits will never
1650          * change from zero.
1651          */
1652         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1653         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1654         r->virtAddr = idx;
1655         r->physAddr = cpu_to_le32(dma_addr);
1656         rxb->skb = skb;
1657         rxb->dma_addr = dma_addr;
1658
1659         /* Tell the card about it */
1660         wmb();
1661         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1662         return 0;
1663 }
1664
1665 static int
1666 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile u32 * ready,
1667            volatile u32 * cleared, int budget)
1668 {
1669         struct rx_desc *rx;
1670         struct sk_buff *skb, *new_skb;
1671         struct rxbuff_ent *rxb;
1672         dma_addr_t dma_addr;
1673         u32 local_ready;
1674         u32 rxaddr;
1675         int pkt_len;
1676         u32 idx;
1677         u32 csum_bits;
1678         int received;
1679
1680         received = 0;
1681         local_ready = le32_to_cpu(*ready);
1682         rxaddr = le32_to_cpu(*cleared);
1683         while(rxaddr != local_ready && budget > 0) {
1684                 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1685                 idx = rx->addr;
1686                 rxb = &tp->rxbuffers[idx];
1687                 skb = rxb->skb;
1688                 dma_addr = rxb->dma_addr;
1689
1690                 typhoon_inc_rx_index(&rxaddr, 1);
1691
1692                 if(rx->flags & TYPHOON_RX_ERROR) {
1693                         typhoon_recycle_rx_skb(tp, idx);
1694                         continue;
1695                 }
1696
1697                 pkt_len = le16_to_cpu(rx->frameLen);
1698
1699                 if(pkt_len < rx_copybreak &&
1700                    (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1701                         new_skb->dev = tp->dev;
1702                         skb_reserve(new_skb, 2);
1703                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1704                                                     PKT_BUF_SZ,
1705                                                     PCI_DMA_FROMDEVICE);
1706                         eth_copy_and_sum(new_skb, skb->tail, pkt_len, 0);
1707                         pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1708                                                        PKT_BUF_SZ,
1709                                                        PCI_DMA_FROMDEVICE);
1710                         skb_put(new_skb, pkt_len);
1711                         typhoon_recycle_rx_skb(tp, idx);
1712                 } else {
1713                         new_skb = skb;
1714                         skb_put(new_skb, pkt_len);
1715                         pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1716                                        PCI_DMA_FROMDEVICE);
1717                         typhoon_alloc_rx_skb(tp, idx);
1718                 }
1719                 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1720                 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1721                         TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1722                 if(csum_bits ==
1723                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD)
1724                    || csum_bits ==
1725                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1726                         new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1727                 } else
1728                         new_skb->ip_summed = CHECKSUM_NONE;
1729
1730                 spin_lock(&tp->state_lock);
1731                 if(tp->vlgrp != NULL && rx->rxStatus & TYPHOON_RX_VLAN)
1732                         vlan_hwaccel_receive_skb(new_skb, tp->vlgrp,
1733                                                  ntohl(rx->vlanTag) & 0xffff);
1734                 else
1735                         netif_receive_skb(new_skb);
1736                 spin_unlock(&tp->state_lock);
1737
1738                 tp->dev->last_rx = jiffies;
1739                 received++;
1740                 budget--;
1741         }
1742         *cleared = cpu_to_le32(rxaddr);
1743
1744         return received;
1745 }
1746
1747 static void
1748 typhoon_fill_free_ring(struct typhoon *tp)
1749 {
1750         u32 i;
1751
1752         for(i = 0; i < RXENT_ENTRIES; i++) {
1753                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1754                 if(rxb->skb)
1755                         continue;
1756                 if(typhoon_alloc_rx_skb(tp, i) < 0)
1757                         break;
1758         }
1759 }
1760
1761 static int
1762 typhoon_poll(struct net_device *dev, int *total_budget)
1763 {
1764         struct typhoon *tp = netdev_priv(dev);
1765         struct typhoon_indexes *indexes = tp->indexes;
1766         int orig_budget = *total_budget;
1767         int budget, work_done, done;
1768
1769         rmb();
1770         if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1771                         typhoon_process_response(tp, 0, NULL);
1772
1773         if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1774                 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1775
1776         if(orig_budget > dev->quota)
1777                 orig_budget = dev->quota;
1778
1779         budget = orig_budget;
1780         work_done = 0;
1781         done = 1;
1782
1783         if(indexes->rxHiCleared != indexes->rxHiReady) {
1784                 work_done = typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1785                                         &indexes->rxHiCleared, budget);
1786                 budget -= work_done;
1787         }
1788
1789         if(indexes->rxLoCleared != indexes->rxLoReady) {
1790                 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1791                                         &indexes->rxLoCleared, budget);
1792         }
1793
1794         if(work_done) {
1795                 *total_budget -= work_done;
1796                 dev->quota -= work_done;
1797
1798                 if(work_done >= orig_budget)
1799                         done = 0;
1800         }
1801
1802         if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1803                 /* rxBuff ring is empty, try to fill it. */
1804                 typhoon_fill_free_ring(tp);
1805         }
1806
1807         if(done) {
1808                 netif_rx_complete(dev);
1809                 writel(TYPHOON_INTR_NONE, tp->ioaddr + TYPHOON_REG_INTR_MASK);
1810                 typhoon_post_pci_writes(tp->ioaddr);
1811         }
1812
1813         return (done ? 0 : 1);
1814 }
1815
1816 static irqreturn_t
1817 typhoon_interrupt(int irq, void *dev_instance, struct pt_regs *rgs)
1818 {
1819         struct net_device *dev = (struct net_device *) dev_instance;
1820         struct typhoon *tp = dev->priv;
1821         void __iomem *ioaddr = tp->ioaddr;
1822         u32 intr_status;
1823
1824         intr_status = readl(ioaddr + TYPHOON_REG_INTR_STATUS);
1825         if(!(intr_status & TYPHOON_INTR_HOST_INT))
1826                 return IRQ_NONE;
1827
1828         writel(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1829
1830         if(netif_rx_schedule_prep(dev)) {
1831                 writel(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1832                 typhoon_post_pci_writes(ioaddr);
1833                 __netif_rx_schedule(dev);
1834         } else {
1835                 printk(KERN_ERR "%s: Error, poll already scheduled\n",
1836                        dev->name);
1837         }
1838         return IRQ_HANDLED;
1839 }
1840
1841 static void
1842 typhoon_free_rx_rings(struct typhoon *tp)
1843 {
1844         u32 i;
1845
1846         for(i = 0; i < RXENT_ENTRIES; i++) {
1847                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1848                 if(rxb->skb) {
1849                         pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1850                                        PCI_DMA_FROMDEVICE);
1851                         dev_kfree_skb(rxb->skb);
1852                         rxb->skb = NULL;
1853                 }
1854         }
1855 }
1856
1857 static int
1858 typhoon_sleep(struct typhoon *tp, int state, u16 events)
1859 {
1860         struct pci_dev *pdev = tp->pdev;
1861         void __iomem *ioaddr = tp->ioaddr;
1862         struct cmd_desc xp_cmd;
1863         int err;
1864
1865         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1866         xp_cmd.parm1 = events;
1867         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1868         if(err < 0) {
1869                 printk(KERN_ERR "%s: typhoon_sleep(): wake events cmd err %d\n",
1870                                 tp->name, err);
1871                 return err;
1872         }
1873
1874         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1875         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1876         if(err < 0) {
1877                 printk(KERN_ERR "%s: typhoon_sleep(): sleep cmd err %d\n",
1878                                 tp->name, err);
1879                 return err;
1880         }
1881
1882         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1883                 return -ETIMEDOUT;
1884
1885         /* Since we cannot monitor the status of the link while sleeping,
1886          * tell the world it went away.
1887          */
1888         netif_carrier_off(tp->dev);
1889
1890         pci_enable_wake(tp->pdev, state, 1);
1891         pci_disable_device(pdev);
1892         return pci_set_power_state(pdev, pci_choose_state(pdev, state));
1893 }
1894
1895 static int
1896 typhoon_wakeup(struct typhoon *tp, int wait_type)
1897 {
1898         struct pci_dev *pdev = tp->pdev;
1899         void __iomem *ioaddr = tp->ioaddr;
1900
1901         pci_set_power_state(pdev, PCI_D0);
1902         pci_restore_state(pdev);
1903
1904         /* Post 2.x.x versions of the Sleep Image require a reset before
1905          * we can download the Runtime Image. But let's not make users of
1906          * the old firmware pay for the reset.
1907          */
1908         writel(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1909         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1910                         (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1911                 return typhoon_reset(ioaddr, wait_type);
1912
1913         return 0;
1914 }
1915
1916 static int
1917 typhoon_start_runtime(struct typhoon *tp)
1918 {
1919         struct net_device *dev = tp->dev;
1920         void __iomem *ioaddr = tp->ioaddr;
1921         struct cmd_desc xp_cmd;
1922         int err;
1923
1924         typhoon_init_rings(tp);
1925         typhoon_fill_free_ring(tp);
1926
1927         err = typhoon_download_firmware(tp);
1928         if(err < 0) {
1929                 printk("%s: cannot load runtime on 3XP\n", tp->name);
1930                 goto error_out;
1931         }
1932
1933         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1934                 printk("%s: cannot boot 3XP\n", tp->name);
1935                 err = -EIO;
1936                 goto error_out;
1937         }
1938
1939         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1940         xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1941         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1942         if(err < 0)
1943                 goto error_out;
1944
1945         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1946         xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
1947         xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
1948         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1949         if(err < 0)
1950                 goto error_out;
1951
1952         /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1953          * us some more information on how to control it.
1954          */
1955         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1956         xp_cmd.parm1 = 0;
1957         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1958         if(err < 0)
1959                 goto error_out;
1960
1961         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1962         xp_cmd.parm1 = tp->xcvr_select;
1963         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1964         if(err < 0)
1965                 goto error_out;
1966
1967         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1968         xp_cmd.parm1 = __constant_cpu_to_le16(ETH_P_8021Q);
1969         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1970         if(err < 0)
1971                 goto error_out;
1972
1973         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1974         spin_lock_bh(&tp->state_lock);
1975         xp_cmd.parm2 = tp->offload;
1976         xp_cmd.parm3 = tp->offload;
1977         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1978         spin_unlock_bh(&tp->state_lock);
1979         if(err < 0)
1980                 goto error_out;
1981
1982         typhoon_set_rx_mode(dev);
1983
1984         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1985         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1986         if(err < 0)
1987                 goto error_out;
1988
1989         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1990         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1991         if(err < 0)
1992                 goto error_out;
1993
1994         tp->card_state = Running;
1995         smp_wmb();
1996
1997         writel(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1998         writel(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1999         typhoon_post_pci_writes(ioaddr);
2000
2001         return 0;
2002
2003 error_out:
2004         typhoon_reset(ioaddr, WaitNoSleep);
2005         typhoon_free_rx_rings(tp);
2006         typhoon_init_rings(tp);
2007         return err;
2008 }
2009
2010 static int
2011 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
2012 {
2013         struct typhoon_indexes *indexes = tp->indexes;
2014         struct transmit_ring *txLo = &tp->txLoRing;
2015         void __iomem *ioaddr = tp->ioaddr;
2016         struct cmd_desc xp_cmd;
2017         int i;
2018
2019         /* Disable interrupts early, since we can't schedule a poll
2020          * when called with !netif_running(). This will be posted
2021          * when we force the posting of the command.
2022          */
2023         writel(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2024
2025         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
2026         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2027
2028         /* Wait 1/2 sec for any outstanding transmits to occur
2029          * We'll cleanup after the reset if this times out.
2030          */
2031         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
2032                 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
2033                         break;
2034                 udelay(TYPHOON_UDELAY);
2035         }
2036
2037         if(i == TYPHOON_WAIT_TIMEOUT)
2038                 printk(KERN_ERR
2039                        "%s: halt timed out waiting for Tx to complete\n",
2040                        tp->name);
2041
2042         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
2043         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2044
2045         /* save the statistics so when we bring the interface up again,
2046          * the values reported to userspace are correct.
2047          */
2048         tp->card_state = Sleeping;
2049         smp_wmb();
2050         typhoon_do_get_stats(tp);
2051         memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2052
2053         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2054         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2055
2056         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2057                 printk(KERN_ERR "%s: timed out waiting for 3XP to halt\n",
2058                        tp->name);
2059
2060         if(typhoon_reset(ioaddr, wait_type) < 0) {
2061                 printk(KERN_ERR "%s: unable to reset 3XP\n", tp->name);
2062                 return -ETIMEDOUT;
2063         }
2064
2065         /* cleanup any outstanding Tx packets */
2066         if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2067                 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2068                 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2069         }
2070
2071         return 0;
2072 }
2073
2074 static void
2075 typhoon_tx_timeout(struct net_device *dev)
2076 {
2077         struct typhoon *tp = netdev_priv(dev);
2078
2079         if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2080                 printk(KERN_WARNING "%s: could not reset in tx timeout\n",
2081                                         dev->name);
2082                 goto truely_dead;
2083         }
2084
2085         /* If we ever start using the Hi ring, it will need cleaning too */
2086         typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2087         typhoon_free_rx_rings(tp);
2088
2089         if(typhoon_start_runtime(tp) < 0) {
2090                 printk(KERN_ERR "%s: could not start runtime in tx timeout\n",
2091                                         dev->name);
2092                 goto truely_dead;
2093         }
2094
2095         netif_wake_queue(dev);
2096         return;
2097
2098 truely_dead:
2099         /* Reset the hardware, and turn off carrier to avoid more timeouts */
2100         typhoon_reset(tp->ioaddr, NoWait);
2101         netif_carrier_off(dev);
2102 }
2103
2104 static int
2105 typhoon_open(struct net_device *dev)
2106 {
2107         struct typhoon *tp = netdev_priv(dev);
2108         int err;
2109
2110         err = typhoon_wakeup(tp, WaitSleep);
2111         if(err < 0) {
2112                 printk(KERN_ERR "%s: unable to wakeup device\n", dev->name);
2113                 goto out_sleep;
2114         }
2115
2116         err = request_irq(dev->irq, &typhoon_interrupt, SA_SHIRQ,
2117                                 dev->name, dev);
2118         if(err < 0)
2119                 goto out_sleep;
2120
2121         err = typhoon_start_runtime(tp);
2122         if(err < 0)
2123                 goto out_irq;
2124
2125         netif_start_queue(dev);
2126         return 0;
2127
2128 out_irq:
2129         free_irq(dev->irq, dev);
2130
2131 out_sleep:
2132         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2133                 printk(KERN_ERR "%s: unable to reboot into sleep img\n",
2134                                 dev->name);
2135                 typhoon_reset(tp->ioaddr, NoWait);
2136                 goto out;
2137         }
2138
2139         if(typhoon_sleep(tp, 3, 0) < 0)
2140                 printk(KERN_ERR "%s: unable to go back to sleep\n", dev->name);
2141
2142 out:
2143         return err;
2144 }
2145
2146 static int
2147 typhoon_close(struct net_device *dev)
2148 {
2149         struct typhoon *tp = netdev_priv(dev);
2150
2151         netif_stop_queue(dev);
2152
2153         if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2154                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2155
2156         /* Make sure there is no irq handler running on a different CPU. */
2157         typhoon_synchronize_irq(dev->irq);
2158         free_irq(dev->irq, dev);
2159
2160         typhoon_free_rx_rings(tp);
2161         typhoon_init_rings(tp);
2162
2163         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2164                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2165
2166         if(typhoon_sleep(tp, 3, 0) < 0)
2167                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2168
2169         return 0;
2170 }
2171
2172 #ifdef CONFIG_PM
2173 static int
2174 typhoon_resume(struct pci_dev *pdev)
2175 {
2176         struct net_device *dev = pci_get_drvdata(pdev);
2177         struct typhoon *tp = netdev_priv(dev);
2178
2179         /* If we're down, resume when we are upped.
2180          */
2181         if(!netif_running(dev))
2182                 return 0;
2183
2184         if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2185                 printk(KERN_ERR "%s: critical: could not wake up in resume\n",
2186                                 dev->name);
2187                 goto reset;
2188         }
2189
2190         if(typhoon_start_runtime(tp) < 0) {
2191                 printk(KERN_ERR "%s: critical: could not start runtime in "
2192                                 "resume\n", dev->name);
2193                 goto reset;
2194         }
2195
2196         netif_device_attach(dev);
2197         netif_start_queue(dev);
2198         return 0;
2199
2200 reset:
2201         typhoon_reset(tp->ioaddr, NoWait);
2202         return -EBUSY;
2203 }
2204
2205 static int
2206 typhoon_suspend(struct pci_dev *pdev, u32 state)
2207 {
2208         struct net_device *dev = pci_get_drvdata(pdev);
2209         struct typhoon *tp = netdev_priv(dev);
2210         struct cmd_desc xp_cmd;
2211
2212         /* If we're down, we're already suspended.
2213          */
2214         if(!netif_running(dev))
2215                 return 0;
2216
2217         spin_lock_bh(&tp->state_lock);
2218         if(tp->vlgrp && tp->wol_events & TYPHOON_WAKE_MAGIC_PKT) {
2219                 spin_unlock_bh(&tp->state_lock);
2220                 printk(KERN_ERR "%s: cannot do WAKE_MAGIC with VLANS\n",
2221                                 dev->name);
2222                 return -EBUSY;
2223         }
2224         spin_unlock_bh(&tp->state_lock);
2225
2226         netif_device_detach(dev);
2227
2228         if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2229                 printk(KERN_ERR "%s: unable to stop runtime\n", dev->name);
2230                 goto need_resume;
2231         }
2232
2233         typhoon_free_rx_rings(tp);
2234         typhoon_init_rings(tp);
2235
2236         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2237                 printk(KERN_ERR "%s: unable to boot sleep image\n", dev->name);
2238                 goto need_resume;
2239         }
2240
2241         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2242         xp_cmd.parm1 = cpu_to_le16(ntohs(*(u16 *)&dev->dev_addr[0]));
2243         xp_cmd.parm2 = cpu_to_le32(ntohl(*(u32 *)&dev->dev_addr[2]));
2244         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2245                 printk(KERN_ERR "%s: unable to set mac address in suspend\n",
2246                                 dev->name);
2247                 goto need_resume;
2248         }
2249
2250         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2251         xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2252         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2253                 printk(KERN_ERR "%s: unable to set rx filter in suspend\n",
2254                                 dev->name);
2255                 goto need_resume;
2256         }
2257
2258         if(typhoon_sleep(tp, state, tp->wol_events) < 0) {
2259                 printk(KERN_ERR "%s: unable to put card to sleep\n", dev->name);
2260                 goto need_resume;
2261         }
2262
2263         return 0;
2264
2265 need_resume:
2266         typhoon_resume(pdev);
2267         return -EBUSY;
2268 }
2269
2270 static int
2271 typhoon_enable_wake(struct pci_dev *pdev, u32 state, int enable)
2272 {
2273         return pci_enable_wake(pdev, state, enable);
2274 }
2275 #endif
2276
2277 static int __devinit
2278 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2279 {
2280         static int did_version = 0;
2281         struct net_device *dev;
2282         struct typhoon *tp;
2283         int card_id = (int) ent->driver_data;
2284         unsigned long ioaddr;
2285         void __iomem *ioaddr_mapped;
2286         void *shared;
2287         dma_addr_t shared_dma;
2288         struct cmd_desc xp_cmd;
2289         struct resp_desc xp_resp[3];
2290         int i;
2291         int err = 0;
2292
2293         if(!did_version++)
2294                 printk(KERN_INFO "%s", version);
2295
2296         dev = alloc_etherdev(sizeof(*tp));
2297         if(dev == NULL) {
2298                 printk(ERR_PFX "%s: unable to alloc new net device\n",
2299                        pci_name(pdev));
2300                 err = -ENOMEM;
2301                 goto error_out;
2302         }
2303         SET_MODULE_OWNER(dev);
2304         SET_NETDEV_DEV(dev, &pdev->dev);
2305
2306         err = pci_enable_device(pdev);
2307         if(err < 0) {
2308                 printk(ERR_PFX "%s: unable to enable device\n",
2309                        pci_name(pdev));
2310                 goto error_out_dev;
2311         }
2312
2313         err = pci_set_mwi(pdev);
2314         if(err < 0) {
2315                 printk(ERR_PFX "%s: unable to set MWI\n", pci_name(pdev));
2316                 goto error_out_disable;
2317         }
2318
2319         err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2320         if(err < 0) {
2321                 printk(ERR_PFX "%s: No usable DMA configuration\n",
2322                        pci_name(pdev));
2323                 goto error_out_mwi;
2324         }
2325
2326         /* sanity checks, resource #1 is our mmio area
2327          */
2328         if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2329                 printk(ERR_PFX
2330                        "%s: region #1 not a PCI MMIO resource, aborting\n",
2331                        pci_name(pdev));
2332                 err = -ENODEV;
2333                 goto error_out_mwi;
2334         }
2335         if(pci_resource_len(pdev, 1) < 128) {
2336                 printk(ERR_PFX "%s: Invalid PCI MMIO region size, aborting\n",
2337                        pci_name(pdev));
2338                 err = -ENODEV;
2339                 goto error_out_mwi;
2340         }
2341
2342         err = pci_request_regions(pdev, "typhoon");
2343         if(err < 0) {
2344                 printk(ERR_PFX "%s: could not request regions\n",
2345                        pci_name(pdev));
2346                 goto error_out_mwi;
2347         }
2348
2349         /* map our MMIO region
2350          */
2351         ioaddr = pci_resource_start(pdev, 1);
2352         ioaddr_mapped = ioremap(ioaddr, 128);
2353         if (!ioaddr_mapped) {
2354                 printk(ERR_PFX "%s: cannot remap MMIO, aborting\n",
2355                        pci_name(pdev));
2356                 err = -EIO;
2357                 goto error_out_regions;
2358         }
2359
2360         /* allocate pci dma space for rx and tx descriptor rings
2361          */
2362         shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2363                                       &shared_dma);
2364         if(!shared) {
2365                 printk(ERR_PFX "%s: could not allocate DMA memory\n",
2366                        pci_name(pdev));
2367                 err = -ENOMEM;
2368                 goto error_out_remap;
2369         }
2370
2371         dev->irq = pdev->irq;
2372         tp = netdev_priv(dev);
2373         tp->shared = (struct typhoon_shared *) shared;
2374         tp->shared_dma = shared_dma;
2375         tp->pdev = pdev;
2376         tp->tx_pdev = pdev;
2377         tp->ioaddr = ioaddr_mapped;
2378         tp->tx_ioaddr = ioaddr_mapped;
2379         tp->dev = dev;
2380
2381         /* need to be able to restore PCI state after a suspend */
2382         pci_save_state(pdev);
2383
2384         /* Init sequence:
2385          * 1) Reset the adapter to clear any bad juju
2386          * 2) Reload the sleep image
2387          * 3) Boot the sleep image
2388          * 4) Get the hardware address.
2389          * 5) Put the card to sleep.
2390          */
2391         if (typhoon_reset(ioaddr_mapped, WaitSleep) < 0) {
2392                 printk(ERR_PFX "%s: could not reset 3XP\n", pci_name(pdev));
2393                 err = -EIO;
2394                 goto error_out_dma;
2395         }
2396
2397         /* Now that we've reset the 3XP and are sure it's not going to
2398          * write all over memory, enable bus mastering.
2399          */
2400         pci_set_master(pdev);
2401
2402         /* dev->name is not valid until we register, but we need to
2403          * use some common routines to initialize the card. So that those
2404          * routines print the right name, we keep our oun pointer to the name
2405          */
2406         tp->name = pci_name(pdev);
2407
2408         typhoon_init_interface(tp);
2409         typhoon_init_rings(tp);
2410
2411         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2412                 printk(ERR_PFX "%s: cannot boot 3XP sleep image\n",
2413                        pci_name(pdev));
2414                 err = -EIO;
2415                 goto error_out_reset;
2416         }
2417
2418         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2419         if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2420                 printk(ERR_PFX "%s: cannot read MAC address\n",
2421                        pci_name(pdev));
2422                 err = -EIO;
2423                 goto error_out_reset;
2424         }
2425
2426         *(u16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2427         *(u32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2428
2429         if(!is_valid_ether_addr(dev->dev_addr)) {
2430                 printk(ERR_PFX "%s: Could not obtain valid ethernet address, "
2431                        "aborting\n", pci_name(pdev));
2432                 goto error_out_reset;
2433         }
2434
2435         /* Read the Sleep Image version last, so the response is valid
2436          * later when we print out the version reported.
2437          */
2438         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2439         if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2440                 printk(ERR_PFX "%s: Could not get Sleep Image version\n",
2441                         pdev->slot_name);
2442                 goto error_out_reset;
2443         }
2444
2445         tp->capabilities = typhoon_card_info[card_id].capabilities;
2446         tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2447
2448         /* Typhoon 1.0 Sleep Images return one response descriptor to the
2449          * READ_VERSIONS command. Those versions are OK after waking up
2450          * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2451          * seem to need a little extra help to get started. Since we don't
2452          * know how to nudge it along, just kick it.
2453          */
2454         if(xp_resp[0].numDesc != 0)
2455                 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2456
2457         if(typhoon_sleep(tp, 3, 0) < 0) {
2458                 printk(ERR_PFX "%s: cannot put adapter to sleep\n",
2459                        pci_name(pdev));
2460                 err = -EIO;
2461                 goto error_out_reset;
2462         }
2463
2464         /* The chip-specific entries in the device structure. */
2465         dev->open               = typhoon_open;
2466         dev->hard_start_xmit    = typhoon_start_tx;
2467         dev->stop               = typhoon_close;
2468         dev->set_multicast_list = typhoon_set_rx_mode;
2469         dev->tx_timeout         = typhoon_tx_timeout;
2470         dev->poll               = typhoon_poll;
2471         dev->weight             = 16;
2472         dev->watchdog_timeo     = TX_TIMEOUT;
2473         dev->get_stats          = typhoon_get_stats;
2474         dev->set_mac_address    = typhoon_set_mac_address;
2475         dev->vlan_rx_register   = typhoon_vlan_rx_register;
2476         dev->vlan_rx_kill_vid   = typhoon_vlan_rx_kill_vid;
2477         SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2478
2479         /* We can handle scatter gather, up to 16 entries, and
2480          * we can do IP checksumming (only version 4, doh...)
2481          */
2482         dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
2483         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2484         dev->features |= NETIF_F_TSO;
2485
2486         if(register_netdev(dev) < 0)
2487                 goto error_out_reset;
2488
2489         /* fixup our local name */
2490         tp->name = dev->name;
2491
2492         pci_set_drvdata(pdev, dev);
2493
2494         printk(KERN_INFO "%s: %s at 0x%lx, ",
2495                dev->name, typhoon_card_info[card_id].name, ioaddr);
2496         for(i = 0; i < 5; i++)
2497                 printk("%2.2x:", dev->dev_addr[i]);
2498         printk("%2.2x\n", dev->dev_addr[i]);
2499
2500         /* xp_resp still contains the response to the READ_VERSIONS command.
2501          * For debugging, let the user know what version he has.
2502          */
2503         if(xp_resp[0].numDesc == 0) {
2504                 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2505                  * of version is Month/Day of build.
2506                  */
2507                 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2508                 printk(KERN_INFO "%s: Typhoon 1.0 Sleep Image built "
2509                         "%02u/%02u/2000\n", dev->name, monthday >> 8,
2510                         monthday & 0xff);
2511         } else if(xp_resp[0].numDesc == 2) {
2512                 /* This is the Typhoon 1.1+ type Sleep Image
2513                  */
2514                 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2515                 u8 *ver_string = (u8 *) &xp_resp[1];
2516                 ver_string[25] = 0;
2517                 printk(KERN_INFO "%s: Typhoon 1.1+ Sleep Image version "
2518                         "%u.%u.%u.%u %s\n", dev->name, HIPQUAD(sleep_ver),
2519                         ver_string);
2520         } else {
2521                 printk(KERN_WARNING "%s: Unknown Sleep Image version "
2522                         "(%u:%04x)\n", dev->name, xp_resp[0].numDesc,
2523                         le32_to_cpu(xp_resp[0].parm2));
2524         }
2525
2526         return 0;
2527
2528 error_out_reset:
2529         typhoon_reset(ioaddr_mapped, NoWait);
2530
2531 error_out_dma:
2532         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2533                             shared, shared_dma);
2534 error_out_remap:
2535         iounmap(ioaddr_mapped);
2536 error_out_regions:
2537         pci_release_regions(pdev);
2538 error_out_mwi:
2539         pci_clear_mwi(pdev);
2540 error_out_disable:
2541         pci_disable_device(pdev);
2542 error_out_dev:
2543         free_netdev(dev);
2544 error_out:
2545         return err;
2546 }
2547
2548 static void __devexit
2549 typhoon_remove_one(struct pci_dev *pdev)
2550 {
2551         struct net_device *dev = pci_get_drvdata(pdev);
2552         struct typhoon *tp = netdev_priv(dev);
2553
2554         unregister_netdev(dev);
2555         pci_set_power_state(pdev, PCI_D0);
2556         pci_restore_state(pdev);
2557         typhoon_reset(tp->ioaddr, NoWait);
2558         iounmap(tp->ioaddr);
2559         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2560                             tp->shared, tp->shared_dma);
2561         pci_release_regions(pdev);
2562         pci_clear_mwi(pdev);
2563         pci_disable_device(pdev);
2564         pci_set_drvdata(pdev, NULL);
2565         free_netdev(dev);
2566 }
2567
2568 static struct pci_driver typhoon_driver = {
2569         .name           = DRV_MODULE_NAME,
2570         .id_table       = typhoon_pci_tbl,
2571         .probe          = typhoon_init_one,
2572         .remove         = __devexit_p(typhoon_remove_one),
2573 #ifdef CONFIG_PM
2574         .suspend        = typhoon_suspend,
2575         .resume         = typhoon_resume,
2576         .enable_wake    = typhoon_enable_wake,
2577 #endif
2578 };
2579
2580 static int __init
2581 typhoon_init(void)
2582 {
2583         return pci_module_init(&typhoon_driver);
2584 }
2585
2586 static void __exit
2587 typhoon_cleanup(void)
2588 {
2589         pci_unregister_driver(&typhoon_driver);
2590 }
2591
2592 module_init(typhoon_init);
2593 module_exit(typhoon_cleanup);