2 * SDL Inc. RISCom/N2 synchronous serial card driver for Linux
4 * Copyright (C) 1998-2003 Krzysztof Halasa <khc@pm.waw.pl>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of version 2 of the GNU General Public License
8 * as published by the Free Software Foundation.
10 * For information see http://hq.pm.waw.pl/hdlc/
12 * Note: integrated CSU/DSU/DDS are not supported by this driver
14 * Sources of information:
15 * Hitachi HD64570 SCA User's Manual
16 * SDL Inc. PPP/HDLC/CISCO driver
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <linux/fcntl.h>
25 #include <linux/string.h>
26 #include <linux/errno.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/hdlc.h>
36 static const char* version = "SDL RISCom/N2 driver version: 1.15";
37 static const char* devname = "RISCom/N2";
42 #define USE_WINDOWSIZE 16384
43 #define USE_BUS16BITS 1
44 #define CLOCK_BASE 9830400 /* 9.8304 MHz */
45 #define MAX_PAGES 16 /* 16 RAM pages at max */
46 #define MAX_RAM_SIZE 0x80000 /* 512 KB */
47 #if MAX_RAM_SIZE > MAX_PAGES * USE_WINDOWSIZE
49 #define MAX_RAM_SIZE (MAX_PAGES * USE_WINDOWSIZE)
51 #define N2_IOPORTS 0x10
52 #define NEED_DETECT_RAM
53 #define NEED_SCA_MSCI_INTR
54 #define MAX_TX_BUFFERS 10
56 static char *hw = NULL; /* pointer to hw=xxx command line string */
58 /* RISCom/N2 Board Registers */
60 /* PC Control Register */
62 #define PCR_RUNSCA 1 /* Run 64570 */
63 #define PCR_VPM 2 /* Enable VPM - needed if using RAM above 1 MB */
64 #define PCR_ENWIN 4 /* Open window */
65 #define PCR_BUS16 8 /* 16-bit bus */
68 /* Memory Base Address Register */
72 /* Page Scan Register */
77 #define PSR_WINBITS 0x60
78 #define PSR_DMAEN 0x80
79 #define PSR_PAGEBITS 0x0F
82 /* Modem Control Reg */
84 #define CLOCK_OUT_PORT1 0x80
85 #define CLOCK_OUT_PORT0 0x40
86 #define TX422_PORT1 0x20
87 #define TX422_PORT0 0x10
88 #define DSR_PORT1 0x08
89 #define DSR_PORT0 0x04
90 #define DTR_PORT1 0x02
91 #define DTR_PORT0 0x01
94 typedef struct port_s {
95 struct net_device *dev;
97 spinlock_t lock; /* TX lock */
98 sync_serial_settings settings;
99 int valid; /* port enabled */
100 int rxpart; /* partial frame received, next frame invalid*/
101 unsigned short encoding;
102 unsigned short parity;
103 u16 rxin; /* rx ring buffer 'in' pointer */
104 u16 txin; /* tx ring buffer 'in' and 'last' pointers */
106 u8 rxs, txs, tmc; /* SCA registers */
107 u8 phy_node; /* physical port # - 0 or 1 */
108 u8 log_node; /* logical port # */
113 typedef struct card_s {
114 u8 *winbase; /* ISA window base address */
115 u32 phy_winbase; /* ISA physical base address */
116 u32 ram_size; /* number of bytes */
117 u16 io; /* IO Base address */
118 u16 buff_offset; /* offset of first buffer of first channel */
119 u16 rx_ring_buffers; /* number of buffers in a ring */
121 u8 irq; /* IRQ (3-15) */
124 struct card_s *next_card;
128 static card_t *first_card;
129 static card_t **new_card = &first_card;
132 #define sca_reg(reg, card) (0x8000 | (card)->io | \
133 ((reg) & 0x0F) | (((reg) & 0xF0) << 6))
134 #define sca_in(reg, card) inb(sca_reg(reg, card))
135 #define sca_out(value, reg, card) outb(value, sca_reg(reg, card))
136 #define sca_inw(reg, card) inw(sca_reg(reg, card))
137 #define sca_outw(value, reg, card) outw(value, sca_reg(reg, card))
139 #define port_to_card(port) ((port)->card)
140 #define log_node(port) ((port)->log_node)
141 #define phy_node(port) ((port)->phy_node)
142 #define winsize(card) (USE_WINDOWSIZE)
143 #define winbase(card) ((card)->winbase)
144 #define get_port(card, port) ((card)->ports[port].valid ? \
145 &(card)->ports[port] : NULL)
149 static __inline__ u8 sca_get_page(card_t *card)
151 return inb(card->io + N2_PSR) & PSR_PAGEBITS;
155 static __inline__ void openwin(card_t *card, u8 page)
157 u8 psr = inb(card->io + N2_PSR);
158 outb((psr & ~PSR_PAGEBITS) | page, card->io + N2_PSR);
162 static __inline__ void close_windows(card_t *card)
164 outb(inb(card->io + N2_PCR) & ~PCR_ENWIN, card->io + N2_PCR);
172 static void n2_set_iface(port_t *port)
174 card_t *card = port->card;
176 u8 mcr = inb(io + N2_MCR);
177 u8 msci = get_msci(port);
178 u8 rxs = port->rxs & CLK_BRG_MASK;
179 u8 txs = port->txs & CLK_BRG_MASK;
181 switch(port->settings.clock_type) {
183 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
184 rxs |= CLK_BRG_RX; /* BRG output */
185 txs |= CLK_RXCLK_TX; /* RX clock */
189 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
190 rxs |= CLK_LINE_RX; /* RXC input */
191 txs |= CLK_BRG_TX; /* BRG output */
195 mcr |= port->phy_node ? CLOCK_OUT_PORT1 : CLOCK_OUT_PORT0;
196 rxs |= CLK_LINE_RX; /* RXC input */
197 txs |= CLK_RXCLK_TX; /* RX clock */
200 default: /* Clock EXTernal */
201 mcr &= port->phy_node ? ~CLOCK_OUT_PORT1 : ~CLOCK_OUT_PORT0;
202 rxs |= CLK_LINE_RX; /* RXC input */
203 txs |= CLK_LINE_TX; /* TXC input */
206 outb(mcr, io + N2_MCR);
209 sca_out(rxs, msci + RXS, card);
210 sca_out(txs, msci + TXS, card);
216 static int n2_open(struct net_device *dev)
218 port_t *port = dev_to_port(dev);
219 int io = port->card->io;
220 u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0);
223 result = hdlc_open(dev);
227 mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */
228 outb(mcr, io + N2_MCR);
230 outb(inb(io + N2_PCR) | PCR_ENWIN, io + N2_PCR); /* open window */
231 outb(inb(io + N2_PSR) | PSR_DMAEN, io + N2_PSR); /* enable dma */
239 static int n2_close(struct net_device *dev)
241 port_t *port = dev_to_port(dev);
242 int io = port->card->io;
243 u8 mcr = inb(io+N2_MCR) | (port->phy_node ? TX422_PORT1 : TX422_PORT0);
246 mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */
247 outb(mcr, io + N2_MCR);
254 static int n2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
256 const size_t size = sizeof(sync_serial_settings);
257 sync_serial_settings new_line, *line = ifr->ifr_settings.ifs_ifsu.sync;
258 port_t *port = dev_to_port(dev);
261 if (cmd == SIOCDEVPRIVATE) {
266 if (cmd != SIOCWANDEV)
267 return hdlc_ioctl(dev, ifr, cmd);
269 switch(ifr->ifr_settings.type) {
271 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
272 if (ifr->ifr_settings.size < size) {
273 ifr->ifr_settings.size = size; /* data size wanted */
276 if (copy_to_user(line, &port->settings, size))
280 case IF_IFACE_SYNC_SERIAL:
281 if(!capable(CAP_NET_ADMIN))
284 if (copy_from_user(&new_line, line, size))
287 if (new_line.clock_type != CLOCK_EXT &&
288 new_line.clock_type != CLOCK_TXFROMRX &&
289 new_line.clock_type != CLOCK_INT &&
290 new_line.clock_type != CLOCK_TXINT)
291 return -EINVAL; /* No such clock setting */
293 if (new_line.loopback != 0 && new_line.loopback != 1)
296 memcpy(&port->settings, &new_line, size); /* Update settings */
301 return hdlc_ioctl(dev, ifr, cmd);
307 static void n2_destroy_card(card_t *card)
311 for (cnt = 0; cnt < 2; cnt++)
312 if (card->ports[cnt].card) {
313 struct net_device *dev = port_to_dev(&card->ports[cnt]);
314 unregister_hdlc_device(dev);
318 free_irq(card->irq, card);
321 iounmap(card->winbase);
322 release_mem_region(card->phy_winbase, USE_WINDOWSIZE);
326 release_region(card->io, N2_IOPORTS);
327 if (card->ports[0].dev)
328 free_netdev(card->ports[0].dev);
329 if (card->ports[1].dev)
330 free_netdev(card->ports[1].dev);
336 static int __init n2_run(unsigned long io, unsigned long irq,
337 unsigned long winbase, long valid0, long valid1)
343 if (io < 0x200 || io > 0x3FF || (io % N2_IOPORTS) != 0) {
344 printk(KERN_ERR "n2: invalid I/O port value\n");
348 if (irq < 3 || irq > 15 || irq == 6) /* FIXME */ {
349 printk(KERN_ERR "n2: invalid IRQ value\n");
353 if (winbase < 0xA0000 || winbase > 0xFFFFF || (winbase & 0xFFF) != 0) {
354 printk(KERN_ERR "n2: invalid RAM value\n");
358 card = kmalloc(sizeof(card_t), GFP_KERNEL);
360 printk(KERN_ERR "n2: unable to allocate memory\n");
363 memset(card, 0, sizeof(card_t));
365 card->ports[0].dev = alloc_hdlcdev(&card->ports[0]);
366 card->ports[1].dev = alloc_hdlcdev(&card->ports[1]);
367 if (!card->ports[0].dev || !card->ports[1].dev) {
368 printk(KERN_ERR "n2: unable to allocate memory\n");
369 n2_destroy_card(card);
373 if (!request_region(io, N2_IOPORTS, devname)) {
374 printk(KERN_ERR "n2: I/O port region in use\n");
375 n2_destroy_card(card);
380 if (request_irq(irq, &sca_intr, 0, devname, card)) {
381 printk(KERN_ERR "n2: could not allocate IRQ\n");
382 n2_destroy_card(card);
387 if (!request_mem_region(winbase, USE_WINDOWSIZE, devname)) {
388 printk(KERN_ERR "n2: could not request RAM window\n");
389 n2_destroy_card(card);
392 card->phy_winbase = winbase;
393 card->winbase = ioremap(winbase, USE_WINDOWSIZE);
395 outb(0, io + N2_PCR);
396 outb(winbase >> 12, io + N2_BAR);
398 switch (USE_WINDOWSIZE) {
400 outb(WIN16K, io + N2_PSR);
404 outb(WIN32K, io + N2_PSR);
408 outb(WIN64K, io + N2_PSR);
412 printk(KERN_ERR "n2: invalid window size\n");
413 n2_destroy_card(card);
417 pcr = PCR_ENWIN | PCR_VPM | (USE_BUS16BITS ? PCR_BUS16 : 0);
418 outb(pcr, io + N2_PCR);
420 card->ram_size = sca_detect_ram(card, card->winbase, MAX_RAM_SIZE);
422 /* number of TX + RX buffers for one port */
423 i = card->ram_size / ((valid0 + valid1) * (sizeof(pkt_desc) +
426 card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
427 card->rx_ring_buffers = i - card->tx_ring_buffers;
429 card->buff_offset = (valid0 + valid1) * sizeof(pkt_desc) *
430 (card->tx_ring_buffers + card->rx_ring_buffers);
432 printk(KERN_INFO "n2: RISCom/N2 %u KB RAM, IRQ%u, "
433 "using %u TX + %u RX packets rings\n", card->ram_size / 1024,
434 card->irq, card->tx_ring_buffers, card->rx_ring_buffers);
436 if (card->tx_ring_buffers < 1) {
437 printk(KERN_ERR "n2: RAM test failed\n");
438 n2_destroy_card(card);
442 pcr |= PCR_RUNSCA; /* run SCA */
443 outb(pcr, io + N2_PCR);
444 outb(0, io + N2_MCR);
447 for (cnt = 0; cnt < 2; cnt++) {
448 port_t *port = &card->ports[cnt];
449 struct net_device *dev = port_to_dev(port);
450 hdlc_device *hdlc = dev_to_hdlc(dev);
452 if ((cnt == 0 && !valid0) || (cnt == 1 && !valid1))
455 port->phy_node = cnt;
458 if ((cnt == 1) && valid0)
461 spin_lock_init(&port->lock);
462 SET_MODULE_OWNER(dev);
464 dev->mem_start = winbase;
465 dev->mem_end = winbase + USE_WINDOWSIZE - 1;
466 dev->tx_queue_len = 50;
467 dev->do_ioctl = n2_ioctl;
469 dev->stop = n2_close;
470 hdlc->attach = sca_attach;
471 hdlc->xmit = sca_xmit;
472 port->settings.clock_type = CLOCK_EXT;
475 if (register_hdlc_device(dev)) {
476 printk(KERN_WARNING "n2: unable to register hdlc "
479 n2_destroy_card(card);
482 sca_init_sync_port(port); /* Set up SCA memory */
484 printk(KERN_INFO "%s: RISCom/N2 node %d\n",
485 dev->name, port->phy_node);
489 new_card = &card->next_card;
496 static int __init n2_init(void)
500 printk(KERN_INFO "n2: no card initialized\n");
502 return -ENOSYS; /* no parameters specified, abort */
505 printk(KERN_INFO "%s\n", version);
508 unsigned long io, irq, ram;
509 long valid[2] = { 0, 0 }; /* Default = both ports disabled */
511 io = simple_strtoul(hw, &hw, 0);
515 irq = simple_strtoul(hw, &hw, 0);
519 ram = simple_strtoul(hw, &hw, 0);
524 if (*hw == '0' && !valid[0])
525 valid[0] = 1; /* Port 0 enabled */
526 else if (*hw == '1' && !valid[1])
527 valid[1] = 1; /* Port 1 enabled */
533 if (!valid[0] && !valid[1])
534 break; /* at least one port must be used */
536 if (*hw == ':' || *hw == '\x0')
537 n2_run(io, irq, ram, valid[0], valid[1]);
540 return first_card ? 0 : -ENOSYS;
541 }while(*hw++ == ':');
543 printk(KERN_ERR "n2: invalid hardware parameters\n");
544 return first_card ? 0 : -ENOSYS;
548 static void __exit n2_cleanup(void)
550 card_t *card = first_card;
554 card = card->next_card;
555 n2_destroy_card(ptr);
560 module_init(n2_init);
561 module_exit(n2_cleanup);
563 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
564 MODULE_DESCRIPTION("RISCom/N2 serial port driver");
565 MODULE_LICENSE("GPL v2");
566 module_param(hw, charp, 0444); /* hw=io,irq,ram,ports:io,irq,... */