2 * pc300.h Cyclades-PC300(tm) Kernel API Definitions.
4 * Author: Ivan Passos <ivan@cyclades.com>
6 * Copyright: (c) 1999-2002 Cyclades Corp.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 * Revision 3.12 2002/03/07 14:17:09 henrique
17 * Revision 3.11 2002/01/28 21:09:39 daniela
18 * Included ';' after pc300hw.bus.
20 * Revision 3.10 2002/01/17 17:58:52 ivan
21 * Support for PC300-TE/M (PMC).
23 * Revision 3.9 2001/09/28 13:30:53 daniela
24 * Renamed dma_start routine to rx_dma_start.
26 * Revision 3.8 2001/09/24 13:03:45 daniela
27 * Fixed BOF interrupt treatment. Created dma_start routine.
29 * Revision 3.7 2001/08/10 17:19:58 daniela
30 * Fixed IOCTLs defines.
32 * Revision 3.6 2001/07/18 19:24:42 daniela
33 * Included kernel version.
35 * Revision 3.5 2001/07/05 18:38:08 daniela
36 * DMA transmission bug fix.
38 * Revision 3.4 2001/06/26 17:10:40 daniela
39 * New configuration parameters (line code, CRC calculation and clock).
41 * Revision 3.3 2001/06/22 13:13:02 regina
42 * MLPPP implementation
44 * Revision 3.2 2001/06/18 17:56:09 daniela
45 * Increased DEF_MTU and TX_QUEUE_LEN.
47 * Revision 3.1 2001/06/15 12:41:10 regina
48 * upping major version number
50 * Revision 1.1.1.1 2001/06/13 20:25:06 daniela
51 * PC300 initial CVS version (3.4.0-pre1)
53 * Revision 2.3 2001/03/05 daniela
54 * Created struct pc300conf, to provide the hardware information to pc300util.
55 * Inclusion of 'alloc_ramsize' field on structure 'pc300hw'.
57 * Revision 2.2 2000/12/22 daniela
58 * Structures and defines to support pc300util: statistics, status,
59 * loopback tests, trace.
61 * Revision 2.1 2000/09/28 ivan
62 * Inclusion of 'iophys' and 'iosize' fields on structure 'pc300hw', to
63 * allow release of I/O region at module unload.
64 * Changed location of include files.
66 * Revision 2.0 2000/03/27 ivan
67 * Added support for the PC300/TE cards.
69 * Revision 1.1 2000/01/31 ivan
70 * Replaced 'pc300[drv|sca].h' former PC300 driver include files.
72 * Revision 1.0 1999/12/16 ivan
73 * First official release.
74 * Inclusion of 'nchan' field on structure 'pc300hw', to allow variable
75 * number of ports per card.
76 * Inclusion of 'if_ptr' field on structure 'pc300dev'.
78 * Revision 0.6 1999/11/17 ivan
79 * Changed X.25-specific function names to comply with adopted convention.
81 * Revision 0.5 1999/11/16 Daniela Squassoni
84 * Revision 0.4 1999/11/15 ivan
85 * Inclusion of 'clock' field on structure 'pc300hw'.
87 * Revision 0.3 1999/11/10 ivan
88 * IOCTL name changing.
89 * Inclusion of driver function prototypes.
91 * Revision 0.2 1999/11/03 ivan
92 * Inclusion of 'tx_skb' and union 'ifu' on structure 'pc300dev'.
94 * Revision 0.1 1999/01/15 ivan
102 #include <linux/hdlc.h>
104 #include "pc300-falc-lh.h"
108 #if defined(__alpha__)
109 typedef unsigned long ucdouble; /* 64 bits, unsigned */
110 typedef unsigned int uclong; /* 32 bits, unsigned */
112 typedef unsigned long uclong; /* 32 bits, unsigned */
114 typedef unsigned short ucshort; /* 16 bits, unsigned */
115 typedef unsigned char ucchar; /* 8 bits, unsigned */
116 #endif /* CY_TYPES */
118 #define PC300_PROTO_MLPPP 1
120 #define PC300_KERNEL "2.4.x" /* Kernel supported by this driver */
122 #define PC300_DEVNAME "hdlc" /* Dev. name base (for hdlc0, hdlc1, etc.) */
123 #define PC300_MAXINDEX 100 /* Max dev. name index (the '0' in hdlc0) */
125 #define PC300_MAXCARDS 4 /* Max number of cards per system */
126 #define PC300_MAXCHAN 2 /* Number of channels per card */
128 #define PC300_PLX_WIN 0x80 /* PLX control window size (128b) */
129 #define PC300_RAMSIZE 0x40000 /* RAM window size (256Kb) */
130 #define PC300_SCASIZE 0x400 /* SCA window size (1Kb) */
131 #define PC300_FALCSIZE 0x400 /* FALC window size (1Kb) */
133 #define PC300_OSC_CLOCK 24576000
134 #define PC300_PCI_CLOCK 33000000
136 #define BD_DEF_LEN 0x0800 /* DMA buffer length (2KB) */
137 #define DMA_TX_MEMSZ 0x8000 /* Total DMA Tx memory size (32KB/ch) */
138 #define DMA_RX_MEMSZ 0x10000 /* Total DMA Rx memory size (64KB/ch) */
140 #define N_DMA_TX_BUF (DMA_TX_MEMSZ / BD_DEF_LEN) /* DMA Tx buffers */
141 #define N_DMA_RX_BUF (DMA_RX_MEMSZ / BD_DEF_LEN) /* DMA Rx buffers */
143 /* DMA Buffer Offsets */
144 #define DMA_TX_BASE ((N_DMA_TX_BUF + N_DMA_RX_BUF) * \
145 PC300_MAXCHAN * sizeof(pcsca_bd_t))
146 #define DMA_RX_BASE (DMA_TX_BASE + PC300_MAXCHAN*DMA_TX_MEMSZ)
148 /* DMA Descriptor Offsets */
149 #define DMA_TX_BD_BASE 0x0000
150 #define DMA_RX_BD_BASE (DMA_TX_BD_BASE + ((PC300_MAXCHAN*DMA_TX_MEMSZ / \
151 BD_DEF_LEN) * sizeof(pcsca_bd_t)))
153 /* DMA Descriptor Macros */
154 #define TX_BD_ADDR(chan, n) (DMA_TX_BD_BASE + \
155 ((N_DMA_TX_BUF*chan) + n) * sizeof(pcsca_bd_t))
156 #define RX_BD_ADDR(chan, n) (DMA_RX_BD_BASE + \
157 ((N_DMA_RX_BUF*chan) + n) * sizeof(pcsca_bd_t))
159 /* Macro to access the FALC registers (TE only) */
160 #define F_REG(reg, chan) (0x200*(chan) + ((reg)<<2))
162 /***************************************
163 * Memory access functions/macros *
164 * (required to support Alpha systems) *
165 ***************************************/
167 #define cpc_writeb(port,val) {writeb((ucchar)(val),(ulong)(port)); mb();}
168 #define cpc_writew(port,val) {writew((ushort)(val),(ulong)(port)); mb();}
169 #define cpc_writel(port,val) {writel((uclong)(val),(ulong)(port)); mb();}
171 #define cpc_readb(port) readb(port)
172 #define cpc_readw(port) readw(port)
173 #define cpc_readl(port) readl(port)
175 #else /* __KERNEL__ */
176 #define cpc_writeb(port,val) (*(volatile ucchar *)(port) = (ucchar)(val))
177 #define cpc_writew(port,val) (*(volatile ucshort *)(port) = (ucshort)(val))
178 #define cpc_writel(port,val) (*(volatile uclong *)(port) = (uclong)(val))
180 #define cpc_readb(port) (*(volatile ucchar *)(port))
181 #define cpc_readw(port) (*(volatile ucshort *)(port))
182 #define cpc_readl(port) (*(volatile uclong *)(port))
184 #endif /* __KERNEL__ */
186 /****** Data Structures *****************************************************/
189 * RUNTIME_9050 - PLX PCI9050-1 local configuration and shared runtime
190 * registers. This structure can be used to access the 9050 registers
193 struct RUNTIME_9050 {
194 uclong loc_addr_range[4]; /* 00-0Ch : Local Address Ranges */
195 uclong loc_rom_range; /* 10h : Local ROM Range */
196 uclong loc_addr_base[4]; /* 14-20h : Local Address Base Addrs */
197 uclong loc_rom_base; /* 24h : Local ROM Base */
198 uclong loc_bus_descr[4]; /* 28-34h : Local Bus Descriptors */
199 uclong rom_bus_descr; /* 38h : ROM Bus Descriptor */
200 uclong cs_base[4]; /* 3C-48h : Chip Select Base Addrs */
201 uclong intr_ctrl_stat; /* 4Ch : Interrupt Control/Status */
202 uclong init_ctrl; /* 50h : EEPROM ctrl, Init Ctrl, etc */
205 #define PLX_9050_LINT1_ENABLE 0x01
206 #define PLX_9050_LINT1_POL 0x02
207 #define PLX_9050_LINT1_STATUS 0x04
208 #define PLX_9050_LINT2_ENABLE 0x08
209 #define PLX_9050_LINT2_POL 0x10
210 #define PLX_9050_LINT2_STATUS 0x20
211 #define PLX_9050_INTR_ENABLE 0x40
212 #define PLX_9050_SW_INTR 0x80
214 /* Masks to access the init_ctrl PLX register */
215 #define PC300_CLKSEL_MASK (0x00000004UL)
216 #define PC300_CHMEDIA_MASK(chan) (0x00000020UL<<(chan*3))
217 #define PC300_CTYPE_MASK (0x00000800UL)
219 /* CPLD Registers (base addr = falcbase, TE only) */
221 #define CPLD_REG1 0x140 /* Chip resets, DCD/CTS status */
222 #define CPLD_REG2 0x144 /* Clock enable , LED control */
223 /* CPLD v. 2 or higher */
224 #define CPLD_V2_REG1 0x100 /* Chip resets, DCD/CTS status */
225 #define CPLD_V2_REG2 0x104 /* Clock enable , LED control */
226 #define CPLD_ID_REG 0x108 /* CPLD version */
228 /* CPLD Register bit description: for the FALC bits, they should always be
229 set based on the channel (use (bit<<(2*ch)) to access the correct bit for
231 #define CPLD_REG1_FALC_RESET 0x01
232 #define CPLD_REG1_SCA_RESET 0x02
233 #define CPLD_REG1_GLOBAL_CLK 0x08
234 #define CPLD_REG1_FALC_DCD 0x10
235 #define CPLD_REG1_FALC_CTS 0x20
237 #define CPLD_REG2_FALC_TX_CLK 0x01
238 #define CPLD_REG2_FALC_RX_CLK 0x02
239 #define CPLD_REG2_FALC_LED1 0x10
240 #define CPLD_REG2_FALC_LED2 0x20
242 /* Structure with FALC-related fields (TE only) */
243 #define PC300_FALC_MAXLOOP 0x0000ffff /* for falc_issue_cmd() */
245 typedef struct falc {
246 ucchar sync; /* If true FALC is synchronized */
247 ucchar active; /* if TRUE then already active */
248 ucchar loop_active; /* if TRUE a line loopback UP was received */
249 ucchar loop_gen; /* if TRUE a line loopback UP was issued */
252 ucchar offset; /* 1 for T1, 0 for E1 */
253 ucchar full_bandwidth;
256 ucchar multiframe_mode;
259 ucshort pden; /* Pulse Density violation count */
260 ucshort los; /* Loss of Signal count */
261 ucshort losr; /* Loss of Signal recovery count */
262 ucshort lfa; /* Loss of frame alignment count */
263 ucshort farec; /* Frame Alignment Recovery count */
264 ucshort lmfa; /* Loss of multiframe alignment count */
265 ucshort ais; /* Remote Alarm indication Signal count */
266 ucshort sec; /* One-second timer */
267 ucshort es; /* Errored second */
268 ucshort rai; /* remote alarm received */
284 typedef struct falc_status {
285 ucchar sync; /* If true FALC is synchronized */
294 typedef struct rsv_x21_status {
302 typedef struct pc300stats {
306 struct net_device_stats gen_stats;
310 typedef struct pc300status {
312 rsv_x21_status_t gen_status;
313 falc_status_t te_status;
316 typedef struct pc300loopback {
321 typedef struct pc300patterntst {
322 char patrntst_on; /* 0 - off; 1 - on; 2 - read num_errors */
326 typedef struct pc300dev {
327 void *if_ptr; /* General purpose pointer */
328 struct pc300ch *chan;
330 uclong line_on; /* DCD(X.21, RSV) / sync(TE) change counters */
334 struct net_device *dev;
337 struct sk_buff *tx_skb;
338 union { /* This union has all the protocol-specific structures */
339 struct ppp_device pppdev;
341 #ifdef CONFIG_PC300_MLPPP
342 void *cpc_tty; /* information to PC300 TTY driver */
344 #endif /* __KERNEL__ */
347 typedef struct pc300hw {
348 int type; /* RSV, X21, etc. */
349 int bus; /* Bus (PCI, PMC, etc.) */
350 int nchan; /* number of channels */
351 int irq; /* interrupt request level */
352 uclong clock; /* Board clock */
353 ucchar cpld_id; /* CPLD ID (TE only) */
354 ucshort cpld_reg1; /* CPLD reg 1 (TE only) */
355 ucshort cpld_reg2; /* CPLD reg 2 (TE only) */
356 ucshort gpioc_reg; /* PLX GPIOC reg */
357 ucshort intctl_reg; /* PLX Int Ctrl/Status reg */
358 uclong iophys; /* PLX registers I/O base */
359 uclong iosize; /* PLX registers I/O size */
360 uclong plxphys; /* PLX registers MMIO base (physical) */
361 uclong plxbase; /* PLX registers MMIO base (virtual) */
362 uclong plxsize; /* PLX registers MMIO size */
363 uclong scaphys; /* SCA registers MMIO base (physical) */
364 uclong scabase; /* SCA registers MMIO base (virtual) */
365 uclong scasize; /* SCA registers MMIO size */
366 uclong ramphys; /* On-board RAM MMIO base (physical) */
367 uclong rambase; /* On-board RAM MMIO base (virtual) */
368 uclong alloc_ramsize; /* RAM MMIO size allocated by the PCI bridge */
369 uclong ramsize; /* On-board RAM MMIO size */
370 uclong falcphys; /* FALC registers MMIO base (physical) */
371 uclong falcbase; /* FALC registers MMIO base (virtual) */
372 uclong falcsize; /* FALC registers MMIO size */
375 typedef struct pc300chconf {
376 sync_serial_settings phys_settings; /* Clock type/rate (in bps),
378 raw_hdlc_proto proto_settings; /* Encoding, parity (CRC) */
379 uclong media; /* HW media (RS232, V.35, etc.) */
380 uclong proto; /* Protocol (PPP, X.25, etc.) */
381 ucchar monitor; /* Monitor mode (0 = off, !0 = on) */
383 /* TE-specific parameters */
384 ucchar lcode; /* Line Code (AMI, B8ZS, etc.) */
385 ucchar fr_mode; /* Frame Mode (ESF, D4, etc.) */
386 ucchar lbo; /* Line Build Out */
387 ucchar rx_sens; /* Rx Sensitivity (long- or short-haul) */
388 uclong tslot_bitmap; /* bit[i]=1 => timeslot _i_ is active */
391 typedef struct pc300ch {
396 ucchar tx_first_bd; /* First TX DMA block descr. w/ data */
397 ucchar tx_next_bd; /* Next free TX DMA block descriptor */
398 ucchar rx_first_bd; /* First free RX DMA block descriptor */
399 ucchar rx_last_bd; /* Last free RX DMA block descriptor */
400 ucchar nfree_tx_bd; /* Number of free TX DMA block descriptors */
401 falc_t falc; /* FALC structure (TE only) */
404 typedef struct pc300 {
405 pc300hw_t hw; /* hardware config. */
406 pc300ch_t chan[PC300_MAXCHAN];
408 spinlock_t card_lock;
409 #endif /* __KERNEL__ */
412 typedef struct pc300conf {
417 /* DEV ioctl() commands */
418 #define N_SPPP_IOCTLS 2
420 enum pc300_ioctl_cmds {
421 SIOCCPCRESERVED = (SIOCDEVPRIVATE + N_SPPP_IOCTLS),
425 SIOCGPC300FALCSTATUS,
427 SIOCGPC300UTILSTATUS,
430 SIOCSPC300PATTERNTEST,
433 /* Loopback types - PC300/TE boards */
434 enum pc300_loopback_cmds {
442 /* Control Constant Definitions */
443 #define PC300_RSV 0x01
444 #define PC300_X21 0x02
445 #define PC300_TE 0x03
447 #define PC300_PCI 0x00
448 #define PC300_PMC 0x01
450 #define PC300_LC_AMI 0x01
451 #define PC300_LC_B8ZS 0x02
452 #define PC300_LC_NRZ 0x03
453 #define PC300_LC_HDB3 0x04
456 #define PC300_FR_ESF 0x01
457 #define PC300_FR_D4 0x02
458 #define PC300_FR_ESF_JAPAN 0x03
461 #define PC300_FR_MF_CRC4 0x04
462 #define PC300_FR_MF_NON_CRC4 0x05
463 #define PC300_FR_UNFRAMED 0x06
465 #define PC300_LBO_0_DB 0x00
466 #define PC300_LBO_7_5_DB 0x01
467 #define PC300_LBO_15_DB 0x02
468 #define PC300_LBO_22_5_DB 0x03
470 #define PC300_RX_SENS_SH 0x01
471 #define PC300_RX_SENS_LH 0x02
473 #define PC300_TX_TIMEOUT (2*HZ)
474 #define PC300_TX_QUEUE_LEN 100
475 #define PC300_DEF_MTU 1600
478 /* Function Prototypes */
479 int dma_buf_write(pc300_t *, int, ucchar *, int);
480 int dma_buf_read(pc300_t *, int, struct sk_buff *);
481 void tx_dma_start(pc300_t *, int);
482 void rx_dma_start(pc300_t *, int);
483 void tx_dma_stop(pc300_t *, int);
484 void rx_dma_stop(pc300_t *, int);
485 int cpc_queue_xmit(struct sk_buff *, struct net_device *);
486 void cpc_net_rx(struct net_device *);
487 void cpc_sca_status(pc300_t *, int);
488 int cpc_change_mtu(struct net_device *, int);
489 int cpc_ioctl(struct net_device *, struct ifreq *, int);
490 int ch_config(pc300dev_t *);
491 int rx_config(pc300dev_t *);
492 int tx_config(pc300dev_t *);
493 void cpc_opench(pc300dev_t *);
494 void cpc_closech(pc300dev_t *);
495 int cpc_open(struct net_device *dev);
496 int cpc_close(struct net_device *dev);
497 int cpc_set_media(hdlc_device *, int);
498 #endif /* __KERNEL__ */
500 #endif /* _PC300_H */