drivers/net/wireless/bcm43xx/bcm43xx_dma.c

   1 /*
   2
   3   Broadcom BCM43xx wireless driver
   4
   5   DMA ringbuffer and descriptor allocation/management
   6
   7   Copyright (c) 2005, 2006 Michael Buesch <mbuesch@freenet.de>
   8
   9   Some code in this file is derived from the b44.c driver
  10   Copyright (C) 2002 David S. Miller
  11   Copyright (C) Pekka Pietikainen
  12
  13   This program is free software; you can redistribute it and/or modify
  14   it under the terms of the GNU General Public License as published by
  15   the Free Software Foundation; either version 2 of the License, or
  16   (at your option) any later version.
  17
  18   This program is distributed in the hope that it will be useful,
  19   but WITHOUT ANY WARRANTY; without even the implied warranty of
  20   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21   GNU General Public License for more details.
  22
  23   You should have received a copy of the GNU General Public License
  24   along with this program; see the file COPYING.  If not, write to
  25   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  26   Boston, MA 02110-1301, USA.
  27
  28 */
  29
  30 #include "bcm43xx.h"
  31 #include "bcm43xx_dma.h"
  32 #include "bcm43xx_main.h"
  33 #include "bcm43xx_debugfs.h"
  34 #include "bcm43xx_power.h"
  35 #include "bcm43xx_xmit.h"
  36
  37 #include <linux/dma-mapping.h>
  38 #include <linux/pci.h>
  39 #include <linux/delay.h>
  40 #include <linux/skbuff.h>
  41
  42
  43 static inline int free_slots(struct bcm43xx_dmaring *ring)
  44 {
  45         return (ring->nr_slots - ring->used_slots);
  46 }
  47
  48 static inline int next_slot(struct bcm43xx_dmaring *ring, int slot)
  49 {
  50         assert(slot >= -1 && slot <= ring->nr_slots - 1);
  51         if (slot == ring->nr_slots - 1)
  52                 return 0;
  53         return slot + 1;
  54 }
  55
  56 static inline int prev_slot(struct bcm43xx_dmaring *ring, int slot)
  57 {
  58         assert(slot >= 0 && slot <= ring->nr_slots - 1);
  59         if (slot == 0)
  60                 return ring->nr_slots - 1;
  61         return slot - 1;
  62 }
  63
  64 /* Request a slot for usage. */
  65 static inline
  66 int request_slot(struct bcm43xx_dmaring *ring)
  67 {
  68         int slot;
  69
  70         assert(ring->tx);
  71         assert(!ring->suspended);
  72         assert(free_slots(ring) != 0);
  73
  74         slot = next_slot(ring, ring->current_slot);
  75         ring->current_slot = slot;
  76         ring->used_slots++;
  77
  78         /* Check the number of available slots and suspend TX,
  79          * if we are running low on free slots.
  80          */
  81         if (unlikely(free_slots(ring) < ring->suspend_mark)) {
  82                 netif_stop_queue(ring->bcm->net_dev);
  83                 ring->suspended = 1;
  84         }
  85 #ifdef CONFIG_BCM43XX_DEBUG
  86         if (ring->used_slots > ring->max_used_slots)
  87                 ring->max_used_slots = ring->used_slots;
  88 #endif /* CONFIG_BCM43XX_DEBUG*/
  89
  90         return slot;
  91 }
  92
  93 /* Return a slot to the free slots. */
  94 static inline
  95 void return_slot(struct bcm43xx_dmaring *ring, int slot)
  96 {
  97         assert(ring->tx);
  98
  99         ring->used_slots--;
 100
 101         /* Check if TX is suspended and check if we have
 102          * enough free slots to resume it again.
 103          */
 104         if (unlikely(ring->suspended)) {
 105                 if (free_slots(ring) >= ring->resume_mark) {
 106                         ring->suspended = 0;
 107                         netif_wake_queue(ring->bcm->net_dev);
 108                 }
 109         }
 110 }
 111
 112 u16 bcm43xx_dmacontroller_base(int dma64bit, int controller_idx)
 113 {
 114         static const u16 map64[] = {
 115                 BCM43xx_MMIO_DMA64_BASE0,
 116                 BCM43xx_MMIO_DMA64_BASE1,
 117                 BCM43xx_MMIO_DMA64_BASE2,
 118                 BCM43xx_MMIO_DMA64_BASE3,
 119                 BCM43xx_MMIO_DMA64_BASE4,
 120                 BCM43xx_MMIO_DMA64_BASE5,
 121         };
 122         static const u16 map32[] = {
 123                 BCM43xx_MMIO_DMA32_BASE0,
 124                 BCM43xx_MMIO_DMA32_BASE1,
 125                 BCM43xx_MMIO_DMA32_BASE2,
 126                 BCM43xx_MMIO_DMA32_BASE3,
 127                 BCM43xx_MMIO_DMA32_BASE4,
 128                 BCM43xx_MMIO_DMA32_BASE5,
 129         };
 130
 131         if (dma64bit) {
 132                 assert(controller_idx >= 0 &&
 133                        controller_idx < ARRAY_SIZE(map64));
 134                 return map64[controller_idx];
 135         }
 136         assert(controller_idx >= 0 &&
 137                controller_idx < ARRAY_SIZE(map32));
 138         return map32[controller_idx];
 139 }
 140
 141 static inline
 142 dma_addr_t map_descbuffer(struct bcm43xx_dmaring *ring,
 143                           unsigned char *buf,
 144                           size_t len,
 145                           int tx)
 146 {
 147         dma_addr_t dmaaddr;
 148
 149         if (tx) {
 150                 dmaaddr = dma_map_single(&ring->bcm->pci_dev->dev,
 151                                          buf, len,
 152                                          DMA_TO_DEVICE);
 153         } else {
 154                 dmaaddr = dma_map_single(&ring->bcm->pci_dev->dev,
 155                                          buf, len,
 156                                          DMA_FROM_DEVICE);
 157         }
 158
 159         return dmaaddr;
 160 }
 161
 162 static inline
 163 void unmap_descbuffer(struct bcm43xx_dmaring *ring,
 164                       dma_addr_t addr,
 165                       size_t len,
 166                       int tx)
 167 {
 168         if (tx) {
 169                 dma_unmap_single(&ring->bcm->pci_dev->dev,
 170                                  addr, len,
 171                                  DMA_TO_DEVICE);
 172         } else {
 173                 dma_unmap_single(&ring->bcm->pci_dev->dev,
 174                                  addr, len,
 175                                  DMA_FROM_DEVICE);
 176         }
 177 }
 178
 179 static inline
 180 void sync_descbuffer_for_cpu(struct bcm43xx_dmaring *ring,
 181                              dma_addr_t addr,
 182                              size_t len)
 183 {
 184         assert(!ring->tx);
 185
 186         dma_sync_single_for_cpu(&ring->bcm->pci_dev->dev,
 187                                 addr, len, DMA_FROM_DEVICE);
 188 }
 189
 190 static inline
 191 void sync_descbuffer_for_device(struct bcm43xx_dmaring *ring,
 192                                 dma_addr_t addr,
 193                                 size_t len)
 194 {
 195         assert(!ring->tx);
 196
 197         dma_sync_single_for_device(&ring->bcm->pci_dev->dev,
 198                                    addr, len, DMA_FROM_DEVICE);
 199 }
 200
 201 /* Unmap and free a descriptor buffer. */
 202 static inline
 203 void free_descriptor_buffer(struct bcm43xx_dmaring *ring,
 204                             struct bcm43xx_dmadesc_meta *meta,
 205                             int irq_context)
 206 {
 207         assert(meta->skb);
 208         if (irq_context)
 209                 dev_kfree_skb_irq(meta->skb);
 210         else
 211                 dev_kfree_skb(meta->skb);
 212         meta->skb = NULL;
 213 }
 214
 215 static int alloc_ringmemory(struct bcm43xx_dmaring *ring)
 216 {
 217         struct device *dev = &(ring->bcm->pci_dev->dev);
 218
 219         ring->descbase = dma_alloc_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
 220                                             &(ring->dmabase), GFP_KERNEL);
 221         if (!ring->descbase) {
 222                 printk(KERN_ERR PFX "DMA ringmemory allocation failed\n");
 223                 return -ENOMEM;
 224         }
 225         memset(ring->descbase, 0, BCM43xx_DMA_RINGMEMSIZE);
 226
 227         return 0;
 228 }
 229
 230 static void free_ringmemory(struct bcm43xx_dmaring *ring)
 231 {
 232         struct device *dev = &(ring->bcm->pci_dev->dev);
 233
 234         dma_free_coherent(dev, BCM43xx_DMA_RINGMEMSIZE,
 235                           ring->descbase, ring->dmabase);
 236 }
 237
 238 /* Reset the RX DMA channel */
 239 int bcm43xx_dmacontroller_rx_reset(struct bcm43xx_private *bcm,
 240                                    u16 mmio_base, int dma64)
 241 {
 242         int i;
 243         u32 value;
 244         u16 offset;
 245
 246         offset = dma64 ? BCM43xx_DMA64_RXCTL : BCM43xx_DMA32_RXCTL;
 247         bcm43xx_write32(bcm, mmio_base + offset, 0);
 248         for (i = 0; i < 1000; i++) {
 249                 offset = dma64 ? BCM43xx_DMA64_RXSTATUS : BCM43xx_DMA32_RXSTATUS;
 250                 value = bcm43xx_read32(bcm, mmio_base + offset);
 251                 if (dma64) {
 252                         value &= BCM43xx_DMA64_RXSTAT;
 253                         if (value == BCM43xx_DMA64_RXSTAT_DISABLED) {
 254                                 i = -1;
 255                                 break;
 256                         }
 257                 } else {
 258                         value &= BCM43xx_DMA32_RXSTATE;
 259                         if (value == BCM43xx_DMA32_RXSTAT_DISABLED) {
 260                                 i = -1;
 261                                 break;
 262                         }
 263                 }
 264                 udelay(10);
 265         }
 266         if (i != -1) {
 267                 printk(KERN_ERR PFX "Error: Wait on DMA RX status timed out.\n");
 268                 return -ENODEV;
 269         }
 270
 271         return 0;
 272 }
 273
 274 /* Reset the RX DMA channel */
 275 int bcm43xx_dmacontroller_tx_reset(struct bcm43xx_private *bcm,
 276                                    u16 mmio_base, int dma64)
 277 {
 278         int i;
 279         u32 value;
 280         u16 offset;
 281
 282         for (i = 0; i < 1000; i++) {
 283                 offset = dma64 ? BCM43xx_DMA64_TXSTATUS : BCM43xx_DMA32_TXSTATUS;
 284                 value = bcm43xx_read32(bcm, mmio_base + offset);
 285                 if (dma64) {
 286                         value &= BCM43xx_DMA64_TXSTAT;
 287                         if (value == BCM43xx_DMA64_TXSTAT_DISABLED ||
 288                             value == BCM43xx_DMA64_TXSTAT_IDLEWAIT ||
 289                             value == BCM43xx_DMA64_TXSTAT_STOPPED)
 290                                 break;
 291                 } else {
 292                         value &= BCM43xx_DMA32_TXSTATE;
 293                         if (value == BCM43xx_DMA32_TXSTAT_DISABLED ||
 294                             value == BCM43xx_DMA32_TXSTAT_IDLEWAIT ||
 295                             value == BCM43xx_DMA32_TXSTAT_STOPPED)
 296                                 break;
 297                 }
 298                 udelay(10);
 299         }
 300         offset = dma64 ? BCM43xx_DMA64_TXCTL : BCM43xx_DMA32_TXCTL;
 301         bcm43xx_write32(bcm, mmio_base + offset, 0);
 302         for (i = 0; i < 1000; i++) {
 303                 offset = dma64 ? BCM43xx_DMA64_TXSTATUS : BCM43xx_DMA32_TXSTATUS;
 304                 value = bcm43xx_read32(bcm, mmio_base + offset);
 305                 if (dma64) {
 306                         value &= BCM43xx_DMA64_TXSTAT;
 307                         if (value == BCM43xx_DMA64_TXSTAT_DISABLED) {
 308                                 i = -1;
 309                                 break;
 310                         }
 311                 } else {
 312                         value &= BCM43xx_DMA32_TXSTATE;
 313                         if (value == BCM43xx_DMA32_TXSTAT_DISABLED) {
 314                                 i = -1;
 315                                 break;
 316                         }
 317                 }
 318                 udelay(10);
 319         }
 320         if (i != -1) {
 321                 printk(KERN_ERR PFX "Error: Wait on DMA TX status timed out.\n");
 322                 return -ENODEV;
 323         }
 324         /* ensure the reset is completed. */
 325         udelay(300);
 326
 327         return 0;
 328 }
 329
 330 static void fill_descriptor(struct bcm43xx_dmaring *ring,
 331                             struct bcm43xx_dmadesc_generic *desc,
 332                             dma_addr_t dmaaddr,
 333                             u16 bufsize,
 334                             int start, int end, int irq)
 335 {
 336         int slot;
 337
 338         slot = bcm43xx_dma_desc2idx(ring, desc);
 339         assert(slot >= 0 && slot < ring->nr_slots);
 340
 341         if (ring->dma64) {
 342                 u32 ctl0 = 0, ctl1 = 0;
 343                 u32 addrlo, addrhi;
 344                 u32 addrext;
 345
 346                 addrlo = (u32)(dmaaddr & 0xFFFFFFFF);
 347                 addrhi = (((u64)dmaaddr >> 32) & ~BCM43xx_DMA64_ROUTING);
 348                 addrext = (((u64)dmaaddr >> 32) >> BCM43xx_DMA64_ROUTING_SHIFT);
 349                 addrhi |= ring->routing;
 350                 if (slot == ring->nr_slots - 1)
 351                         ctl0 |= BCM43xx_DMA64_DCTL0_DTABLEEND;
 352                 if (start)
 353                         ctl0 |= BCM43xx_DMA64_DCTL0_FRAMESTART;
 354                 if (end)
 355                         ctl0 |= BCM43xx_DMA64_DCTL0_FRAMEEND;
 356                 if (irq)
 357                         ctl0 |= BCM43xx_DMA64_DCTL0_IRQ;
 358                 ctl1 |= (bufsize - ring->frameoffset)
 359                         & BCM43xx_DMA64_DCTL1_BYTECNT;
 360                 ctl1 |= (addrext << BCM43xx_DMA64_DCTL1_ADDREXT_SHIFT)
 361                         & BCM43xx_DMA64_DCTL1_ADDREXT_MASK;
 362
 363                 desc->dma64.control0 = cpu_to_le32(ctl0);
 364                 desc->dma64.control1 = cpu_to_le32(ctl1);
 365                 desc->dma64.address_low = cpu_to_le32(addrlo);
 366                 desc->dma64.address_high = cpu_to_le32(addrhi);
 367         } else {
 368                 u32 ctl;
 369                 u32 addr;
 370                 u32 addrext;
 371
 372                 addr = (u32)(dmaaddr & ~BCM43xx_DMA32_ROUTING);
 373                 addrext = (u32)(dmaaddr & BCM43xx_DMA32_ROUTING)
 374                            >> BCM43xx_DMA32_ROUTING_SHIFT;
 375                 addr |= ring->routing;
 376                 ctl = (bufsize - ring->frameoffset)
 377                       & BCM43xx_DMA32_DCTL_BYTECNT;
 378                 if (slot == ring->nr_slots - 1)
 379                         ctl |= BCM43xx_DMA32_DCTL_DTABLEEND;
 380                 if (start)
 381                         ctl |= BCM43xx_DMA32_DCTL_FRAMESTART;
 382                 if (end)
 383                         ctl |= BCM43xx_DMA32_DCTL_FRAMEEND;
 384                 if (irq)
 385                         ctl |= BCM43xx_DMA32_DCTL_IRQ;
 386                 ctl |= (addrext << BCM43xx_DMA32_DCTL_ADDREXT_SHIFT)
 387                        & BCM43xx_DMA32_DCTL_ADDREXT_MASK;
 388
 389                 desc->dma32.control = cpu_to_le32(ctl);
 390                 desc->dma32.address = cpu_to_le32(addr);
 391         }
 392 }
 393
 394 static int setup_rx_descbuffer(struct bcm43xx_dmaring *ring,
 395                                struct bcm43xx_dmadesc_generic *desc,
 396                                struct bcm43xx_dmadesc_meta *meta,
 397                                gfp_t gfp_flags)
 398 {
 399         struct bcm43xx_rxhdr *rxhdr;
 400         struct bcm43xx_hwxmitstatus *xmitstat;
 401         dma_addr_t dmaaddr;
 402         struct sk_buff *skb;
 403
 404         assert(!ring->tx);
 405
 406         skb = __dev_alloc_skb(ring->rx_buffersize, gfp_flags);
 407         if (unlikely(!skb))
 408                 return -ENOMEM;
 409         dmaaddr = map_descbuffer(ring, skb->data, ring->rx_buffersize, 0);
 410         meta->skb = skb;
 411         meta->dmaaddr = dmaaddr;
 412         skb->dev = ring->bcm->net_dev;
 413
 414         fill_descriptor(ring, desc, dmaaddr,
 415                         ring->rx_buffersize, 0, 0, 0);
 416
 417         rxhdr = (struct bcm43xx_rxhdr *)(skb->data);
 418         rxhdr->frame_length = 0;
 419         rxhdr->flags1 = 0;
 420         xmitstat = (struct bcm43xx_hwxmitstatus *)(skb->data);
 421         xmitstat->cookie = 0;
 422
 423         return 0;
 424 }
 425
 426 /* Allocate the initial descbuffers.
 427  * This is used for an RX ring only.
 428  */
 429 static int alloc_initial_descbuffers(struct bcm43xx_dmaring *ring)
 430 {
 431         int i, err = -ENOMEM;
 432         struct bcm43xx_dmadesc_generic *desc;
 433         struct bcm43xx_dmadesc_meta *meta;
 434
 435         for (i = 0; i < ring->nr_slots; i++) {
 436                 desc = bcm43xx_dma_idx2desc(ring, i, &meta);
 437
 438                 err = setup_rx_descbuffer(ring, desc, meta, GFP_KERNEL);
 439                 if (err)
 440                         goto err_unwind;
 441         }
 442         mb();
 443         ring->used_slots = ring->nr_slots;
 444         err = 0;
 445 out:
 446         return err;
 447
 448 err_unwind:
 449         for (i--; i >= 0; i--) {
 450                 desc = bcm43xx_dma_idx2desc(ring, i, &meta);
 451
 452                 unmap_descbuffer(ring, meta->dmaaddr, ring->rx_buffersize, 0);
 453                 dev_kfree_skb(meta->skb);
 454         }
 455         goto out;
 456 }
 457
 458 /* Do initial setup of the DMA controller.
 459  * Reset the controller, write the ring busaddress
 460  * and switch the "enable" bit on.
 461  */
 462 static int dmacontroller_setup(struct bcm43xx_dmaring *ring)
 463 {
 464         int err = 0;
 465         u32 value;
 466         u32 addrext;
 467
 468         if (ring->tx) {
 469                 if (ring->dma64) {
 470                         u64 ringbase = (u64)(ring->dmabase);
 471
 472                         addrext = ((ringbase >> 32) >> BCM43xx_DMA64_ROUTING_SHIFT);
 473                         value = BCM43xx_DMA64_TXENABLE;
 474                         value |= (addrext << BCM43xx_DMA64_TXADDREXT_SHIFT)
 475                                 & BCM43xx_DMA64_TXADDREXT_MASK;
 476                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL, value);
 477                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGLO,
 478                                         (ringbase & 0xFFFFFFFF));
 479                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGHI,
 480                                         ((ringbase >> 32) & ~BCM43xx_DMA64_ROUTING)
 481                                         | ring->routing);
 482                 } else {
 483                         u32 ringbase = (u32)(ring->dmabase);
 484
 485                         addrext = (ringbase >> BCM43xx_DMA32_ROUTING_SHIFT);
 486                         value = BCM43xx_DMA32_TXENABLE;
 487                         value |= (addrext << BCM43xx_DMA32_TXADDREXT_SHIFT)
 488                                 & BCM43xx_DMA32_TXADDREXT_MASK;
 489                         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL, value);
 490                         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXRING,
 491                                         (ringbase & ~BCM43xx_DMA32_ROUTING)
 492                                         | ring->routing);
 493                 }
 494         } else {
 495                 err = alloc_initial_descbuffers(ring);
 496                 if (err)
 497                         goto out;
 498                 if (ring->dma64) {
 499                         u64 ringbase = (u64)(ring->dmabase);
 500
 501                         addrext = ((ringbase >> 32) >> BCM43xx_DMA64_ROUTING_SHIFT);
 502                         value = (ring->frameoffset << BCM43xx_DMA64_RXFROFF_SHIFT);
 503                         value |= BCM43xx_DMA64_RXENABLE;
 504                         value |= (addrext << BCM43xx_DMA64_RXADDREXT_SHIFT)
 505                                 & BCM43xx_DMA64_RXADDREXT_MASK;
 506                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXCTL, value);
 507                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGLO,
 508                                         (ringbase & 0xFFFFFFFF));
 509                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGHI,
 510                                         ((ringbase >> 32) & ~BCM43xx_DMA64_ROUTING)
 511                                         | ring->routing);
 512                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXINDEX, 200);
 513                 } else {
 514                         u32 ringbase = (u32)(ring->dmabase);
 515
 516                         addrext = (ringbase >> BCM43xx_DMA32_ROUTING_SHIFT);
 517                         value = (ring->frameoffset << BCM43xx_DMA32_RXFROFF_SHIFT);
 518                         value |= BCM43xx_DMA32_RXENABLE;
 519                         value |= (addrext << BCM43xx_DMA32_RXADDREXT_SHIFT)
 520                                 & BCM43xx_DMA32_RXADDREXT_MASK;
 521                         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXCTL, value);
 522                         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXRING,
 523                                         (ringbase & ~BCM43xx_DMA32_ROUTING)
 524                                         | ring->routing);
 525                         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXINDEX, 200);
 526                 }
 527         }
 528
 529 out:
 530         return err;
 531 }
 532
 533 /* Shutdown the DMA controller. */
 534 static void dmacontroller_cleanup(struct bcm43xx_dmaring *ring)
 535 {
 536         if (ring->tx) {
 537                 bcm43xx_dmacontroller_tx_reset(ring->bcm, ring->mmio_base, ring->dma64);
 538                 if (ring->dma64) {
 539                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGLO, 0);
 540                         bcm43xx_dma_write(ring, BCM43xx_DMA64_TXRINGHI, 0);
 541                 } else
 542                         bcm43xx_dma_write(ring, BCM43xx_DMA32_TXRING, 0);
 543         } else {
 544                 bcm43xx_dmacontroller_rx_reset(ring->bcm, ring->mmio_base, ring->dma64);
 545                 if (ring->dma64) {
 546                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGLO, 0);
 547                         bcm43xx_dma_write(ring, BCM43xx_DMA64_RXRINGHI, 0);
 548                 } else
 549                         bcm43xx_dma_write(ring, BCM43xx_DMA32_RXRING, 0);
 550         }
 551 }
 552
 553 static void free_all_descbuffers(struct bcm43xx_dmaring *ring)
 554 {
 555         struct bcm43xx_dmadesc_generic *desc;
 556         struct bcm43xx_dmadesc_meta *meta;
 557         int i;
 558
 559         if (!ring->used_slots)
 560                 return;
 561         for (i = 0; i < ring->nr_slots; i++) {
 562                 desc = bcm43xx_dma_idx2desc(ring, i, &meta);
 563
 564                 if (!meta->skb) {
 565                         assert(ring->tx);
 566                         continue;
 567                 }
 568                 if (ring->tx) {
 569                         unmap_descbuffer(ring, meta->dmaaddr,
 570                                         meta->skb->len, 1);
 571                 } else {
 572                         unmap_descbuffer(ring, meta->dmaaddr,
 573                                         ring->rx_buffersize, 0);
 574                 }
 575                 free_descriptor_buffer(ring, meta, 0);
 576         }
 577 }
 578
 579 /* Main initialization function. */
 580 static
 581 struct bcm43xx_dmaring * bcm43xx_setup_dmaring(struct bcm43xx_private *bcm,
 582                                                int controller_index,
 583                                                int for_tx,
 584                                                int dma64)
 585 {
 586         struct bcm43xx_dmaring *ring;
 587         int err;
 588         int nr_slots;
 589
 590         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
 591         if (!ring)
 592                 goto out;
 593
 594         nr_slots = BCM43xx_RXRING_SLOTS;
 595         if (for_tx)
 596                 nr_slots = BCM43xx_TXRING_SLOTS;
 597
 598         ring->meta = kcalloc(nr_slots, sizeof(struct bcm43xx_dmadesc_meta),
 599                              GFP_KERNEL);
 600         if (!ring->meta)
 601                 goto err_kfree_ring;
 602
 603         ring->routing = BCM43xx_DMA32_CLIENTTRANS;
 604         if (dma64)
 605                 ring->routing = BCM43xx_DMA64_CLIENTTRANS;
 606 #ifdef CONFIG_BCM947XX
 607         if (bcm->pci_dev->bus->number == 0)
 608                 ring->routing = dma64 ? BCM43xx_DMA64_NOTRANS : BCM43xx_DMA32_NOTRANS;
 609 #endif
 610
 611         ring->bcm = bcm;
 612         ring->nr_slots = nr_slots;
 613         ring->suspend_mark = ring->nr_slots * BCM43xx_TXSUSPEND_PERCENT / 100;
 614         ring->resume_mark = ring->nr_slots * BCM43xx_TXRESUME_PERCENT / 100;
 615         assert(ring->suspend_mark < ring->resume_mark);
 616         ring->mmio_base = bcm43xx_dmacontroller_base(dma64, controller_index);
 617         ring->index = controller_index;
 618         ring->dma64 = !!dma64;
 619         if (for_tx) {
 620                 ring->tx = 1;
 621                 ring->current_slot = -1;
 622         } else {
 623                 if (ring->index == 0) {
 624                         ring->rx_buffersize = BCM43xx_DMA0_RX_BUFFERSIZE;
 625                         ring->frameoffset = BCM43xx_DMA0_RX_FRAMEOFFSET;
 626                 } else if (ring->index == 3) {
 627                         ring->rx_buffersize = BCM43xx_DMA3_RX_BUFFERSIZE;
 628                         ring->frameoffset = BCM43xx_DMA3_RX_FRAMEOFFSET;
 629                 } else
 630                         assert(0);
 631         }
 632
 633         err = alloc_ringmemory(ring);
 634         if (err)
 635                 goto err_kfree_meta;
 636         err = dmacontroller_setup(ring);
 637         if (err)
 638                 goto err_free_ringmemory;
 639
 640 out:
 641         return ring;
 642
 643 err_free_ringmemory:
 644         free_ringmemory(ring);
 645 err_kfree_meta:
 646         kfree(ring->meta);
 647 err_kfree_ring:
 648         kfree(ring);
 649         ring = NULL;
 650         goto out;
 651 }
 652
 653 /* Main cleanup function. */
 654 static void bcm43xx_destroy_dmaring(struct bcm43xx_dmaring *ring)
 655 {
 656         if (!ring)
 657                 return;
 658
 659         dprintk(KERN_INFO PFX "DMA-%s 0x%04X (%s) max used slots: %d/%d\n",
 660                 (ring->dma64) ? "64" : "32",
 661                 ring->mmio_base,
 662                 (ring->tx) ? "TX" : "RX",
 663                 ring->max_used_slots, ring->nr_slots);
 664         /* Device IRQs are disabled prior entering this function,
 665          * so no need to take care of concurrency with rx handler stuff.
 666          */
 667         dmacontroller_cleanup(ring);
 668         free_all_descbuffers(ring);
 669         free_ringmemory(ring);
 670
 671         kfree(ring->meta);
 672         kfree(ring);
 673 }
 674
 675 void bcm43xx_dma_free(struct bcm43xx_private *bcm)
 676 {
 677         struct bcm43xx_dma *dma;
 678
 679         if (bcm43xx_using_pio(bcm))
 680                 return;
 681         dma = bcm43xx_current_dma(bcm);
 682
 683         bcm43xx_destroy_dmaring(dma->rx_ring3);
 684         dma->rx_ring3 = NULL;
 685         bcm43xx_destroy_dmaring(dma->rx_ring0);
 686         dma->rx_ring0 = NULL;
 687
 688         bcm43xx_destroy_dmaring(dma->tx_ring5);
 689         dma->tx_ring5 = NULL;
 690         bcm43xx_destroy_dmaring(dma->tx_ring4);
 691         dma->tx_ring4 = NULL;
 692         bcm43xx_destroy_dmaring(dma->tx_ring3);
 693         dma->tx_ring3 = NULL;
 694         bcm43xx_destroy_dmaring(dma->tx_ring2);
 695         dma->tx_ring2 = NULL;
 696         bcm43xx_destroy_dmaring(dma->tx_ring1);
 697         dma->tx_ring1 = NULL;
 698         bcm43xx_destroy_dmaring(dma->tx_ring0);
 699         dma->tx_ring0 = NULL;
 700 }
 701
 702 int bcm43xx_dma_init(struct bcm43xx_private *bcm)
 703 {
 704         struct bcm43xx_dma *dma = bcm43xx_current_dma(bcm);
 705         struct bcm43xx_dmaring *ring;
 706         int err = -ENOMEM;
 707         int dma64 = 0;
 708         u32 sbtmstatehi;
 709
 710         sbtmstatehi = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
 711         if (sbtmstatehi & BCM43xx_SBTMSTATEHIGH_DMA64BIT)
 712                 dma64 = 1;
 713
 714         /* setup TX DMA channels. */
 715         ring = bcm43xx_setup_dmaring(bcm, 0, 1, dma64);
 716         if (!ring)
 717                 goto out;
 718         dma->tx_ring0 = ring;
 719
 720         ring = bcm43xx_setup_dmaring(bcm, 1, 1, dma64);
 721         if (!ring)
 722                 goto err_destroy_tx0;
 723         dma->tx_ring1 = ring;
 724
 725         ring = bcm43xx_setup_dmaring(bcm, 2, 1, dma64);
 726         if (!ring)
 727                 goto err_destroy_tx1;
 728         dma->tx_ring2 = ring;
 729
 730         ring = bcm43xx_setup_dmaring(bcm, 3, 1, dma64);
 731         if (!ring)
 732                 goto err_destroy_tx2;
 733         dma->tx_ring3 = ring;
 734
 735         ring = bcm43xx_setup_dmaring(bcm, 4, 1, dma64);
 736         if (!ring)
 737                 goto err_destroy_tx3;
 738         dma->tx_ring4 = ring;
 739
 740         ring = bcm43xx_setup_dmaring(bcm, 5, 1, dma64);
 741         if (!ring)
 742                 goto err_destroy_tx4;
 743         dma->tx_ring5 = ring;
 744
 745         /* setup RX DMA channels. */
 746         ring = bcm43xx_setup_dmaring(bcm, 0, 0, dma64);
 747         if (!ring)
 748                 goto err_destroy_tx5;
 749         dma->rx_ring0 = ring;
 750
 751         if (bcm->current_core->rev < 5) {
 752                 ring = bcm43xx_setup_dmaring(bcm, 3, 0, dma64);
 753                 if (!ring)
 754                         goto err_destroy_rx0;
 755                 dma->rx_ring3 = ring;
 756         }
 757
 758         dprintk(KERN_INFO PFX "%s DMA initialized\n",
 759                         dma64 ? "64-bit" : "32-bit");
 760         err = 0;
 761 out:
 762         return err;
 763
 764 err_destroy_rx0:
 765         bcm43xx_destroy_dmaring(dma->rx_ring0);
 766         dma->rx_ring0 = NULL;
 767 err_destroy_tx5:
 768         bcm43xx_destroy_dmaring(dma->tx_ring5);
 769         dma->tx_ring5 = NULL;
 770 err_destroy_tx4:
 771         bcm43xx_destroy_dmaring(dma->tx_ring4);
 772         dma->tx_ring4 = NULL;
 773 err_destroy_tx3:
 774         bcm43xx_destroy_dmaring(dma->tx_ring3);
 775         dma->tx_ring3 = NULL;
 776 err_destroy_tx2:
 777         bcm43xx_destroy_dmaring(dma->tx_ring2);
 778         dma->tx_ring2 = NULL;
 779 err_destroy_tx1:
 780         bcm43xx_destroy_dmaring(dma->tx_ring1);
 781         dma->tx_ring1 = NULL;
 782 err_destroy_tx0:
 783         bcm43xx_destroy_dmaring(dma->tx_ring0);
 784         dma->tx_ring0 = NULL;
 785         goto out;
 786 }
 787
 788 /* Generate a cookie for the TX header. */
 789 static u16 generate_cookie(struct bcm43xx_dmaring *ring,
 790                            int slot)
 791 {
 792         u16 cookie = 0x1000;
 793
 794         /* Use the upper 4 bits of the cookie as
 795          * DMA controller ID and store the slot number
 796          * in the lower 12 bits.
 797          * Note that the cookie must never be 0, as this
 798          * is a special value used in RX path.
 799          */
 800         switch (ring->index) {
 801         case 0:
 802                 cookie = 0xA000;
 803                 break;
 804         case 1:
 805                 cookie = 0xB000;
 806                 break;
 807         case 2:
 808                 cookie = 0xC000;
 809                 break;
 810         case 3:
 811                 cookie = 0xD000;
 812                 break;
 813         case 4:
 814                 cookie = 0xE000;
 815                 break;
 816         case 5:
 817                 cookie = 0xF000;
 818                 break;
 819         }
 820         assert(((u16)slot & 0xF000) == 0x0000);
 821         cookie |= (u16)slot;
 822
 823         return cookie;
 824 }
 825
 826 /* Inspect a cookie and find out to which controller/slot it belongs. */
 827 static
 828 struct bcm43xx_dmaring * parse_cookie(struct bcm43xx_private *bcm,
 829                                       u16 cookie, int *slot)
 830 {
 831         struct bcm43xx_dma *dma = bcm43xx_current_dma(bcm);
 832         struct bcm43xx_dmaring *ring = NULL;
 833
 834         switch (cookie & 0xF000) {
 835         case 0xA000:
 836                 ring = dma->tx_ring0;
 837                 break;
 838         case 0xB000:
 839                 ring = dma->tx_ring1;
 840                 break;
 841         case 0xC000:
 842                 ring = dma->tx_ring2;
 843                 break;
 844         case 0xD000:
 845                 ring = dma->tx_ring3;
 846                 break;
 847         case 0xE000:
 848                 ring = dma->tx_ring4;
 849                 break;
 850         case 0xF000:
 851                 ring = dma->tx_ring5;
 852                 break;
 853         default:
 854                 assert(0);
 855         }
 856         *slot = (cookie & 0x0FFF);
 857         assert(*slot >= 0 && *slot < ring->nr_slots);
 858
 859         return ring;
 860 }
 861
 862 static void dmacontroller_poke_tx(struct bcm43xx_dmaring *ring,
 863                                   int slot)
 864 {
 865         u16 offset;
 866         int descsize;
 867
 868         /* Everything is ready to start. Buffers are DMA mapped and
 869          * associated with slots.
 870          * "slot" is the last slot of the new frame we want to transmit.
 871          * Close your seat belts now, please.
 872          */
 873         wmb();
 874         slot = next_slot(ring, slot);
 875         offset = (ring->dma64) ? BCM43xx_DMA64_TXINDEX : BCM43xx_DMA32_TXINDEX;
 876         descsize = (ring->dma64) ? sizeof(struct bcm43xx_dmadesc64)
 877                 : sizeof(struct bcm43xx_dmadesc32);
 878         bcm43xx_dma_write(ring, offset,
 879                         (u32)(slot * descsize));
 880 }
 881
 882 static void dma_tx_fragment(struct bcm43xx_dmaring *ring,
 883                             struct sk_buff *skb,
 884                             u8 cur_frag)
 885 {
 886         int slot;
 887         struct bcm43xx_dmadesc_generic *desc;
 888         struct bcm43xx_dmadesc_meta *meta;
 889         dma_addr_t dmaaddr;
 890
 891         assert(skb_shinfo(skb)->nr_frags == 0);
 892
 893         slot = request_slot(ring);
 894         desc = bcm43xx_dma_idx2desc(ring, slot, &meta);
 895
 896         /* Add a device specific TX header. */
 897         assert(skb_headroom(skb) >= sizeof(struct bcm43xx_txhdr));
 898         /* Reserve enough headroom for the device tx header. */
 899         __skb_push(skb, sizeof(struct bcm43xx_txhdr));
 900         /* Now calculate and add the tx header.
 901          * The tx header includes the PLCP header.
 902          */
 903         bcm43xx_generate_txhdr(ring->bcm,
 904                                (struct bcm43xx_txhdr *)skb->data,
 905                                skb->data + sizeof(struct bcm43xx_txhdr),
 906                                skb->len - sizeof(struct bcm43xx_txhdr),
 907                                (cur_frag == 0),
 908                                generate_cookie(ring, slot));
 909
 910         meta->skb = skb;
 911         dmaaddr = map_descbuffer(ring, skb->data, skb->len, 1);
 912         meta->dmaaddr = dmaaddr;
 913
 914         fill_descriptor(ring, desc, dmaaddr,
 915                         skb->len, 1, 1, 1);
 916
 917         /* Now transfer the whole frame. */
 918         dmacontroller_poke_tx(ring, slot);
 919 }
 920
 921 int bcm43xx_dma_tx(struct bcm43xx_private *bcm,
 922                    struct ieee80211_txb *txb)
 923 {
 924         /* We just received a packet from the kernel network subsystem.
 925          * Add headers and DMA map the memory. Poke
 926          * the device to send the stuff.
 927          * Note that this is called from atomic context.
 928          */
 929         struct bcm43xx_dmaring *ring = bcm43xx_current_dma(bcm)->tx_ring1;
 930         u8 i;
 931         struct sk_buff *skb;
 932
 933         assert(ring->tx);
 934         if (unlikely(free_slots(ring) < txb->nr_frags)) {
 935                 /* The queue should be stopped,
 936                  * if we are low on free slots.
 937                  * If this ever triggers, we have to lower the suspend_mark.
 938                  */
 939                 dprintkl(KERN_ERR PFX "Out of DMA descriptor slots!\n");
 940                 return -ENOMEM;
 941         }
 942
 943         for (i = 0; i < txb->nr_frags; i++) {
 944                 skb = txb->fragments[i];
 945                 /* Take skb from ieee80211_txb_free */
 946                 txb->fragments[i] = NULL;
 947                 dma_tx_fragment(ring, skb, i);
 948         }
 949         ieee80211_txb_free(txb);
 950
 951         return 0;
 952 }
 953
 954 void bcm43xx_dma_handle_xmitstatus(struct bcm43xx_private *bcm,
 955                                    struct bcm43xx_xmitstatus *status)
 956 {
 957         struct bcm43xx_dmaring *ring;
 958         struct bcm43xx_dmadesc_generic *desc;
 959         struct bcm43xx_dmadesc_meta *meta;
 960         int is_last_fragment;
 961         int slot;
 962         u32 tmp;
 963
 964         ring = parse_cookie(bcm, status->cookie, &slot);
 965         assert(ring);
 966         assert(ring->tx);
 967         while (1) {
 968                 assert(slot >= 0 && slot < ring->nr_slots);
 969                 desc = bcm43xx_dma_idx2desc(ring, slot, &meta);
 970
 971                 if (ring->dma64) {
 972                         tmp = le32_to_cpu(desc->dma64.control0);
 973                         is_last_fragment = !!(tmp & BCM43xx_DMA64_DCTL0_FRAMEEND);
 974                 } else {
 975                         tmp = le32_to_cpu(desc->dma32.control);
 976                         is_last_fragment = !!(tmp & BCM43xx_DMA32_DCTL_FRAMEEND);
 977                 }
 978                 unmap_descbuffer(ring, meta->dmaaddr, meta->skb->len, 1);
 979                 free_descriptor_buffer(ring, meta, 1);
 980                 /* Everything belonging to the slot is unmapped
 981                  * and freed, so we can return it.
 982                  */
 983                 return_slot(ring, slot);
 984
 985                 if (is_last_fragment)
 986                         break;
 987                 slot = next_slot(ring, slot);
 988         }
 989         bcm->stats.last_tx = jiffies;
 990 }
 991
 992 static void dma_rx(struct bcm43xx_dmaring *ring,
 993                    int *slot)
 994 {
 995         struct bcm43xx_dmadesc_generic *desc;
 996         struct bcm43xx_dmadesc_meta *meta;
 997         struct bcm43xx_rxhdr *rxhdr;
 998         struct sk_buff *skb;
 999         u16 len;
1000         int err;
1001         dma_addr_t dmaaddr;
1002
1003         desc = bcm43xx_dma_idx2desc(ring, *slot, &meta);
1004
1005         sync_descbuffer_for_cpu(ring, meta->dmaaddr, ring->rx_buffersize);
1006         skb = meta->skb;
1007
1008         if (ring->index == 3) {
1009                 /* We received an xmit status. */
1010                 struct bcm43xx_hwxmitstatus *hw = (struct bcm43xx_hwxmitstatus *)skb->data;
1011                 struct bcm43xx_xmitstatus stat;
1012                 int i = 0;
1013
1014                 stat.cookie = le16_to_cpu(hw->cookie);
1015                 while (stat.cookie == 0) {
1016                         if (unlikely(++i >= 10000)) {
1017                                 assert(0);
1018                                 break;
1019                         }
1020                         udelay(2);
1021                         barrier();
1022                         stat.cookie = le16_to_cpu(hw->cookie);
1023                 }
1024                 stat.flags = hw->flags;
1025                 stat.cnt1 = hw->cnt1;
1026                 stat.cnt2 = hw->cnt2;
1027                 stat.seq = le16_to_cpu(hw->seq);
1028                 stat.unknown = le16_to_cpu(hw->unknown);
1029
1030                 bcm43xx_debugfs_log_txstat(ring->bcm, &stat);
1031                 bcm43xx_dma_handle_xmitstatus(ring->bcm, &stat);
1032                 /* recycle the descriptor buffer. */
1033                 sync_descbuffer_for_device(ring, meta->dmaaddr, ring->rx_buffersize);
1034
1035                 return;
1036         }
1037         rxhdr = (struct bcm43xx_rxhdr *)skb->data;
1038         len = le16_to_cpu(rxhdr->frame_length);
1039         if (len == 0) {
1040                 int i = 0;
1041
1042                 do {
1043                         udelay(2);
1044                         barrier();
1045                         len = le16_to_cpu(rxhdr->frame_length);
1046                 } while (len == 0 && i++ < 5);
1047                 if (unlikely(len == 0)) {
1048                         /* recycle the descriptor buffer. */
1049                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1050                                                    ring->rx_buffersize);
1051                         goto drop;
1052                 }
1053         }
1054         if (unlikely(len > ring->rx_buffersize)) {
1055                 /* The data did not fit into one descriptor buffer
1056                  * and is split over multiple buffers.
1057                  * This should never happen, as we try to allocate buffers
1058                  * big enough. So simply ignore this packet.
1059                  */
1060                 int cnt = 0;
1061                 s32 tmp = len;
1062
1063                 while (1) {
1064                         desc = bcm43xx_dma_idx2desc(ring, *slot, &meta);
1065                         /* recycle the descriptor buffer. */
1066                         sync_descbuffer_for_device(ring, meta->dmaaddr,
1067                                                    ring->rx_buffersize);
1068                         *slot = next_slot(ring, *slot);
1069                         cnt++;
1070                         tmp -= ring->rx_buffersize;
1071                         if (tmp <= 0)
1072                                 break;
1073                 }
1074                 printkl(KERN_ERR PFX "DMA RX buffer too small "
1075                         "(len: %u, buffer: %u, nr-dropped: %d)\n",
1076                         len, ring->rx_buffersize, cnt);
1077                 goto drop;
1078         }
1079         len -= IEEE80211_FCS_LEN;
1080
1081         dmaaddr = meta->dmaaddr;
1082         err = setup_rx_descbuffer(ring, desc, meta, GFP_ATOMIC);
1083         if (unlikely(err)) {
1084                 dprintkl(KERN_ERR PFX "DMA RX: setup_rx_descbuffer() failed\n");
1085                 sync_descbuffer_for_device(ring, dmaaddr,
1086                                            ring->rx_buffersize);
1087                 goto drop;
1088         }
1089
1090         unmap_descbuffer(ring, dmaaddr, ring->rx_buffersize, 0);
1091         skb_put(skb, len + ring->frameoffset);
1092         skb_pull(skb, ring->frameoffset);
1093
1094         err = bcm43xx_rx(ring->bcm, skb, rxhdr);
1095         if (err) {
1096                 dev_kfree_skb_irq(skb);
1097                 goto drop;
1098         }
1099
1100 drop:
1101         return;
1102 }
1103
1104 void bcm43xx_dma_rx(struct bcm43xx_dmaring *ring)
1105 {
1106         u32 status;
1107         u16 descptr;
1108         int slot, current_slot;
1109 #ifdef CONFIG_BCM43XX_DEBUG
1110         int used_slots = 0;
1111 #endif
1112
1113         assert(!ring->tx);
1114         if (ring->dma64) {
1115                 status = bcm43xx_dma_read(ring, BCM43xx_DMA64_RXSTATUS);
1116                 descptr = (status & BCM43xx_DMA64_RXSTATDPTR);
1117                 current_slot = descptr / sizeof(struct bcm43xx_dmadesc64);
1118         } else {
1119                 status = bcm43xx_dma_read(ring, BCM43xx_DMA32_RXSTATUS);
1120                 descptr = (status & BCM43xx_DMA32_RXDPTR);
1121                 current_slot = descptr / sizeof(struct bcm43xx_dmadesc32);
1122         }
1123         assert(current_slot >= 0 && current_slot < ring->nr_slots);
1124
1125         slot = ring->current_slot;
1126         for ( ; slot != current_slot; slot = next_slot(ring, slot)) {
1127                 dma_rx(ring, &slot);
1128 #ifdef CONFIG_BCM43XX_DEBUG
1129                 if (++used_slots > ring->max_used_slots)
1130                         ring->max_used_slots = used_slots;
1131 #endif
1132         }
1133         if (ring->dma64) {
1134                 bcm43xx_dma_write(ring, BCM43xx_DMA64_RXINDEX,
1135                                 (u32)(slot * sizeof(struct bcm43xx_dmadesc64)));
1136         } else {
1137                 bcm43xx_dma_write(ring, BCM43xx_DMA32_RXINDEX,
1138                                 (u32)(slot * sizeof(struct bcm43xx_dmadesc32)));
1139         }
1140         ring->current_slot = slot;
1141 }
1142
1143 void bcm43xx_dma_tx_suspend(struct bcm43xx_dmaring *ring)
1144 {
1145         assert(ring->tx);
1146         bcm43xx_power_saving_ctl_bits(ring->bcm, -1, 1);
1147         if (ring->dma64) {
1148                 bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL,
1149                                 bcm43xx_dma_read(ring, BCM43xx_DMA64_TXCTL)
1150                                 | BCM43xx_DMA64_TXSUSPEND);
1151         } else {
1152                 bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL,
1153                                 bcm43xx_dma_read(ring, BCM43xx_DMA32_TXCTL)
1154                                 | BCM43xx_DMA32_TXSUSPEND);
1155         }
1156 }
1157
1158 void bcm43xx_dma_tx_resume(struct bcm43xx_dmaring *ring)
1159 {
1160         assert(ring->tx);
1161         if (ring->dma64) {
1162                 bcm43xx_dma_write(ring, BCM43xx_DMA64_TXCTL,
1163                                 bcm43xx_dma_read(ring, BCM43xx_DMA64_TXCTL)
1164                                 & ~BCM43xx_DMA64_TXSUSPEND);
1165         } else {
1166                 bcm43xx_dma_write(ring, BCM43xx_DMA32_TXCTL,
1167                                 bcm43xx_dma_read(ring, BCM43xx_DMA32_TXCTL)
1168                                 & ~BCM43xx_DMA32_TXSUSPEND);
1169         }
1170         bcm43xx_power_saving_ctl_bits(ring->bcm, -1, -1);
1171 }