3 * Copyright (C) 2002 Intersil Americas Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/version.h>
26 #if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,75))
27 #include <linux/device.h>
28 # define _REQ_FW_DEV_T struct device *
30 # define _REQ_FW_DEV_T char *
33 #include <asm/byteorder.h>
35 #define ISL38XX_CB_RX_QSIZE 8
36 #define ISL38XX_CB_TX_QSIZE 32
38 /* ISL38XX Access Point Specific definitions */
39 #define ISL38XX_MAX_WDS_LINKS 8
41 /* ISL38xx Client Specific definitions */
42 #define ISL38XX_PSM_ACTIVE_STATE 0
43 #define ISL38XX_PSM_POWERSAVE_STATE 1
45 /* ISL38XX Host Interface Definitions */
46 #define ISL38XX_PCI_MEM_SIZE 0x02000
47 #define ISL38XX_MEMORY_WINDOW_SIZE 0x01000
48 #define ISL38XX_DEV_FIRMWARE_ADDRES 0x20000
49 #define ISL38XX_WRITEIO_DELAY 10 /* in us */
50 #define ISL38XX_RESET_DELAY 50 /* in ms */
51 #define ISL38XX_WAIT_CYCLE 10 /* in 10ms */
52 #define ISL38XX_MAX_WAIT_CYCLES 10
55 #define ISL38XX_HARDWARE_REG 0x0000
56 #define ISL38XX_CARDBUS_CIS 0x0800
57 #define ISL38XX_DIRECT_MEM_WIN 0x1000
59 /* Hardware registers */
60 #define ISL38XX_DEV_INT_REG 0x0000
61 #define ISL38XX_INT_IDENT_REG 0x0010
62 #define ISL38XX_INT_ACK_REG 0x0014
63 #define ISL38XX_INT_EN_REG 0x0018
64 #define ISL38XX_GEN_PURP_COM_REG_1 0x0020
65 #define ISL38XX_GEN_PURP_COM_REG_2 0x0024
66 #define ISL38XX_CTRL_BLK_BASE_REG ISL38XX_GEN_PURP_COM_REG_1
67 #define ISL38XX_DIR_MEM_BASE_REG 0x0030
68 #define ISL38XX_CTRL_STAT_REG 0x0078
70 /* High end mobos queue up pci writes, the following
71 * is used to "read" from after a write to force flush */
72 #define ISL38XX_PCI_POSTING_FLUSH ISL38XX_INT_EN_REG
75 * isl38xx_w32_flush - PCI iomem write helper
76 * @base: (host) memory base address of the device
77 * @val: 32bit value (host order) to write
78 * @offset: byte offset into @base to write value to
80 * This helper takes care of writing a 32bit datum to the
81 * specified offset into the device's pci memory space, and making sure
82 * the pci memory buffers get flushed by performing one harmless read
83 * from the %ISL38XX_PCI_POSTING_FLUSH offset.
86 isl38xx_w32_flush(void *base, u32 val, unsigned long offset)
88 writel(val, base + offset);
89 (void) readl(base + ISL38XX_PCI_POSTING_FLUSH);
92 /* Device Interrupt register bits */
93 #define ISL38XX_DEV_INT_RESET 0x0001
94 #define ISL38XX_DEV_INT_UPDATE 0x0002
95 #define ISL38XX_DEV_INT_WAKEUP 0x0008
96 #define ISL38XX_DEV_INT_SLEEP 0x0010
98 /* Interrupt Identification/Acknowledge/Enable register bits */
99 #define ISL38XX_INT_IDENT_UPDATE 0x0002
100 #define ISL38XX_INT_IDENT_INIT 0x0004
101 #define ISL38XX_INT_IDENT_WAKEUP 0x0008
102 #define ISL38XX_INT_IDENT_SLEEP 0x0010
103 #define ISL38XX_INT_SOURCES 0x001E
105 /* Control/Status register bits */
106 #define ISL38XX_CTRL_STAT_SLEEPMODE 0x00000200
107 #define ISL38XX_CTRL_STAT_CLKRUN 0x00800000
108 #define ISL38XX_CTRL_STAT_RESET 0x10000000
109 #define ISL38XX_CTRL_STAT_RAMBOOT 0x20000000
110 #define ISL38XX_CTRL_STAT_STARTHALTED 0x40000000
111 #define ISL38XX_CTRL_STAT_HOST_OVERRIDE 0x80000000
113 /* Control Block definitions */
114 #define ISL38XX_CB_RX_DATA_LQ 0
115 #define ISL38XX_CB_TX_DATA_LQ 1
116 #define ISL38XX_CB_RX_DATA_HQ 2
117 #define ISL38XX_CB_TX_DATA_HQ 3
118 #define ISL38XX_CB_RX_MGMTQ 4
119 #define ISL38XX_CB_TX_MGMTQ 5
120 #define ISL38XX_CB_QCOUNT 6
121 #define ISL38XX_CB_MGMT_QSIZE 4
122 #define ISL38XX_MIN_QTHRESHOLD 4 /* fragments */
124 /* Memory Manager definitions */
125 #define MGMT_FRAME_SIZE 1500 /* >= size struct obj_bsslist */
126 #define MGMT_TX_FRAME_COUNT 24 /* max 4 + spare 4 + 8 init */
127 #define MGMT_RX_FRAME_COUNT 24 /* 4*4 + spare 8 */
128 #define MGMT_FRAME_COUNT (MGMT_TX_FRAME_COUNT + MGMT_RX_FRAME_COUNT)
129 #define CONTROL_BLOCK_SIZE 1024 /* should be enough */
130 #define PSM_FRAME_SIZE 1536
131 #define PSM_MINIMAL_STATION_COUNT 64
132 #define PSM_FRAME_COUNT PSM_MINIMAL_STATION_COUNT
133 #define PSM_BUFFER_SIZE PSM_FRAME_SIZE * PSM_FRAME_COUNT
134 #define MAX_TRAP_RX_QUEUE 4
135 #define HOST_MEM_BLOCK CONTROL_BLOCK_SIZE + PSM_BUFFER_SIZE
137 /* Fragment package definitions */
138 #define FRAGMENT_FLAG_MF 0x0001
139 #define MAX_FRAGMENT_SIZE 1536
141 /* In monitor mode frames have a header. I don't know exactly how big those
142 * frame can be but I've never seen any frame bigger than 1584... :
144 #define MAX_FRAGMENT_SIZE_RX 1600
147 u32 address; /* physical address on host */
148 u16 size; /* packet size */
149 u16 flags; /* set of bit-wise flags */
153 u32 driver_curr_frag[ISL38XX_CB_QCOUNT];
154 u32 device_curr_frag[ISL38XX_CB_QCOUNT];
155 isl38xx_fragment rx_data_low[ISL38XX_CB_RX_QSIZE];
156 isl38xx_fragment tx_data_low[ISL38XX_CB_TX_QSIZE];
157 isl38xx_fragment rx_data_high[ISL38XX_CB_RX_QSIZE];
158 isl38xx_fragment tx_data_high[ISL38XX_CB_TX_QSIZE];
159 isl38xx_fragment rx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
160 isl38xx_fragment tx_data_mgmt[ISL38XX_CB_MGMT_QSIZE];
163 typedef struct isl38xx_cb isl38xx_control_block;
165 /* determine number of entries currently in queue */
166 int isl38xx_in_queue(isl38xx_control_block *cb, int queue);
168 void isl38xx_disable_interrupts(void *);
169 void isl38xx_enable_common_interrupts(void *);
171 void isl38xx_handle_sleep_request(isl38xx_control_block *, int *,
173 void isl38xx_handle_wakeup(isl38xx_control_block *, int *, void *);
174 void isl38xx_trigger_device(int, void *);
175 void isl38xx_interface_reset(void *, dma_addr_t);
177 int isl38xx_upload_firmware(char *, _REQ_FW_DEV_T, void *, dma_addr_t);
179 #endif /* _ISL_38XX_H */