drivers/pci/hotplug/shpchp_hpc.c

   1 /*
   2  * Standard PCI Hot Plug Driver
   3  *
   4  * Copyright (C) 1995,2001 Compaq Computer Corporation
   5  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
   6  * Copyright (C) 2001 IBM Corp.
   7  * Copyright (C) 2003-2004 Intel Corporation
   8  *
   9  * All rights reserved.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  19  * NON INFRINGEMENT.  See the GNU General Public License for more
  20  * details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25  *
  26  * Send feedback to <greg@kroah.com>,<dely.l.sy@intel.com>
  27  *
  28  */
  29
  30 #include <linux/config.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/types.h>
  34 #include <linux/slab.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/spinlock.h>
  38 #include <linux/pci.h>
  39 #include <asm/system.h>
  40 #include "shpchp.h"
  41
  42 #ifdef DEBUG
  43 #define DBG_K_TRACE_ENTRY      ((unsigned int)0x00000001)       /* On function entry */
  44 #define DBG_K_TRACE_EXIT       ((unsigned int)0x00000002)       /* On function exit */
  45 #define DBG_K_INFO             ((unsigned int)0x00000004)       /* Info messages */
  46 #define DBG_K_ERROR            ((unsigned int)0x00000008)       /* Error messages */
  47 #define DBG_K_TRACE            (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
  48 #define DBG_K_STANDARD         (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
  49 /* Redefine this flagword to set debug level */
  50 #define DEBUG_LEVEL            DBG_K_STANDARD
  51
  52 #define DEFINE_DBG_BUFFER     char __dbg_str_buf[256];
  53
  54 #define DBG_PRINT( dbg_flags, args... )              \
  55         do {                                             \
  56           if ( DEBUG_LEVEL & ( dbg_flags ) )             \
  57           {                                              \
  58             int len;                                     \
  59             len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
  60                   __FILE__, __LINE__, __FUNCTION__ );    \
  61             sprintf( __dbg_str_buf + len, args );        \
  62             printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
  63           }                                              \
  64         } while (0)
  65
  66 #define DBG_ENTER_ROUTINE       DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
  67 #define DBG_LEAVE_ROUTINE       DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
  68 #else
  69 #define DEFINE_DBG_BUFFER
  70 #define DBG_ENTER_ROUTINE
  71 #define DBG_LEAVE_ROUTINE
  72 #endif                          /* DEBUG */
  73
  74 /* Slot Available Register I field definition */
  75 #define SLOT_33MHZ              0x0000001f
  76 #define SLOT_66MHZ_PCIX         0x00001f00
  77 #define SLOT_100MHZ_PCIX        0x001f0000
  78 #define SLOT_133MHZ_PCIX        0x1f000000
  79
  80 /* Slot Available Register II field definition */
  81 #define SLOT_66MHZ              0x0000001f
  82 #define SLOT_66MHZ_PCIX_266     0x00000f00
  83 #define SLOT_100MHZ_PCIX_266    0x0000f000
  84 #define SLOT_133MHZ_PCIX_266    0x000f0000
  85 #define SLOT_66MHZ_PCIX_533     0x00f00000
  86 #define SLOT_100MHZ_PCIX_533    0x0f000000
  87 #define SLOT_133MHZ_PCIX_533    0xf0000000
  88
  89
  90 /* Secondary Bus Configuration Register */
  91 /* For PI = 1, Bits 0 to 2 have been encoded as follows to show current bus speed/mode */
  92 #define PCI_33MHZ               0x0
  93 #define PCI_66MHZ               0x1
  94 #define PCIX_66MHZ              0x2
  95 #define PCIX_100MHZ             0x3
  96 #define PCIX_133MHZ             0x4
  97
  98 /* For PI = 2, Bits 0 to 3 have been encoded as follows to show current bus speed/mode */
  99 #define PCI_33MHZ               0x0
 100 #define PCI_66MHZ               0x1
 101 #define PCIX_66MHZ              0x2
 102 #define PCIX_100MHZ             0x3
 103 #define PCIX_133MHZ             0x4
 104 #define PCIX_66MHZ_ECC          0x5
 105 #define PCIX_100MHZ_ECC         0x6
 106 #define PCIX_133MHZ_ECC         0x7
 107 #define PCIX_66MHZ_266          0x9
 108 #define PCIX_100MHZ_266         0xa
 109 #define PCIX_133MHZ_266         0xb
 110 #define PCIX_66MHZ_533          0x11
 111 #define PCIX_100MHZ_533         0x12
 112 #define PCIX_133MHZ_533         0x13
 113
 114 /* Slot Configuration */
 115 #define SLOT_NUM                0x0000001F
 116 #define FIRST_DEV_NUM           0x00001F00
 117 #define PSN                     0x07FF0000
 118 #define UPDOWN                  0x20000000
 119 #define MRLSENSOR               0x40000000
 120 #define ATTN_BUTTON             0x80000000
 121
 122 /* Slot Status Field Definitions */
 123 /* Slot State */
 124 #define PWR_ONLY                0x0001
 125 #define ENABLED                 0x0002
 126 #define DISABLED                0x0003
 127
 128 /* Power Indicator State */
 129 #define PWR_LED_ON              0x0004
 130 #define PWR_LED_BLINK           0x0008
 131 #define PWR_LED_OFF             0x000c
 132
 133 /* Attention Indicator State */
 134 #define ATTEN_LED_ON            0x0010
 135 #define ATTEN_LED_BLINK         0x0020
 136 #define ATTEN_LED_OFF           0x0030
 137
 138 /* Power Fault */
 139 #define pwr_fault               0x0040
 140
 141 /* Attention Button */
 142 #define ATTEN_BUTTON            0x0080
 143
 144 /* MRL Sensor */
 145 #define MRL_SENSOR              0x0100
 146
 147 /* 66 MHz Capable */
 148 #define IS_66MHZ_CAP            0x0200
 149
 150 /* PRSNT1#/PRSNT2# */
 151 #define SLOT_EMP                0x0c00
 152
 153 /* PCI-X Capability */
 154 #define NON_PCIX                0x0000
 155 #define PCIX_66                 0x1000
 156 #define PCIX_133                0x3000
 157 #define PCIX_266                0x4000  /* For PI = 2 only */
 158 #define PCIX_533                0x5000  /* For PI = 2 only */
 159
 160 /* SHPC 'write' operations/commands */
 161
 162 /* Slot operation - 0x00h to 0x3Fh */
 163
 164 #define NO_CHANGE               0x00
 165
 166 /* Slot state - Bits 0 & 1 of controller command register */
 167 #define SET_SLOT_PWR            0x01
 168 #define SET_SLOT_ENABLE         0x02
 169 #define SET_SLOT_DISABLE        0x03
 170
 171 /* Power indicator state - Bits 2 & 3 of controller command register*/
 172 #define SET_PWR_ON              0x04
 173 #define SET_PWR_BLINK           0x08
 174 #define SET_PWR_OFF             0x0C
 175
 176 /* Attention indicator state - Bits 4 & 5 of controller command register*/
 177 #define SET_ATTN_ON             0x010
 178 #define SET_ATTN_BLINK          0x020
 179 #define SET_ATTN_OFF            0x030
 180
 181 /* Set bus speed/mode A - 0x40h to 0x47h */
 182 #define SETA_PCI_33MHZ          0x40
 183 #define SETA_PCI_66MHZ          0x41
 184 #define SETA_PCIX_66MHZ         0x42
 185 #define SETA_PCIX_100MHZ        0x43
 186 #define SETA_PCIX_133MHZ        0x44
 187 #define RESERV_1                0x45
 188 #define RESERV_2                0x46
 189 #define RESERV_3                0x47
 190
 191 /* Set bus speed/mode B - 0x50h to 0x5fh */
 192 #define SETB_PCI_33MHZ          0x50
 193 #define SETB_PCI_66MHZ          0x51
 194 #define SETB_PCIX_66MHZ_PM      0x52
 195 #define SETB_PCIX_100MHZ_PM     0x53
 196 #define SETB_PCIX_133MHZ_PM     0x54
 197 #define SETB_PCIX_66MHZ_EM      0x55
 198 #define SETB_PCIX_100MHZ_EM     0x56
 199 #define SETB_PCIX_133MHZ_EM     0x57
 200 #define SETB_PCIX_66MHZ_266     0x58
 201 #define SETB_PCIX_100MHZ_266    0x59
 202 #define SETB_PCIX_133MHZ_266    0x5a
 203 #define SETB_PCIX_66MHZ_533     0x5b
 204 #define SETB_PCIX_100MHZ_533    0x5c
 205 #define SETB_PCIX_133MHZ_533    0x5d
 206
 207
 208 /* Power-on all slots - 0x48h */
 209 #define SET_PWR_ON_ALL          0x48
 210
 211 /* Enable all slots     - 0x49h */
 212 #define SET_ENABLE_ALL          0x49
 213
 214 /*  SHPC controller command error code */
 215 #define SWITCH_OPEN             0x1
 216 #define INVALID_CMD             0x2
 217 #define INVALID_SPEED_MODE      0x4
 218
 219 /* For accessing SHPC Working Register Set */
 220 #define DWORD_SELECT            0x2
 221 #define DWORD_DATA              0x4
 222 #define BASE_OFFSET             0x0
 223
 224 /* Field Offset in Logical Slot Register - byte boundary */
 225 #define SLOT_EVENT_LATCH        0x2
 226 #define SLOT_SERR_INT_MASK      0x3
 227
 228 static spinlock_t hpc_event_lock;
 229
 230 DEFINE_DBG_BUFFER               /* Debug string buffer for entire HPC defined here */
 231 static struct php_ctlr_state_s *php_ctlr_list_head = 0; /* HPC state linked list */
 232 static int ctlr_seq_num = 0;    /* Controller sequenc # */
 233 static spinlock_t list_lock;
 234
 235 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
 236
 237 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
 238
 239 /* This is the interrupt polling timeout function. */
 240 static void int_poll_timeout(unsigned long lphp_ctlr)
 241 {
 242     struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
 243
 244     DBG_ENTER_ROUTINE
 245
 246     if ( !php_ctlr ) {
 247                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 248                 return;
 249     }
 250
 251     /* Poll for interrupt events.  regs == NULL => polling */
 252     shpc_isr( 0, (void *)php_ctlr, NULL );
 253
 254     init_timer(&php_ctlr->int_poll_timer);
 255         if (!shpchp_poll_time)
 256                 shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
 257
 258     start_int_poll_timer(php_ctlr, shpchp_poll_time);
 259
 260         return;
 261 }
 262
 263 /* This function starts the interrupt polling timer. */
 264 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
 265 {
 266     if (!php_ctlr) {
 267                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 268                 return;
 269         }
 270
 271     if ( ( seconds <= 0 ) || ( seconds > 60 ) )
 272         seconds = 2;            /* Clamp to sane value */
 273
 274     php_ctlr->int_poll_timer.function = &int_poll_timeout;
 275     php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr;    /* Instance data */
 276     php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
 277     add_timer(&php_ctlr->int_poll_timer);
 278
 279         return;
 280 }
 281
 282 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
 283 {
 284         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 285         u16 cmd_status;
 286         int retval = 0;
 287         u16 temp_word;
 288         int i;
 289
 290         DBG_ENTER_ROUTINE
 291
 292         if (!php_ctlr) {
 293                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 294                 return -1;
 295         }
 296
 297         for (i = 0; i < 10; i++) {
 298                 cmd_status = readw(php_ctlr->creg + CMD_STATUS);
 299
 300                 if (!(cmd_status & 0x1))
 301                         break;
 302                 /*  Check every 0.1 sec for a total of 1 sec*/
 303                 set_current_state(TASK_INTERRUPTIBLE);
 304                 schedule_timeout(HZ/10);
 305         }
 306
 307         cmd_status = readw(php_ctlr->creg + CMD_STATUS);
 308
 309         if (cmd_status & 0x1) {
 310                 /* After 1 sec and and the controller is still busy */
 311                 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
 312                 return -1;
 313         }
 314
 315         ++t_slot;
 316         temp_word =  (t_slot << 8) | (cmd & 0xFF);
 317         dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
 318
 319         /* To make sure the Controller Busy bit is 0 before we send out the
 320          * command.
 321          */
 322         writew(temp_word, php_ctlr->creg + CMD);
 323         dbg("%s: temp_word written %x\n", __FUNCTION__, temp_word);
 324
 325         DBG_LEAVE_ROUTINE
 326         return retval;
 327 }
 328
 329 static int hpc_check_cmd_status(struct controller *ctrl)
 330 {
 331         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
 332         u16 cmd_status;
 333         int retval = 0;
 334
 335         DBG_ENTER_ROUTINE
 336
 337         if (!ctrl->hpc_ctlr_handle) {
 338                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 339                 return -1;
 340         }
 341
 342         cmd_status = readw(php_ctlr->creg + CMD_STATUS) & 0x000F;
 343
 344         switch (cmd_status >> 1) {
 345         case 0:
 346                 retval = 0;
 347                 break;
 348         case 1:
 349                 retval = SWITCH_OPEN;
 350                 err("%s: Switch opened!\n", __FUNCTION__);
 351                 break;
 352         case 2:
 353                 retval = INVALID_CMD;
 354                 err("%s: Invalid HPC command!\n", __FUNCTION__);
 355                 break;
 356         case 4:
 357                 retval = INVALID_SPEED_MODE;
 358                 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
 359                 break;
 360         default:
 361                 retval = cmd_status;
 362         }
 363
 364         DBG_LEAVE_ROUTINE
 365         return retval;
 366 }
 367
 368
 369 static int hpc_get_attention_status(struct slot *slot, u8 *status)
 370 {
 371         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 372         u32 slot_reg;
 373         u16 slot_status;
 374         u8 atten_led_state;
 375
 376         DBG_ENTER_ROUTINE
 377
 378         if (!slot->ctrl->hpc_ctlr_handle) {
 379                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 380                 return -1;
 381         }
 382
 383         slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
 384         slot_status = (u16) slot_reg;
 385         atten_led_state = (slot_status & 0x0030) >> 4;
 386
 387         switch (atten_led_state) {
 388         case 0:
 389                 *status = 0xFF; /* Reserved */
 390                 break;
 391         case 1:
 392                 *status = 1;    /* On */
 393                 break;
 394         case 2:
 395                 *status = 2;    /* Blink */
 396                 break;
 397         case 3:
 398                 *status = 0;    /* Off */
 399                 break;
 400         default:
 401                 *status = 0xFF;
 402                 break;
 403         }
 404
 405         DBG_LEAVE_ROUTINE
 406         return 0;
 407 }
 408
 409 static int hpc_get_power_status(struct slot * slot, u8 *status)
 410 {
 411         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 412         u32 slot_reg;
 413         u16 slot_status;
 414         u8 slot_state;
 415         int     retval = 0;
 416
 417         DBG_ENTER_ROUTINE
 418
 419         if (!slot->ctrl->hpc_ctlr_handle) {
 420                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 421                 return -1;
 422         }
 423
 424         slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
 425         slot_status = (u16) slot_reg;
 426         slot_state = (slot_status & 0x0003);
 427
 428         switch (slot_state) {
 429         case 0:
 430                 *status = 0xFF;
 431                 break;
 432         case 1:
 433                 *status = 2;    /* Powered only */
 434                 break;
 435         case 2:
 436                 *status = 1;    /* Enabled */
 437                 break;
 438         case 3:
 439                 *status = 0;    /* Disabled */
 440                 break;
 441         default:
 442                 *status = 0xFF;
 443                 break;
 444         }
 445
 446         DBG_LEAVE_ROUTINE
 447         return retval;
 448 }
 449
 450
 451 static int hpc_get_latch_status(struct slot *slot, u8 *status)
 452 {
 453         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 454         u32 slot_reg;
 455         u16 slot_status;
 456
 457         DBG_ENTER_ROUTINE
 458
 459         if (!slot->ctrl->hpc_ctlr_handle) {
 460                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 461                 return -1;
 462         }
 463
 464         slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
 465         slot_status = (u16)slot_reg;
 466
 467         *status = ((slot_status & 0x0100) == 0) ? 0 : 1;   /* 0 -> close; 1 -> open */
 468
 469
 470         DBG_LEAVE_ROUTINE
 471         return 0;
 472 }
 473
 474 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
 475 {
 476         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 477         u32 slot_reg;
 478         u16 slot_status;
 479         u8 card_state;
 480
 481         DBG_ENTER_ROUTINE
 482
 483         if (!slot->ctrl->hpc_ctlr_handle) {
 484                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 485                 return -1;
 486         }
 487
 488         slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
 489         slot_status = (u16)slot_reg;
 490         card_state = (u8)((slot_status & 0x0C00) >> 10);
 491         *status = (card_state != 0x3) ? 1 : 0;
 492
 493         DBG_LEAVE_ROUTINE
 494         return 0;
 495 }
 496
 497 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
 498 {
 499         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 500
 501         DBG_ENTER_ROUTINE
 502
 503         if (!slot->ctrl->hpc_ctlr_handle) {
 504                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 505                 return -1;
 506         }
 507
 508         *prog_int = readb(php_ctlr->creg + PROG_INTERFACE);
 509
 510         DBG_LEAVE_ROUTINE
 511         return 0;
 512 }
 513
 514 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
 515 {
 516         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 517         u32 slot_reg;
 518         u16 slot_status, sec_bus_status;
 519         u8 m66_cap, pcix_cap, pi;
 520         int retval = 0;
 521
 522         DBG_ENTER_ROUTINE
 523
 524         if (!slot->ctrl->hpc_ctlr_handle) {
 525                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 526                 return -1;
 527         }
 528
 529         if (slot->hp_slot >= php_ctlr->num_slots) {
 530                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
 531                 return -1;
 532         }
 533
 534         pi = readb(php_ctlr->creg + PROG_INTERFACE);
 535         slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
 536         dbg("%s: pi = %d, slot_reg = %x\n", __FUNCTION__, pi, slot_reg);
 537         slot_status = (u16) slot_reg;
 538         dbg("%s: slot_status = %x\n", __FUNCTION__, slot_status);
 539         sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
 540
 541         pcix_cap = (u8) ((slot_status & 0x3000) >> 12);
 542         dbg("%s:  pcix_cap = %x\n", __FUNCTION__, pcix_cap);
 543         m66_cap = (u8) ((slot_status & 0x0200) >> 9);
 544         dbg("%s:  m66_cap = %x\n", __FUNCTION__, m66_cap);
 545
 546
 547         if (pi == 2) {
 548                 switch (pcix_cap) {
 549                 case 0:
 550                         *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
 551                         break;
 552                 case 1:
 553                         *value = PCI_SPEED_66MHz_PCIX;
 554                         break;
 555                 case 3:
 556                         *value = PCI_SPEED_133MHz_PCIX;
 557                         break;
 558                 case 4:
 559                         *value = PCI_SPEED_133MHz_PCIX_266;
 560                         break;
 561                 case 5:
 562                         *value = PCI_SPEED_133MHz_PCIX_533;
 563                         break;
 564                 case 2: /* Reserved */
 565                 default:
 566                         *value = PCI_SPEED_UNKNOWN;
 567                         retval = -ENODEV;
 568                         break;
 569                 }
 570         } else {
 571                 switch (pcix_cap) {
 572                 case 0:
 573                         *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
 574                         break;
 575                 case 1:
 576                         *value = PCI_SPEED_66MHz_PCIX;
 577                         break;
 578                 case 3:
 579                         *value = PCI_SPEED_133MHz_PCIX;
 580                         break;
 581                 case 2: /* Reserved */
 582                 default:
 583                         *value = PCI_SPEED_UNKNOWN;
 584                         retval = -ENODEV;
 585                         break;
 586                 }
 587         }
 588
 589         dbg("Adapter speed = %d\n", *value);
 590
 591         DBG_LEAVE_ROUTINE
 592         return retval;
 593 }
 594
 595 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
 596 {
 597         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 598         u16 sec_bus_status;
 599         u8 pi;
 600         int retval = 0;
 601
 602         DBG_ENTER_ROUTINE
 603
 604         if (!slot->ctrl->hpc_ctlr_handle) {
 605                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 606                 return -1;
 607         }
 608
 609         pi = readb(php_ctlr->creg + PROG_INTERFACE);
 610         sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
 611
 612         if (pi == 2) {
 613                 *mode = (sec_bus_status & 0x0100) >> 7;
 614         } else {
 615                 retval = -1;
 616         }
 617
 618         dbg("Mode 1 ECC cap = %d\n", *mode);
 619
 620         DBG_LEAVE_ROUTINE
 621         return retval;
 622 }
 623
 624 static int hpc_query_power_fault(struct slot * slot)
 625 {
 626         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 627         u32 slot_reg;
 628         u16 slot_status;
 629         u8 pwr_fault_state, status;
 630
 631         DBG_ENTER_ROUTINE
 632
 633         if (!slot->ctrl->hpc_ctlr_handle) {
 634                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 635                 return -1;
 636         }
 637
 638         slot_reg = readl(php_ctlr->creg + SLOT1 + 4*(slot->hp_slot));
 639         slot_status = (u16) slot_reg;
 640         pwr_fault_state = (slot_status & 0x0040) >> 7;
 641         status = (pwr_fault_state == 1) ? 0 : 1;
 642
 643         DBG_LEAVE_ROUTINE
 644         /* Note: Logic 0 => fault */
 645         return status;
 646 }
 647
 648 static int hpc_set_attention_status(struct slot *slot, u8 value)
 649 {
 650         struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 651         u8 slot_cmd = 0;
 652         int rc = 0;
 653
 654         if (!slot->ctrl->hpc_ctlr_handle) {
 655                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 656                 return -1;
 657         }
 658
 659         if (slot->hp_slot >= php_ctlr->num_slots) {
 660                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
 661                 return -1;
 662         }
 663
 664         switch (value) {
 665                 case 0 :
 666                         slot_cmd = 0x30;        /* OFF */
 667                         break;
 668                 case 1:
 669                         slot_cmd = 0x10;        /* ON */
 670                         break;
 671                 case 2:
 672                         slot_cmd = 0x20;        /* BLINK */
 673                         break;
 674                 default:
 675                         return -1;
 676         }
 677
 678         shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
 679
 680         return rc;
 681 }
 682
 683
 684 static void hpc_set_green_led_on(struct slot *slot)
 685 {
 686         struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 687         u8 slot_cmd;
 688
 689         if (!slot->ctrl->hpc_ctlr_handle) {
 690                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 691                 return ;
 692         }
 693
 694         if (slot->hp_slot >= php_ctlr->num_slots) {
 695                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
 696                 return ;
 697         }
 698
 699         slot_cmd = 0x04;
 700
 701         shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
 702
 703         return;
 704 }
 705
 706 static void hpc_set_green_led_off(struct slot *slot)
 707 {
 708         struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 709         u8 slot_cmd;
 710
 711         if (!slot->ctrl->hpc_ctlr_handle) {
 712                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 713                 return ;
 714         }
 715
 716         if (slot->hp_slot >= php_ctlr->num_slots) {
 717                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
 718                 return ;
 719         }
 720
 721         slot_cmd = 0x0C;
 722
 723         shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
 724
 725         return;
 726 }
 727
 728 static void hpc_set_green_led_blink(struct slot *slot)
 729 {
 730         struct php_ctlr_state_s *php_ctlr =(struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 731         u8 slot_cmd;
 732
 733         if (!slot->ctrl->hpc_ctlr_handle) {
 734                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 735                 return ;
 736         }
 737
 738         if (slot->hp_slot >= php_ctlr->num_slots) {
 739                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
 740                 return ;
 741         }
 742
 743         slot_cmd = 0x08;
 744
 745         shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
 746
 747         return;
 748 }
 749
 750 int shpc_get_ctlr_slot_config(struct controller *ctrl,
 751         int *num_ctlr_slots,    /* number of slots in this HPC                  */
 752         int *first_device_num,  /* PCI dev num of the first slot in this SHPC   */
 753         int *physical_slot_num, /* phy slot num of the first slot in this SHPC  */
 754         int *updown,            /* physical_slot_num increament: 1 or -1        */
 755         int *flags)
 756 {
 757         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
 758
 759         DBG_ENTER_ROUTINE
 760
 761         if (!ctrl->hpc_ctlr_handle) {
 762                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 763                 return -1;
 764         }
 765
 766         *first_device_num = php_ctlr->slot_device_offset;       /* Obtained in shpc_init() */
 767         *num_ctlr_slots = php_ctlr->num_slots;                  /* Obtained in shpc_init() */
 768
 769         *physical_slot_num = (readl(php_ctlr->creg + SLOT_CONFIG) & PSN) >> 16;
 770         dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
 771         *updown = ((readl(php_ctlr->creg + SLOT_CONFIG) & UPDOWN ) >> 29) ? 1 : -1;
 772
 773         DBG_LEAVE_ROUTINE
 774         return 0;
 775 }
 776
 777 static void hpc_release_ctlr(struct controller *ctrl)
 778 {
 779         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) ctrl->hpc_ctlr_handle;
 780         struct php_ctlr_state_s *p, *p_prev;
 781
 782         DBG_ENTER_ROUTINE
 783
 784         if (!ctrl->hpc_ctlr_handle) {
 785                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 786                 return ;
 787         }
 788
 789         if (shpchp_poll_mode) {
 790             del_timer(&php_ctlr->int_poll_timer);
 791         } else {
 792                 if (php_ctlr->irq) {
 793                         free_irq(php_ctlr->irq, ctrl);
 794                         php_ctlr->irq = 0;
 795                 }
 796         }
 797         if (php_ctlr->pci_dev) {
 798                 dbg("%s: before calling iounmap & release_mem_region\n", __FUNCTION__);
 799                 iounmap(php_ctlr->creg);
 800                 release_mem_region(pci_resource_start(php_ctlr->pci_dev, 0), pci_resource_len(php_ctlr->pci_dev, 0));
 801                 dbg("%s: before calling iounmap & release_mem_region\n", __FUNCTION__);
 802                 php_ctlr->pci_dev = 0;
 803         }
 804
 805         spin_lock(&list_lock);
 806         p = php_ctlr_list_head;
 807         p_prev = NULL;
 808         while (p) {
 809                 if (p == php_ctlr) {
 810                         if (p_prev)
 811                                 p_prev->pnext = p->pnext;
 812                         else
 813                                 php_ctlr_list_head = p->pnext;
 814                         break;
 815                 } else {
 816                         p_prev = p;
 817                         p = p->pnext;
 818                 }
 819         }
 820         spin_unlock(&list_lock);
 821
 822         kfree(php_ctlr);
 823
 824 DBG_LEAVE_ROUTINE
 825
 826 }
 827
 828 static int hpc_power_on_slot(struct slot * slot)
 829 {
 830         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 831         u8 slot_cmd;
 832         int retval = 0;
 833
 834         DBG_ENTER_ROUTINE
 835
 836         if (!slot->ctrl->hpc_ctlr_handle) {
 837                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 838                 return -1;
 839         }
 840
 841         if (slot->hp_slot >= php_ctlr->num_slots) {
 842                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
 843                 return -1;
 844         }
 845         slot_cmd = 0x01;
 846
 847         retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
 848
 849         if (retval) {
 850                 err("%s: Write command failed!\n", __FUNCTION__);
 851                 return -1;
 852         }
 853
 854         DBG_LEAVE_ROUTINE
 855
 856         return retval;
 857 }
 858
 859 static int hpc_slot_enable(struct slot * slot)
 860 {
 861         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 862         u8 slot_cmd;
 863         int retval = 0;
 864
 865         DBG_ENTER_ROUTINE
 866
 867         if (!slot->ctrl->hpc_ctlr_handle) {
 868                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 869                 return -1;
 870         }
 871
 872         if (slot->hp_slot >= php_ctlr->num_slots) {
 873                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
 874                 return -1;
 875         }
 876         /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
 877         slot_cmd = 0x3A;
 878
 879         retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
 880
 881         if (retval) {
 882                 err("%s: Write command failed!\n", __FUNCTION__);
 883                 return -1;
 884         }
 885
 886         DBG_LEAVE_ROUTINE
 887         return retval;
 888 }
 889
 890 static int hpc_slot_disable(struct slot * slot)
 891 {
 892         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 893         u8 slot_cmd;
 894         int retval = 0;
 895
 896         DBG_ENTER_ROUTINE
 897
 898         if (!slot->ctrl->hpc_ctlr_handle) {
 899                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 900                 return -1;
 901         }
 902
 903         if (slot->hp_slot >= php_ctlr->num_slots) {
 904                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
 905                 return -1;
 906         }
 907
 908         /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
 909         slot_cmd = 0x1F;
 910
 911         retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
 912
 913         if (retval) {
 914                 err("%s: Write command failed!\n", __FUNCTION__);
 915                 return -1;
 916         }
 917
 918         DBG_LEAVE_ROUTINE
 919         return retval;
 920 }
 921
 922 static int hpc_enable_all_slots( struct slot *slot )
 923 {
 924         int retval = 0;
 925
 926         DBG_ENTER_ROUTINE
 927
 928         if (!slot->ctrl->hpc_ctlr_handle) {
 929                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 930                 return -1;
 931         }
 932
 933         retval = shpc_write_cmd(slot, 0, SET_ENABLE_ALL);
 934         if (retval) {
 935                 err("%s: Write command failed!\n", __FUNCTION__);
 936                 return -1;
 937         }
 938
 939         DBG_LEAVE_ROUTINE
 940
 941         return retval;
 942 }
 943
 944 static int hpc_pwr_on_all_slots(struct slot *slot)
 945 {
 946         int retval = 0;
 947
 948         DBG_ENTER_ROUTINE
 949
 950         retval = shpc_write_cmd(slot, 0, SET_PWR_ON_ALL);
 951
 952         if (retval) {
 953                 err("%s: Write command failed!\n", __FUNCTION__);
 954                 return -1;
 955         }
 956
 957         DBG_LEAVE_ROUTINE
 958         return retval;
 959 }
 960
 961 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
 962 {
 963         u8 slot_cmd;
 964         u8 pi;
 965         int retval = 0;
 966         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
 967
 968         DBG_ENTER_ROUTINE
 969
 970         if (!slot->ctrl->hpc_ctlr_handle) {
 971                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
 972                 return -1;
 973         }
 974
 975         pi = readb(php_ctlr->creg + PROG_INTERFACE);
 976
 977         if (pi == 1) {
 978                 switch (value) {
 979                 case 0:
 980                         slot_cmd = SETA_PCI_33MHZ;
 981                         break;
 982                 case 1:
 983                         slot_cmd = SETA_PCI_66MHZ;
 984                         break;
 985                 case 2:
 986                         slot_cmd = SETA_PCIX_66MHZ;
 987                         break;
 988                 case 3:
 989                         slot_cmd = SETA_PCIX_100MHZ;
 990                         break;
 991                 case 4:
 992                         slot_cmd = SETA_PCIX_133MHZ;
 993                         break;
 994                 default:
 995                         slot_cmd = PCI_SPEED_UNKNOWN;
 996                         retval = -ENODEV;
 997                         return retval;
 998                 }
 999         } else {
1000                 switch (value) {
1001                 case 0:
1002                         slot_cmd = SETB_PCI_33MHZ;
1003                         break;
1004                 case 1:
1005                         slot_cmd = SETB_PCI_66MHZ;
1006                         break;
1007                 case 2:
1008                         slot_cmd = SETB_PCIX_66MHZ_PM;
1009                         break;
1010                 case 3:
1011                         slot_cmd = SETB_PCIX_100MHZ_PM;
1012                         break;
1013                 case 4:
1014                         slot_cmd = SETB_PCIX_133MHZ_PM;
1015                         break;
1016                 case 5:
1017                         slot_cmd = SETB_PCIX_66MHZ_EM;
1018                         break;
1019                 case 6:
1020                         slot_cmd = SETB_PCIX_100MHZ_EM;
1021                         break;
1022                 case 7:
1023                         slot_cmd = SETB_PCIX_133MHZ_EM;
1024                         break;
1025                 case 8:
1026                         slot_cmd = SETB_PCIX_66MHZ_266;
1027                         break;
1028                 case 0x9:
1029                         slot_cmd = SETB_PCIX_100MHZ_266;
1030                         break;
1031                 case 0xa:
1032                         slot_cmd = SETB_PCIX_133MHZ_266;
1033                         break;
1034                 case 0xb:
1035                         slot_cmd = SETB_PCIX_66MHZ_533;
1036                         break;
1037                 case 0xc:
1038                         slot_cmd = SETB_PCIX_100MHZ_533;
1039                         break;
1040                 case 0xd:
1041                         slot_cmd = SETB_PCIX_133MHZ_533;
1042                         break;
1043                 default:
1044                         slot_cmd = PCI_SPEED_UNKNOWN;
1045                         retval = -ENODEV;
1046                         return retval;
1047                 }
1048
1049         }
1050         retval = shpc_write_cmd(slot, 0, slot_cmd);
1051         if (retval) {
1052                 err("%s: Write command failed!\n", __FUNCTION__);
1053                 return -1;
1054         }
1055
1056         DBG_LEAVE_ROUTINE
1057         return retval;
1058 }
1059
1060 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1061 {
1062         struct controller *ctrl = NULL;
1063         struct php_ctlr_state_s *php_ctlr;
1064         u8 schedule_flag = 0;
1065         u8 temp_byte;
1066         u32 temp_dword, intr_loc, intr_loc2;
1067         int hp_slot;
1068
1069         if (!dev_id)
1070                 return IRQ_NONE;
1071
1072         if (!shpchp_poll_mode) {
1073                 ctrl = (struct controller *)dev_id;
1074                 php_ctlr = ctrl->hpc_ctlr_handle;
1075         } else {
1076                 php_ctlr = (struct php_ctlr_state_s *) dev_id;
1077                 ctrl = (struct controller *)php_ctlr->callback_instance_id;
1078         }
1079
1080         if (!ctrl)
1081                 return IRQ_NONE;
1082
1083         if (!php_ctlr || !php_ctlr->creg)
1084                 return IRQ_NONE;
1085
1086         /* Check to see if it was our interrupt */
1087         intr_loc = readl(php_ctlr->creg + INTR_LOC);
1088
1089         if (!intr_loc)
1090                 return IRQ_NONE;
1091         dbg("%s: shpc_isr proceeds\n", __FUNCTION__);
1092         dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
1093
1094         if(!shpchp_poll_mode) {
1095                 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
1096                 /* of SHPC spec rev 1.0*/
1097                 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1098                 dbg("%s: Before masking global interrupt, temp_dword = %x\n",
1099                         __FUNCTION__, temp_dword);
1100                 temp_dword |= 0x00000001;
1101                 dbg("%s: After masking global interrupt, temp_dword = %x\n",
1102                         __FUNCTION__, temp_dword);
1103                 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1104
1105                 intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
1106                 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1107         }
1108
1109         if (intr_loc & 0x0001) {
1110                 /*
1111                  * Command Complete Interrupt Pending
1112                  * RO only - clear by writing 0 to the Command Completion
1113                  * Detect bit in Controller SERR-INT register
1114                  */
1115                 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1116                 dbg("%s: Before clearing CCIP, temp_dword = %x\n",
1117                         __FUNCTION__, temp_dword);
1118                 temp_dword &= 0xfffeffff;
1119                 dbg("%s: After clearing CCIP, temp_dword = %x\n",
1120                         __FUNCTION__, temp_dword);
1121                 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1122                 wake_up_interruptible(&ctrl->queue);
1123         }
1124
1125         if ((intr_loc = (intr_loc >> 1)) == 0) {
1126                 /* Unmask Global Interrupt Mask */
1127                 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1128                 dbg("%s: 1-Before unmasking global interrupt, temp_dword = %x\n",
1129                         __FUNCTION__, temp_dword);
1130                 temp_dword &= 0xfffffffe;
1131                 dbg("%s: 1-After unmasking global interrupt, temp_dword = %x\n",
1132                         __FUNCTION__, temp_dword);
1133                 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1134
1135                 return IRQ_NONE;
1136         }
1137
1138         for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1139         /* To find out which slot has interrupt pending */
1140                 if ((intr_loc >> hp_slot) & 0x01) {
1141                         temp_dword = readl(php_ctlr->creg + SLOT1 + (4*hp_slot));
1142                         dbg("%s: Slot %x with intr, temp_dword = %x\n",
1143                                 __FUNCTION__, hp_slot, temp_dword);
1144                         temp_byte = (temp_dword >> 16) & 0xFF;
1145                         dbg("%s: Slot with intr, temp_byte = %x\n",
1146                                 __FUNCTION__, temp_byte);
1147                         if ((php_ctlr->switch_change_callback) && (temp_byte & 0x08))
1148                                 schedule_flag += php_ctlr->switch_change_callback(
1149                                         hp_slot, php_ctlr->callback_instance_id);
1150                         if ((php_ctlr->attention_button_callback) && (temp_byte & 0x04))
1151                                 schedule_flag += php_ctlr->attention_button_callback(
1152                                         hp_slot, php_ctlr->callback_instance_id);
1153                         if ((php_ctlr->presence_change_callback) && (temp_byte & 0x01))
1154                                 schedule_flag += php_ctlr->presence_change_callback(
1155                                         hp_slot , php_ctlr->callback_instance_id);
1156                         if ((php_ctlr->power_fault_callback) && (temp_byte & 0x12))
1157                                 schedule_flag += php_ctlr->power_fault_callback(
1158                                         hp_slot, php_ctlr->callback_instance_id);
1159
1160                         /* Clear all slot events */
1161                         temp_dword = 0xe01fffff;
1162                         dbg("%s: Clearing slot events, temp_dword = %x\n",
1163                                 __FUNCTION__, temp_dword);
1164                         writel(temp_dword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1165
1166                         intr_loc2 = readl(php_ctlr->creg + INTR_LOC);
1167                         dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1168                 }
1169         }
1170         if (!shpchp_poll_mode) {
1171                 /* Unmask Global Interrupt Mask */
1172                 temp_dword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1173                 dbg("%s: 2-Before unmasking global interrupt, temp_dword = %x\n",
1174                         __FUNCTION__, temp_dword);
1175                 temp_dword &= 0xfffffffe;
1176                 dbg("%s: 2-After unmasking global interrupt, temp_dword = %x\n",
1177                         __FUNCTION__, temp_dword);
1178                 writel(temp_dword, php_ctlr->creg + SERR_INTR_ENABLE);
1179         }
1180
1181         return IRQ_HANDLED;
1182 }
1183
1184 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1185 {
1186         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1187         enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1188         int retval = 0;
1189         u8 pi;
1190         u32 slot_avail1, slot_avail2;
1191         int slot_num;
1192
1193         DBG_ENTER_ROUTINE
1194
1195         if (!slot->ctrl->hpc_ctlr_handle) {
1196                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1197                 return -1;
1198         }
1199
1200         if (slot->hp_slot >= php_ctlr->num_slots) {
1201                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1202                 return -1;
1203         }
1204
1205         pi = readb(php_ctlr->creg + PROG_INTERFACE);
1206         slot_avail1 = readl(php_ctlr->creg + SLOT_AVAIL1);
1207         slot_avail2 = readl(php_ctlr->creg + SLOT_AVAIL2);
1208
1209         if (pi == 2) {
1210                 if ((slot_num = ((slot_avail2 & SLOT_133MHZ_PCIX_533) >> 27)  ) != 0 )
1211                         bus_speed = PCIX_133MHZ_533;
1212                 else if ((slot_num = ((slot_avail2 & SLOT_100MHZ_PCIX_533) >> 23)  ) != 0 )
1213                         bus_speed = PCIX_100MHZ_533;
1214                 else if ((slot_num = ((slot_avail2 & SLOT_66MHZ_PCIX_533) >> 19)  ) != 0 )
1215                         bus_speed = PCIX_66MHZ_533;
1216                 else if ((slot_num = ((slot_avail2 & SLOT_133MHZ_PCIX_266) >> 15)  ) != 0 )
1217                         bus_speed = PCIX_133MHZ_266;
1218                 else if ((slot_num = ((slot_avail2 & SLOT_100MHZ_PCIX_266) >> 11)  ) != 0 )
1219                         bus_speed = PCIX_100MHZ_266;
1220                 else if ((slot_num = ((slot_avail2 & SLOT_66MHZ_PCIX_266) >> 7)  ) != 0 )
1221                         bus_speed = PCIX_66MHZ_266;
1222                 else if ((slot_num = ((slot_avail1 & SLOT_133MHZ_PCIX) >> 23)  ) != 0 )
1223                         bus_speed = PCIX_133MHZ;
1224                 else if ((slot_num = ((slot_avail1 & SLOT_100MHZ_PCIX) >> 15)  ) != 0 )
1225                         bus_speed = PCIX_100MHZ;
1226                 else if ((slot_num = ((slot_avail1 & SLOT_66MHZ_PCIX) >> 7)  ) != 0 )
1227                         bus_speed = PCIX_66MHZ;
1228                 else if ((slot_num = (slot_avail2 & SLOT_66MHZ)) != 0 )
1229                         bus_speed = PCI_66MHZ;
1230                 else if ((slot_num = (slot_avail1 & SLOT_33MHZ)) != 0 )
1231                         bus_speed = PCI_33MHZ;
1232                 else bus_speed = PCI_SPEED_UNKNOWN;
1233         } else {
1234                 if ((slot_num = ((slot_avail1 & SLOT_133MHZ_PCIX) >> 23)  ) != 0 )
1235                         bus_speed = PCIX_133MHZ;
1236                 else if ((slot_num = ((slot_avail1 & SLOT_100MHZ_PCIX) >> 15)  ) != 0 )
1237                         bus_speed = PCIX_100MHZ;
1238                 else if ((slot_num = ((slot_avail1 & SLOT_66MHZ_PCIX) >> 7)  ) != 0 )
1239                         bus_speed = PCIX_66MHZ;
1240                 else if ((slot_num = (slot_avail2 & SLOT_66MHZ)) != 0 )
1241                         bus_speed = PCI_66MHZ;
1242                 else if ((slot_num = (slot_avail1 & SLOT_33MHZ)) != 0 )
1243                         bus_speed = PCI_33MHZ;
1244                 else bus_speed = PCI_SPEED_UNKNOWN;
1245         }
1246
1247         *value = bus_speed;
1248         dbg("Max bus speed = %d\n", bus_speed);
1249         DBG_LEAVE_ROUTINE
1250         return retval;
1251 }
1252
1253 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1254 {
1255         struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *) slot->ctrl->hpc_ctlr_handle;
1256         enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1257         u16 sec_bus_status;
1258         int retval = 0;
1259         u8 pi;
1260
1261         DBG_ENTER_ROUTINE
1262
1263         if (!slot->ctrl->hpc_ctlr_handle) {
1264                 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
1265                 return -1;
1266         }
1267
1268         if (slot->hp_slot >= php_ctlr->num_slots) {
1269                 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
1270                 return -1;
1271         }
1272
1273         pi = readb(php_ctlr->creg + PROG_INTERFACE);
1274         sec_bus_status = readw(php_ctlr->creg + SEC_BUS_CONFIG);
1275
1276         if (pi == 2) {
1277                 switch (sec_bus_status & 0x000f) {
1278                 case 0:
1279                         bus_speed = PCI_SPEED_33MHz;
1280                         break;
1281                 case 1:
1282                         bus_speed = PCI_SPEED_66MHz;
1283                         break;
1284                 case 2:
1285                         bus_speed = PCI_SPEED_66MHz_PCIX;
1286                         break;
1287                 case 3:
1288                         bus_speed = PCI_SPEED_100MHz_PCIX;
1289                         break;
1290                 case 4:
1291                         bus_speed = PCI_SPEED_133MHz_PCIX;
1292                         break;
1293                 case 5:
1294                         bus_speed = PCI_SPEED_66MHz_PCIX_ECC;
1295                         break;
1296                 case 6:
1297                         bus_speed = PCI_SPEED_100MHz_PCIX_ECC;
1298                         break;
1299                 case 7:
1300                         bus_speed = PCI_SPEED_133MHz_PCIX_ECC;
1301                         break;
1302                 case 8:
1303                         bus_speed = PCI_SPEED_66MHz_PCIX_266;
1304                         break;
1305                 case 9:
1306                         bus_speed = PCI_SPEED_100MHz_PCIX_266;
1307                         break;
1308                 case 0xa:
1309                         bus_speed = PCI_SPEED_133MHz_PCIX_266;
1310                         break;
1311                 case 0xb:
1312                         bus_speed = PCI_SPEED_66MHz_PCIX_533;
1313                         break;
1314                 case 0xc:
1315                         bus_speed = PCI_SPEED_100MHz_PCIX_533;
1316                         break;
1317                 case 0xd:
1318                         bus_speed = PCI_SPEED_133MHz_PCIX_533;
1319                         break;
1320                 case 0xe:
1321                 case 0xf:
1322                 default:
1323                         bus_speed = PCI_SPEED_UNKNOWN;
1324                         break;
1325                 }
1326         } else {
1327                 /* In the case where pi is undefined, default it to 1 */
1328                 switch (sec_bus_status & 0x0007) {
1329                 case 0:
1330                         bus_speed = PCI_SPEED_33MHz;
1331                         break;
1332                 case 1:
1333                         bus_speed = PCI_SPEED_66MHz;
1334                         break;
1335                 case 2:
1336                         bus_speed = PCI_SPEED_66MHz_PCIX;
1337                         break;
1338                 case 3:
1339                         bus_speed = PCI_SPEED_100MHz_PCIX;
1340                         break;
1341                 case 4:
1342                         bus_speed = PCI_SPEED_133MHz_PCIX;
1343                         break;
1344                 case 5:
1345                         bus_speed = PCI_SPEED_UNKNOWN;          /*      Reserved */
1346                         break;
1347                 case 6:
1348                         bus_speed = PCI_SPEED_UNKNOWN;          /*      Reserved */
1349                         break;
1350                 case 7:
1351                         bus_speed = PCI_SPEED_UNKNOWN;          /*      Reserved */
1352                         break;
1353                 default:
1354                         bus_speed = PCI_SPEED_UNKNOWN;
1355                         break;
1356                 }
1357         }
1358
1359         *value = bus_speed;
1360         dbg("Current bus speed = %d\n", bus_speed);
1361         DBG_LEAVE_ROUTINE
1362         return retval;
1363 }
1364
1365 static struct hpc_ops shpchp_hpc_ops = {
1366         .power_on_slot                  = hpc_power_on_slot,
1367         .slot_enable                    = hpc_slot_enable,
1368         .slot_disable                   = hpc_slot_disable,
1369         .enable_all_slots               = hpc_enable_all_slots,
1370         .pwr_on_all_slots               = hpc_pwr_on_all_slots,
1371         .set_bus_speed_mode             = hpc_set_bus_speed_mode,
1372         .set_attention_status   = hpc_set_attention_status,
1373         .get_power_status               = hpc_get_power_status,
1374         .get_attention_status   = hpc_get_attention_status,
1375         .get_latch_status               = hpc_get_latch_status,
1376         .get_adapter_status             = hpc_get_adapter_status,
1377
1378         .get_max_bus_speed              = hpc_get_max_bus_speed,
1379         .get_cur_bus_speed              = hpc_get_cur_bus_speed,
1380         .get_adapter_speed              = hpc_get_adapter_speed,
1381         .get_mode1_ECC_cap              = hpc_get_mode1_ECC_cap,
1382         .get_prog_int                   = hpc_get_prog_int,
1383
1384         .query_power_fault              = hpc_query_power_fault,
1385         .green_led_on                   = hpc_set_green_led_on,
1386         .green_led_off                  = hpc_set_green_led_off,
1387         .green_led_blink                = hpc_set_green_led_blink,
1388
1389         .release_ctlr                   = hpc_release_ctlr,
1390         .check_cmd_status               = hpc_check_cmd_status,
1391 };
1392
1393 int shpc_init(struct controller * ctrl,
1394                 struct pci_dev * pdev,
1395                 php_intr_callback_t attention_button_callback,
1396                 php_intr_callback_t switch_change_callback,
1397                 php_intr_callback_t presence_change_callback,
1398                 php_intr_callback_t power_fault_callback)
1399 {
1400         struct php_ctlr_state_s *php_ctlr, *p;
1401         void *instance_id = ctrl;
1402         int rc;
1403         u8 hp_slot;
1404         static int first = 1;
1405         u32 shpc_cap_offset, shpc_base_offset;
1406         u32 tempdword, slot_reg;
1407         u16 vendor_id, device_id;
1408         u8 i;
1409
1410         DBG_ENTER_ROUTINE
1411
1412         spin_lock_init(&list_lock);
1413         php_ctlr = (struct php_ctlr_state_s *) kmalloc(sizeof(struct php_ctlr_state_s), GFP_KERNEL);
1414
1415         if (!php_ctlr) {        /* allocate controller state data */
1416                 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1417                 goto abort;
1418         }
1419
1420         memset(php_ctlr, 0, sizeof(struct php_ctlr_state_s));
1421
1422         php_ctlr->pci_dev = pdev;       /* save pci_dev in context */
1423
1424         rc = pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor_id);
1425         dbg("%s: Vendor ID: %x\n",__FUNCTION__, vendor_id);
1426         if (rc) {
1427                 err("%s: unable to read PCI configuration data\n", __FUNCTION__);
1428                 goto abort_free_ctlr;
1429         }
1430
1431         rc = pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
1432         dbg("%s: Device ID: %x\n",__FUNCTION__, device_id);
1433         if (rc) {
1434                 err("%s: unable to read PCI configuration data\n", __FUNCTION__);
1435                 goto abort_free_ctlr;
1436         }
1437
1438         if ((vendor_id == PCI_VENDOR_ID_AMD) || (device_id == PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1439                 shpc_base_offset = 0;  /* amd shpc driver doesn't use this; assume 0 */
1440         } else {
1441                 if ((shpc_cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC)) == 0) {
1442                         err("%s : shpc_cap_offset == 0\n", __FUNCTION__);
1443                         goto abort_free_ctlr;
1444                 }
1445                 dbg("%s: shpc_cap_offset = %x\n", __FUNCTION__, shpc_cap_offset);
1446
1447                 rc = pci_write_config_byte(pdev, (u8)shpc_cap_offset + DWORD_SELECT , BASE_OFFSET);
1448                 if (rc) {
1449                         err("%s : pci_word_config_byte failed\n", __FUNCTION__);
1450                         goto abort_free_ctlr;
1451                 }
1452
1453                 rc = pci_read_config_dword(pdev, (u8)shpc_cap_offset + DWORD_DATA, &shpc_base_offset);
1454                 if (rc) {
1455                         err("%s : pci_read_config_dword failed\n", __FUNCTION__);
1456                         goto abort_free_ctlr;
1457                 }
1458
1459                 for (i = 0; i <= 14; i++) {
1460                         rc = pci_write_config_byte(pdev, (u8)shpc_cap_offset +  DWORD_SELECT , i);
1461                         if (rc) {
1462                                 err("%s : pci_word_config_byte failed\n", __FUNCTION__);
1463                                 goto abort_free_ctlr;
1464                         }
1465
1466                         rc = pci_read_config_dword(pdev, (u8)shpc_cap_offset + DWORD_DATA, &tempdword);
1467                         if (rc) {
1468                                 err("%s : pci_read_config_dword failed\n", __FUNCTION__);
1469                                 goto abort_free_ctlr;
1470                         }
1471                         dbg("%s: offset %d: tempdword %x\n", __FUNCTION__,i, tempdword);
1472                 }
1473         }
1474
1475         if (first) {
1476                 spin_lock_init(&hpc_event_lock);
1477                 first = 0;
1478         }
1479
1480         dbg("pdev = %p: b:d:f:irq=0x%x:%x:%x:%x\n", pdev, pdev->bus->number, PCI_SLOT(pdev->devfn),
1481                 PCI_FUNC(pdev->devfn), pdev->irq);
1482         for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1483                 if (pci_resource_len(pdev, rc) > 0)
1484                         dbg("pci resource[%d] start=0x%lx(len=0x%lx), shpc_base_offset %x\n", rc,
1485                                 pci_resource_start(pdev, rc), pci_resource_len(pdev, rc), shpc_base_offset);
1486
1487         info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1488                 pdev->subsystem_device);
1489
1490         if (!request_mem_region(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0), MY_NAME)) {
1491                 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1492                 goto abort_free_ctlr;
1493         }
1494
1495         php_ctlr->creg = (struct ctrl_reg *)
1496                 ioremap(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0));
1497         if (!php_ctlr->creg) {
1498                 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__, pci_resource_len(pdev, 0),
1499                         pci_resource_start(pdev, 0) + shpc_base_offset);
1500                 release_mem_region(pci_resource_start(pdev, 0) + shpc_base_offset, pci_resource_len(pdev, 0));
1501                 goto abort_free_ctlr;
1502         }
1503         dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1504         dbg("%s: physical addr %p\n", __FUNCTION__, (void*)pci_resource_start(pdev, 0));
1505
1506         init_MUTEX(&ctrl->crit_sect);
1507         /* Setup wait queue */
1508         init_waitqueue_head(&ctrl->queue);
1509
1510         /* Find the IRQ */
1511         php_ctlr->irq = pdev->irq;
1512         dbg("HPC interrupt = %d\n", php_ctlr->irq);
1513
1514         /* Save interrupt callback info */
1515         php_ctlr->attention_button_callback = attention_button_callback;
1516         php_ctlr->switch_change_callback = switch_change_callback;
1517         php_ctlr->presence_change_callback = presence_change_callback;
1518         php_ctlr->power_fault_callback = power_fault_callback;
1519         php_ctlr->callback_instance_id = instance_id;
1520
1521         /* Return PCI Controller Info */
1522         php_ctlr->slot_device_offset = (readl(php_ctlr->creg + SLOT_CONFIG) & FIRST_DEV_NUM ) >> 8;
1523         php_ctlr->num_slots = readl(php_ctlr->creg + SLOT_CONFIG) & SLOT_NUM;
1524         dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1525         dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1526
1527         /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1528         tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1529         dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1530         tempdword = 0x0003000f;
1531         writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
1532         tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1533         dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1534
1535         /* Mask the MRL sensor SERR Mask of individual slot in
1536          * Slot SERR-INT Mask & clear all the existing event if any
1537          */
1538         for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1539                 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
1540                 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1541                         hp_slot, slot_reg);
1542                 tempdword = 0xffffffff;
1543                 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1544         }
1545
1546         if (shpchp_poll_mode)  {/* Install interrupt polling code */
1547                 /* Install and start the interrupt polling timer */
1548                 init_timer(&php_ctlr->int_poll_timer);
1549                 start_int_poll_timer( php_ctlr, 10 );   /* start with 10 second delay */
1550         } else {
1551                 /* Installs the interrupt handler */
1552                 rc = pci_enable_msi(pdev);
1553                 if (rc) {
1554                         info("Can't get msi for the hotplug controller\n");
1555                         info("Use INTx for the hotplug controller\n");
1556                         dbg("%s: rc = %x\n", __FUNCTION__, rc);
1557                 } else
1558                         php_ctlr->irq = pdev->irq;
1559
1560                 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1561                 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1562                 if (rc) {
1563                         err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1564                         goto abort_free_ctlr;
1565                 }
1566                 /* Execute OSHP method here */
1567         }
1568         dbg("%s: Before adding HPC to HPC list\n", __FUNCTION__);
1569
1570         /*  Add this HPC instance into the HPC list */
1571         spin_lock(&list_lock);
1572         if (php_ctlr_list_head == 0) {
1573                 php_ctlr_list_head = php_ctlr;
1574                 p = php_ctlr_list_head;
1575                 p->pnext = 0;
1576         } else {
1577                 p = php_ctlr_list_head;
1578
1579                 while (p->pnext)
1580                         p = p->pnext;
1581
1582                 p->pnext = php_ctlr;
1583         }
1584         spin_unlock(&list_lock);
1585
1586
1587         ctlr_seq_num++;
1588         ctrl->hpc_ctlr_handle = php_ctlr;
1589         ctrl->hpc_ops = &shpchp_hpc_ops;
1590
1591         for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1592                 slot_reg = readl(php_ctlr->creg + SLOT1 + 4*hp_slot );
1593                 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1594                         hp_slot, slot_reg);
1595                 tempdword = 0xe01fffff;
1596                 writel(tempdword, php_ctlr->creg + SLOT1 + (4*hp_slot));
1597         }
1598         if (!shpchp_poll_mode) {
1599                 /* Unmask all general input interrupts and SERR */
1600                 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1601                 tempdword = 0x0000000a;
1602                 writel(tempdword, php_ctlr->creg + SERR_INTR_ENABLE);
1603                 tempdword = readl(php_ctlr->creg + SERR_INTR_ENABLE);
1604                 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1605         }
1606
1607         dbg("%s: Leaving shpc_init\n", __FUNCTION__);
1608         DBG_LEAVE_ROUTINE
1609         return 0;
1610
1611         /* We end up here for the many possible ways to fail this API.  */
1612 abort_free_ctlr:
1613         kfree(php_ctlr);
1614 abort:
1615         DBG_LEAVE_ROUTINE
1616         return -1;
1617 }