3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
20 #include <asm/errno.h>
27 static DEFINE_SPINLOCK(msi_lock);
28 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
29 static struct kmem_cache* msi_cachep;
31 static int pci_msi_enable = 0;
33 static int msi_cache_init(void)
35 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
36 0, SLAB_HWCACHE_ALIGN, NULL, NULL);
43 void msix_flush_writes(unsigned int irq)
45 struct msi_desc *entry;
47 entry = msi_desc[irq];
48 BUG_ON(!entry || !entry->dev);
49 switch (entry->msi_attrib.type) {
55 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
56 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
57 readl(entry->mask_base + offset);
66 static void msi_set_mask_bit(unsigned int irq, int flag)
68 struct msi_desc *entry;
70 entry = msi_desc[irq];
71 BUG_ON(!entry || !entry->dev);
72 switch (entry->msi_attrib.type) {
74 if (entry->msi_attrib.maskbit) {
78 pos = (long)entry->mask_base;
79 pci_read_config_dword(entry->dev, pos, &mask_bits);
82 pci_write_config_dword(entry->dev, pos, mask_bits);
87 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
88 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
89 writel(flag, entry->mask_base + offset);
98 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
100 struct msi_desc *entry = get_irq_data(irq);
101 switch(entry->msi_attrib.type) {
104 struct pci_dev *dev = entry->dev;
105 int pos = entry->msi_attrib.pos;
108 pci_read_config_dword(dev, msi_lower_address_reg(pos),
110 if (entry->msi_attrib.is_64) {
111 pci_read_config_dword(dev, msi_upper_address_reg(pos),
113 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
116 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
121 case PCI_CAP_ID_MSIX:
124 base = entry->mask_base +
125 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
127 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
128 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
129 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
137 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
139 struct msi_desc *entry = get_irq_data(irq);
140 switch (entry->msi_attrib.type) {
143 struct pci_dev *dev = entry->dev;
144 int pos = entry->msi_attrib.pos;
146 pci_write_config_dword(dev, msi_lower_address_reg(pos),
148 if (entry->msi_attrib.is_64) {
149 pci_write_config_dword(dev, msi_upper_address_reg(pos),
151 pci_write_config_word(dev, msi_data_reg(pos, 1),
154 pci_write_config_word(dev, msi_data_reg(pos, 0),
159 case PCI_CAP_ID_MSIX:
162 base = entry->mask_base +
163 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
165 writel(msg->address_lo,
166 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
167 writel(msg->address_hi,
168 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
169 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
177 void mask_msi_irq(unsigned int irq)
179 msi_set_mask_bit(irq, 1);
182 void unmask_msi_irq(unsigned int irq)
184 msi_set_mask_bit(irq, 0);
187 void disable_msi_irq(unsigned int irq)
189 msi_set_mask_bit(irq, 1);
190 msix_flush_writes(irq);
193 void enable_msi_irq(unsigned int irq)
195 msi_set_mask_bit(irq, 0);
196 msix_flush_writes(irq);
198 static int msi_free_irq(struct pci_dev* dev, int irq);
199 static int msi_init(void)
201 static int status = -ENOMEM;
208 printk(KERN_WARNING "PCI: MSI quirk detected. MSI disabled.\n");
213 status = msi_cache_init();
216 printk(KERN_WARNING "PCI: MSI cache init failed\n");
223 static struct msi_desc* alloc_msi_entry(void)
225 struct msi_desc *entry;
227 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
231 entry->link.tail = entry->link.head = 0; /* single message */
237 static void attach_msi_entry(struct msi_desc *entry, int irq)
241 spin_lock_irqsave(&msi_lock, flags);
242 msi_desc[irq] = entry;
243 spin_unlock_irqrestore(&msi_lock, flags);
246 static int create_msi_irq(void)
248 struct msi_desc *entry;
251 entry = alloc_msi_entry();
257 kmem_cache_free(msi_cachep, entry);
261 set_irq_data(irq, entry);
266 static void destroy_msi_irq(unsigned int irq)
268 struct msi_desc *entry;
270 entry = get_irq_data(irq);
271 set_irq_chip(irq, NULL);
272 set_irq_data(irq, NULL);
274 kmem_cache_free(msi_cachep, entry);
277 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
281 pci_read_config_word(dev, msi_control_reg(pos), &control);
282 if (type == PCI_CAP_ID_MSI) {
283 /* Set enabled bits to single MSI & enable MSI_enable bit */
284 msi_enable(control, 1);
285 pci_write_config_word(dev, msi_control_reg(pos), control);
286 dev->msi_enabled = 1;
288 msix_enable(control);
289 pci_write_config_word(dev, msi_control_reg(pos), control);
290 dev->msix_enabled = 1;
293 pci_intx(dev, 0); /* disable intx */
296 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
300 pci_read_config_word(dev, msi_control_reg(pos), &control);
301 if (type == PCI_CAP_ID_MSI) {
302 /* Set enabled bits to single MSI & enable MSI_enable bit */
303 msi_disable(control);
304 pci_write_config_word(dev, msi_control_reg(pos), control);
305 dev->msi_enabled = 0;
307 msix_disable(control);
308 pci_write_config_word(dev, msi_control_reg(pos), control);
309 dev->msix_enabled = 0;
312 pci_intx(dev, 1); /* enable intx */
315 static int msi_lookup_irq(struct pci_dev *dev, int type)
320 spin_lock_irqsave(&msi_lock, flags);
321 for (irq = 0; irq < NR_IRQS; irq++) {
322 if (!msi_desc[irq] || msi_desc[irq]->dev != dev ||
323 msi_desc[irq]->msi_attrib.type != type ||
324 msi_desc[irq]->msi_attrib.default_irq != dev->irq)
326 spin_unlock_irqrestore(&msi_lock, flags);
327 /* This pre-assigned MSI irq for this device
328 already exits. Override dev->irq with this irq */
332 spin_unlock_irqrestore(&msi_lock, flags);
337 void pci_scan_msi_device(struct pci_dev *dev)
344 int pci_save_msi_state(struct pci_dev *dev)
348 struct pci_cap_saved_state *save_state;
351 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
352 if (pos <= 0 || dev->no_msi)
355 pci_read_config_word(dev, msi_control_reg(pos), &control);
356 if (!(control & PCI_MSI_FLAGS_ENABLE))
359 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
362 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
365 cap = &save_state->data[0];
367 pci_read_config_dword(dev, pos, &cap[i++]);
368 control = cap[0] >> 16;
369 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
370 if (control & PCI_MSI_FLAGS_64BIT) {
371 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
372 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
374 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
375 if (control & PCI_MSI_FLAGS_MASKBIT)
376 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
377 save_state->cap_nr = PCI_CAP_ID_MSI;
378 pci_add_saved_cap(dev, save_state);
382 void pci_restore_msi_state(struct pci_dev *dev)
386 struct pci_cap_saved_state *save_state;
389 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
390 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
391 if (!save_state || pos <= 0)
393 cap = &save_state->data[0];
395 control = cap[i++] >> 16;
396 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
397 if (control & PCI_MSI_FLAGS_64BIT) {
398 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
399 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
401 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
402 if (control & PCI_MSI_FLAGS_MASKBIT)
403 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
404 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
405 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
406 pci_remove_saved_cap(save_state);
410 int pci_save_msix_state(struct pci_dev *dev)
414 int irq, head, tail = 0;
416 struct pci_cap_saved_state *save_state;
418 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
419 if (pos <= 0 || dev->no_msi)
422 /* save the capability */
423 pci_read_config_word(dev, msi_control_reg(pos), &control);
424 if (!(control & PCI_MSIX_FLAGS_ENABLE))
426 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
429 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
432 *((u16 *)&save_state->data[0]) = control;
436 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
441 irq = head = dev->irq;
442 while (head != tail) {
443 struct msi_desc *entry;
445 entry = msi_desc[irq];
446 read_msi_msg(irq, &entry->msg_save);
448 tail = msi_desc[irq]->link.tail;
453 save_state->cap_nr = PCI_CAP_ID_MSIX;
454 pci_add_saved_cap(dev, save_state);
458 void pci_restore_msix_state(struct pci_dev *dev)
462 int irq, head, tail = 0;
463 struct msi_desc *entry;
465 struct pci_cap_saved_state *save_state;
467 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
470 save = *((u16 *)&save_state->data[0]);
471 pci_remove_saved_cap(save_state);
474 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
478 /* route the table */
480 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX))
482 irq = head = dev->irq;
483 while (head != tail) {
484 entry = msi_desc[irq];
485 write_msi_msg(irq, &entry->msg_save);
487 tail = msi_desc[irq]->link.tail;
492 pci_write_config_word(dev, msi_control_reg(pos), save);
493 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
498 * msi_capability_init - configure device's MSI capability structure
499 * @dev: pointer to the pci_dev data structure of MSI device function
501 * Setup the MSI capability structure of device function with a single
502 * MSI irq, regardless of device function is capable of handling
503 * multiple messages. A return of zero indicates the successful setup
504 * of an entry zero with the new MSI irq or non-zero for otherwise.
506 static int msi_capability_init(struct pci_dev *dev)
509 struct msi_desc *entry;
513 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
514 pci_read_config_word(dev, msi_control_reg(pos), &control);
515 /* MSI Entry Initialization */
516 irq = create_msi_irq();
520 entry = get_irq_data(irq);
521 entry->link.head = irq;
522 entry->link.tail = irq;
523 entry->msi_attrib.type = PCI_CAP_ID_MSI;
524 entry->msi_attrib.is_64 = is_64bit_address(control);
525 entry->msi_attrib.entry_nr = 0;
526 entry->msi_attrib.maskbit = is_mask_bit_support(control);
527 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
528 entry->msi_attrib.pos = pos;
529 if (is_mask_bit_support(control)) {
530 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
531 is_64bit_address(control));
534 if (entry->msi_attrib.maskbit) {
535 unsigned int maskbits, temp;
536 /* All MSIs are unmasked by default, Mask them all */
537 pci_read_config_dword(dev,
538 msi_mask_bits_reg(pos, is_64bit_address(control)),
540 temp = (1 << multi_msi_capable(control));
541 temp = ((temp - 1) & ~temp);
543 pci_write_config_dword(dev,
544 msi_mask_bits_reg(pos, is_64bit_address(control)),
547 /* Configure MSI capability structure */
548 status = arch_setup_msi_irq(irq, dev);
550 destroy_msi_irq(irq);
554 attach_msi_entry(entry, irq);
555 /* Set MSI enabled bits */
556 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
563 * msix_capability_init - configure device's MSI-X capability
564 * @dev: pointer to the pci_dev data structure of MSI-X device function
565 * @entries: pointer to an array of struct msix_entry entries
566 * @nvec: number of @entries
568 * Setup the MSI-X capability structure of device function with a
569 * single MSI-X irq. A return of zero indicates the successful setup of
570 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
572 static int msix_capability_init(struct pci_dev *dev,
573 struct msix_entry *entries, int nvec)
575 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
577 int irq, pos, i, j, nr_entries, temp = 0;
578 unsigned long phys_addr;
584 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
585 /* Request & Map MSI-X table region */
586 pci_read_config_word(dev, msi_control_reg(pos), &control);
587 nr_entries = multi_msix_capable(control);
589 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
590 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
591 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
592 phys_addr = pci_resource_start (dev, bir) + table_offset;
593 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
597 /* MSI-X Table Initialization */
598 for (i = 0; i < nvec; i++) {
599 irq = create_msi_irq();
603 entry = get_irq_data(irq);
604 j = entries[i].entry;
605 entries[i].vector = irq;
606 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
607 entry->msi_attrib.is_64 = 1;
608 entry->msi_attrib.entry_nr = j;
609 entry->msi_attrib.maskbit = 1;
610 entry->msi_attrib.default_irq = dev->irq;
611 entry->msi_attrib.pos = pos;
613 entry->mask_base = base;
615 entry->link.head = irq;
616 entry->link.tail = irq;
619 entry->link.head = temp;
620 entry->link.tail = tail->link.tail;
621 tail->link.tail = irq;
622 head->link.head = irq;
626 /* Configure MSI-X capability structure */
627 status = arch_setup_msi_irq(irq, dev);
629 destroy_msi_irq(irq);
633 attach_msi_entry(entry, irq);
638 for (; i >= 0; i--) {
639 irq = (entries + i)->vector;
640 msi_free_irq(dev, irq);
641 (entries + i)->vector = 0;
643 /* If we had some success report the number of irqs
644 * we succeeded in setting up.
650 /* Set MSI-X enabled bits */
651 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
657 * pci_msi_supported - check whether MSI may be enabled on device
658 * @dev: pointer to the pci_dev data structure of MSI device function
660 * Look at global flags, the device itself, and its parent busses
661 * to return 0 if MSI are supported for the device.
664 int pci_msi_supported(struct pci_dev * dev)
668 /* MSI must be globally enabled and supported by the device */
669 if (!pci_msi_enable || !dev || dev->no_msi)
672 /* Any bridge which does NOT route MSI transactions from it's
673 * secondary bus to it's primary bus must set NO_MSI flag on
674 * the secondary pci_bus.
675 * We expect only arch-specific PCI host bus controller driver
676 * or quirks for specific PCI bridges to be setting NO_MSI.
678 for (bus = dev->bus; bus; bus = bus->parent)
679 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
686 * pci_enable_msi - configure device's MSI capability structure
687 * @dev: pointer to the pci_dev data structure of MSI device function
689 * Setup the MSI capability structure of device function with
690 * a single MSI irq upon its software driver call to request for
691 * MSI mode enabled on its hardware device function. A return of zero
692 * indicates the successful setup of an entry zero with the new MSI
693 * irq or non-zero for otherwise.
695 int pci_enable_msi(struct pci_dev* dev)
697 int pos, temp, status;
699 if (pci_msi_supported(dev) < 0)
708 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
712 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI));
714 /* Check whether driver already requested for MSI-X irqs */
715 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
716 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
717 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
718 "Device already has MSI-X irq assigned\n",
723 status = msi_capability_init(dev);
727 void pci_disable_msi(struct pci_dev* dev)
729 struct msi_desc *entry;
730 int pos, default_irq;
739 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
743 pci_read_config_word(dev, msi_control_reg(pos), &control);
744 if (!(control & PCI_MSI_FLAGS_ENABLE))
747 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
749 spin_lock_irqsave(&msi_lock, flags);
750 entry = msi_desc[dev->irq];
751 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
752 spin_unlock_irqrestore(&msi_lock, flags);
755 if (irq_has_action(dev->irq)) {
756 spin_unlock_irqrestore(&msi_lock, flags);
757 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
758 "free_irq() on MSI irq %d\n",
759 pci_name(dev), dev->irq);
760 BUG_ON(irq_has_action(dev->irq));
762 default_irq = entry->msi_attrib.default_irq;
763 spin_unlock_irqrestore(&msi_lock, flags);
764 msi_free_irq(dev, dev->irq);
766 /* Restore dev->irq to its default pin-assertion irq */
767 dev->irq = default_irq;
771 static int msi_free_irq(struct pci_dev* dev, int irq)
773 struct msi_desc *entry;
774 int head, entry_nr, type;
778 arch_teardown_msi_irq(irq);
780 spin_lock_irqsave(&msi_lock, flags);
781 entry = msi_desc[irq];
782 if (!entry || entry->dev != dev) {
783 spin_unlock_irqrestore(&msi_lock, flags);
786 type = entry->msi_attrib.type;
787 entry_nr = entry->msi_attrib.entry_nr;
788 head = entry->link.head;
789 base = entry->mask_base;
790 msi_desc[entry->link.head]->link.tail = entry->link.tail;
791 msi_desc[entry->link.tail]->link.head = entry->link.head;
793 msi_desc[irq] = NULL;
794 spin_unlock_irqrestore(&msi_lock, flags);
796 destroy_msi_irq(irq);
798 if (type == PCI_CAP_ID_MSIX) {
799 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
800 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
810 * pci_enable_msix - configure device's MSI-X capability structure
811 * @dev: pointer to the pci_dev data structure of MSI-X device function
812 * @entries: pointer to an array of MSI-X entries
813 * @nvec: number of MSI-X irqs requested for allocation by device driver
815 * Setup the MSI-X capability structure of device function with the number
816 * of requested irqs upon its software driver call to request for
817 * MSI-X mode enabled on its hardware device function. A return of zero
818 * indicates the successful configuration of MSI-X capability structure
819 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
820 * Or a return of > 0 indicates that driver request is exceeding the number
821 * of irqs available. Driver should use the returned value to re-send
824 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
826 int status, pos, nr_entries;
830 if (!entries || pci_msi_supported(dev) < 0)
837 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
841 pci_read_config_word(dev, msi_control_reg(pos), &control);
842 nr_entries = multi_msix_capable(control);
843 if (nvec > nr_entries)
846 /* Check for any invalid entries */
847 for (i = 0; i < nvec; i++) {
848 if (entries[i].entry >= nr_entries)
849 return -EINVAL; /* invalid entry */
850 for (j = i + 1; j < nvec; j++) {
851 if (entries[i].entry == entries[j].entry)
852 return -EINVAL; /* duplicate entry */
856 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX));
858 /* Check whether driver already requested for MSI irq */
859 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
860 !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
861 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
862 "Device already has an MSI irq assigned\n",
867 status = msix_capability_init(dev, entries, nvec);
871 void pci_disable_msix(struct pci_dev* dev)
881 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
885 pci_read_config_word(dev, msi_control_reg(pos), &control);
886 if (!(control & PCI_MSIX_FLAGS_ENABLE))
889 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
892 if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
893 int irq, head, tail = 0, warning = 0;
896 irq = head = dev->irq;
897 dev->irq = temp; /* Restore pin IRQ */
898 while (head != tail) {
899 spin_lock_irqsave(&msi_lock, flags);
900 tail = msi_desc[irq]->link.tail;
901 spin_unlock_irqrestore(&msi_lock, flags);
902 if (irq_has_action(irq))
904 else if (irq != head) /* Release MSI-X irq */
905 msi_free_irq(dev, irq);
908 msi_free_irq(dev, irq);
910 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
911 "free_irq() on all MSI-X irqs\n",
919 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
920 * @dev: pointer to the pci_dev data structure of MSI(X) device function
922 * Being called during hotplug remove, from which the device function
923 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
924 * allocated for this device function, are reclaimed to unused state,
925 * which may be used later on.
927 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
932 if (!pci_msi_enable || !dev)
935 temp = dev->irq; /* Save IOAPIC IRQ */
936 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
937 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
938 if (irq_has_action(dev->irq)) {
939 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
940 "called without free_irq() on MSI irq %d\n",
941 pci_name(dev), dev->irq);
942 BUG_ON(irq_has_action(dev->irq));
943 } else /* Release MSI irq assigned to this device */
944 msi_free_irq(dev, dev->irq);
945 dev->irq = temp; /* Restore IOAPIC IRQ */
947 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
948 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
949 int irq, head, tail = 0, warning = 0;
950 void __iomem *base = NULL;
952 irq = head = dev->irq;
953 while (head != tail) {
954 spin_lock_irqsave(&msi_lock, flags);
955 tail = msi_desc[irq]->link.tail;
956 base = msi_desc[irq]->mask_base;
957 spin_unlock_irqrestore(&msi_lock, flags);
958 if (irq_has_action(irq))
960 else if (irq != head) /* Release MSI-X irq */
961 msi_free_irq(dev, irq);
964 msi_free_irq(dev, irq);
967 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
968 "called without free_irq() on all MSI-X irqs\n",
972 dev->irq = temp; /* Restore IOAPIC IRQ */
976 void pci_no_msi(void)
980 void pci_yes_msi(void)
985 EXPORT_SYMBOL(pci_enable_msi);
986 EXPORT_SYMBOL(pci_disable_msi);
987 EXPORT_SYMBOL(pci_enable_msix);
988 EXPORT_SYMBOL(pci_disable_msix);